A semiconductor device and a method for manufacturing the same

Abstract

This application relates to the field of semiconductors, and discloses a semiconductor device and a manufacturing method thereof. The device includes: a substrate; an epitaxial structure layer located on the upper surface of the substrate; a two-dimensional electron gas existing in the epitaxial structure layer; a passivation layer located on the upper surface of the epitaxial structure layer; the passivation layer has a first through hole and a second through hole penetrating the thickness of the passivation layer; a second electrode and a first electrode located in the first through hole, and the second through hole is located between the second electrode and the first electrode. In the passivation layer of this application, the second through hole is between the first electrode and the second electrode, blocking the leakage channel at the interface between the passivation layer and the epitaxial structure layer. By comparing the electrical characteristics between the first electrode and the second electrode of the semiconductor device in this application and the semiconductor device without the second through hole in the related art, the leakage of the passivation interface can be characterized. Therefore, the semiconductor device in this application can accurately determine the influence of the passivation layer and takes a short time.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Passivation in a High Electron Mobility Transistor (HEMT) directly affects its characteristics such as gate leakage current, current collapse, and breakdown leakage current. The development and research of the passivation process, the characterization of the passivation material, and the related research on the impact of this process on device performance become particularly important.

[0003] A cross-sectional schematic diagram of a high electron mobility transistor is as Figure 1 shown. The passivation layer is located on the surface of the epitaxial structure layer and is in direct contact with the barrier layer. The gate, source, and drain are embedded in the passivation layer. The electrical properties of the passivation layer are monitored using a MIM (Metal-Insulator-Metal) structure to measure its breakdown and capacitance characteristics. However, since the passivation layer is in direct contact with the barrier layer, it is difficult to use this method to characterize its electrical characteristics. It is necessary to wait until the high electron mobility transistor is fabricated and then perform electrical tests on the high electron mobility transistor to infer the role of the passivation layer. Currently, this method has a long iteration cycle, high cost, and is affected by processes such as gate etching and gate annealing, making it difficult to accurately locate the impact of the passivation layer on the transistor device.

[0004] Therefore, how to solve the above technical problems should be the key concern of those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which can accurately determine the impact of the passivation layer, with short time consumption and low cost.

[0006] To solve the above technical problems, this application provides a semiconductor device, including:

[0007] A substrate;

[0008] An epitaxial structure layer located on the upper surface of the substrate; the epitaxial structure layer has a two-dimensional electron gas;

[0009] A passivation layer located on the upper surface of the epitaxial structure layer; the passivation layer has a first through hole and a second through hole penetrating the thickness of the passivation layer;

[0010] A second electrode and a first electrode located in the first through hole, and the second through hole is located between the second electrode and the first electrode.

[0011] Optionally, the semiconductor device is a diode, and the first electrode surrounds the second electrode.

[0012] Optionally, the number of the first electrodes is two. The two first electrodes are a source electrode and a drain electrode, the second electrode is a gate electrode, and the two first electrodes are respectively located on two sides of the second electrode.

[0013] Optionally, the epitaxial structure layer includes a GaN / AlGaN stack, a GaN / AlN / AlGaN stack, or a GaN / AlN / AlGaN / GaN stack.

[0014] Optionally, the second electrode is located on the upper surface of the passivation layer.

[0015] Optionally, it further includes:

[0016] A third via hole, which is located in the passivation layer and penetrates through the thickness of the passivation layer, and the second electrode is located in the third via hole.

[0017] This application also provides a method for manufacturing a semiconductor device, including:

[0018] Preparing a substrate;

[0019] Growing an epitaxial structure layer on the upper surface of the substrate and forming a two-dimensional electron gas in the epitaxial structure layer;

[0020] Growing a passivation layer on the upper surface of the epitaxial structure layer;

[0021] Etching the passivation layer to form a first via hole;

[0022] Fabricating a first electrode in the first via hole;

[0023] Fabricating a second electrode;

[0024] Etching the passivation layer between the second electrode and the first electrode to form a second via hole.

[0025] Optionally, forming a two-dimensional electron gas in the epitaxial structure layer includes:

[0026] Growing a protection layer on the upper surface of the epitaxial structure layer;

[0027] Under the protection of the protection layer, injecting a first ion into the epitaxial structure layer and activating the first ion to form a heavily doped N-type semiconductor connected to the two-dimensional electron gas;

[0028] Removing the protection layer;

[0029] After growing the passivation layer on the upper surface of the epitaxial structure layer, it further includes:

[0030] Injecting a second ion into the area of the epitaxial structure layer corresponding to the passive region to destroy the two-dimensional electron gas in the passive region.

[0031] Optionally, preparing the second electrode includes:

[0032] Preparing the second electrode on the surface of the passivation layer.

[0033] Optionally, preparing the second electrode includes:

[0034] Etching the passivation layer to form a third through hole;

[0035] Preparing the second electrode in the third through hole.

[0036] A semiconductor device provided by the present application includes: a substrate; an epitaxial structure layer located on the upper surface of the substrate; a two-dimensional electron gas in the epitaxial structure layer; a passivation layer located on the upper surface of the epitaxial structure layer; the passivation layer has a first through hole and a second through hole penetrating through the thickness of the passivation layer; a second electrode and a first electrode located in the first through hole, and the second through hole is located between the second electrode and the first electrode.

[0037] It can be seen that the semiconductor device in the present application includes a substrate, an epitaxial structure layer, a passivation layer, a first electrode and a second electrode. The passivation layer has a first through hole and a second through hole, and the second through hole is between the first electrode and the second electrode, that is, the passivation layer between the first electrode and the second electrode is disconnected through the second through hole, so as to block the leakage channel at the interface between the passivation layer and the epitaxial structure layer. By comparing the electrical characteristics between the first electrode and the second electrode of the semiconductor device in the present application and the semiconductor device without the second through hole in the related art, the leakage of the passivation interface can be characterized. Therefore, the semiconductor device in the present application can accurately determine the influence of the passivation layer, and the time consumption is short and it is not easily affected by other factors.

[0038] In addition, the present application also provides a method for manufacturing a semiconductor device having the above advantages. Description of the Drawings

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0040] Figure 1 Is a cross-sectional schematic diagram of a HEMT device in the related art;

[0041] Figure 2 Is a top view of a semiconductor device provided by an embodiment of the present application Figure 1 ;

[0042] Figure 3 The top view of a semiconductor device provided by an embodiment of the present application Figure 2 ;

[0043] Figure 4 is Figure 3 a schematic cross-sectional view of the semiconductor device shown along AA;

[0044] Figure 5 a schematic cross-sectional view of a semiconductor device provided by an embodiment of the present application;

[0045] Figure 6 is Figure 4 a schematic cross-sectional view of a HEMT device for providing a comparison when determining the leakage situation of the device shown;

[0046] Figure 7 the flow of a method for manufacturing a semiconductor device provided by an embodiment of the present application Figure 1 ;

[0047] Figure 8 the flow of a method for manufacturing a semiconductor device provided by an embodiment of the present application Figure 2 ;

[0048] Figures 9 to 13 a process flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0049] In the figure: 1', silicon substrate; 2', AlGaN barrier layer; 3', silicon nitride passivation layer; 4', gate; 5', source; 6', drain; 1, substrate; 2, epitaxial structure layer; 3, passivation layer; 4, two-dimensional electron gas; 5, second electrode; 6, first electrode; 7, second via hole; 8, protective layer; 21, GaN layer; 22, AlGaN layer; 23, GaN cap layer. Detailed implementation manners

[0050] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.

[0051] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0052] As Figure 1As shown, in a high electron mobility transistor, an epitaxial structure layer is located on the surface of a silicon substrate 1', a silicon nitride passivation layer 3' is located on the surface of the epitaxial structure layer and is in direct contact with an AlGaN barrier layer 2', and a gate 4', a source 5' and a drain 6' are embedded in the silicon nitride passivation layer 3'. It is necessary to wait until the high electron mobility transistor is fabricated and then perform electrical tests on the high electron mobility transistor to infer the function of the silicon nitride passivation layer. Currently, this method has a long iteration cycle, high cost, and is affected by processes such as gate etching and gate annealing, making it difficult to accurately locate the impact of the passivation layer on the transistor device.

[0053] In view of this, the present application provides a semiconductor device. Please refer to Figures 2 to 8 , including:

[0054] A substrate 1;

[0055] An epitaxial structure layer 2 located on the upper surface of the substrate 1; a two-dimensional electron gas 4 is present in the epitaxial structure layer 2;

[0056] A passivation layer 3 located on the upper surface of the epitaxial structure layer 2; the passivation layer 3 has a first through hole and a second through hole 7 penetrating the thickness of the passivation layer 3;

[0057] A second electrode 5 and a first electrode 6 located in the first through hole, and the second through hole 7 is located between the second electrode 5 and the first electrode 6.

[0058] The substrate 1 includes, but is not limited to, a silicon carbide (SiC) substrate, a silicon (Si) substrate, and a sapphire substrate.

[0059] It should be noted that the structure in the epitaxial structure layer 2 in the present application is not limited and can be set by itself. For example, the epitaxial structure layer 2 includes, but is not limited to, any one of a GaN / AlGaN stack, a GaN / AlN / AlGaN stack, and a GaN / AlN / AlGaN / GaN stack. Among them, the AlGaN layer serves as a barrier layer.

[0060] When the epitaxial structure layer 2 is a GaN / AlGaN stack, the GaN (gallium nitride) layer is in contact with the substrate 1, and the AlGaN (aluminum gallium nitride) layer is stacked on the GaN layer. When the epitaxial structure layer 2 is a GaN / AlN / AlGaN stack, the GaN layer is in contact with the substrate 1, the AlN (aluminum nitride) layer is stacked on the GaN layer, and the AlGaN layer is stacked on the AlN layer. When the epitaxial structure layer 2 is a GaN / AlN / AlGaN / GaN stack, the first GaN layer is in contact with the substrate 1, the AlN layer is stacked on the first GaN layer, the AlGaN layer is stacked on the AlN layer, and the second GaN layer is stacked on the AlGaN layer.

[0061] The epitaxial structure layer 2 may include a GaN cap layer.

[0062] The material of the passivation layer 3 can be silicon nitride (SiN).

[0063] There is a second through hole 7 in the passivation layer 3 between the second electrode 5 and the first electrode 6, that is, the passivation layer 3 between the second electrode 5 and the first electrode 6 is disconnected, that is, the leakage channel at the SiN / AlGaN interface is blocked.

[0064] It should be noted that the type of the semiconductor device is not limited in this application.

[0065] As an implementable manner, the semiconductor device can be a diode, and the first electrode 6 surrounds the second electrode 5. Please refer to Figure 2 , the diode is of a circular structure, the second electrode 5 can be an anode and is located in the central region, and the first electrode 6 can be a cathode and surrounds the anode. The number of the first electrodes 6 is one, and the number of the second electrodes 5 is also one.

[0066] As another implementable manner, the semiconductor device can be a HEMT device. Please refer to Figure 3 and Figure 4 , the number of the first electrodes 6 is two, the two first electrodes 6 are a source electrode and a drain electrode, the second electrode 5 is a gate electrode, and the two first electrodes 6 are respectively located on both sides of the second electrode 5.

[0067] Please refer to Figure 3 and Figure 4 , when the semiconductor device can be a HEMT device, the metal of the source electrode and the drain electrode reacts with the semiconductor to form an ohmic metal. The metal of the source electrode and the drain electrode can be Ti / Al / Ni / Au, Ti / Al / Ti or Ti / Pt / Au / Ti, etc. The metal of the gate electrode can be NiAu, NiPbAu, etc. After annealing, a MIS structure is formed. The gate electrode is located between the source electrode and the drain electrode. The gate length is not limited under the condition of ensuring the distances between the gate electrode and the source electrode and between the gate electrode and the drain electrode, and can be less than 1 micron or dozens of microns.

[0068] It should also be noted that the position of the second electrode 5 is not limited in this application and can be set by itself.

[0069] As an implementable manner, the second electrode 5 is located on the upper surface of the passivation layer 3, as shown in Figure 4 .

[0070] As another implementable manner, as shown in Figure 5 , the semiconductor device further includes: a third through hole, the third through hole is located in the passivation layer 3 and penetrates through the thickness of the passivation layer 3, and the second electrode 5 is located in the third through hole.

[0071] Please refer to Figure 5When the semiconductor device can be a HEMT device, the metal of the gate can be NiAu, NiPbAu, etc. After annealing, a Schottky contact is formed, and the Schottky gate can be a T-shaped, Y-shaped, or Γ-shaped gate.

[0072] Figure 5 Taking the semiconductor device as a HEMT device as an example shown in [the relevant content], the second electrode 5 located in the third through hole is also applicable to the diode device.

[0073] The semiconductor device in this embodiment includes a substrate 1, an epitaxial structure layer 2, a passivation layer 3, a first electrode 6, and a second electrode 5. The passivation layer 3 has a first through hole and a second through hole 7. The second through hole 7 is between the first electrode 6 and the second electrode 5, that is, the passivation layer 3 between the first electrode 6 and the second electrode 5 is disconnected through the second through hole 7, so as to block the leakage channel at the interface between the passivation layer 3 and the epitaxial structure layer 2. By comparing the electrical characteristics between the first electrode 6 and the second electrode 5 of the semiconductor device in this application and the semiconductor device without the second through hole 7 in the related technology, the leakage of the passivation interface can be characterized. Therefore, the semiconductor device in this application can accurately determine the influence of the passivation layer 3, with short time consumption and being not easily affected by other factors.

[0074] Taking the device shown in this application Figure 4 as an example, the leakage of the passivation layer 3 (SiN) is characterized. Taking Figure 6 the shown HEMT device as a control, Figure 6 in the shown HEMT device, there is no second through hole 7 in the passivation layer 3 between the gate and the source, and between the gate and the drain. Comparing Figure 4 the device shown during the process of etching the second through hole 7 in the passivation layer 3, at different etching depths until the leakage channel at the interface with the epitaxial structure layer 2 is blocked, it can be used to monitor the leakage situation at the interface of the passivation layer 3 and the leakage situation of the passivation layer 3 material.

[0075] The source and drain of the HEMT device are connected to a 0V potential or grounded, and a reverse electrical stress (which can be 0 to -60V) is applied to the gate, and the Ig current is measured and recorded as I_leak.

[0076] Subtract Figure 6 the gate current Ig1 of the shown HEMT device from Figure 4 the gate current Ig2 of the shown HEMT device at different etching depths of the passivation layer 3, and a series of current differences ΔIg can be obtained; after normalizing ΔIg, it reflects the leakage level of the passivation layer 3 material; when the passivation layer 3 is etched to the surface of the epitaxial structure layer 2, the leakage channel of the passivation layer 3 is blocked, and at this time the leakage is the smallest.

[0077] The total leakage of the passivation layer 3 can be calculated according to the thickness of the passivation layer 3, Figure 6The interface leakage of the passivation layer 3 can be obtained by subtracting the leakage etched to the surface of the epitaxial structure layer 2 (GaN layer) from the leakage of the HEMT device shown and then subtracting the total leakage of the passivation layer 3.

[0078] When the passivation layer 3 is etched to different thicknesses, the measured Ig current and the current difference ΔIg are shown in Table 1.

[0079] Table 1

[0080]

[0081] Determination of the leakage of the passivation layer 3 material: According to the variation law of ΔIg, the leakage density of the SiN material of the passivation layer 3 can be obtained. That is, after the current difference ΔIg is divided by the corresponding etching thickness to obtain multiple leakage densities, the average value of the multiple leakage densities is taken as the leakage density of the SiN material of the passivation layer 3.

[0082] Determination of interface leakage: According to the leakage density of SiN material and SiN thickness, the total leakage of SiN can be calculated; Ig_0-Ig_GaN, then subtract the total leakage of SiN, and the SiN interface leakage can be obtained. Among them, the total leakage of SiN is the leakage density of SiN material multiplied by the thickness of SiN.

[0083] for Figure 5 For the HEMT device shown, the leakage current of the passivation layer 3 (SiN) needs to be characterized by Figure 1 The HEMT device shown is used as a control. The specific leakage characterization process is the same as the above process, but Figure 5 and Figure 1 The gate of the HEMT device shown is a Schottky gate, and the measured Ig leakage will be larger.

[0084] Compare the two device structures with and without the passivation layer 3 under the gate (for example Figure 4 and Figure 5 The semiconductor device shown, Figure 1 and Figure 6 The capacitance-voltage test (CV test) of the semiconductor device shown in the figure is performed. The horizontal coordinate of the curve obtained by the test is voltage, and the vertical coordinate is capacitance. The thickness and capacitance density information of the passivation layer 3 can be obtained, and the interface state density information of the passivation layer 3 can be obtained.

[0085] Characterization method of passivation layer capacitance value:

[0086] (1) Test scheme: The source or drain of the HEMT device is connected to the Low_force terminal of the CV test module, and the gate is connected to the High_force terminal. The frequency is 1 MHz. Stress is applied to the gate to obtain the capacitance value.

[0087] (2) Figure 6The capacitance value of the SiN passivation layer + AlGaN barrier layer was measured for the device shown. Figure 1 The capacitance value of the AlGaN barrier layer was measured for the device shown. The dielectric capacitance density and dielectric thickness of the SiN passivation layer were obtained according to Formula (1) and Formula (2).

[0088]

[0089] C OX =ε0ε OX A / d OX (2)

[0090] In the formula, C MOS-HEMT is Figure 6 the capacitance measured for the device shown; C OX is the dielectric capacitance of the passivation layer; C HEMT is Figure 1 the capacitance measured for the device shown; ε0 is the vacuum permittivity; ε OX is the dielectric constant of the passivation layer, which can be measured by ellipsometric offset; A is the metal facing area, determined by the process and layout; d OX is the thickness of the passivation layer.

[0091] This application also provides a method for fabricating a semiconductor device. Please refer to Figure 7 , including:

[0092] Step S101: Prepare a substrate.

[0093] The substrate is a clean substrate, which can be a silicon carbide substrate, a silicon substrate, a sapphire substrate, etc.

[0094] Step S102: Grow an epitaxial structure layer on the upper surface of the substrate and form a two-dimensional electron gas in the epitaxial structure layer.

[0095] The epitaxial structure layer can be a GaN / AlGaN stack, a GaN / AlN / AlGaN stack, a GaN / AlN / AlGaN / GaN stack, etc.

[0096] Step S103: Grow a passivation layer on the upper surface of the epitaxial structure layer.

[0097] The material of the passivation layer can be silicon nitride, and the growth method of the passivation layer can be low-pressure chemical vapor deposition (LPCVD) method.

[0098] Step S104: Etch the passivation layer to form a first through hole.

[0099] Step S105: Fabricate a first electrode in the first through hole.

[0100] The first electrode can be prepared by electron beam evaporation.

[0101] The number of the first electrodes depends on the type of the semiconductor device. When the semiconductor device is a circular diode, the number of the first electrodes is one. The first electrode is the cathode, and the second electrode is the anode. The anode is located in the central region, and the cathode surrounds the anode. When the semiconductor device is a HEMT device, the number of the first electrodes is two. The two first electrodes are the source electrode and the drain electrode, and the second electrode is the gate electrode. The two first electrodes are respectively located on both sides of the second electrode.

[0102] Step S106: Prepare the second electrode.

[0103] The second electrode can be prepared by electron beam evaporation.

[0104] As an implementable manner, preparing the second electrode includes:

[0105] Prepare the second electrode on the surface of the passivation layer, that is, the second electrode is located on the surface of the passivation layer.

[0106] As another implementable manner, preparing the second electrode includes:

[0107] Etch the passivation layer to form a third through hole;

[0108] Prepare the second electrode in the third through hole.

[0109] The third through hole penetrates the passivation layer, and the second electrode is in the third through hole, that is, there is no passivation layer under the second electrode.

[0110] Step S107: Etch the passivation layer between the second electrode and the first electrode to form a second through hole.

[0111] The semiconductor device prepared in this embodiment includes a substrate, an epitaxial structure layer, a passivation layer, a first electrode and a second electrode. The passivation layer has a first through hole and a second through hole. The second through hole is between the first electrode and the second electrode, that is, the passivation layer between the first electrode and the second electrode is disconnected through the second through hole, so as to block the leakage channel at the interface between the passivation layer and the epitaxial structure layer. By comparing the electrical characteristics between the first electrode and the second electrode of the semiconductor device in this application and the semiconductor device without the second through hole in the related art, the leakage of the passivation interface can be characterized. Therefore, the semiconductor device in this application can accurately determine the influence of the passivation layer, and takes a short time and is not easily affected by other factors.

[0112] When the semiconductor device is a HEMT device, please refer to Figure 8 , the semiconductor device preparation method includes:

[0113] Step S201: Prepare a substrate.

[0114] Step S202: Grow an epitaxial structure layer on the upper surface of the substrate.

[0115] As Figure 9 shown, the epitaxial structure layer 2 is grown on the upper surface of the substrate 1. In the direction away from the substrate 1, the epitaxial structure layer 2 includes a GaN layer 21, an AlGaN layer 22, and a GaN cap layer 23.

[0116] Step S203: Grow a protective layer on the upper surface of the epitaxial structure layer.

[0117] The protective layer 8 can be grown by the LPCVD method, and the material of the protective layer 8 can be silicon nitride.

[0118] As Figure 10 shown, the protective layer 8 is located on the upper surface of the epitaxial structure layer 2 and is in contact with the GaN cap layer.

[0119] Step S204: Under the protection of the protective layer, inject a first ion into the epitaxial structure layer and activate the first ion to form a heavily doped N-type semiconductor connected to the two-dimensional electron gas.

[0120] The heavily doped N-type semiconductor is beneficial to form a better ohmic contact.

[0121] The first ion can be a Si ion, and the activation method of the first ion can be high-temperature activation to form ion doping through activation.

[0122] As Figure 11 shown, the Si ion implantation region is below the source, drain ohmic, and scribe lane regions, and the source and drain ohmic regions are the regions corresponding to the first electrode 6.

[0123] It should be noted that when using a Ti / Al system metal high-temperature alloy to prepare an ohmic contact, it may not be necessary to implant and activate Si ions.

[0124] Step S205: Remove the protective layer.

[0125] The protective layer can be removed by etching.

[0126] Step S206: Grow a passivation layer on the upper surface of the epitaxial structure layer.

[0127] As Figure 12 shown, the passivation layer 3 is located on the upper surface of the epitaxial structure layer 2 and is in contact with the GaN cap layer 23.

[0128] Step S207: Inject a second ion into the region of the epitaxial structure layer corresponding to the passive region to destroy the two-dimensional electron gas in the passive region.

[0129] AsFigure 13 As shown, a second ion is implanted into the passive region of the device. The passive region is the area corresponding to outside the dashed box in the figure, so as to destroy the two-dimensional electron gas below and form an insulating region.

[0130] In the region where the second ion implantation is not performed, the two-dimensional electron gas below the dashed box is retained for preparing the active region of the device.

[0131] Step S208: Etch the passivation layer to form a first via hole.

[0132] Etch the passivation layer corresponding to the source and drain ohmic regions to form a first via hole.

[0133] Step S209: Prepare a first electrode in the first via hole.

[0134] By using the electron beam evaporation method, evaporate ohmic metal in the source and drain regions (inside the first via hole), and perform annealing to make the ohmic region and the semiconductor undergo an alloy reaction to form ohmic metal. The metal can be Ti / Al / Ni / Au, Ti / Al / Ti or Ti / Pt / Au / Ti, etc.

[0135] Step S210: Prepare a second electrode.

[0136] By using the electron beam evaporation method, evaporate gate metal. The gate can be NiAu, NiPbAu, etc., and perform annealing to form a MIS structure. The gate is located between the source electrode and the drain electrode.

[0137] Step S211: Etch the passivation layer between the second electrode and the first electrode to form a second via hole.

[0138] As Figure 4 shown, there is a second via hole 7 in the passivation layer 3 between the gate (second electrode 5) and the source electrode (the first electrode 6 on the left side of the gate), and between the gate (second electrode 5) and the drain electrode (the first electrode 6 on the right side of the gate).

[0139] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0140] The semiconductor device and its manufacturing method provided by the present application have been introduced in detail above. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate (1); An epitaxial structure layer (2) located on the upper surface of the substrate (1); a two-dimensional electron gas (4) is present in the epitaxial structure layer (2); the epitaxial structure layer includes a GaN cap layer; A passivation layer (3) located on the upper surface of the epitaxial structure layer (2); the passivation layer (3) has a first through-hole and a second through-hole (7) penetrating the thickness of the passivation layer (3); A second electrode (5) and a first electrode (6) located in the first through-hole, the second through-hole (7) is located between the second electrode (5) and the first electrode (6), and the second through-hole (7) is used to disconnect the passivation layer (3) between the first electrode (6) and the second electrode (5), blocking the leakage path at the interface between the passivation layer (3) and the epitaxial structure layer (2); During the process of etching the passivation layer (3) to form the second through-hole (7), at different etching depths until the leakage path at the interface of the epitaxial structure layer (2) is blocked, which is used to monitor the leakage situation at the interface of the passivation layer (3) and the leakage situation of the passivation layer (3) material; The number of the first electrodes (6) is two, the two first electrodes (6) are a source electrode and a drain electrode, the second electrode (5) is a gate electrode, the two first electrodes (6) are respectively located on both sides of the second electrode (5), and there is a second through-hole (7) between each first electrode (6) and the second electrode (5); Further comprising: A third through-hole, the third through-hole is located in the passivation layer (3) and penetrates the thickness of the passivation layer (3), the second electrode (5) is located in the third through-hole, and the side walls on both sides of the second electrode (5) are in contact with the passivation layer (3).

2. The semiconductor device according to claim 1, wherein, The epitaxial structure layer (2) includes a GaN / AlGaN stack, a GaN / AlN / AlGaN stack, a GaN / AlN / AlGaN / GaN stack.

3. A method for manufacturing a semiconductor device, characterized in that, Comprising: Prepare a substrate (1); Grow an epitaxial structure layer (2) on the upper surface of the substrate (1), and form a two-dimensional electron gas (4) in the epitaxial structure layer (2); the epitaxial structure layer includes a GaN cap layer; Grow a passivation layer (3) on the upper surface of the epitaxial structure layer (2); Etch the passivation layer (3) to form a first through-hole; Fabricate a first electrode (6) in the first through-hole; Fabricate a second electrode (5); Etch the passivation layer (3) between the second electrode (5) and the first electrode (6) to form a second through-hole (7), and the second through-hole (7) is used to disconnect the passivation layer (3) between the first electrode (6) and the second electrode (5), blocking the leakage path at the interface between the passivation layer (3) and the epitaxial structure layer (2); During the process of etching the passivation layer (3) to form the second through-hole (7), at different etching depths until the leakage path at the interface of the epitaxial structure layer (2) is blocked, which is used to monitor the leakage situation at the interface of the passivation layer (3) and the leakage situation of the passivation layer (3) material; The number of the first electrodes (6) is two. The two first electrodes (6) are a source electrode and a drain electrode. The second electrode (5) is a gate electrode. The two first electrodes (6) are respectively located on both sides of the second electrode (5), and there is a second through hole (7) between each first electrode (6) and the second electrode (5). The preparation of the second electrode (5) includes: etching the passivation layer (3) to form a third through hole; preparing the second electrode (5) in the third through hole, and the side wall of the second electrode (5) is in contact with the passivation layer (3).

4. The method for manufacturing a semiconductor device according to claim 3, wherein, Forming a two-dimensional electron gas (4) in the epitaxial structure layer (2) includes: Growing a protective layer (8) on the upper surface of the epitaxial structure layer (2); Under the protection of the protective layer (8), injecting a first ion into the epitaxial structure layer (2) and activating the first ion to form a heavily doped N-type semiconductor connected to the two-dimensional electron gas (4); Removing the protective layer (8); After growing the passivation layer (3) on the upper surface of the epitaxial structure layer (2), it further includes: Injecting a second ion into the region of the epitaxial structure layer (2) corresponding to the passive region to destroy the two-dimensional electron gas (4) in the passive region.

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