Package substrate and manufacturing method thereof

Abstract

A packaging substrate and its manufacturing method include forming a first circuit structure on a core board, and then forming a second circuit structure on the first circuit structure, and using ABF material to make a second insulating layer of the second circuit structure. The second insulating layer of the second circuit structure is different from the forming material of the first insulating layer of the first circuit structure. Therefore, the second insulating layer of the ABF material can form a second circuit layer with fine circuits / fine pitches, thereby achieving the purpose of multi-layer fine circuits.

Description

Technical Field

[0001] The present invention relates to a packaging substrate for carrying a chip, and in particular to a packaging substrate with ABF and a manufacturing method thereof. Background Art

[0002] Current chip packaging technologies include chip scale packaging (CSP), direct chip attach (DCA), and multi-chip module (MCM). As the functional requirements of end products increase, semiconductor chips need to have more input / output (I / O) contacts, resulting in a corresponding increase in the number of external pads on the package substrate used to support the semiconductor chip.

[0003] Figure 1 FIG is a cross-sectional view of an existing packaging substrate 1. Figure 1 As shown, the packaging substrate 1 includes a core board body 10, which has a first side 10a and a second side 10b opposite to each other, and the first side 10a and the second side 10b of the core board body 10 are formed with a circuit structure 11, wherein the circuit structure includes multiple insulating layers 111 and multiple circuit layers 110 formed on each of the insulating layers 111, and the core board body 10 has multiple conductive through-holes 100 connecting the first side 10a and the second side 10b to electrically connect the circuit layers 110.

[0004] Currently, the circuit structure 11 is manufactured using a conventional build-up process to perform wiring on a prepreg (PP) material with glass fiber, thereby forming a symmetrical packaging substrate 1 .

[0005] However, in the conventional package substrate 1 , it is difficult to form a fine circuit / fine pitch circuit layer 110 using PP material with glass fiber as the insulating layer 111 . Therefore, the package substrate 1 cannot meet the requirements of multi-layer fine circuits, resulting in limited functional development of electronic products.

[0006] Therefore, how to overcome the problems of the above-mentioned existing methods has become a topic that needs to be solved urgently. Summary of the Invention

[0007] In view of the above-mentioned deficiencies of the prior art, the present invention provides a packaging substrate and a method for manufacturing the same, which can at least partially solve the problems of the prior art.

[0008] The packaging substrate of the present invention includes: a core board body having a first side and a second side opposite to each other, and at least one conductive through-hole connecting the first side and the second side; a first circuit structure, which is arranged on the first side of the core board body, wherein the first circuit structure includes at least one first insulating layer formed on the core board body and a first circuit layer arranged on the first insulating layer and electrically connected to the conductive through-hole; and a second circuit structure, which is arranged on the first circuit structure, wherein the second circuit structure includes at least one second insulating layer formed on the first insulating layer and a second circuit layer arranged on the second insulating layer and electrically connected to the first circuit layer, and the material forming the second insulating layer is Ajinomoto build-up film, which is different from the material forming the first insulating layer.

[0009] The present invention also provides a method for manufacturing a packaging substrate, comprising: providing a core board having a first side and a second side relative to each other; forming a first circuit structure on the first side of the core board, wherein the first circuit structure includes at least one first insulating layer formed on the core board and a first circuit layer disposed on the first insulating layer, and the core board has at least one conductive through-hole connecting the first side and the second side to electrically connect the first circuit layer; and forming a second circuit structure on the first circuit structure, wherein the second circuit structure includes at least one second insulating layer formed on the first insulating layer and a second circuit layer disposed on the second insulating layer and electrically connected to the first circuit layer, and the material forming the second insulating layer is an Ajinomoto build-up film, which is different from the material forming the first insulating layer.

[0010] In the aforementioned packaging substrate and its manufacturing method, the first circuit structure further includes a plurality of first conductive blind vias disposed in the first insulating layer and electrically connected to the first circuit layer.

[0011] In the aforementioned packaging substrate and manufacturing method thereof, the conductive via extends into the first circuit structure to electrically connect the first circuit layer.

[0012] In the aforementioned packaging substrate and its manufacturing method, the first circuit structure is also formed on the second side of the core board. Further, the second circuit structure is also formed on the first circuit structure on the second side of the core board.

[0013] As can be seen from the above, the packaging substrate and its manufacturing method of the present invention primarily utilize different materials for the first and second insulating layers. The PP first insulating layer provides excellent rigidity and dimensional stability, while the ABF second insulating layer enables the formation of a second circuit layer with fine circuits and fine pitches. Therefore, compared to the prior art, the packaging substrate can achieve the goals of multi-layer fine circuits, thinness, and no warping. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A cross-sectional view of a conventional packaging substrate.

[0015] Figures 2A to 2F FIG. 1 is a cross-sectional view of a first embodiment of a method for manufacturing a package substrate according to the present invention.

[0016] Figures 3A to 3E FIG. 1 is a cross-sectional view of a second embodiment of a method for manufacturing a package substrate according to the present invention.

[0017] Figures 4A to 4D It is a cross-sectional schematic diagram of a third embodiment of the method for manufacturing a package substrate of the present invention.

[0018] 5A to 5D It is a cross-sectional schematic diagram of a fourth embodiment of a method for manufacturing a package substrate of the present invention.

[0019] Figures 6A to 6E It is a cross-sectional schematic diagram of a fifth embodiment of a method for manufacturing a package substrate of the present invention.

[0020] The description of the accompanying drawings is as follows:

[0021] 1, 2, 3, 4, 5, 6 package substrates

[0022] 10, 20 core board

[0023] 10a, 20a first side

[0024] 10b, 20b second side

[0025] 100, 200, 300 conductive through holes

[0026] 11 Line structure

[0027] 110 circuit layer

[0028] 111 insulation layer

[0029] 2a, 3a, 6a core structures

[0030] 200a plug material

[0031] 201, 202 inner circuit layer

[0032] 21a, 21b, 31a, 31b, 61 first line structure

[0033] 210 first circuit layer

[0034] 211 first insulating layer

[0035] 2110 first opening

[0036] 212 first conductive blind hole

[0037] 22a, 22b, 42, 52, 62 second line structure

[0038] 220 second circuit layer

[0039] 221 second insulation layer

[0040] 2210 second opening

[0041] 220 second conductive blind hole

[0042] 30 piercings

[0043] 40 first support plate

[0044] 41 second support plate

[0045] 9 bearing parts

[0046] 9a first surface

[0047] 9b Second surface

[0048] 90 plate body

[0049] 91 copper foil

[0050] 92 peeling layer

[0051] d0, d1 thickness. DETAILED DESCRIPTION

[0052] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0053] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those familiar with this technology, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0054] Figures 2A to 2F FIG. 1 is a cross-sectional view of a first embodiment of a method for manufacturing a package substrate 2 according to the present invention.

[0055] like Figure 2AAs shown, a core board 20 is provided, which has a first side 20a and a second side 20b relative to each other, and inner circuit layers 201 and 202 are arranged on the first side 20a and the second side 20b of the core board 20, and the core board 20 has a plurality of conductive through holes 200 connecting the first side 20a and the second side 20b, so that the conductive through holes 200 are electrically connected to the inner circuit layers 201 and 202.

[0056] In this embodiment, the core board 20 can be an organic polymer board including bismaleimide triazine (BT), glass fiber prepreg (PP), or other board materials. The conductive vias 200 are hollow columns that can be filled with plugging material 200a. The plugging material 200a can be made of a variety of materials, such as conductive adhesives and inks, and is not particularly limited. It should be understood that in other embodiments, the conductive vias 200 can also be solid metal columns without being filled with plugging material 200a.

[0057] like Figure 2B As shown, a first insulating layer 211 is formed on the first side 20a and the second side 20b of the core board 20, for example, by laminating the first insulating layer 211, so that the inner circuit layers 201 and 202 are embedded in the first insulating layer 211. Then, a plurality of first openings 2110 are formed on each of the first insulating layers 211, such as by laser or other means, so that part of the surface of the inner circuit layers 201 and 202 is exposed in the first openings 2110.

[0058] In this embodiment, each of the first insulating layers 211 is a dielectric layer, such as polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP), or other dielectric materials.

[0059] like Figure 2C As shown, a patterning process is performed to form a first circuit layer 210 on each of the first insulating layers 211 , and a plurality of first conductive blind vias 212 electrically connecting the inner circuit layers 201 , 202 and the first circuit layer 210 are formed in the first openings 2110 .

[0060] In this embodiment, a build-up process is used to fabricate the first wiring layer 210, the first conductive blind vias 212, and the first insulating layer 211. These first wiring layer 210, the first conductive blind vias 212, and the first insulating layer 211 serve as first wiring structures 21a and 21b, respectively. The core board 20 and the first wiring structures 21a and 21b on its first and second sides 20a and 20b serve as a core structure 2a. For example, the first wiring layer 210 and the first conductive blind vias 212 may be integrally formed using electroplating metal (e.g., copper) or other methods.

[0061] It should be understood that, by using a build-up method, the first circuit structures 21 a and 21 b can be further provided with multiple layers of the first insulating layer 211 as needed to manufacture a multi-layer first circuit layer 210 .

[0062] like Figures 2D to 2F As shown, a second circuit structure 22 a , 22 b is formed on the first circuit structures 21 a , 21 b on two opposite sides of the core structure 2 a , respectively, to form a symmetrical packaging substrate 2 .

[0063] In this embodiment, each of the second circuit structures 22a and 22b includes at least one second insulating layer 221 formed on the first insulating layer 211, a second circuit layer 220 formed on the second insulating layer 221, and a plurality of second conductive blind vias 222 formed in the second insulating layer 221, such that the second conductive blind vias 222 electrically connect the second circuit layer 220 with the first circuit layer 210. For example, the second circuit structures 22a and 22b are fabricated using a build-up method to form a plurality of second openings 2210 in the second insulating layer 221, exposing the first circuit layer 210. Therefore, when the second circuit layer 220 is formed on the second insulating layer 221 by electroplating, the second conductive blind vias 222 are also formed in the second openings 2210 by electroplating.

[0064] Furthermore, the material forming the second insulating layer 221 is different from the material forming the first insulating layer 211. For example, the material forming the second insulating layer 221 is Ajinomoto build-up film (ABF), while the material forming the first insulating layer 211 is prepreg (PP). Therefore, the coefficient of thermal expansion (CTE) of the second insulating layer 221 is lower than the CTE of the first insulating layer 211. Furthermore, the thickness of the second insulating layer 221 is also lower than that of the first insulating layer 211. Even more, the thickness of the second wiring layer 220 is different from the thickness of the first wiring layer 210.

[0065] Furthermore, the two opposing sides of the package substrate 2 have different uses, resulting in different residual copper rates for the second circuit structures 22a and 22b. For example, the second circuit structure 22a corresponding to the first side 20a serves as the die-stack side (not shown) for receiving semiconductor chips, while the second circuit structure 22b corresponding to the second side 20b serves as the ball-bumping side (not shown) for receiving circuit boards. Therefore, the wiring density on the die-stack side is higher than that on the ball-bumping side. Consequently, the residual copper rate of the outermost second circuit layer 220 of the second circuit structure 22a on the die-stack side is higher than the residual copper rate of the outermost second circuit layer 220 of the second circuit structure 22b on the ball-bumping side.

[0066] Therefore, the manufacturing method of the present invention performs related operations in a symmetrical manner in the upper and lower sides during the manufacturing process. Therefore, even if dielectric materials with different materials or different CTEs are used for the build-up operation, the material combination and symmetrical build-up method can still be used to reduce the warping of the packaging substrate 2 during the manufacturing process. When the semiconductor chip (not shown) is connected to the packaging substrate 2 in the subsequent manufacturing process, the two can be effectively bonded, thereby improving the process yield.

[0067] Furthermore, a PP material with glass fiber (first insulating layer 211) is formed on the core board 20 to provide good rigidity and dimensional stability, and a Flip Chip Ball Grid Array (FCBGA) type package substrate 2 with multi-layer wiring specifications can be manufactured in a symmetrical manner. Therefore, even if the copper plating area (or residual copper rate) and copper thickness of each layer of wiring (the first and second circuit layers 210 and 220) are different, warping can still be avoided.

[0068] In addition, by using a glass-free interlayer material as a build-up layer material (such as ABF), without the limitation of glass fiber, it is advantageous to form a smaller laser opening (second opening 2210) or smaller fine line / fine pitch (L / S) wiring (second circuit layer 220), and it is advantageous to form a thinner second circuit structure 22a, 22b (second insulating layer 221 or second circuit layer 220), so as to achieve the purpose of thinning the entire packaging substrate 2. Therefore, the packaging substrate 2 can realize multi-layer fine circuits and a thin design.

[0069] Figures 3A to 3E 1 is a cross-sectional view of a second embodiment of the method for manufacturing the package substrate 3 of the present invention. The difference between this embodiment and the first embodiment lies in the process of manufacturing the conductive via 300. The other processes are substantially the same, so the similarities will not be described again.

[0070] like Figure 3A As shown, a core board 20 is provided, which has a first side 20 a and a second side 20 b opposite to each other, and inner circuit layers 201 and 202 are arranged on the first side 20 a and the second side 20 b of the core board 20 .

[0071] like Figure 3B As shown, the inner circuit layers 201 and 202 are respectively formed on the first side 20 a and the second side 20 b of the core board 20 . For example, the first insulating layer 211 is pressed together so that the inner circuit layers 201 and 202 are embedded in the first insulating layer 211 .

[0072] like Figure 3C As shown, a plurality of through holes 30 are formed penetrating the core board 20 and each of the first insulating layers 211 .

[0073] In this embodiment, the through holes 30 pass through portions of the inner circuit layers 201 and 202 on the first side 20 a and the second side 20 b of the core board 20 .

[0074] like Figure 3D As shown, a first circuit layer 210 is formed on each of the first insulating layers 211 , and conductive vias 300 electrically connecting the inner circuit layers 201 , 202 and the first circuit layer 210 are formed in the through holes 30 .

[0075] In this embodiment, the opposite ends of the conductive through-holes 300 replace the first conductive blind hole 212, so that the first circuit layer 210 and the first insulating layer 211 serve as the first circuit structures 31a, 31b, and the core board 20 and the first circuit structures 31a, 31b on the first side 20a and the second side 20b serve as a core structure 3a.

[0076] like Figure 3E As shown, a second circuit structure 22 a , 22 b is formed on the first circuit structures 31 a , 31 b on two opposite sides of the core structure 3 a , respectively, to form a symmetrical packaging substrate 3 .

[0077] Therefore, the manufacturing method of the present invention performs related operations in a symmetrical manner in the upper and lower sides during the process. Therefore, even if dielectric materials with different materials or different CTEs are used for the build-up operation, the material combination and symmetrical build-up method can still be used to reduce the warping of the packaging substrate 3 during the manufacturing process. When the semiconductor chip (not shown) is connected to the packaging substrate 3 in the subsequent process, the two can be effectively bonded, thereby improving the process yield.

[0078] Furthermore, a PP material with glass fiber (first insulating layer 211) is formed on the BT material core board 20 to provide good rigidity and dimensional stability. In addition, a Flip Chip Ball Grid Array (FCBGA) type package substrate 2 with multi-layer wiring specifications can be manufactured in a symmetrical manner. Therefore, even if the copper plating area (or residual copper rate) and copper thickness of each layer of wiring (the first and second circuit layers 210 and 220) are different, warping can still be avoided.

[0079] In addition, by using a glass-free interlayer material as a build-up layer material (such as ABF), without the limitation of glass fiber, it is advantageous to form a smaller laser opening (second opening 2210) or smaller fine line / fine pitch (L / S) wiring (second circuit layer 220), and it is advantageous to form a thinner second circuit structure 22a, 22b (second insulating layer 221 or second circuit layer 220), so as to achieve the purpose of thinning the entire packaging substrate 3. Therefore, the packaging substrate 3 can realize multi-layer fine circuits and a thin design.

[0080] Figures 4A to 4D 1 is a cross-sectional view of a third embodiment of the present invention's method for manufacturing a package substrate 4. The difference between this embodiment and the first embodiment lies in the process of manufacturing the second circuit structure 42. The other processes are substantially the same, so the similarities will not be described again.

[0081] like Figure 4A As shown, provide Figure 2D The core structure 2a is shown.

[0082] like Figure 4B As shown, a first support plate 40 is formed on the first circuit structure 21b on one side (such as the second side 20b) of the core structure 2a, and a second circuit structure 42 is formed on the first circuit structure 21a on the other side (such as the first side 20a) of the core structure 2a.

[0083] In this embodiment, the second circuit structure 42 includes at least one second insulating layer 221, a second circuit layer 220 formed on the second insulating layer 221, and a plurality of second conductive blind vias 222 formed in the second insulating layer 221, such that the second conductive blind vias 222 electrically connect the second circuit layer 220 with the first circuit layer 210. For example, the second circuit structure 42 can be fabricated using a build-up method. Therefore, the second insulating layer 221 and the first support plate 40 can be simultaneously laminated onto the first side 20a and the second side 20b of the core structure 2a, and then the second circuit layer 220 and the second conductive blind vias 222 can be fabricated.

[0084] Furthermore, multiple layers of the second circuit layer 220 can be formed as required, such as Figure 4C As shown, before adding a second wiring layer 220, another second insulating layer 221 and a second support plate 41 can be laminated onto the first side 20a and the second side 20b of the core structure 2a, respectively, to balance the stress on the opposite sides of the core structure 2a and prevent the core structure 2a from warping during the manufacturing process. Furthermore, the thicknesses of the support plates can be different, such as the thickness d1 of the second support plate 41 located on the outside being greater than the thickness d0 of the first support plate 40 located on the inside, to help suppress warping.

[0085] In addition, the first and second support plates 40 and 41 may be made of epoxy, PI, FR4, metal or other recyclable materials with rigid support.

[0086] like Figure 4D As shown, the first support plate 40 and the second support plate 41 are removed to obtain an asymmetric packaging substrate 4 .

[0087] Therefore, the manufacturing method of the present invention utilizes the design of the first and second support plates 40 and 41 to avoid the warping problem caused by the asymmetric structure during the pressing process of the second insulating layer 221 .

[0088] Furthermore, PP material with glass fiber is used as the material of the core structure 2a to have the stability and thermal stability to maintain the predetermined size, and is matched with a dielectric layer without glass fiber (second insulating layer 221) as a build-up layer material (such as ABF) to facilitate the wiring process of fine lines and micro-holes (second circuit layer 220), so that the packaging substrate 4 can realize multi-layer fine lines and thin design.

[0089] In addition, the first and second support plates 40 and 41 made of recyclable materials of corresponding thickness are used as support members to avoid warpage during the process, thereby eliminating the need for traditional extremely thick temporary carriers (such as copper foil substrates), thereby significantly saving material costs.

[0090] 5A to 5D 1 is a cross-sectional view of a fourth embodiment of the present invention for manufacturing a package substrate 4. The difference between this embodiment and the fourth embodiment lies in the production method. The other processes are substantially the same, so the similarities will not be described again.

[0091] like Figure 5A As shown, a carrier 9 and a plurality of Figure 2D In the core structure 2 a shown, the carrier 9 has a first surface 9 a and a second surface 9 b that are opposite to each other.

[0092] In this embodiment, the carrier 9 is a temporary carrier, and its plate body 90 can be a copper foil substrate or other plate material. For example, the carrier 9 is a copper foil substrate, which includes copper foil 91, and a release layer 92 such as a dielectric layer can be provided on the copper foil 91 as required.

[0093] like Figure 5B As shown, the core structures 2a are symmetrically formed on the first surface 9a and the second surface 9b of the carrier 9 by pressing, so that the first circuit structure 21b of the second side 20b of the core structure 2a is combined with the peeling layer 92, and the first circuit structure 21a of the first side 20a of the core structure 2a faces outward.

[0094] In this embodiment, the peeling layer 92 covers the first circuit layer 210 of the first circuit structure 21 b on the second side 20 b , so that the first circuit layer 210 of the first circuit structure 21 b on the second side 20 b is embedded in the peeling layer 92 .

[0095] like Figure 5C As shown, a second circuit structure 52 is formed on each of the first circuit structures 21 a on the first side 20 a of the core structure 2 a .

[0096] In this embodiment, the second circuit layer 220, the second conductive blind via 222 and the second insulating layer 221 serve as the second circuit structure 52, so that the second circuit structure 52 is similar to Figure 4C For example, the second circuit structure 52 is manufactured by a build-up method, so the second insulating layers 221 are first pressed onto the first side 20a and the second side 20b of the core structure 2a, and then the second circuit layer 220 and the second conductive blind via 222 are manufactured.

[0097] like Figure 5D As shown, the carrier 9 is removed to obtain a plurality of packaging substrates 5, the structure of which is as shown in FIG. Figure 4D The asymmetric packaging substrate 4 is shown.

[0098] Therefore, the manufacturing method of the present invention avoids the warping problem caused by the asymmetric structure by simultaneously pressing the second insulating layer 221 on the opposite sides of the carrier 9.

[0099] Furthermore, by using the carrier 9 , during the process of manufacturing the package substrate 5 , related operations can be performed on the first surface 9 a and the second surface 9 b of the carrier 9 simultaneously, thereby improving productivity.

[0100] In addition, PP material with glass fiber is used as the material of the core structure 2a to have the stability and thermal stability to maintain the predetermined size, and is matched with a dielectric layer without glass fiber (second insulating layer 221) as a build-up layer material (such as ABF) to facilitate the wiring process of fine lines and micro-holes (second wiring layer 220). Therefore, the packaging substrate 5 can realize multi-layer fine lines and thin design.

[0101] Figures 6A to 6E 1 is a cross-sectional view of a fifth embodiment of the present invention's method for manufacturing a package substrate 6. The difference between this embodiment and the fourth embodiment lies in the lamination process, and the other processes are substantially the same, so the similarities will not be described again.

[0102] like Figure 6A As shown, a carrier 9 and a plurality of Figure 2A The core plate 20 is shown.

[0103] like Figure 6BAs shown, the core board 2 and the core boards 20 are symmetrically formed on the first surface 9a and the second surface 9b of the carrier 9 by pressing, so that the core board 20 is combined with the peeling layer 92 with its second side 20b and the first side 20a of the core board 20 faces outward.

[0104] In this embodiment, the peeling layer 92 covers the inner circuit layer 202 on the second side 20 b of the core board 20 , so that the inner circuit layer 202 is embedded in the peeling layer 92 .

[0105] like Figure 6C As shown, a first circuit structure 61 is formed on the first side 20 a of each core board 20 .

[0106] In this embodiment, the first circuit layer 210, the first conductive blind via 212 and the first insulating layer 211 serve as the first circuit structure 61, so that the first circuit structure 61 is similar to Figure 2C The first circuit structure 21 a shown in FIG. 1 is used to make the core board 20 and the first circuit structure 61 on the first side 20 a thereof serve as a core structure 6 a .

[0107] like Figure 6D As shown, a second circuit structure 62 is formed on the first circuit structure 61 of each core structure 6a.

[0108] In this embodiment, the second circuit layer 220, the second conductive blind via 222 and the second insulating layer 221 serve as the second circuit structure 62, so that the second circuit structure 62 is similar to Figure 2F The second circuit structure 22a is shown.

[0109] like Figure 6E As shown, the carrier 9 is removed to obtain a plurality of asymmetric package substrates 6 , and the inner circuit layer 202 of the second side 20 b of the core board 20 is exposed.

[0110] Therefore, the manufacturing method of the present invention avoids the warping problem caused by the asymmetric structure by simultaneously pressing the second insulating layer 221 on the opposite sides of the carrier 9.

[0111] Furthermore, by using the carrier 9 , during the process of manufacturing the package substrate 6 , related operations can be performed on the first surface 9 a and the second surface 9 b of the carrier 9 simultaneously, thereby improving productivity.

[0112] In addition, PP material with glass fiber is used as the material of the core board 20 and the first insulating layer 211 to have the stability and thermal stability to maintain the predetermined size, and is matched with a dielectric layer without glass fiber (second insulating layer 221) as a build-up layer material (such as ABF) to facilitate the wiring process of fine lines and micro-holes (second line layer 220), so that the packaging substrate 6 can realize multi-layer fine lines and thin design.

[0113] On the other hand, it can be seen from the third to fifth embodiments that the package substrates 4 , 5 , 6 of the present invention have a high degree of design freedom and can arbitrarily combine circuit structures of various wiring specifications according to requirements.

[0114] The present invention also provides a packaging substrate 2, 3, 4, 5, 6, including: a core board 20 having a first side 20a and a second side 20b opposite to each other; a first circuit structure 21a, 31a, 61 arranged on the first side 20a of the core board 20; and a second circuit structure 22a, 42, 52, 62 arranged on the first circuit structure 21a, 31a, 61.

[0115] The core board 20 has at least one conductive through hole 200 , 300 connecting the first side 20 a and the second side 20 b .

[0116] The first circuit structure 21 a , 31 a , 61 includes at least one first insulating layer 211 formed on the core board 20 and a first circuit layer 210 disposed on the first insulating layer 211 and electrically connected to the conductive vias 200 , 300 .

[0117] The second circuit structure 22a, 42, 52, 62 includes at least one second insulating layer 221 formed on the first insulating layer 211 and a second circuit layer 220 provided on the second insulating layer 221 and electrically connected to the first circuit layer 210, and the material forming the second insulating layer 220 is Ajinomoto build-up film, which is different from the material forming the first insulating layer 210.

[0118] In one embodiment, the first circuit structure 21 a , 61 further includes a plurality of first conductive blind vias 212 disposed in the first insulating layer 211 and electrically connected to the first circuit layer 210 .

[0119] In one embodiment, the conductive via 300 extends into the first circuit structure 21 to electrically connect the first circuit layer 210 .

[0120] In one embodiment, the first circuit structures 21b, 31b are further disposed on the second side 20b of the core board 20. Furthermore, the second circuit structure 22b is further disposed on the first circuit structures 21b, 31b on the second side 20b of the core board 20 to form symmetrical package substrates 2, 3.

[0121] In summary, the package substrate and its manufacturing method of the present invention utilize different materials for the first and second insulating layers. The PP first insulating layer provides excellent rigidity and dimensional stability, while the ABF second insulating layer enables the formation of a second circuit layer with fine circuits and fine pitches. Therefore, compared to the prior art, the package substrate can achieve the goals of multi-layer fine circuits, thinness, and no warping.

[0122] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. A packaging substrate, comprising: A core board having a first side and a second side opposite to each other, and at least one conductive through hole connecting the first side and the second side; a first circuit structure disposed on the first and second sides of the core board, wherein the first circuit structure comprises at least a first insulating layer formed on the core board and a first circuit layer disposed on the first insulating layer and electrically connected to the conductive via; and A second circuit structure is provided on the first circuit structure, wherein the second circuit structure includes at least one second insulating layer formed on the first insulating layer and a second circuit layer provided on the second insulating layer and electrically connected to the first circuit layer, wherein the second insulating layer is formed of a glutinous rice flour build-up film and the first insulating layer is formed of a prepreg material, so that the thermal expansion coefficient of the second insulating layer is smaller than the thermal expansion coefficient of the first insulating layer. The lines / spacing of the second circuit layer are smaller than the lines / spacing of the first circuit layer; and Among them, the second circuit structure corresponding to the first side serves as the die placement side, and the second circuit structure corresponding to the second side serves as the ball implantation side, and the residual copper rate of the outermost second circuit layer of the second circuit structure on the die placement side is greater than the residual copper rate of the outermost second circuit layer of the second circuit structure on the ball implantation side.

2. The packaging substrate according to claim 1, wherein: The first circuit structure further includes a plurality of first conductive blind vias disposed in the first insulating layer and electrically connected to the first circuit layer.

3. The packaging substrate according to claim 1, wherein: The conductive via extends into the first circuit structure to electrically connect the first circuit layer.

4. A method for manufacturing a packaging substrate, comprising: Providing a core plate having a first side and a second side opposite to each other; forming a first circuit structure on a first side and a second side of the core board, wherein the first circuit structure comprises at least one first insulating layer formed on the core board and a first circuit layer disposed on the first insulating layer, and the core board has at least one conductive through hole connecting the first side and the second side to electrically connect the first circuit layer; and A second circuit structure is formed on the first circuit structure, wherein the second circuit structure includes at least one second insulating layer formed on the first insulating layer and a second circuit layer provided on the second insulating layer and electrically connected to the first circuit layer, wherein the second insulating layer is formed of a build-up film and the first insulating layer is formed of a prepreg material, so that the thermal expansion coefficient of the second insulating layer is smaller than the thermal expansion coefficient of the first insulating layer. The lines / spacing of the second circuit layer are smaller than the lines / spacing of the first circuit layer; and Among them, the second circuit structure corresponding to the first side serves as the die placement side, and the second circuit structure corresponding to the second side serves as the ball implantation side, and the residual copper rate of the outermost second circuit layer of the second circuit structure on the die placement side is greater than the residual copper rate of the outermost second circuit layer of the second circuit structure on the ball implantation side.

5. The method for manufacturing a package substrate according to claim 4, wherein: The first circuit structure further includes a plurality of first conductive blind vias disposed in the first insulating layer and electrically connected to the first circuit layer.

6. The method for manufacturing a package substrate according to claim 4, wherein: The conductive via extends into the first circuit structure to electrically connect the first circuit layer.

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