A semiconductor device and its fabrication method

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes a substrate; an epitaxial structure located on one side of the substrate; and a plurality of gates located on the side of the epitaxial structure away from the substrate. The gates extend along a first direction, and the plurality of gates are arranged along a second direction. The first direction and the second direction intersect and are both parallel to the plane of the substrate. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on the side of the second gate closer to the edge of the semiconductor device. The highest temperature of the first gate is T1, and the highest temperature of the second gate is T2, wherein (T2-T1) / T1≤20%. Using the above technical solution, the temperature of the semiconductor device can be uniformly distributed, which can reduce the degradation of the device's radio frequency performance and improve the output power.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] GaN (gallium nitride) semiconductor devices have significant advantages such as large bandgap, high electron mobility, high breakdown field strength, and high temperature resistance. Compared with first-generation semiconductor silicon and second-generation semiconductor gallium arsenide, they are more suitable for manufacturing high-temperature, high-voltage, high-frequency, and high-power electronic devices, and have broad application prospects. They can be widely used in the fields of radio frequency microwave and power electronics, and have become a research hotspot in the semiconductor industry.

[0003] Currently, 5G communication places increasingly higher demands on the bandwidth and operating frequency of semiconductor chips. Gallium nitride high electron mobility transistors (GaN high electron mobility transistors) are high electron mobility devices formed by the two-dimensional electron gas at the AlGaN / GaN heterojunction. They can be better applied to high-frequency, high-voltage, and high-power fields, and are naturally favored by the 5G communication field.

[0004] For gallium nitride (GaN) RF power amplifiers, improving device power and RF performance has always been a primary goal. However, in the design and use of semiconductor devices, numerous factors influence output power, RF performance, and reliability. For example, uneven temperature distribution within the device can lead to high heat generation and low reliability, consequently affecting output power and reliability. Therefore, achieving uniform temperature distribution within semiconductor devices is a crucial technology in their design. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a semiconductor device and a method for fabricating the same, so as to achieve uniform temperature distribution in the semiconductor device, reduce the degradation of the device's radio frequency performance, and improve the output power.

[0006] In a first aspect, embodiments of the present invention provide a semiconductor device, comprising:

[0007] Substrate;

[0008] An epitaxial structure located on one side of the substrate;

[0009] A plurality of gates are located on the side of the epitaxial structure away from the substrate, the gates extending along a first direction and the plurality of gates arranged along a second direction; the first direction and the second direction intersect and are both parallel to the plane of the substrate;

[0010] The plurality of gates includes a first gate and a second gate, wherein along the second direction, the first gate is located on the side of the second gate closer to the edge of the semiconductor device; the highest temperature of the first gate is T1, the highest temperature of the second gate is T2, wherein (T2-T1) / T1≤20%.

[0011] Optionally, the semiconductor device further includes a plurality of sources located on the side of the epitaxial structure away from the substrate, the sources extending along the first direction and the plurality of sources arranged along the second direction;

[0012] The plurality of sources include a first source and a second source. Along the second direction, the first source is disposed adjacent to the first gate, the second source is disposed adjacent to the second gate, and the first source is located on the side of the second source closer to the edge of the semiconductor device.

[0013] The semiconductor device further includes vias penetrating the substrate and the epitaxial structure. The vias include a first type of via and a second type of via. Along the thickness direction of the semiconductor device, the first source electrode overlaps with the first type of via, and the second source electrode overlaps with the second type of via.

[0014] The total opening area of ​​the first type of through holes is greater than the total opening area of ​​the second type of through holes.

[0015] Optionally, the first type of through hole includes at least one first through hole, and the second type of through hole includes at least one second through hole;

[0016] The opening area of ​​the first through hole is larger than the opening area of ​​the second through hole.

[0017] Optionally, along the second direction, the first via is located on the side of any other via closer to the edge of the semiconductor device, and the second via is located on the side of any other via closer to the center of the semiconductor device;

[0018] Along the direction from the first through hole to the second through hole, the opening area of ​​the through hole gradually decreases.

[0019] Optionally, along the second direction, the first via is located on the side of any other via closer to the edge of the semiconductor device, and the second via is located on the side of any other via closer to the center of the semiconductor device;

[0020] The opening area of ​​the first through hole is S1, and the opening area of ​​the second through hole is S2, where S2 < S1 ≤ 4 * S2.

[0021] Optionally, the first type of through hole includes at least two first through holes, and the second type of through hole includes at least one second through hole;

[0022] The number of the first through holes is greater than the number of the second through holes.

[0023] Optionally, along the second direction, the first via is located on the side of any other via closer to the edge of the semiconductor device, and the second via is located on the side of any other via closer to the center of the semiconductor device;

[0024] The number of through holes gradually decreases along the direction from the first through hole to the second through hole.

[0025] Optionally, along the second direction, the first via is located on the side of any other via closer to the edge of the semiconductor device, and the second via is located on the side of any other via closer to the center of the semiconductor device;

[0026] The number of first through holes in the first type is n1, and the number of second through holes in the second type is n2, where n1-n2≤5.

[0027] Optionally, the semiconductor device further includes a plurality of sources located on the side of the epitaxial structure away from the substrate, the sources extending along the first direction and the plurality of sources arranged along the second direction;

[0028] The plurality of sources include a first source and a second source. Along the second direction, the first source is disposed adjacent to the first gate, the second source is disposed adjacent to the second gate, and the first source is located on the side of the second source closer to the edge of the semiconductor device.

[0029] The semiconductor device further includes vias penetrating the substrate and the epitaxial structure. The vias include a first type of via and a second type of via. Along the thickness direction of the semiconductor device, the first source electrode overlaps with the first type of via, and the second source electrode overlaps with the second type of via.

[0030] Along the first direction, the center of the first type of via is located on the side of the center of the second type of via closer to the center of the semiconductor device.

[0031] Optionally, along the second direction, there is a gate spacing between two adjacent gates;

[0032] The plurality of gate pitches include a first gate pitch along the second direction near the edge of the semiconductor device and a second gate pitch located on the side of the first gate pitch away from the edge of the semiconductor device;

[0033] Along the second direction, the first gate spacing is smaller than the second gate spacing.

[0034] Optionally, the second gate pitch is located on the side of any other gate pitch closer to the center of the semiconductor device;

[0035] The gate spacing gradually increases along one side from the first gate spacing to the second gate spacing.

[0036] Secondly, embodiments of the present invention also provide a method for fabricating a semiconductor device, comprising:

[0037] Provide substrate;

[0038] An epitaxial structure is fabricated on one side of the substrate;

[0039] A plurality of gates are fabricated on the side of the epitaxial structure away from the substrate. The gates extend along a first direction and are arranged along a second direction. The first direction and the second direction intersect and are both parallel to the plane of the substrate. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on the side of the second gate closer to the edge of the semiconductor device. The highest temperature of the first gate is T1, and the highest temperature of the second gate is T2, wherein (T2-T1) / T1≤20%.

[0040] The semiconductor device provided in this embodiment of the invention provides a plurality of gates on the side of the epitaxial structure away from the substrate, and the first gate of the plurality of gates is located on the side of the second gate close to the edge of the semiconductor device. By making the highest temperature T1 of the first gate and the highest temperature T2 of the second gate satisfy (T2-T1) / T1≤20%, the temperature difference between the gates can be kept small, thereby making the temperature of the semiconductor device uniformly distributed, reducing the degradation of the device's radio frequency performance and improving the output power. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0042] Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line A-A';

[0043] Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line B-B';

[0044] Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0048] Figure 8 This is a schematic diagram of the semiconductor device fabrication method provided in the embodiments of the present invention. Detailed Implementation

[0049] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0050] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a substrate 110; an epitaxial structure 120 located on one side of the substrate 110; and a plurality of gates 130 located on the side of the epitaxial structure 120 away from the substrate 110, the gates 130 being aligned along a first direction (e.g., ...). Figure 1 Extending in the X direction shown, a plurality of gates 130 extend along a second direction (as shown in the figure). Figure 1 The first direction X and the second direction Y are arranged in the Y direction shown in the figure; the first direction X and the second direction Y intersect and are both parallel to the plane where the substrate 110 is located; the plurality of gates 130 include a first gate 1301 and a second gate 1302, and along the second direction Y, the first gate 1301 is located on the side of the second gate 1302 closer to the edge of the semiconductor device; the highest temperature of the first gate 1301 is T1, the highest temperature of the second gate 1302 is T2, wherein (T2-T1) / T1≤20%.

[0051] For details, please refer to [link / reference]. Figure 1 The substrate 110 can be formed from one or more of the following materials: silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, and diamond. It can also be other materials suitable for growing gallium nitride. The epitaxial structure 120 is located on one side of the substrate 110. Specifically, the epitaxial structure 120 can be a III-V compound semiconductor material, such as gallium arsenide, aluminum gallium arsenide, gallium nitride, aluminum gallium nitride, or indium gallium nitride, or one or more of these materials.

[0052] Furthermore, multiple gates 130 are located on the side of the epitaxial structure 120 away from the substrate 110. The first gate 1301 is located on the side of the second gate 1302 closer to the edge of the semiconductor device. During operation, each gate 130 in the active region generates a self-heating effect, i.e., a thermal effect generated by each gate itself. Furthermore, the self-heating generated by each gate 130 diffuses to adjacent gates 130, resulting in a mutual heating effect between adjacent gates 130. In other words, during normal operation of the semiconductor device, each gate 130 generates both a self-heating effect and a mutual heating effect, and the temperature of each gate 130 is obtained by superimposing the temperatures generated by the self-heating effect and the mutual heating effect. It is understandable that the temperature difference caused by the self-heating effect of each gate 130 is relatively small. However, because the first gate 1301 is located closer to the edge of the semiconductor device along the second direction Y, the number of adjacent gates 130 is relatively small, resulting in a lower temperature for the first gate 1301 due to the mutual heating effect.

[0053] Specifically, by ensuring that the highest temperature T1 of the first gate 1301 and the highest temperature T2 of the second gate satisfy (T2-T1) / T1≤20%, the temperature difference between the highest temperature T1 of the first gate 1301 and the highest temperature T2 of the second gate 1302 located near the edge of the semiconductor device is small, thereby enabling a more uniform temperature distribution in the semiconductor device, which in turn reduces heat loss and increases the output power of the semiconductor device.

[0054] The semiconductor device provided in this embodiment of the invention provides a semiconductor device by setting multiple gates on the side of the epitaxial structure away from the substrate, and the first gate of the multiple gates is located on the side of the second gate close to the edge of the semiconductor device. By making the highest temperature T1 of the first gate and the highest temperature T2 of the second gate satisfy (T2-T1) / T1≤20%, the temperature difference between the gates can be kept small, thereby making the temperature of the semiconductor device uniformly distributed, reducing the degradation of radio frequency performance and improving the output power.

[0055] Optional, continue to refer to Figure 1 The highest temperatures of any two adjacent gates 130 are approximately the same.

[0056] Specifically, the maximum temperatures of any two adjacent gates 130 are approximately the same, which can ensure a uniform temperature distribution in the semiconductor device and significantly reduce the degradation of radio frequency performance.

[0057] Optional, Figure 2 yes Figure 1 A schematic cross-sectional view of the provided semiconductor device along section line A-A'. (Reference) Figure 1 and Figure 2The semiconductor device also includes a plurality of sources 140 located on the side of the epitaxial structure 120 away from the substrate 110. The sources 140 extend along a first direction X, and the plurality of sources 140 are arranged along a second direction Y. The plurality of sources 140 includes a first source 1401 and a second source 1402. Along the second direction Y, the first source 1401 is disposed adjacent to a first gate 1301, and the second source 1402 is disposed adjacent to a second gate 1302. The first source 1401 is located on the side of the second source 1402 closer to the edge of the semiconductor device. The semiconductor device also includes a via 150 penetrating the substrate 110 and the epitaxial structure 120. The via 150 includes a first type of via 1501 and a second type of via 1502. Along the thickness direction of the semiconductor device (e.g., ...), the via 150 extends along the thickness direction of the semiconductor device. Figure 2 (As shown in the Z direction), the first source 1401 overlaps with the first type of through hole 1501, and the second source 1402 overlaps with the second type of through hole 1502; wherein, the total opening area of ​​the first type of through hole 1501 is greater than the total opening area of ​​the second type of through hole.

[0058] Specifically, the source electrode 140 can be connected to the back side of the semiconductor device through a via 150. For example, the via 150 can penetrate the substrate 110 and the epitaxial structure 120, that is, it is connected to the source electrode 140 through the source signal input electrode D located on the side of the substrate 110 away from the epitaxial structure 120. In other words, the source electrode 140 is electrically connected to the source signal input electrode D through the via 150. For example, during the sequential fabrication of the substrate 110 and the epitaxial structure 120, holes can be drilled, and the holes in the substrate 110 and each layer of the epitaxial structure 120 can be filled with a metal bonding material, thereby enabling the source signal input electrode D to be electrically connected to the source electrode 140.

[0059] It should be noted that since the via 150 penetrates both the substrate 110 and the epitaxial structure 120, the thermal conductivity of the via 150 is worse than that of the substrate 110. Therefore, the temperature at the via 150 is higher. Furthermore, the larger the area of ​​the via 150, the worse its thermal conductivity and the higher its temperature.

[0060] Furthermore, the via 150 includes a first type of via 1501 and a second type of via 1502. The total opening area of ​​the first type of via 1501 is greater than the total opening area of ​​the second type of via 1502. In other words, the product of the number of first type of via 1501 and the area of ​​a single first type of via 1501 is greater than the product of the number of second type of via 1502 and the area of ​​a single second type of via 1502. This can balance the temperature between the first gate 1301 and the second gate 1302. That is, the temperature at the first type of via 1501 is higher than that at the second type of via 1502, which can neutralize the less mutual heating effect of the first gate 1301. This can ensure that the temperature difference between the first gate 1301 and the second gate 1302 is small, thereby achieving a uniform temperature distribution in the semiconductor device.

[0061] Optional, Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line B-B'. (Reference) Figures 1-3 The first type of through hole 1501 includes at least one first through hole 15011, and the second type of through hole 1502 includes at least one second through hole 15022; the opening area of ​​the first through hole 15011 is larger than the opening area of ​​the second through hole 15022.

[0062] Specifically, the opening area of ​​the first via 15011 is larger than that of the second via 15022. That is, compared with the second via 15022, the first via 15011 has a larger opening area. This results in the first type of via 1501, composed of at least one first via 15011, having a larger total opening area. This ensures that the first type of via 1501 has less heat dissipation and a higher temperature, thereby neutralizing the mutual heating effect of the first gate 1301 and achieving a uniform temperature distribution in the semiconductor device. This can reduce the degradation of the device's radio frequency performance and improve the output power.

[0063] Optional, Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 4 As shown, along the second direction Y, the first through hole 15011 is located on the side of any other through hole 150 near the edge of the semiconductor device, and the second through hole 15022 is located on the side of any other through hole 150 near the center of the semiconductor device; along the direction from the first through hole 15011 to the second through hole 15022, the opening area of ​​the through hole 150 gradually decreases.

[0064] For example, the first via 15011 may be located on the side near the edge of the semiconductor device, which can be understood as the first via being located near the edge of the semiconductor device and on both sides of the semiconductor device along the second direction Y. The second via 15022 being located on the side of any other via 150 near the center of the semiconductor device can be understood as the second via 15022 covering the center of the semiconductor device or the distance between the second via 15022 and the center of the semiconductor device being less than the distance between any other via 150 and the center of the semiconductor device.

[0065] Specifically, along the direction from the first via 15011 to the second via 15022, the opening area of ​​the via 150 gradually decreases. That is, along the second direction Y, from both sides of the second direction Y towards the center of the semiconductor device, the opening area of ​​the via 150 gradually decreases. In other words, the opening area of ​​the first via 15011 is larger than the opening area of ​​the second via 15022. This ensures that the first via 150 dissipates less heat, thereby neutralizing the mutual heating effect of the first gate 1301. This also ensures that the temperature difference between the first gate 1301 and the second gate 1302 is small, thus achieving a uniform temperature distribution in the semiconductor device, reducing the degradation of the device's radio frequency performance and improving the output power.

[0066] Optional, continue to refer to Figure 1 Along the second direction Y, the first through hole 15011 is located on the side of any other through hole 150 near the edge of the semiconductor device, and the second through hole 15022 is located on the side of any other through hole 150 near the center of the semiconductor device; the opening area of ​​the first through hole 15011 is S1, and the opening area of ​​the second through hole 15022 is S2, where S2<S1≤4*S2.

[0067] Specifically, the opening area S1 of the first through hole 15011 and the opening area S2 of the second through hole 15022 satisfy S2<S1≤4*S2. This can reduce the heat dissipation of the first through hole 15011 on the one hand, and avoid affecting the normal heat dissipation of the semiconductor device due to the large opening area of ​​the first through hole 15011 on the other hand. At the same time, it can also ensure that the fabrication of the through hole meets the process requirements.

[0068] Optional, Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. For example... Figure 5 As shown, the first type of through hole 1501 includes at least two first through holes 15011, and the second type of through hole 1502 includes at least one second through hole 15022; the number of first through holes 15011 is greater than the number of second through holes 15022.

[0069] Specifically, the number of first vias 15011 is greater than the number of second vias 15022. By setting a larger number of first vias 15011, the temperature difference between the first gate 1301 and the second gate 1302 can be balanced, thereby ensuring that the first via 15011 has a higher temperature to neutralize the less mutual heating effect of the first gate 1301, thus achieving a uniform temperature distribution of the semiconductor device, reducing the degradation of the device's radio frequency performance and improving the output power.

[0070] Optional, Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. For example... Figure 6As shown, along the second direction Y, the first via 15011 is located on the side of any other via 150 near the edge of the semiconductor device, and the second via 15022 is located on the side of any other via 150 near the center of the semiconductor device; along the direction from the first via 15011 to the second via 15022, the number of vias 150 gradually decreases.

[0071] Specifically, along the direction from the first through-hole 15011 to the second through-hole 15022, the number of through-holes 150 gradually decreases. By setting a large number of first through-holes 15011, on the one hand, the temperature at the first through-hole 15011 can be kept high and the small mutual heating effect of the first gate 1301 can be neutralized, thereby making the temperature of the semiconductor device uniformly distributed and reducing the heat loss of the device. On the other hand, the through-hole fabrication process can be simplified.

[0072] Optional, continue to refer to Figure 5 Along the second direction Y, the first through hole 15011 is located on the side of any other through hole 150 near the edge of the semiconductor device, and the second through hole 15022 is located on the side of any other through hole 150 near the center of the semiconductor device; the number of first through holes 15011 in the first type of through holes 1501 is n1, and the number of second through holes 15022 in the second type of through holes 1502 is n2, where n1-n2≤5.

[0073] Specifically, the number of first vias 15011 (n1) and the number of second vias 15022 (n2) satisfy n1-n2≤5. This ensures that the number of first vias 15011 is greater than that of second vias 15022, thus balancing the temperature difference between the first gate 1301 and the second gate 1302. It also ensures the overall heat dissipation of the semiconductor device, preventing excessive vias from affecting the overall heat dissipation and ensuring normal operation. Furthermore, it simplifies the via fabrication process, avoiding the increased complexity of semiconductor device manufacturing due to excessive vias.

[0074] Optional, continue to refer to Figure 1The semiconductor device also includes a plurality of sources 140 located on the side of the epitaxial structure 120 away from the substrate 110. The sources 140 extend along a first direction X, and the plurality of sources 140 are arranged along a second direction Y. The plurality of sources 140 includes a first source 1401 and a second source 1402. Along the second direction Y, the first source 1401 is disposed adjacent to the first gate 1301, and the second source 1402 is disposed adjacent to the second gate 1302. The first source 1401 is located near the second source 1402. The semiconductor device also includes a via 150 penetrating the substrate 110 and the epitaxial structure 120. The via 150 includes a first type via 1501 and a second type via 1502. Along the thickness direction Z of the semiconductor device, a first source 1401 overlaps with the first type via 1501, and a second source 1402 overlaps with the second type via 1502. Along the first direction X, the center of the first type via 1501 is located on the side of the center of the second type via 1502 that is close to the center of the semiconductor device.

[0075] It should be noted that during semiconductor device operation, more heat is generated along the first direction X, resulting in a higher temperature on the central side of the semiconductor device. Specifically, along the first direction X, the center of the first via 1501 is located on the side of the center of the second via 1502 closer to the center of the semiconductor device. This ensures that the temperature at the first via 15011 is higher, thereby neutralizing the less mutual heating effect of the first gate 1301, balancing the temperature difference between the first gate 1301 and the second gate 1302, and reducing RF performance degradation.

[0076] Optional, continue to refer to Figure 1 Along the second direction Y, there is a gate spacing between two adjacent gates 130; the multiple gate spacings include a first gate spacing d1 along the second direction Y near the edge of the semiconductor device and a second gate spacing d2 located on the side of the first gate spacing d1 away from the edge of the semiconductor device; along the second direction Y, the first gate spacing d1 is smaller than the second gate spacing d2.

[0077] It should be noted that the larger the gate pitch between two adjacent gates 130, the smaller the mutual thermal impact. Specifically, along the second direction Y, the first gate pitch d1 is smaller than the second gate pitch d2. That is, the first gate pitch d1 closer to the edge of the semiconductor device is smaller, resulting in less mutual thermal impact. In order to balance the mutual thermal difference between the first gate 1301 and the second gate 130, the first gate pitch d1 is set to be smaller than the second gate pitch d2 along the second direction Y. This can reduce the temperature difference between the first gate 1301 and the second gate 1302, thereby making the temperature distribution of the semiconductor device more uniform, reducing the degradation of the device's RF performance and improving the output power.

[0078] Optional, Figure 7Schematic diagram of another semiconductor device provided by an embodiment of the present invention. As Figure 7 shown, the second gate pitch d2 is located on one side of any other gate pitch closer to the center of the semiconductor device; along one side of the first gate pitch d1 pointing to the second gate pitch d2, the gate pitch gradually increases.

[0079] Specifically, continue to refer to Figure 7 , the gate pitch between the first gate 1301 and the adjacent second gate 1302 is d1, and the gate pitches between two adjacent second gates 1302 are d21 and d2 respectively, and d1 < d21 < d2, that is, along one side of the first gate pitch d1 pointing to the second gate pitch d2, the gate pitch gradually increases. It can be understood that the maximum gate pitch is located at the center position of the semiconductor device, which is beneficial to reducing the mutual heating effect of the second gate 1302; it can also be understood that from the center position of the semiconductor device to the direction away from the center position, the gate pitch gradually decreases. In this way, the mutual heating difference between the first gate 1301 and the second gate 1302 can be balanced, that is, the temperature at the center of the semiconductor device can be reduced, and then the temperature of the semiconductor device can be evenly distributed, that is, the device thermal loss can be reduced.

[0080] It should be understood that the embodiments of the present invention improve the output power of semiconductor devices from the perspective of semiconductor device structure design. The semiconductor devices include, but are not limited to: high-power gallium nitride high electron mobility transistors (HEMTs) operating under high voltage and high current conditions; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor heterojunction field-effect transistors (MESFETs). Transistor (MISHFET) or other field-effect transistors.

[0081] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a semiconductor device, such as... Figure 5 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention may include:

[0082] S101, Provide substrate.

[0083] For example, the substrate material can be Si, SiC, or sapphire, or other materials suitable for growing gallium nitride. The substrate can be prepared using methods such as atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal-organic compound vapor deposition, low-pressure chemical vapor deposition, high-density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical-chemical vapor deposition, rapid thermochemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

[0084] S102. An epitaxial structure is prepared on one side of the substrate.

[0085] For example, the epitaxial structure can be formed from one or more group III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride, and a two-dimensional electron gas can be formed in the epitaxial structure. The growth methods for the epitaxial structure include metal-organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, and liquid phase epitaxy, etc., and the embodiments of the present invention are not limited thereto. Specifically, a two-dimensional electron gas is formed in the epitaxial structure.

[0086] Optionally, the epitaxial structure may include a nucleation layer, a buffer layer, a channel layer, and a barrier layer.

[0087] For example, the nucleation layer can be made of aluminum nitride and is located between the substrate and the buffer layer, serving to bond the semiconductor material layer that will be grown next. The buffer layer is located on one side of the substrate and can be made of gallium nitride. The buffer layer may also contain iron atoms, which helps to achieve high resistance performance of the buffer layer, ensuring that vertical leakage current can be blocked and the pinch-off performance of the semiconductor device can be improved.

[0088] For example, the channel layer can be a group III nitride, such as Al. x Ga 1－x N, where 0 ≤ x < 1, means that the energy at the interface between the channel layer and the barrier layer, i.e., the conduction band edge of the channel layer, is lower than the energy at the conduction band edge of the barrier layer. For example, x = 0 indicates that the channel layer is GaN. The channel layer can also be other group III nitrides, such as InGaN or AlInGaN. The channel layer can be undoped or unintentionally doped. The channel layer can also be a multilayer structure, such as a combination of superlattice, GaN, or AlGaN.

[0089] For example, a barrier layer is fabricated on the side of the channel layer away from the substrate, forming a heterojunction structure with the channel layer. The barrier layer can be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer has sufficient thickness and a sufficiently high Al composition to create a significant carrier concentration at the interface between the channel layer and the barrier layer. For example, the thickness of the barrier layer can be 20 nm, and the Al doping concentration can be 25%.

[0090] For example, the channel layer may include GaN, and the barrier layer may include AlGaN, meaning the barrier layer material has a higher band gap than the channel layer material, and the channel layer may also have a greater electron affinity than the barrier layer. Due to the band gap difference between the barrier layer and the channel layer, as well as the piezoelectric effect at the interface between the barrier layer and the channel layer, a two-dimensional electron gas is formed in both the channel layer and the barrier layer.

[0091] Understandably, epitaxial structures can also include a cap layer, which is located on the surface of the barrier layer away from the substrate. The cap layer can reduce surface states, reduce surface leakage current in subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure and semiconductor devices.

[0092] S103. A plurality of gates are fabricated on the side of the epitaxial structure away from the substrate. The gates extend along a first direction and the plurality of gates are arranged along a second direction. The first direction and the second direction intersect and are both parallel to the plane of the substrate. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on the side of the second gate closer to the edge of the semiconductor device. The highest temperature of the first gate is T1 and the highest temperature of the second gate is T2, wherein (T2-T1) / T1≤20%.

[0093] For details, please refer to Figure 1 Multiple gates 130 are fabricated on the side of the epitaxial structure 120 away from the substrate 110. A first gate 1301 is located on the side of the second gate 1302 closest to the edge of the semiconductor device. During operation, each gate 130 in the active region of the semiconductor device generates a self-heating effect, i.e., a thermal effect generated by each gate itself. Since the self-heating generated by each gate 130 diffuses to adjacent gates 130, a mutual heating effect also occurs between adjacent gates 130. In other words, during normal operation of the semiconductor device, each gate 130 generates both a self-heating effect and a mutual heating effect, and the temperature of each gate 130 is obtained by superimposing the temperatures generated by the self-heating effect and the mutual heating effect. It is understandable that the temperature difference caused by the self-heating effect of each gate 130 is small. However, because the first gate 1301 is located closer to the edge of the semiconductor device along the second direction Y, the number of adjacent gates 130 is small, resulting in a lower temperature for the first gate 1301 due to the mutual heating effect.

[0094] For details, please refer to [link / reference]. Figure 1 By ensuring that the highest temperature T1 of the first gate 1301 and the highest temperature T2 of the second gate 1302 satisfy (T2-T1) / T1≤20%, the temperature difference between the highest temperature T1 of the first gate 1301 and the highest temperature T2 of the second gate 1302 located near the edge of the semiconductor device can be reduced, thereby enabling a more uniform temperature distribution in the semiconductor device, which in turn reduces heat loss and increases the output power of the semiconductor device.

[0095] The semiconductor device fabrication method provided in this invention involves fabricating multiple gates on the side of the epitaxial structure away from the substrate, with the first gate located on the side of the second gate close to the edge of the semiconductor device. By ensuring that the highest temperature T1 of the first gate and the highest temperature T2 of the second gate satisfy (T2-T1) / T1≤20%, the temperature difference between the gates can be kept small, thereby making the temperature distribution of the semiconductor device uniform, reducing radio frequency performance degradation, and improving output power.

[0096] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; An epitaxial structure located on one side of the substrate; A plurality of gates are located on the side of the epitaxial structure away from the substrate, the gates extending along a first direction and the plurality of gates arranged along a second direction; the first direction and the second direction intersect and are both parallel to the plane of the substrate; The plurality of gates includes a first gate and a second gate, wherein along the second direction, the first gate is located on the side of the second gate closer to the edge of the semiconductor device; the highest temperature of the first gate is T1, the highest temperature of the second gate is T2, wherein (T2-T1) / T1≤20%; The semiconductor device further includes a plurality of sources located on the side of the epitaxial structure away from the substrate, the sources extending along the first direction and the plurality of sources arranged along the second direction; The plurality of sources include a first source and a second source. Along the second direction, the first source is disposed adjacent to the first gate, the second source is disposed adjacent to the second gate, and the first source is located on the side of the second source closer to the edge of the semiconductor device. The semiconductor device further includes vias penetrating the substrate and the epitaxial structure. The vias include a first type of via and a second type of via. Along the thickness direction of the semiconductor device, the first source electrode overlaps with the first type of via, and the second source electrode overlaps with the second type of via. Wherein, the total opening area of ​​the first type of via is greater than the total opening area of ​​the second type of via; or, along the first direction, the center of the first type of via is located on the side of the center of the second type of via closer to the center of the semiconductor device; or, along the second direction, there is a gate spacing between two adjacent gates; the plurality of gate spacings include a first gate spacing along the second direction closer to the edge of the semiconductor device and a second gate spacing located on the side of the first gate spacing away from the edge of the semiconductor device; along the second direction, the first gate spacing is smaller than the second gate spacing.

2. The semiconductor device according to claim 1, characterized in that, The first type of through hole includes at least one first through hole, and the second type of through hole includes at least one second through hole; The opening area of ​​the first through hole is larger than the opening area of ​​the second through hole.

3. The semiconductor device according to claim 2, characterized in that, Along the second direction, the first via is located on the side of any other via closer to the edge of the semiconductor device, and the second via is located on the side of any other via closer to the center of the semiconductor device; Along the direction from the first through hole to the second through hole, the opening area of ​​the through hole gradually decreases.

4. The semiconductor device according to claim 2, characterized in that, Along the second direction, the first via is located on the side of any other via closer to the edge of the semiconductor device, and the second via is located on the side of any other via closer to the center of the semiconductor device; The opening area of ​​the first through hole is S1, and the opening area of ​​the second through hole is S2, where S2 < S1 ≤ 4 * S2.

5. The semiconductor device according to claim 1, characterized in that, The first type of through hole includes at least two first through holes, and the second type of through hole includes at least one second through hole; The number of the first through holes is greater than the number of the second through holes.

6. The semiconductor device according to claim 5, characterized in that, Along the second direction, the first via is located on the side of any other via closer to the edge of the semiconductor device, and the second via is located on the side of any other via closer to the center of the semiconductor device; The number of through holes gradually decreases along the direction from the first through hole to the second through hole.

7. The semiconductor device according to claim 5, characterized in that, Along the second direction, the first via is located on the side of any other via closer to the edge of the semiconductor device, and the second via is located on the side of any other via closer to the center of the semiconductor device; The number of first through holes in the first type is n1, and the number of second through holes in the second type is n2, where n1 - n2 ≤ 5.

8. The semiconductor device according to claim 1, characterized in that, The second gate pitch is located on the side of any other gate pitch closer to the center of the semiconductor device; The gate spacing gradually increases along one side from the first gate spacing to the second gate spacing.

9. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1-8, characterized in that, The preparation method includes: Provide substrate; An epitaxial structure is fabricated on one side of the substrate; A plurality of gates are fabricated on the side of the epitaxial structure away from the substrate. The gates extend along a first direction and are arranged along a second direction. The first and second directions intersect and are both parallel to the plane of the substrate. The plurality of gates includes a first gate and a second gate. Along the second direction, the first gate is located on the side of the second gate closer to the edge of the semiconductor device. The highest temperature of the first gate is T1, and the highest temperature of the second gate is T2, wherein (T2-T1) / T1≤20%. The semiconductor device further includes a plurality of sources located on the side of the epitaxial structure away from the substrate, the sources extending along the first direction and the plurality of sources arranged along the second direction; The plurality of sources include a first source and a second source. Along the second direction, the first source is disposed adjacent to the first gate, the second source is disposed adjacent to the second gate, and the first source is located on the side of the second source closer to the edge of the semiconductor device. The semiconductor device further includes vias penetrating the substrate and the epitaxial structure. The vias include a first type of via and a second type of via. Along the thickness direction of the semiconductor device, the first source electrode overlaps with the first type of via, and the second source electrode overlaps with the second type of via. Wherein, the total opening area of ​​the first type of via is greater than the total opening area of ​​the second type of via; or, along the first direction, the center of the first type of via is located on the side of the center of the second type of via closer to the center of the semiconductor device; or, along the second direction, there is a gate spacing between two adjacent gates; the plurality of gate spacings include a first gate spacing along the second direction closer to the edge of the semiconductor device and a second gate spacing located on the side of the first gate spacing away from the edge of the semiconductor device; along the second direction, the first gate spacing is smaller than the second gate spacing.

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