Semiconductor device and method for manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor device, a method for manufacturing a semiconductor device, and an integrated circuit. The semiconductor device includes: a substrate having a first doping type; a first transistor portion located on the substrate to form a first-type transistor structure; and a second transistor portion located on the substrate to form a second-type transistor structure, the second transistor portion including: a first doping region and a fourth doping region; a first region surrounding and contacting the first doping region; a body region closer to the first transistor portion than the first doping region and the fourth doping region; and a second region having the first doping type, surrounding and contacting the fourth doping region and the body region, with the second region contacting the substrate. The solution disclosed herein can significantly simplify the manufacturing process of semiconductor devices and reduce manufacturing costs.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device. Background Art

[0002] With the rapid development of the electronics industry, the demand for integrated circuits and semiconductor devices is increasing, and it is expected that their manufacturing costs can be reduced. At present, the preparation process of semiconductor devices is relatively complex and the cost is high. In particular, different types of transistors usually need to be manufactured separately, resulting in high manufacturing costs. In order to simplify the process, some monolithic integration technologies have been proposed, such as BCD (Bipolar-CMOS-DMOS) technology, which can produce bipolar transistors, CMOS (Complementary Metal-Oxide-Semiconductor) devices and DMOS (Double-diffused Metal Oxide Semiconductor) devices on the same chip. However, monolithic integration technologies such as BCD technology require complex masks and processes, such as epitaxy processes, and therefore still have the problem of high manufacturing costs and complex processes. Summary of the Invention

[0003] To at least partially address the above and other possible problems, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device.

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided, which includes: a substrate having a first doping type; a first transistor portion located on the substrate to form a first type transistor structure; and a second transistor portion located on the substrate to form a second type transistor structure, the second transistor portion including: a first doping region and a fourth doping region having a second doping type; a first region having the second doping type, surrounding and contacting the first doping region; a body region having the first doping type, closer to the first transistor portion than the first doping region and the fourth doping region; and a second region having the first doping type, surrounding and contacting the fourth doping region and the body region, and the second region contacting the substrate.

[0005] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a substrate of a first doping type, performing an implantation of a second doping type on the substrate to form a drift region; performing an implantation of the first doping type in the drift region using a first mask to form a well region, the well region being in contact with the substrate; performing an implantation of the second doping type in the drift region and the well region using a second mask to form a first doping region in the drift region on one side of the well region, forming a second doping region and a third doping region in the drift region on the other side of the well region and forming a fourth doping region in the well region; and performing an implantation of the first doping type in the well region and the drift region using a third mask to form a first gate region in the drift region and integrally form a body region and a second gate region in the well region.

[0006] According to a third aspect of the present disclosure, a semiconductor device is provided, which includes: a substrate having a first doping type; a first transistor portion located on the substrate to form a first type transistor; and a second transistor portion located on the substrate to form a second type transistor, the second transistor portion including: a first doping region and a fourth doping region having a second doping type; a first region having the second doping type surrounding and contacting the first doping region; a body region having the first doping type, which is closer to the first transistor portion than the first doping region and the fourth doping region; and a second region having the first doping type surrounding and contacting the fourth doping region and the body region, wherein a depth of the body region in an extension direction toward the substrate is greater than a depth of the fourth doping region in the extension direction, and wherein the doping concentration of the body region is greater than the doping concentration of the second region.

[0007] According to a fourth aspect of the present disclosure, an integrated circuit is provided. The integrated circuit includes the semiconductor device according to the first and third aspects.

[0008] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present disclosure.

[0010] Figure 1 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 A schematic structural diagram of a semiconductor device according to another embodiment of the present disclosure is shown.

[0012] Figures 3A to 3H Schematic diagrams showing various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 4 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0014] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. Those skilled in the art can derive alternative technical solutions from the following description without departing from the spirit and scope of protection of the present disclosure.

[0015] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based, at least in part, on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." Other explicit and implicit definitions may be included below.

[0016] Embodiments of the present disclosure provide an improved semiconductor device and a method for manufacturing the same. In the improved solution, a first-type transistor, such as a junction gate field-effect transistor (JFET), is integrated with a second-type transistor, such as a laterally diffused metal-oxide semiconductor (LDMOS) transistor, and the well region of the second-type transistor is used to isolate the two transistors. In this way, the process steps can be simplified and the number of masks required in the manufacturing process can be reduced, thereby significantly reducing manufacturing costs.

[0017] Figure 1 FIG2 shows a schematic structural diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 can be used in an integrated circuit (IC). For example, the semiconductor device 100 can include a high-voltage LDMOS transistor and a high-voltage JFET, and be applied to an intelligent power IC.

[0018] like Figure 1As shown, the semiconductor device 100 includes a substrate 110. The substrate 110 may include a first substrate portion 111 and a second substrate portion 112, and has a first doping type. For example, the first doping type may be a P-type, that is, the substrate 110 may be a P-type substrate. Further, the semiconductor device 100 also includes a first transistor portion 120 and a second transistor portion 130. The first transistor portion 120 is located on the substrate 110 to form a first type transistor. For example, the first transistor portion 120 may be located on the first substrate portion 111 and form a first type transistor ( Figure 1 The second transistor section 130 is located on the substrate 110 to form a second type transistor. For example, the second transistor section 130 may be located on the second substrate section 112 and form a second type transistor together with the second substrate section 112. Figure 1 to the left of the dotted line in ).

[0019] Second transistor portion 130 includes a first region 131, a second region 132, a first doped region 133, a fourth doped region 134, and a body region 135. First region 131, first doped region 133, and fourth doped region 134 have the second doping type, while second region 132 and body region 135 have the first doping type. For example, the first doping type may be P-type, and the second doping type may be N-type. First region 131 surrounds and contacts first doped region 133, second region 132 surrounds and contacts fourth doped region 134 and body region 135, and body region 135 is closer to first transistor portion 120 than first doped region 133 and fourth doped region 134.

[0020] As an example, the second-type transistor formed by the second transistor portion 130 and the second substrate portion 112 can be an LDMOS transistor. The first region 131 can be the N-type drift region of the LDMOS transistor, the second region 132 can be the P-type well region of the LDMOS transistor, and the first doped region 133, the fourth doped region 134, and the body region 135 can be used to form the drain, source, and body of the LDMOS transistor, respectively. In some embodiments, the first doped region 133 is a drain region, and the fourth doped region 134 is a source region. The LDMOS transistor can also include a gate 136, which is located between the first doped region 133 and the fourth doped region 134 and at least above the second region 132. Thus, by controlling the voltage applied to the gate 136, a conductive channel can be formed in the second region 132 and between the first doped region 133 and the fourth doped region 134, thereby controlling the on and off state of the LDMOS transistor.

[0021] In some embodiments, the substrate 110 (or the second substrate portion 112) having the first doping type, the second region 132, and the body region 135 have different doping concentrations, and the first doping region 133 and the fourth doping region 134 having the second doping type have different doping concentrations than the first region 131. In one embodiment, the doping concentration of the body region 135 is higher than the doping concentration of the second region 132, the doping concentration of the second region 132 is higher than the doping concentration of the substrate 110 (or the second substrate portion 112), and the doping concentrations of the first doping region 133 and the fourth doping region 134 are higher than the doping concentration of the first region 131.

[0022] According to an embodiment of the present disclosure, the second region 132 can contact the substrate 110. Specifically, the second region 132 serving as a well region can extend toward the substrate 110 and pass through the first region 131 serving as a drift region to reach and contact the second substrate portion 112. In conventional LDMOS transistors, the depth of the well region does not exceed the drift region, whereby the drift region actually separates the well region from the substrate, and an additional structure needs to be provided to lead the substrate out to the external ground. Unlike conventional LDMOS transistors, the semiconductor device 100 in an embodiment of the present disclosure increases the depth of the second region 132 serving as the well region and makes it reach the surface of the substrate 110 or enter the substrate 110, which can provide a variety of benefits. Specifically, by utilizing the second region 132 with increased depth and the body region 135 in contact with the second region 132, the substrate 110 can be led out to the outside for grounding without having to manufacture additional paths to lead out the substrate 110, which simplifies the process steps of the semiconductor device. Furthermore, and more importantly, because the substrate 110, the second region 132, and the body region 135 are always grounded, they can form an isolation between the first type transistor and the second type transistor, thereby effectively isolating the two different types of transistors. Thus, the two types of transistors can be integrated on the same substrate and manufactured using the same simplified process flow. This greatly simplifies the process and reduces manufacturing costs compared to methods of manufacturing the two types of transistors separately and using BCD technology.

[0023] In some embodiments of the present disclosure, the first transistor portion 120 includes a third region 121, a second doping region 123, a third doping region 124, a first gate region 125, and a second gate region 126. The third region 121, the second doping region 123, and the third doping region 124 have a second doping type, such as an N-type, and the first gate region 125 and the second gate region 126 have a first doping type, such as a P-type. The third region 121 surrounds and contacts the second doping region 123, the third doping region 124, and the first gate region 125, and the first gate region 125 and the second gate region 126 are located on both sides of the third doping region 124.

[0024] As an example, the first-type transistor formed by the first transistor portion 120 and the first substrate portion 111 may be a JFET. The third region 121 may be the N-type drift region of the JFET, and the second doped region 123 and the third doped region 124 may form the drain and source of the JFET, respectively. In some embodiments, the second doped region 123 is the drain region, and the third doped region 124 is the source region. The first gate region 125 and the second gate region 126 form the gate of the JFET. The first transistor portion 120 may also include a gate field plate 127. The third region 121, as an N-type drift region, may form a conductive channel between the source and drain of the JFET, and the channel may be pinched off or its degree of conduction controlled by controlling the voltage applied to the gate. In some embodiments, the second doped region 123 and the third doped region 124 may have a different doping concentration than the third region 121. In one embodiment, the doping concentrations of the second doped region 123 and the third doped region 124 may be greater than the doping concentration of the third region 121.

[0025] In some embodiments of the present disclosure, the second gate region 126 of the first transistor portion 120 is formed integrally with the body region 135 of the second transistor portion 130. Specifically, the second gate region 126 of the first type transistor and the body region 135 of the second type transistor can be the same doped region formed integrally, such as a P+ type doped region. That is, the gate region of a transistor such as a JFET can be shared with an adjacent transistor such as an LDMOS transistor to serve as the body region of the adjacent transistor, or the body region of the LDMOS transistor can be shared with a JFET to serve as the gate region of the JFET. In this way, the body region of the LDMOS transistor and the gate region of the JFET can be formed using only one mask. In contrast, when the JFET and LDMOS transistor are manufactured separately, the process of forming the JFET gate region generally requires first using one mask to form a P-type drift region, and then using another mask to form a P+ type doped region, and the formation of the body region of the LDMOS transistor also requires the use of another mask. As can be seen, by sharing doped regions between the two transistors, the process steps can be further simplified. For example, the gate of the JFET and the body region of the LDMOS transistor can be formed through a single P+ implant. At the same time, the simplified manufacturing process also reduces the manufacturing cost.

[0026] In some embodiments of the present disclosure, the depth of the body region 135 of the second transistor portion 130 in the extension direction toward the second substrate portion 112 is greater than the depth of the fourth doped region 134 in the extension direction, and the doping concentration of the body region 135 is greater than the doping concentration of the second region 132. Specifically, the gate region of a first-type transistor such as a JFET generally requires a greater depth. For example, the gate region of a separately manufactured JFET generally includes a P+-type doped region and a P-type drift region located below the P+-type doped region. As a result, the conduction channel can be easily controlled and the appropriate pinch-off voltage can be obtained by adjusting the doping concentration. At the same time, as described above, the body region 135 of the second-type transistor is formed integrally with or shared with the second gate region 126 of the first-type transistor. Therefore, in order to obtain a gate region of the first-type transistor with better performance, the body region 135 and the second gate region 126 can be formed as regions with a greater depth. In other words, the body region 135 can become deeper along with the second gate region 126 and thus be greater than the depth of the fourth doped region 134. The body region 135 with increased depth further improves the performance of second type transistors such as LDMOS transistors. The reason is that when electron-hole pairs are generated, the deeper body region 135 with a larger doping concentration can effectively absorb holes and guide them to the ground. In this way, while simplifying the manufacturing process and reducing manufacturing costs, the device performance of the LDMOS transistor is further improved. In one embodiment, each gate region in the first gate region 125 and the second gate region 126 can have two or more sub-regions with different doping concentrations. For example, the first gate region 125 and the second gate region 126 can be doped twice or more to form a sub-region with a higher doping concentration at a shallower depth and a sub-region with a lower doping concentration at a deeper depth. Thus, the appropriate pinch-off voltage can be obtained by adjusting the concentration of the sub-region.

[0027] In some embodiments of the present disclosure, the first transistor portion 120 further includes a fourth region 122 having the first doping type, the fourth region 122 surrounding and contacting the second gate region 126, and the fourth region 122 is integrally formed with the second region 132 of the second transistor portion 130. In this manner, the well region of the LDMOS transistor can be shared with the JFET, and effective ground isolation is formed between the LDMOS transistor and the JFET transistor.

[0028] In some embodiments of the present disclosure, the second transistor portion 130 further includes a source metal 137 connected to the fourth doping region 134, and a body metal 138 connected to the body region 135, and the body metal 138 is further connected to the source metal 137 and the ground. Thus, the first substrate 111 and the second substrate 112 can be drawn out and always grounded, thereby forming effective isolation between the two transistors. In one embodiment, the second transistor portion 130 may further include a drain metal 139 connected to the first doping region 133 and a gate metal connected to the gate 136, and the first transistor portion 120 may further include a drain metal 129 connected to the second doping region 123, a source metal connected to the third doping region 124, and a gate metal 128 connected to the first gate region 125, the second gate region 126 and the field plate 127. As an example, the drain metals 139 and 129 can be connected to a power line with a voltage range of 0 to 150V, and the gate metal 128 can be connected to the ground.

[0029] It is understandable that Figure 1 The semiconductor device 110 shown in FIG. 1 is merely schematic, and additional regions and elements may be added, or some regions and elements may be reduced or replaced as needed.

[0030] Figure 2 FIG. 1 shows a schematic structural diagram of a semiconductor device 100 according to another embodiment of the present disclosure. Figure 2 As shown, the semiconductor device 100 may further include a third transistor section 140 and a fourth transistor section 150. The third transistor section 140 is axially symmetrical with the first transistor section 120 and is located on the substrate 110 to form another first-type transistor structure, such as another JFET structure. The other first-type transistor structure formed by the third transistor section 140, together with the first-type transistor structure formed by the first transistor section 120, constitutes a first-type transistor. The fourth transistor section 150 is axially symmetrical with the second transistor section 130 and is located on the substrate 110 to form another second-type transistor structure. The other second-type transistor structure formed by the fourth transistor section 150, together with the second-type transistor structure formed by the second transistor section 130, constitutes a second-type transistor. The substrate 110 may accordingly include a third substrate section 113 and a fourth substrate section 114. The third transistor section 140 may be formed on the third substrate section 113 of the substrate 110, and the fourth transistor section 150 may be formed on the fourth substrate section 114 of the substrate 110. Other structures of the third transistor section 140 and the fourth transistor section 150 are similar to those of the first transistor section 120 and the second transistor section 130 , respectively, and thus are not described again.

[0031] Figure 2The semiconductor device 100 shown is merely exemplary, and the semiconductor device 100 may include more or fewer transistor structures. For example, only one additional first-type transistor structure or one additional second-type transistor structure may be provided, or more transistor structures may be arranged in a similar manner outside the third transistor section 140 and the fourth transistor section 150. These transistor structures may be first-type transistor structures such as JFET structures or second-type transistor structures such as LDMOS transistor structures, and the embodiments of the present disclosure are not limited thereto.

[0032] It is understandable that Figure 1 and Figure 2 The first doping type shown in FIG is P-type and the second doping type is N-type, but the first doping type may also be N-type and the second doping type may be P-type. However, compared to the first doping type being N-type, the first doping type being P-type is more preferred because the substrate 110 having the first doping type can be a P-type substrate with a lower cost, thereby helping to reduce the overall cost of the semiconductor device 100. In addition, the above description describes that the first-type transistor is a JFET and the second-type transistor is an LDMOS transistor, but it is understood that the integrated first-type transistor and the second-type transistor may also be other suitable types of transistors, as long as they can be implemented according to the principles of the present disclosure.

[0033] Figures 3A to 3H Shown Figure 2 Schematic diagram of various stages of the manufacturing process of the semiconductor device 100 in FIG. The manufacturing process of the semiconductor device 100 will be described below by way of example using P-type as the first doping type, N-type as the second doping type, JFET as the first type transistor, and LDMOS transistor as the second type transistor.

[0034] like Figure 3A As shown, an initial P-type substrate PS is provided. Using a P-type substrate can reduce the overall cost of the integrated device. The initial substrate PS can provide a substrate 110, which includes a first substrate portion 111, a second substrate portion 112, a third substrate portion 113, and a fourth substrate portion 114.

[0035] like Figure 3BAs shown, N-type implantation is performed on the initial substrate PS to form an N-type drift region ND including a first region 131 and a third region 121. In one embodiment, the N-type implantation performed includes a blanket implantation. Since the blanket implantation process does not require the use of a mask, the process complexity and manufacturing cost can be effectively reduced. Furthermore, the N-type implantation performed may also include performing a thermal drive-in after the blanket implantation to ensure that the N-type dopant can extend to a sufficient depth. Thus, the entire upper region of the initial substrate PS becomes the N-type drift region ND, and the lower region of the initial substrate PS becomes the substrate 110.

[0036] like Figure 3C As shown, a local oxidation of silicon (LOCOS) is performed on the N-type drift region ND using a mask to form a silicon oxide layer OXS.

[0037] like Figure 3D As shown, a P-type implant is performed in the N-type drift region ND using a mask to form a P-type well region PW. This extends through the drift region ND and contacts the surface of the substrate 110 or into the substrate 110. The P-type well region PW may include a second region 132 and a fourth region 122. By extending the well region PW to the substrate 110, the P-type substrate 110 can be directly connected to the well region PW without providing an additional path to connect the substrate. Furthermore, since the P-type substrate 110 and the P-type well region PW are always grounded, the JFET and LDMOS transistors can be isolated. After the P-type well region is formed, the isolation region between the two well regions PW can be used as a high-voltage region for the JFET or LDMOS transistor. In one embodiment, the well region PW can be brought into contact with the substrate 110 by thermal expansion. This allows the well region PW to be simply and efficiently extended to a depth sufficient to contact the substrate 110.

[0038] like Figure 3E As shown, gate oxidation and polysilicon POLY deposition are performed on the N-type drift region ND, the well region PW, and the silicon oxide layer OXS, and polysilicon POLY etching and reoxidation are performed using a mask. In addition, a spacer SP of the polysilicon POLY can be formed. Thus, the gate 136 of the LDMOS transistor and the field plate 127 of the JFET are formed on the silicon oxide layer OXS. Optionally, after performing the polysilicon POLY etching and reoxidation and before forming the spacer SP, an NMOS lightly doped drain (LDD) process and an NLDD annealing process can also be performed to form an NLDD region.

[0039] like Figure 3FAs shown, an N-type implant is performed in the drift region ND and the well region PW using a mask to form a first doped region in the drift region ND on one side of the well region PW, a second doped region and a third doped region in the drift region ND on the other side of the well region PW, and a fourth doped region in the well region PW. Relative to the doping level of the N-type drift region ND, a heavier N-type doping can be performed to form an N+ doped region NP, which serves as the source and drain regions of the JFET and LDMOS transistors. The first doped region 133 can be a first drain region, the second doped region 123 can be a second drain region, the third doped region 124 can be a second source region, and the fourth doped region 134 can be a first source region.

[0040] like Figure 3G As shown, a P-type implant is performed in the P-type well region PW and the N-type drift region using a mask to form a first gate region 125 in the N-type drift region ND and a body region 135 and a second gate region 126 integrally formed in the P-type well region. Relative to the doping level of the P-type well region PW, a heavier P-type doping can be performed to form a P+ doped region PP, which serves as the body region of the LDMOS transistor and the gate region of the JFET. Thus, only one mask and one P+ implant are required to form the body region of the LDMOS transistor and the gate region of the JFET.

[0041] like Figure 3H As shown, a series of back-end processes can be performed, including contact formation, metal (including drain metal, source metal, gate metal, and body metal) formation, via formation, top metal formation, and passivation. For example, the fourth doped region 134 is connected to the source metal 137, the body region 135 is connected to the body metal 138, the first doped region 133 is connected to the first drain metal 139, and the second doped region 123 is connected to the second drain metal 129.

[0042] exist Figures 3A to 3G In the front-end process, the number of masks is reduced to 5. Figure 3HIn the back-end process of the semiconductor device 100, only 10 to 12 masks are required during the manufacturing process of the semiconductor device 100. Compared with separately manufacturing LDMOS transistors and JFET transistors or using BCD technology to manufacture LDMOS transistors and JFET transistors, the number of masks is greatly reduced. In addition to the greatly reduced number of masks, the solution of the present disclosure also has many advantages. Specifically, at least a portion of the implantation can be shared between the two transistors, which simplifies the overall manufacturing process, and in the embodiment of the present disclosure, due to the clever use of the P-type well region PW to achieve substrate extraction and isolation, the termination design of the semiconductor can be simpler. In addition, although the two transistors are integrated in a monolithic integrated circuit, their drains can be biased separately, which makes the application of semiconductor devices more flexible and has a wider range of applications. The solution of the present disclosure also allows the use of low-cost P-type substrates and does not require the use of epitaxial processes. In contrast, separately manufactured LDMOS transistors and JFETs usually require an N+ substrate and a thicker N-type epitaxial layer, and BCD technology also requires high-cost epitaxial layer (especially for high-voltage semiconductor devices). Furthermore, compared to some vertical integrated devices, the integrated device disclosed herein provides top pad connections without the need for backside metallization, thereby providing simpler backside processing and greater packaging flexibility. Advantageously, all process steps disclosed herein can be implemented in a simple and low-cost submicron CMOS process. Thus, compared to both individually fabricated transistors and BCD technology, the disclosed solution offers significant advantages in terms of simpler processing and lower costs.

[0043] Figure 4 FIG. 4 is a schematic flow chart of a method 400 for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1 、 Figure 2 and Figures 3A to 3H The various aspects described can be applied to method 400. For the purpose of discussion, Figure 1 、 Figure 2 and Figures 3A to 3H Method 400 will be described.

[0044] 401: Form a substrate 110 having a first doping type. In some embodiments, the first doping type is P-type.

[0045] 402: Perform a second doping type implantation on the substrate 110 to form a drift region ND. In some embodiments, the second doping type is N-type. In some embodiments, perform a blanket implantation of the second doping type on the substrate 110 to form a drift region.

[0046] 403: Performing implantation of the first dopant type in the drift region ND using a first mask to form a well region PW, wherein the well region PW is in contact with the substrate 110. In some embodiments, performing implantation of the first dopant type in the drift region ND using the first mask to form the well region PW further includes: bringing the well region PW into contact with the substrate 110 by thermal driving.

[0047] 404: Using a second mask, implant a second dopant type into the drift region ND and the well region PW to form a first doped region in the drift region ND on one side of the well region PW, a second doped region and a third doped region in the drift region ND on the other side of the well region PW, and a fourth doped region in the well region PW. In some embodiments, the first doped region 133 is a first drain region connected to the first drain metal 139; the second doped region 123 is a second drain region connected to the second drain metal 129; the third doped region 124 is a second source region; and the fourth doped region 134 is a first source region.

[0048] 405: Using a third mask, perform a first doping type implantation in the well region PW and the drift region ND to form a first gate region 125 in the drift region ND and integrally form a body region 135 and a second gate region 126 in the well region PW.

[0049] In some embodiments of the present disclosure, method 400 may further include: performing local oxidation of silicon on the drift region using a fourth mask to form a silicon oxide layer; performing gate oxidation and polysilicon deposition on the drift region ND, the well region PW and the silicon oxide layer; and performing polysilicon etching and re-oxidation using a fifth mask to form a gate 136 and a field plate 127.

[0050] In addition, although adopting specific order to describe each operation, this should be understood as requiring such operation to be carried out in the specific order shown or in sequential order, or requiring that all illustrated operations should be carried out to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although comprising some specific implementation details in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation also can be implemented in a plurality of implementations individually or in the mode of any suitable subcombination.

[0051] Through the teachings given in the above description and the associated drawings, many modifications and other embodiments of the present disclosure given here will be recognized by those skilled in the art of the present disclosure. Therefore, it is to be understood that the embodiments of the present disclosure are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the present disclosure. In addition, although the above description and the associated drawings have described the example embodiments in the context of certain example combinations of parts and / or functions, it should be appreciated that different combinations of parts and / or functions can be provided by alternative embodiments without departing from the scope of the present disclosure. In this regard, for example, other combinations of parts and / or functions that are different from those explicitly described above are also expected to be within the scope of the present disclosure. Although specific terms are used here, they are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. A semiconductor device (100), comprising: a substrate (110) having a first doping type; A first transistor portion (120) is located on the substrate (110) to form a first type transistor structure; as well as A second transistor section (130) is located on the substrate (110) to form a second type transistor structure, the second transistor section (130) comprising: A first doping region (133) and a fourth doping region (134) having a second doping type; A first region (131) having a second doping type, surrounding and contacting the first doping region (133); a body region (135) having a first doping type, closer to the first transistor portion (120) than the first doping region (133) and the fourth doping region (134); and A second region (132) having a first doping type surrounds and contacts the fourth doping region (134) and the body region (135), and the second region (132) contacts the substrate (110).

2. The semiconductor device (100) according to claim 1, wherein the first transistor portion (120) comprises: a second doping region (123) and a third doping region (124) having a second doping type; a first gate region (125) and a second gate region (126) having a first doping type, located on both sides of the third doping region (124), and the second gate region (126) is formed as a whole with the body region (135) of the second transistor portion (130); and a third region (121) having a second doping type, surrounding and contacting the second doping region (123), the third doping region (124) and the first gate region (125); The second doping region and the third doping region are located on both sides of the first gate region (125).

3. The semiconductor device according to claim 2, wherein the first doping region (133) is a first drain region, the fourth doping region (134) is a first source region; and the second doping region (123) is a second drain region, and the third doping region (124) is a second source region.

4. The semiconductor device (100) according to claim 2, wherein the first transistor portion (120) further comprises: A fourth region (122) having a first doping type surrounds and contacts the second gate region (126), and the fourth region (122) is formed integrally with the second region (132) of the second transistor portion (130).

5. The semiconductor device (100) according to claim 1, wherein the depth of the body region (135) in the extension direction toward the substrate (110) is greater than the depth of the fourth doping region (134) in the extension direction, and wherein the doping concentration of the body region (135) is greater than the doping concentration of the second region (132).

6. The semiconductor device (100) of claim 3, wherein the second transistor portion (130) further comprises a source metal (137) connected to the first source region, and a body metal (138) connected to the body region (135), the body metal (138) further connected to the source metal (137) and ground.

7. The semiconductor device (100) according to any one of claims 1 to 6 further includes a third transistor portion (140) axially symmetrical to the first transistor portion (120), the third transistor portion (140) being located on the substrate (110) to form another first-type transistor structure, the other first-type transistor structure and the first-type transistor structure constituting a first-type transistor.

8. The semiconductor device (100) according to any one of claims 1 to 6 further includes a fourth transistor portion (150) axially symmetrical to the second transistor portion (130), the fourth transistor portion (150) being located on the substrate (110) to form another second-type transistor structure, the other second-type transistor structure and the second-type transistor structure constituting a second-type transistor.

9. The semiconductor device (100) according to any one of claims 1 to 6, wherein the first type transistor comprises a junction field effect transistor, and the second type transistor comprises a laterally diffused metal oxide semiconductor transistor.

10. The semiconductor device (100) according to any one of claims 1 to 6, wherein the first doping type is P-type, and the second doping type is N-type.

11. A method for manufacturing a semiconductor device, comprising: forming a substrate (110) of a first doping type, Performing an implantation of a second doping type on the substrate (110) to form a drift region; Performing an implantation of a first doping type in the drift region using a first mask to form a well region, wherein the well region is in contact with the substrate (110); Performing implantation of a second doping type in the drift region and the well region using a second mask to form a first doping region (133) in the drift region on one side of the well region, a second doping region (123) and a third doping region (124) in the drift region on the other side of the well region, and a fourth doping region (134) in the well region; and Implantation of a first doping type is performed in the well region and the drift region using a third mask to form a first gate region (125) in the drift region and integrally form a body region (135) and a second gate region (126) in the well region.

12. The method according to claim 11, wherein: The first doped region (133) is a first drain region and is connected to a first drain metal (139); The second doped region (123) is a second drain region and is connected to a second drain metal (129); The third doping region (124) is a second source region; and The fourth doping region (134) is a first source region.

13. The method according to claim 11, further comprising: performing local silicon oxidation on the drift region using a fourth mask to form a silicon oxide layer; performing gate oxidation and polysilicon deposition on the drift region, the well region, and the silicon oxide layer; as well as Polysilicon etching and reoxidation are performed using a fifth mask to form a gate (136) and a field plate (127).

14. The method according to claim 11, wherein: A blanket implantation of a second doping type is performed on the substrate (110) to form a drift region.

15. The method according to claim 11, wherein: Performing implantation of the first doping type in the drift region using a first mask to form the well region further comprises: bringing the well region into contact with the substrate (110) by thermal driving.

16. An integrated circuit comprising the semiconductor device (100) according to any one of claims 1 to 10.

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