Power device and method for manufacturing a power device

By setting a ramp structure on the sidewalls of the p-type gate layer and the gate electrode layer, the problems of voltage withstand capability and field plate metal etching in p-GaN gate power devices are solved, thereby improving the device's voltage withstand capability and optimizing its performance.

CN118299415BActive Publication Date: 2026-07-24XIAMEN SANAN INTEGRATED CIRCUIT CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
XIAMEN SANAN INTEGRATED CIRCUIT CO LTD
Filing Date
2024-03-29
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

Existing p-GaN gate power devices suffer from problems such as the inability of the metal-P-GaN contact structure to withstand high voltage, the limited number of two-dimensional electrons in the PN junction depletion gas, large gate leakage current, and electric field concentration in the corners, which lead to reduced device withstand voltage and incomplete or broken field plate metal etching.

Method used

A ramp structure is set on the sidewalls of the p-type gate layer and the gate electrode layer to optimize the electric field distribution at the gate corner. The ramped p-type gate layer reduces the concentration of two-dimensional electron gas and increases the on-resistance, thereby reducing gate leakage and avoiding incomplete etching or breakage of the field plate metal.

Benefits of technology

The electric field distribution at the gate corner was optimized, which improved the device breakdown voltage. The field plate structure was also optimized to ensure device performance. In addition, the leakage path length was reduced, avoiding problems such as incomplete metal etching or breakage.

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Abstract

Embodiments of the present application provide a power device and a preparation method thereof, and relate to the technical field of semiconductors, and the power device comprises a compound semiconductor composite layer, a p-type gate layer, a source, a drain and a gate electrode layer, the p-type gate layer, the source and the drain are all arranged on the compound semiconductor composite layer; the gate electrode layer is arranged on the p-type gate layer; wherein the sidewall of the p-type gate layer close to the side of the drain comprises a p-type gate slope, and the p-type gate slope is arranged to be inclined towards the source relative to the surface of the compound semiconductor composite layer. Compared with the prior art, the present application can optimize the gate corner electric field distribution, improve the device withstand voltage, and optimize the field plate structure near the gate to ensure the device performance.
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