Low power consumption oscillator circuit and electronic device
By designing a low-power oscillator circuit combining the comparator input stage, the problems of high power consumption, poor stability and large temperature drift in the prior art are solved, and the balance of low power consumption, high stability and low temperature drift are achieved, and the accuracy of the oscillator is improved through current source adjustment.
Patent Information
- Application Number
- CN202310009553.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-04
- Publication Date
- 2025-04-11
- Estimated Expiration
- 2043-01-04
AI Technical Summary
Existing oscillators have problems such as high power consumption, poor stability, and large temperature drift, making it difficult to take into account low power consumption, high stability and low temperature drift.
A low-power oscillator circuit is designed, including a first comparator, a second comparator, a first charge and discharge module, a second charge and discharge module and a charge and discharge control signal generation module. By combining the input stages of the two comparators, the output circuit of the comparator is saved, and the oscillator accuracy is adjusted through on-chip current source.
It achieves a low-power design while taking into account both stability and temperature drift, and improves the accuracy of the oscillator through current source adjustment.
Smart Images
Figure CN118300532B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a low-power oscillator circuit and electronic equipment. Background Art
[0002] An oscillator is an electronic component used to generate repetitive electronic signals (usually sine waves or square waves). The circuit it forms is called an oscillation circuit, which can convert direct current into an alternating current signal with a certain frequency. It is widely used in the electronics industry, medical treatment, scientific research, etc. Oscillators can be divided into self-excited oscillators and externally excited oscillators according to the oscillation excitation method; they can be divided into resistor-capacitor oscillators, inductor-capacitor oscillators, crystal oscillators, tuning fork oscillators, etc. according to the circuit structure; they can be divided into sine wave, square wave, sawtooth wave and other oscillators according to the output waveform.
[0003] Existing oscillators generally have problems such as high power consumption, poor stability, and large temperature drift. Therefore, how to solve the above problems has become one of the issues that technical personnel in this field need to solve urgently.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a low-power oscillator circuit and an electronic device, so as to solve the problem that low power consumption, high stability and low temperature drift cannot be taken into account in the prior art.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides a low-power oscillator circuit, which at least includes:
[0007] A first comparator, a second comparator, a first charge and discharge module, a second charge and discharge module, and a charge and discharge control signal generating module;
[0008] The first charge and discharge module charges and discharges based on the output signal of the charge and discharge control signal generating module, and generates a corresponding first voltage; the second charge and discharge module charges and discharges based on the output signal of the charge and discharge control signal generating module, and generates a corresponding second voltage; the charge and discharge states of the first charge and discharge module are opposite to those of the second charge and discharge module;
[0009] The input terminal of the first comparator is respectively connected to the first voltage and the reference voltage, and outputs a first comparison result;
[0010] The input terminal of the second comparator is respectively connected to the second voltage and the reference voltage, and outputs a second comparison result;
[0011] The input end of the charge and discharge control signal generating module is respectively connected to the first comparison result and the second comparison result, and outputs the first charge and discharge control signal and the second charge and discharge control signal for controlling the charging and discharging of the first charge and discharge module and the second charge and discharge module, and an oscillation signal; wherein the first charge and discharge control signal and the second charge and discharge control signal are inverted to each other.
[0012] Optionally, the first comparator includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first current source and a second current source; the sources of the first NMOS tube and the second NMOS tube are grounded via the first current source; the gate of the first NMOS tube is connected to the first voltage, and the drain is connected to the drain and gate of the first PMOS tube; the source of the first PMOS tube is connected to the power supply voltage; the gate of the second PMOS tube is connected to the gate of the first PMOS tube, the source is connected to the power supply voltage, the drain outputs the first comparison result and is grounded via the second current source; the gate of the second NMOS tube is connected to the reference voltage, and the drain is connected to the gate and drain of the third PMOS tube; the source of the third PMOS tube is connected to the power supply voltage.
[0013] More optionally, the second comparator includes a third NMOS tube, a fourth NMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third current source and a fourth current source; the sources of the third NMOS tube and the fourth NMOS tube are grounded via the third current source; the gate of the third NMOS tube is connected to the second voltage, and the drain is connected to the drain and gate of the fourth PMOS tube; the source of the fourth PMOS tube is connected to the power supply voltage; the gate of the fifth PMOS tube is connected to the gate of the fourth PMOS tube, the source is connected to the power supply voltage, the drain outputs the second comparison result and is grounded via the fourth current source; the gate of the fourth NMOS tube is connected to the reference voltage, and the drain is connected to the gate and drain of the sixth PMOS tube; the source of the sixth PMOS tube is connected to the power supply voltage.
[0014] More optionally, the third PMOS tube and the sixth PMOS tube are the same PMOS tube.
[0015] Optionally, the first charging and discharging module includes a fifth current source, a first switch, a second switch and a first capacitor;
[0016] One end of the first switch is connected to the fifth current source, the other end is connected to the upper plate of the first capacitor and outputs the first voltage, and the control end is connected to the second charge and discharge control signal; the lower plate of the first capacitor is grounded;
[0017] The second switch is connected in parallel to both ends of the first capacitor, and a control end thereof is connected to the first charge and discharge control signal.
[0018] More optionally, the second charge and discharge module includes a sixth current source, a third switch, a fourth switch and a second capacitor;
[0019] One end of the third switch is connected to the sixth current source, the other end is connected to the upper plate of the second capacitor and outputs the second voltage, and the control end is connected to the first charge and discharge control signal; the lower plate of the second capacitor is grounded;
[0020] The fourth switch is connected in parallel to both ends of the second capacitor, and a control end thereof is connected to the second charge and discharge control signal.
[0021] More optionally, the low power consumption oscillator circuit further includes a current source trimming module, a seventh PMOS tube, an eighth PMOS tube and a ninth PMOS tube;
[0022] The current source adjustment module comprises n parallel current source branches, each of which comprises a current source and a switch connected in series, and a current output of a corresponding magnitude is set by turning on and off each switch; one end of each current source branch is connected to the drain and the gate of the seventh PMOS tube, and the other end is grounded; n is a natural number greater than 1;
[0023] The source of the seventh PMOS tube is connected to the power supply voltage; the eighth PMOS tube serves as the fifth current source, the source is connected to the power supply voltage, the gate is connected to the gate of the seventh PMOS tube, and the drain is connected to the first switch; the ninth PMOS tube serves as the sixth current source, the source is connected to the power supply voltage, the gate is connected to the gate of the seventh PMOS tube, and the drain is connected to the third switch.
[0024] More optionally, the fifth current source and the sixth current source both include a series of resistor strings, and a switch is connected in parallel to both ends of each resistor in the resistor string, and the current output of corresponding magnitude is set by turning on and off each switch.
[0025] Optionally, the charge and discharge control signal generating module includes an RS trigger and an inverter;
[0026] The set end of the RS trigger is connected to the second comparison result, the reset end is connected to the first comparison result, the positive output end outputs the first charge and discharge control signal, and the negative output end outputs the second charge and discharge control signal;
[0027] The input end of the inverter is connected to the positive phase output end of the RS trigger to output the oscillation signal.
[0028] To achieve the above-mentioned object and other related objects, the present invention further provides an electronic device, which at least includes: the above-mentioned low-power oscillator circuit.
[0029] As described above, the low power consumption oscillator circuit and electronic device of the present invention have the following beneficial effects:
[0030] Compared with the traditional dual-comparator oscillator circuit, the low-power oscillator circuit and electronic device of the present invention combine the input stages of two comparators, saving one output of each of the two comparators, achieving low-power design while taking into account stability and temperature drift, and adding on-chip current source adjustment to adjust the oscillator accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 Shown is a structural schematic diagram of the low power consumption oscillator circuit of the present invention.
[0032] Figure 2 Shown is another structural schematic diagram of the low power consumption oscillator circuit of the present invention.
[0033] Figure 3 Shown is another structural schematic diagram of the low power consumption oscillator circuit of the present invention.
[0034] Figure 4 It is a schematic structural diagram of the fifth current source and the sixth current source of the present invention.
[0035] Component number description
[0036] 1 Low power oscillator circuit
[0037] 11. First comparator
[0038] 12 Second comparator
[0039] 13. The first charging and discharging module
[0040] 14. Second charge and discharge module
[0041] 15. Charge and discharge control signal generation module
[0042] 151 RS flip-flop
[0043] 152 Inverter
[0044] 16 Current source trim module DETAILED DESCRIPTION
[0045] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0046] See also Figure 1 to Figure 4 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0047] Embodiment 1
[0048] like Figure 1 As shown, this embodiment provides a low-power oscillator circuit 1, and the low-power oscillator circuit 1 includes:
[0049] A first comparator 11 , a second comparator 12 , a first charge and discharge module 13 , a second charge and discharge module 14 and a charge and discharge control signal generating module 15 .
[0050] like Figure 1 As shown, the input terminals of the first comparator 11 are respectively connected to the first voltage VC1 output by the first charge and discharge module 13 and the reference voltage VREF, and output a first comparison result Q1.
[0051] Specifically, in this embodiment, the first comparator 11 includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first current source I1, and a second current source I2. The source of the first NMOS transistor NM1 is grounded via the first current source I1, the gate is connected to the first voltage VC1, and the drain is connected to the drain and gate of the first PMOS transistor PM1. The source of the first PMOS transistor PM1 is connected to the power supply voltage VCC. The source of the second PMOS transistor PM2 is connected to the power supply voltage VCC, the gate is connected to the gate of the first PMOS transistor PM1, and the drain outputs the first comparison result Q1 and is grounded via the second current source I2. The source of the second NMOS transistor NM2 is grounded via the first current source I1, the gate is connected to the reference voltage VREF, and the drain is connected to the gate and drain of the third PMOS transistor PM3. The source of the third PMOS transistor PM3 is connected to the power supply voltage VCC. The first PMOS transistor PM1 and the second PMOS transistor PM2 constitute a current mirror load of the first comparator 11 .
[0052] It should be noted that, in actual use, any circuit structure that can compare the first voltage VC1 with the reference voltage and generate a comparison result is applicable to the first comparator 11 of the present invention, and is not limited to this embodiment.
[0053] like Figure 1 As shown, the input terminals of the second comparator 12 are respectively connected to the second voltage VC2 output by the second charge and discharge module 14 and the reference voltage VREF, and outputs a second comparison result Q2.
[0054] Specifically, in this embodiment, the second comparator 12 includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third current source I3, and a fourth current source I4. The source of the third NMOS transistor NM3 is grounded via the third current source I3, the gate is connected to the second voltage VC2, and the drain is connected to the drain and gate of the fourth PMOS transistor PM4. The source of the fourth PMOS transistor PM4 is connected to the power supply voltage VCC. The source of the fifth PMOS transistor PM5 is connected to the power supply voltage VCC, the gate is connected to the gate of the fourth PMOS transistor PM4, and the drain outputs the second comparison result Q2 and is grounded via the fourth current source I4. The source of the fourth NMOS transistor NM4 is grounded via the third current source I3, the gate is connected to the reference voltage VREF, and the drain is connected to the gate and drain of the sixth PMOS transistor PM6. The source of the sixth PMOS transistor PM6 is connected to the power supply voltage VCC. The fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 constitute a current mirror load of the second comparator 12 .
[0055] It should be noted that, in actual use, any circuit structure that can compare the second voltage VC2 with the reference voltage and generate a comparison result is applicable to the second comparator 12 of the present invention, and is not limited to this embodiment. As an example, the third PMOS transistor PM3 and the sixth PMOS transistor PM6 are the same PMOS transistor.
[0056] like Figure 1 As shown, the first charge and discharge module 13 charges and discharges based on the output signal of the charge and discharge control signal generating module 15, and generates a corresponding first voltage VC1.
[0057] Specifically, in this embodiment, the first charge and discharge module 13 includes a fifth current source, a first switch SW1, a second switch SW2 and a first capacitor C1. One end of the first switch SW1 is connected to the fifth current source, the other end is connected to the upper plate of the first capacitor C1 and outputs the first voltage VC1, and the control end is connected to the second charge and discharge control signal Q4. The lower plate of the first capacitor C1 is grounded. The second switch SW2 is connected in parallel to both ends of the first capacitor C1, and the control end is connected to the first charge and discharge control signal Q3.
[0058] like Figure 1 As shown, the second charge and discharge module 14 charges and discharges based on the output signal of the charge and discharge control signal generating module 15, and generates a corresponding second voltage VC2.
[0059] Specifically, in this embodiment, the second charge and discharge module 14 includes a sixth current source, a third switch SW3, a fourth switch SW4 and a second capacitor C2. One end of the third switch SW3 is connected to the sixth current source, the other end is connected to the upper plate of the second capacitor C2 and outputs the second voltage VC2, and the control end is connected to the first charge and discharge control signal Q3. The lower plate of the second capacitor C2 is grounded. The fourth switch SW4 is connected in parallel to both ends of the second capacitor C2, and the control end is connected to the second charge and discharge control signal Q4.
[0060] It should be noted that the charging and discharging states of the first charging and discharging module 13 and the second charging and discharging module 14 are opposite, that is, when the first voltage VC1 is at a low level, the second voltage VC2 is at a high level, and when the first voltage VC1 is at a high level, the second voltage VC2 is at a low level.
[0061] In this embodiment, the fifth current source and the sixth current source are adjustable current sources. Figure 1As shown, the low-power oscillator circuit 1 also includes a current source adjustment module 16, a seventh PMOS tube PM7, an eighth PMOS tube PM8 and a ninth PMOS tube PM9. The current source adjustment module 16 includes n parallel current source branches, where n is a natural number greater than 1; each current source branch includes a current source and a switch connected in series, and the corresponding current output is set by turning on and off each switch (S0, S1, S2...Sn-1). As an example, the magnitude of the current in each current source branch decreases by 2 times. In actual use, the magnitude of the current in each current source branch can be set as needed, not limited to this embodiment. One end of each current source branch is connected to the drain and gate of the seventh PMOS tube PM7, and the other end is grounded. The source of the seventh PMOS transistor PM7 is connected to the power supply voltage VCC; the eighth PMOS transistor PM8 is used as the fifth current source, the source is connected to the power supply voltage VCC, the gate is connected to the gate of the seventh PMOS transistor PM7, and the drain is connected to the first switch SW1; the ninth PMOS transistor PM9 is used as the sixth current source, the source is connected to the power supply voltage VCC, the gate is connected to the gate of the seventh PMOS transistor PM7, and the drain is connected to the third switch SW3. The seventh PMOS transistor PM7, the eighth PMOS transistor PM8 and the ninth PMOS transistor PM9 form a current mirror structure.
[0062] It should be noted that, in actual use, the fifth current source and the sixth current source may also be current sources with fixed current values, and are not limited to this embodiment.
[0063] like Figure 1 As shown, the input end of the charge and discharge control signal generating module 15 is respectively connected to the first comparison result Q1 and the second comparison result Q2, and outputs the first charge and discharge control signal Q3 and the second charge and discharge control signal Q4 for controlling the charging and discharging of the first charge and discharge module 13 and the second charge and discharge module 14, as well as the oscillation signal CLK; wherein the first charge and discharge control signal Q3 and the second charge and discharge control signal Q4 are inverted to each other.
[0064] Specifically, in this embodiment, the charge and discharge control signal generating module 15 includes an RS trigger 151 and an inverter 152. The set end of the RS trigger 151 is connected to the second comparison result Q2, the reset end is connected to the first comparison result Q1, the positive phase output end outputs the first charge and discharge control signal Q3, and the negative phase output end outputs the second charge and discharge control signal Q4. The input end of the inverter 152 is connected to the positive phase output end of the RS trigger 151, and outputs the oscillation signal CLK.
[0065] like Figure 1As shown, in the low-power oscillator circuit of the present invention, the first comparator 11 and the second comparator 12 detect the voltage on the first capacitor C1 and the second capacitor C2 based on the reference voltage VREF, so that the output logic levels Q1 and Q2 of the comparator jump, and then output logic signals Q3 and Q4 through an RS trigger to control the charging and discharging process of the first capacitor C1 and the second capacitor C2, forming positive feedback to make the circuit reach the oscillation condition, and output a stable clock signal CLK. The oscillation frequency of the low-power oscillator circuit of the present invention is mainly related to the capacitance of C1 / C2, the voltage value of VREF and the charging current provided by the fifth current source / sixth current source. Compared with the traditional dual-comparator oscillator circuit, the present invention combines the input stages of two comparators, saves one output of the two comparators, realizes low-power design while taking into account stability and temperature drift, and adds on-chip current source adjustment to adjust the oscillator accuracy.
[0066] Embodiment 2
[0067] like Figure 2 As shown, this embodiment provides a low-power oscillator circuit 1, which is different from the first embodiment in that the current source in this embodiment is implemented by a common-source and common-gate current source.
[0068] Specifically, one end of the bias current source IB is connected to the power supply voltage VCC, and the other end is connected to the drain of the fifth NMOS tube NM5 via the resistor R1. The gate of the fifth NMOS tube NM5 is connected to the connection node of the bias current source IB and the resistor R1, and the source is connected to the drain of the sixth NMOS tube NM6. The gate of the sixth NMOS tube NM6 is connected to the drain of the fifth NMOS tube NM5, and the source is grounded.
[0069] Specifically, the seventh NMOS tube NM7 and the eighth NMOS tube NM8 constitute a current source of a cascode structure; the ninth NMOS tube NM9 and the tenth NMOS tube NM10 constitute a current source of a cascode structure; the eleventh NMOS tube NM11 and the twelfth NMOS tube NM12 constitute a current source of a cascode structure; the thirteenth NMOS tube NM13 and the fourteenth NMOS tube NM14 constitute a current source of a cascode structure; and serve as the current source in each current source branch in the current source adjustment module 16. The fifteenth NMOS tube NM15 and the sixteenth NMOS tube NM16 constitute a current source of a cascode structure and serve as the second current source I2. The seventeenth NMOS tube NM17 and the eighteenth NMOS tube NM18 constitute a current source of a cascode structure and serve as the first current source I1. The nineteenth NMOS tube NM19 and the twentieth NMOS tube NM20 constitute a current source of a cascode structure and serve as the third current source I3. The twenty-first NMOS transistor NM21 and the twenty-second NMOS transistor NM22 form a current source of a cascode structure and serve as a fourth current source I4.
[0070] It should be noted that, in actual use, any current source structure is applicable to the present invention, which will not be described in detail here.
[0071] Embodiment 3
[0072] like Figure 3 As shown, this embodiment provides a low power consumption oscillator circuit 1, which is different from the first and second embodiments in that this embodiment uses R-ray resistor form adjustment.
[0073] Specifically, in this embodiment, the current source trimming module 16 is removed; Figure 4 As shown, the fifth current source I5 and the sixth current source I6 both include a series resistor string. In this example, the number of resistors is set to n, where n is a natural number greater than 1. A switch is connected in parallel to both ends of each resistor in the resistor string, and the corresponding current output is set by turning on and off each switch (S0, S1, S2...Sn-1). As an example, the size of each resistor decreases by 2 times. In actual use, the size of each resistor can be set as needed, not limited to this embodiment.
[0074] Embodiment 4
[0075] This embodiment provides an electronic device, which at least includes the low-power oscillator circuit 1 as described in Embodiment 1, 2, or 3. The low-power oscillator circuit 1 can provide a clock signal with low power consumption, high precision, high stability and low temperature drift for the circuit in the electronic device, and the specific structure and principle are not described in detail here.
[0076] In summary, the present invention provides a low-power oscillator circuit and electronic equipment, including: a first comparator, a second comparator, a first charge and discharge module, a second charge and discharge module and a charge and discharge control signal generating module; the first charge and discharge module is charged and discharged based on the output signal of the charge and discharge control signal generating module, and generates a corresponding first voltage; the second charge and discharge module is charged and discharged based on the output signal of the charge and discharge control signal generating module, and generates a corresponding second voltage; the charge and discharge state of the first charge and discharge module is opposite to that of the second charge and discharge module; the input end of the first comparator is respectively connected to the first voltage and the reference voltage, and outputs a first comparison result; the input end of the second comparator is respectively connected to the second voltage and the reference voltage, and outputs a second comparison result; the input end of the charge and discharge control signal generating module is respectively connected to the first comparison result and the second comparison result, and outputs a first charge and discharge control signal and a second charge and discharge control signal for controlling the charging and discharging of the first charge and discharge module and the second charge and discharge module, and an oscillation signal; wherein, the first charge and discharge control signal and the second charge and discharge control signal are mutually inverted. Compared with the traditional dual-comparator oscillator circuit, the low-power oscillator circuit and electronic device of the present invention combine the input stages of two comparators, save one output of the two comparators respectively, realize low-power design while taking into account stability and temperature drift, and add on-chip current source adjustment to adjust the oscillator accuracy. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0077] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A low power oscillator circuit, characterized in that: The low power consumption oscillator circuit comprises at least: A first comparator, a second comparator, a first charge and discharge module, a second charge and discharge module, and a charge and discharge control signal generating module; The first charge and discharge module charges and discharges based on the output signal of the charge and discharge control signal generating module, and generates a corresponding first voltage; the second charge and discharge module charges and discharges based on the output signal of the charge and discharge control signal generating module, and generates a corresponding second voltage; the charge and discharge states of the first charge and discharge module are opposite to those of the second charge and discharge module; The input end of the first comparator is respectively connected to the first voltage and the reference voltage, and outputs the first comparison result; wherein the first comparator includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first current source and a second current source; the source of the first NMOS tube and the second NMOS tube is grounded via the first current source; the gate of the first NMOS tube is connected to the first voltage, and the drain is connected to the drain and the gate of the first PMOS tube; the source of the first PMOS tube is connected to the power supply voltage; the gate of the second PMOS tube is connected to the gate of the first PMOS tube, the source is connected to the power supply voltage, and the drain outputs the first comparison result and is grounded via the second current source; the gate of the second NMOS tube is connected to the reference voltage, and the drain is connected to the gate and the drain of the third PMOS tube; the source of the third PMOS tube is connected to the power supply voltage; The input end of the second comparator is respectively connected to the second voltage and the reference voltage, and outputs a second comparison result, wherein the second comparator includes a third NMOS tube, a fourth NMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third current source and a fourth current source; the sources of the third NMOS tube and the fourth NMOS tube are grounded via the third current source; the gate of the third NMOS tube is connected to the second voltage, and the drain is connected to the drain and gate of the fourth PMOS tube; the source of the fourth PMOS tube is connected to the power supply voltage; the gate of the fifth PMOS tube is connected to the gate of the fourth PMOS tube, the source is connected to the power supply voltage, and the drain outputs the second comparison result and is grounded via the fourth current source; the gate of the fourth NMOS tube is connected to the reference voltage, and the drain is connected to the gate and drain of the sixth PMOS tube; the source of the sixth PMOS tube is connected to the power supply voltage; the third PMOS tube and the sixth PMOS tube are the same PMOS tube; The input end of the charge and discharge control signal generating module is respectively connected to the first comparison result and the second comparison result, and outputs the first charge and discharge control signal and the second charge and discharge control signal for controlling the charging and discharging of the first charge and discharge module and the second charge and discharge module, and an oscillation signal; wherein the first charge and discharge control signal and the second charge and discharge control signal are inverted to each other.
2. The low power consumption oscillator circuit according to claim 1, characterized in that: The first charge and discharge module includes a fifth current source, a first switch, a second switch and a first capacitor; One end of the first switch is connected to the fifth current source, the other end is connected to the upper plate of the first capacitor and outputs the first voltage, and the control end is connected to the second charge and discharge control signal; the lower plate of the first capacitor is grounded; The second switch is connected in parallel to both ends of the first capacitor, and a control end thereof is connected to the first charge and discharge control signal.
3. The low power consumption oscillator circuit according to claim 2, characterized in that: The second charge and discharge module includes a sixth current source, a third switch, a fourth switch and a second capacitor; One end of the third switch is connected to the sixth current source, the other end is connected to the upper plate of the second capacitor and outputs the second voltage, and the control end is connected to the first charge and discharge control signal; the lower plate of the second capacitor is grounded; The fourth switch is connected in parallel to both ends of the second capacitor, and a control end thereof is connected to the second charge and discharge control signal.
4. The low power consumption oscillator circuit according to claim 3, characterized in that: The low power consumption oscillator circuit further includes a current source trimming module, a seventh PMOS tube, an eighth PMOS tube and a ninth PMOS tube; The current source adjustment module comprises n parallel current source branches, each of which comprises a current source and a switch connected in series, and a current output of a corresponding magnitude is set by turning on and off each switch; one end of each current source branch is connected to the drain and the gate of the seventh PMOS tube, and the other end is grounded; n is a natural number greater than 1; The source of the seventh PMOS tube is connected to the power supply voltage; the eighth PMOS tube serves as the fifth current source, the source is connected to the power supply voltage, the gate is connected to the gate of the seventh PMOS tube, and the drain is connected to the first switch; the ninth PMOS tube serves as the sixth current source, the source is connected to the power supply voltage, the gate is connected to the gate of the seventh PMOS tube, and the drain is connected to the third switch.
5. The low power consumption oscillator circuit according to claim 3, characterized in that: The fifth current source and the sixth current source both include a series of resistor strings, and a switch is connected in parallel to both ends of each resistor in the resistor string. The current output of corresponding magnitude is set by turning on and off each switch.
6. The low power consumption oscillator circuit according to claim 1, characterized in that: The charge and discharge control signal generating module includes an RS trigger and an inverter; The set end of the RS trigger is connected to the second comparison result, the reset end is connected to the first comparison result, the positive output end outputs the first charge and discharge control signal, and the negative output end outputs the second charge and discharge control signal; The input end of the inverter is connected to the positive phase output end of the RS trigger to output the oscillation signal.
7. An electronic device, characterized in that: The electronic device comprises at least: a low-power oscillator circuit as described in any one of claims 1-6.
Citation Information
Patent Citations
Low-power consumption double-capacitance spread type CMOS oscillator
CN101257289A
Calibrated relaxation oscillator using a pll
CN102934363A