A printed circuit board and an inverter

Abstract

This application provides a printed circuit board and an inverter. The printed circuit board includes at least a plurality of wiring layers arranged along a third direction, wherein a first metal region is formed in one wiring layer and a second metal region is formed in another wiring layer; the projection of the first metal region along the third direction and the projection of the second metal region along the third direction have an overlapping area; and the angle between the current direction of the first metal region corresponding to the overlapping area and the current direction of the second metal region corresponding to the overlapping area is greater than 90 degrees; the printed circuit board is used to form a multi-level circuit, which performs a current loop switching operation after triggering a current limiting point. During the current loop switching operation, current exists in both the first metal region and the second metal region, and the angle between the current directions is greater than 90 degrees, thereby canceling out the current magnetic fields of the first metal region and the second metal region, reducing line noise and reducing reverse peaks.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more particularly to a printed circuit board and an inverter. Background Technology

[0002] An inverter is a converter that transforms direct current (DC) energy into alternating current (AC) energy through the switching on and off of semiconductor power switching devices, including multi-level circuits. During operation, if the multi-level conversion circuit reaches its current-limiting point, a current loop switching will occur. This process may result in significant reverse peaks, damaging the switching devices in the multi-level conversion circuit, which is a problem that urgently needs to be solved. Summary of the Invention

[0003] This application provides a printed circuit board and an inverter.

[0004] The technical solution of this application is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a printed circuit board, the printed circuit board including at least a plurality of wiring layers arranged along a third direction, wherein a first metal region is formed in one wiring layer and a second metal region is formed in another wiring layer; the projection of the first metal region along the third direction and the projection of the second metal region along the third direction have an overlapping area; and the angle between the current direction of the first metal region corresponding to the overlapping area and the current direction of the second metal region corresponding to the overlapping area is greater than 90 degrees; the printed circuit board is used to form a multi-level circuit, the multi-level circuit performing a current loop switching operation after triggering a current limiting point, and during the current loop switching operation, current exists in both the first metal region and the second metal region.

[0006] In this way, during the switching operation of the current loop, there is current in both the first metal region and the second metal region, and the angle between the current directions is greater than 90 degrees. As a result, the current magnetic fields in the first metal region and the second metal region cancel each other out, reducing line inductance and lowering reverse peaks.

[0007] In some embodiments, the output of the multilevel circuit includes a first level, a mid-level, and a second level. After the multilevel circuit triggers a current limiting point, at least one main switching device is turned off, causing the multilevel circuit to switch from the current current loop to a mid-level freewheeling loop. At least one freewheeling switching device is also turned off, causing the multilevel circuit to switch from a mid-level freewheeling loop to a reverse freewheeling loop. The switching device located on the mid-level channel serves as the freewheeling switching device, and the switching device located on the first or second level channel serves as the main switching device. When the current current loop is the first level channel, the reverse freewheeling loop is a freewheeling loop passing through the main switching device on the second level channel; when the current level path is the second level channel, the reverse freewheeling loop is a freewheeling loop passing through the main switching device on the first level channel. The mid-level freewheeling loop refers to the loop between the bus capacitor, the freewheeling switching device, and the main switching device. The first metal area is used to form the electrical path between the freewheeling switching devices, and the second metal area is used to form the electrical path between the AC terminal of the multilevel circuit and at least one of the switching devices.

[0008] In this way, both the first and second metal regions are electrical paths between the intermediate freewheeling circuits. Therefore, current exists throughout the entire switching operation of the current circuit, which can provide current cancellation throughout the switching process, effectively reducing line noise and reducing reverse peaks.

[0009] In some embodiments, in the printed circuit board, a third metal region is formed in one of the wiring layers and a fourth metal region is formed in another wiring layer; the third metal region and the fourth metal region are connected in parallel to form an electrical path between the bus capacitor and the freewheeling switch device, and the electrical path formed by the third metal region and the fourth metal region also belongs to the intermediate freewheeling circuit.

[0010] In this way, since the third metal region and the fourth metal region are connected in parallel to form the same electrical path, the overall inductance after the two paths are connected in parallel is reduced, thus reducing the reverse peak.

[0011] In some embodiments, the multilevel circuit further includes decoupling capacitors, each of which is connected between a freewheeling switch and a main switch, and one of the decoupling capacitors is connected in parallel with one of the bus capacitors. The decoupling capacitors are used to shorten the commutation path of the switching process of the current loop.

[0012] In this way, the decoupling capacitor is used to shorten the commutation path in the switching process from one current loop to another, reduce the stray inductance of the path in the commutation process, thereby reducing reverse peaks and improving device lifespan.

[0013] In some embodiments, when the multilevel circuit is a T-type topology, the multilevel circuit includes four switching devices, two bus capacitors, and two decoupling capacitors. The first and fourth switching devices are connected in series to form a vertical bridge arm, the second and third switching devices are connected in series to form a horizontal bridge arm, and the first and second bus capacitors are connected in series to form a capacitor bridge arm. The common point of the first and fourth switching devices serves as the AC terminal of the multilevel circuit, and the common point of the first and second bus capacitors serves as the midpoint. The two free ends of the vertical bridge arm are connected in parallel to the two free ends of the capacitor bridge arm, and the first end of the horizontal bridge arm is connected to the midpoint, and the second end is connected to the AC terminal. The first decoupling capacitor... A capacitor is connected across one free end of the vertical tube bridge arm and the first end of the horizontal tube bridge arm; a second decoupling capacitor is connected across the other free end of the vertical tube bridge arm and the first end of the horizontal tube bridge arm; the first and fourth switching devices are both main switching devices, and the second and third switching devices are both freewheeling switching devices; the first metal region is used to form an electrical path between the second and third switching devices, the second metal region is used to form an electrical path between the third switching device, the first switching device, and the fourth switching device, and the third and fourth metal regions are connected in parallel to form an electrical path between the first bus capacitor, the second bus capacitor, and the second switching device.

[0014] In some embodiments, when the multilevel circuit is a type I topology connection, the multilevel circuit includes six switching devices, two bus capacitors, and two decoupling capacitors. The first to fourth switching devices are connected in series to form a first vertical bridge arm; the fifth and sixth switching devices are connected in series to form a second vertical bridge arm; the first and second bus capacitors are connected in series to form a capacitor bridge arm; the common point of the second and third switching devices serves as the AC terminal; the common point of the first and second bus capacitors serves as the midpoint; the two free ends of the first vertical bridge arm are respectively connected in parallel to the two free ends of the capacitor bridge arm; one free end of the second vertical bridge arm is connected to the common point of the first and second switching devices; the other free end of the second vertical bridge arm is connected to the common point of the third and fourth switching devices; the common point of the fifth and sixth switching devices is connected to the midpoint; the first decoupling capacitor is connected across the... The first vertical tube bridge arm has one free end and the second vertical tube bridge arm has one common end. A second decoupling capacitor is connected across the other free end of the first vertical tube bridge arm and the common end of the second vertical tube bridge arm. The second, third, fifth, and sixth switching devices are all freewheeling switching devices, and the first and fourth switching devices are both main switching devices. There are two first metal regions. The first first metal region is used to form an electrical path between the first, second, and fifth switching devices, and the second first metal region is used to form an electrical path between the third, fourth, and sixth switching devices. The second metal region forms an electrical path between the second and third switching devices. The third and fourth metal regions are connected in parallel to form an electrical path between the first bus capacitor, the second bus capacitor, the fifth switching device, and the sixth switching device.

[0015] In some embodiments, the printed circuit board includes a bottom wiring layer, a second intermediate wiring layer, a first intermediate wiring layer, and a top wiring layer arranged sequentially along a third direction; the second metal region and the third metal region are both located on the bottom wiring layer, the fourth metal region is located on the second intermediate wiring layer, and the first metal region is located on the first intermediate wiring layer; the bottom wiring layer further includes a fifth metal region, which is used to form an electrical path between the first switching device and the first bus capacitor; the third metal region, the first metal region, and the fifth metal region are arranged along a first direction; the first intermediate wiring layer further includes a sixth metal region, which is used to form an electrical path between the first switching device and the fourth switching device; the second metal region and the sixth metal region are arranged along the first direction; the top wiring layer further includes a seventh metal region, which is used to form an electrical path between the fourth switching device and the second bus capacitor.

[0016] In this way, the wiring layers containing the third and fourth metal regions are adjacent, resulting in shorter parallel paths and facilitating current flow.

[0017] In some embodiments, the first switching device includes a plurality of switching transistors; the second metal region is connected to one of the switching transistors in the first switching device, and the fifth metal region is connected to all the switching transistors in the first switching device.

[0018] In this way, since the second metal region is connected to at least the first and third switching devices, and the fifth metal region is connected to at least the first switching device, the current flow between the first and third switching devices can be achieved through the second and fifth metal regions of the same wiring layer; if the first switching device is not connected to the first switching device, the current flow between the first and third switching devices needs to be indirectly provided by different metal regions of different wiring layers; that is, this embodiment can shorten the commutation path and avoid wiring interference.

[0019] In some embodiments, the fifth metal region is also connected to the second terminal of the first decoupling capacitor; the fourth metal region is connected to the first terminal of the first decoupling capacitor and the first terminal of the second decoupling capacitor; and the seventh metal region is also connected to the second terminal of the second decoupling capacitor.

[0020] Secondly, embodiments of this application provide an inverter, the inverter including the printed circuit board as described in the first aspect. Attached Figure Description

[0021] Figure 1 A layered schematic diagram of a printed circuit board provided in an embodiment of this application;

[0022] Figure 2A schematic diagram of the circuit structure of the T-type three-level topology provided in the embodiments of this application;

[0023] Figure 3 A commutation diagram of the T-type three-level topology provided in the embodiments of this application. Figure 1 ;

[0024] Figure 4 A commutation diagram of the T-type three-level topology provided in the embodiments of this application. Figure 2 ;

[0025] Figure 5 A schematic diagram of the circuit structure of the Type I three-level topology provided in the embodiments of this application;

[0026] Figure 6 A commutation diagram of the Type I three-level topology provided in the embodiments of this application. Figure 1 ;

[0027] Figure 7 A commutation diagram of the Type I three-level topology provided in the embodiments of this application. Figure 2 ;

[0028] Figure 8 This is a schematic diagram of the five-level topology provided in the embodiments of this application;

[0029] Figure 9 A schematic diagram of the device distribution on a printed circuit board under a T-type three-level topology provided in an embodiment of this application;

[0030] Figures 10A-10D A schematic diagram of the layered structure of a printed circuit board under a T-type three-level topology provided in an embodiment of this application;

[0031] Figure 11 This is a schematic diagram showing the location of the decoupling capacitor in the T-type three-level topology provided in the embodiments of this application;

[0032] Figure 12 This is a schematic diagram showing the location of the decoupling capacitor in the Type I three-level topology provided in the embodiments of this application;

[0033] Figure 13 This is a schematic diagram showing the location of the decoupling capacitors in the five-level topology provided in the embodiments of this application;

[0034] Figure 14 This is a schematic diagram of the structure of a printed circuit board for a multiphase multilevel circuit provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant application and not for limiting the application. It should also be noted that, for ease of description, only the parts related to the relevant application are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this application are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described.

[0036] IGBT (Insulated Gate Bipolar Transistor): Insulated Gate Bipolar Transistor;

[0037] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): A metal-oxide-semiconductor field-effect transistor.

[0038] BJT (Bipolar Junction Transistor): A bipolar junction transistor.

[0039] HBT (Hetero Junction Bipolar Transistor): A heterojunction bipolar transistor.

[0040] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0041] In one embodiment, a printed circuit board 30 is provided for forming a multi-level circuit. A multi-level circuit is a circuit with multiple output levels and can be used in inverters, rectifiers, converters, etc. Taking an inverter as an example, the multi-level circuit is specifically used to convert direct current (DC) to alternating current (AC), and may include a three-level circuit (see reference). Figure 2 , Figure 5 ), five-level circuit (please refer to) Figure 8 Seven-level circuits, etc., will not be listed here one by one.

[0042] It should be understood that when a multilevel circuit reaches its current-limiting point (i.e., excessive current), the switching devices are controlled to switch the current loop through the bus capacitor. During this process, the current through some switching devices rapidly decreases to 0. The rapidly changing dI / dt (the change in current per unit time) generates an induced voltage ΔV when flowing through the stray inductance of the system. The superposition of ΔV and the bus voltage produces a reverse peak, causing the switching devices to bear voltage stress higher than usual, which may cause permanent damage to the switching devices.

[0043] In this disclosure embodiment, please refer to Figure 1 The printed circuit board 30 includes at least a plurality of wiring layers arranged along a third direction, wherein a first metal region 31 is formed in one wiring layer and a second metal region 32 is formed in another wiring layer; the projection of the first metal region 31 along the third direction and the projection of the second metal region 32 along the third direction have an overlapping area; and the angle between the current direction of the first metal region 31 corresponding to the overlapping area and the current direction of the second metal region 32 corresponding to the overlapping area is greater than 90 degrees.

[0044] As mentioned above, the multi-level circuit performs a current loop switching operation after triggering the current limiting point. During the current loop switching operation, current exists in both the first metal region 31 and the second metal region 32. Moreover, the angle between the current directions of the first metal region 31 and the second metal region 32 corresponding to the overlapping area is greater than 90 degrees. That is, the magnetic fields generated by the currents in the two metal regions are superimposed and cancel each other out. As a result, the stray inductance generated by the two regions also cancels each other out, and the induced voltage ΔV is reduced, thereby reducing the reverse peak and avoiding permanent damage to the switching device, thus improving the circuit life.

[0045] It should be understood that Figure 1 This is merely an example of the printed circuit board 30 and does not limit the specific details of the printed circuit board 30. For example, the number of wiring layers, the specific shape of each metal area, the specific location of each metal area in the wiring layers, and which metal areas each metal area is distributed in are all unrestricted.

[0046] Furthermore, the number of first metal regions 31 and second metal regions 32 can each be one or more. Each first metal region 31 overlaps with at least one of the second metal regions 32, and the angle between the current directions corresponding to the overlapping regions is greater than 90 degrees; similarly, each second metal region 32 overlaps with at least one of the first metal regions 31, and the angle between the current directions corresponding to the overlapping regions is greater than 90 degrees. Different first metal regions 31 can be distributed on the same or different wiring layers, and different second metal regions 32 can be distributed on the same or different wiring layers.

[0047] In some embodiments, for a three-level circuit, its output has three levels, which can be represented by a positive level +V, a negative level -V, and a zero level 0V. One of the positive and negative levels is referred to as the first level or the second level, respectively, and the other of the positive and negative levels is referred to as the other of the first level or the second level, respectively. The zero level is located in the middle of the positive and negative levels, so the zero level can also be expressed as the middle level.

[0048] For a five-level circuit, its five output levels can be simply represented by voltages as +2V, +V, 0V, -V, and -2V, respectively. Among them, +2V and 0V are the first level and the second level, respectively. 0V can be the midpoint between +2V and -2V or between +V and -V, and the first level and the second level can be determined accordingly.

[0049] The same principle applies to other types of multilevel circuits.

[0050] Thus, regardless of the type of multilevel circuit, the first level, the middle level, and the second level can be definitively defined in its output level. Based on this, regardless of the type of multilevel circuit, after triggering the current limiting point, the switching process of the current loop includes at least the following two sub-stages:

[0051] Sub-phase 1: Turn off at least one main switching device to switch the multilevel circuit from the current current loop to the intermediate freewheeling loop;

[0052] Sub-phase two: and turn off at least one freewheeling switch device, so that the multi-level circuit switches from the middle freewheeling loop to the reverse freewheeling loop.

[0053] It should be noted that the switching device located on the middle level channel serves as a freewheeling switching device, and the switching device located on the first level channel or the second level channel serves as the main switching device. When the current current loop is the first level channel, the reverse freewheeling loop is the freewheeling loop through the main switching device on the second level channel. When the current level channel is the second level channel, the reverse freewheeling loop is the freewheeling loop through the main switching device on the first level channel. Those skilled in the art will understand that the aforementioned reverse freewheeling loop refers to the current loop formed by the parasitic diode of the main switching device (in some embodiments, it can be an external diode connected in reverse parallel with the main switching device), while the current loop formed by the main switching portion of the main switching device is referred to as the main current loop in this case. The aforementioned multilevel circuit has multiple current loops, specifically including a selectively conducting middle freewheeling loop, a reverse freewheeling loop, and a main current loop.

[0054] In one specific embodiment, the first metal region 31 and the second metal region 32 are present only during the execution of sub-stage one or sub-stage two.

[0055] In another specific embodiment, current exists in the first metal region 31 and the second metal region 32 during the execution of sub-stage one and sub-stage two, that is, current exists in both the first metal region 31 and the second metal region 32 throughout the entire cycle of current loop switching. For example, both the first metal region 31 and the second metal region 32 are located on the middle freewheeling loop, thereby canceling the current magnetic field throughout the entire cycle of current loop switching, minimizing stray inductance and reverse peaks.

[0056] Specifically, the intermediate freewheeling circuit refers to the circuit between the bus capacitor, the freewheeling switch device, and the main switch device. The first metal region 31 is used to form the electrical path between the freewheeling switch devices (see [link]). Figure 2 Path ① in Figure 5 Path ① or Figure 8 The second metal region 32 is used to form the electrical path between the AC terminal of the multi-level circuit (shown as the output point in the figure; in this application, the output point and the AC terminal both represent the same location) and at least one switching device (see path ①). Figure 2 Path ② in Figure 5 Path ② or Figure 8 Paths ② and ②' in the text.

[0057] In some embodiments, see Figure 1 In the printed circuit board 30, a third metal region 33 is formed in one wiring layer, and a fourth metal region 34 is formed in another wiring layer; the third metal region 33 and the fourth metal region 34 are connected in parallel to form the electrical path between the bus capacitor and the freewheeling switch device (see [link]). Figure 2 Path ③ in Figure 5 Path ③ or Figure 8 The path ③ in the middle, and the electrical path formed by the third metal region 33 and the fourth metal also belong to the middle freewheeling loop.

[0058] In other words, a portion of the middle freewheeling circuit can be achieved by connecting two metal regions in parallel (i.e., the third metal region 33 and the fourth metal region 34), which is equivalent to two paths in parallel. Since the inductance of the two inductors in parallel is smaller, the overall inductance of the third metal region 33 and the fourth metal region 34 in parallel is also smaller, which can also provide the effect of reducing reverse peaks.

[0059] It should be noted that the first metal area 31 and the second metal area 32 are located on different wiring layers, and the third metal area 33 and the fourth metal area 34 are located on different wiring layers. The first metal area 31 and the third metal area 33 (or the fourth metal area 34) can be located on the same wiring layer or different wiring layers, and the second metal area 32 and the third metal area 33 (or the fourth metal area 34) can be located on the same wiring layer or different wiring layers.

[0060] The following describes the structure of a printed circuit board 30, specifically a T-type three-level topology, as an example of a multi-level topology.

[0061] Please see Figure 2 The printed circuit board 30 is specifically used to form a multilevel circuit 10a with a T-type three-level topology. The multilevel circuit 10a includes four switching devices and two bus capacitors. The first switching device 11 and the fourth switching device 14 are connected in series to form a vertical tube bridge arm. The second switching device 12 and the third switching device 13 are connected in series to form a horizontal tube bridge arm. The first bus capacitor 15 and the second bus capacitor 16 are connected in series to form a capacitor bridge arm. The common point of the first switching device 11 and the fourth switching device 14 serves as the AC terminal of the multilevel circuit 10a. The common point of the first bus capacitor 15 and the second bus capacitor 16 serves as the midpoint O. The two free ends of the vertical tube bridge arm are connected in parallel to the two free ends of the capacitor bridge arm. The first end of the horizontal tube bridge arm is connected to the midpoint O, and the second end is connected to the AC terminal.

[0062] It should be understood that Figure 1 This example illustrates that the first switching device 11 to the fourth switching device 14 are all IGBT devices. In other embodiments, the first switching device 11 to the fourth switching device 14 can also be formed by other types of switching devices / combinations of switching devices, such as MOS, BJT, HBT, diode, etc. Furthermore, each switching device can include a single transistor or multiple transistors.

[0063] Both the first switching device 11 and the fourth switching device 14 are main switching devices, while the second switching device 12 and the third switching device 13 are both freewheeling switching devices. The first level channel refers to the channel from the free end of the first bus capacitor 15 and the first switching device 11 to the AC terminal; the second level channel is the channel from the free end of the second bus capacitor 16 and the fourth switching device 14 to the AC terminal; and the mid-level channel is the channel from the midpoint O and the horizontal bridge arm to the AC terminal. The reverse freewheeling circuit is the diode freewheeling channel flowing through either the first switching device 11 or the fourth switching device 14.

[0064] The intermediate freewheeling circuit refers to the electrical path between the first bus capacitor 15 and the second bus capacitor 16, which are sequentially connected to the first switch device 11 and the fourth switch device 14 via the second switch device 12 and the third switch device 13, respectively. This electrical path can be divided into segments ①, ②, and ③. The first metal region 31 is used to form the electrical path ① between the second switch device 12 and the third switch device 13. The second metal region 32 is used to form the electrical path ② between the third switch device 13, the first switch device 11, and the fourth switch device 14. The third metal region 33 and the fourth metal region 34 are connected in parallel to form the electrical path ③ between the first bus capacitor 15, the second bus capacitor 16, and the second switch device 12.

[0065] Specifically, please see Figure 3 It illustrates the commutation operation of the T-type topology multilevel circuit 10a after triggering the current limiting point during the positive half-cycle: Specifically:

[0066] Before switching: Before triggering the current limiting point, the current loop of multi-level circuit 10 is as follows: Figure 3 As shown in (a) above, this is the first level channel;

[0067] Sub-phase 1: After triggering the current limiting point, first shut off the vertical pipe, i.e., the first switching device 11. Please refer to [link to relevant documentation]. Figure 3 In (b), the current loop switches to the middle level channel, the horizontal tube, i.e. the second switching device 12, is turned on, and the parasitic diode of the third switching device 13 is turned on.

[0068] Sub-phase two: After the second switching device 12 is stably turned on, continue to turn off the second switching device 12. Please refer to [link to relevant documentation]. Figure 3 In (c), the parasitic diode of the fourth switching device 14 is turned on, i.e., the reverse freewheeling circuit.

[0069] Please see Figure 4 (a)~ Figure 4 (c) illustrates the commutation operation of the T-type topology multilevel circuit 10a after triggering the current limiting point during the negative half-cycle: Specifically:

[0070] Before switching: Before the current limiting point is triggered, the current loop of the multi-level inverter circuit is as follows: Figure 4 As shown in (a), this is the second level channel;

[0071] Sub-phase 1: After triggering the current limiting point, first shut off the vertical pipe, i.e., the fourth switching device 14. Please refer to [link / reference]. Figure 4 (b) At this time, the current loop switches to the middle level channel, the horizontal tube, i.e. the third switching device 13, is turned on, and the parasitic diode of the second switching device 12 is turned on.

[0072] Sub-phase two: After the third switching device 13 is stably turned on, continue to turn off the third switching device 13. Please refer to [link to relevant documentation]. Figure 3 (c) The parasitic diode of the first switching device 11 is turned on, i.e., the reverse freewheeling circuit.

[0073] As can be seen from the above, regardless of whether it is sub-stage one or sub-stage two of the current limiting point triggered during the positive half-cycle, or sub-stage one or sub-stage two of the current limiting point triggered during the negative half-cycle, there is current in the middle freewheeling circuit (i.e., the path between the first bus capacitor 15, the second bus capacitor 16, the second switching device 12, the third switching device 13, the first switching device 11, and the fourth switching device 14, specifically path ① + path ② + path ③). Based on this:

[0074] On the one hand, in the printed circuit board 30 corresponding to the multi-level circuit 10a, path ① (i.e., the electrical path between the second switching device 12 and the third switching device 13) is realized through the first metal region 31, and path ② (i.e., the electrical path between the third switching device 13, the first switching device 11 and the fourth switching device 14) is realized through the second metal region 32. That is, whether it is the first sub-stage or the second sub-stage, current exists in both path ① and path ② at the same time. That is, in the entire cycle of current loop switching, the current magnetic fields on the first metal region 31 and the second metal region 32 cancel each other out, reducing stray inductance and thus reducing reverse peaks, and extending the life of circuit devices.

[0075] On the other hand, in the printed circuit board 30 corresponding to the multi-level circuit 10, path ③ (i.e., the electrical path between the first bus capacitor 15, the second bus capacitor 16, and the second switching device 12) is realized through the parallel third metal region 33 and the fourth metal region 34, thereby resulting in a lower current density, which can also reduce the circuit and thus reduce the reverse peak, and extend the life of the circuit devices.

[0076] The following describes the structure of a printed circuit board 30, specifically a type I three-level topology, as an example of a multi-level topology.

[0077] Please see Figure 5 The printed circuit board 30 is specifically used to form a multilevel circuit 10b with a type I three-level topology. The multilevel circuit includes 6 switching devices and 2 bus capacitors. The first switching devices 11 to the fourth switching devices 14 are connected in series to form the first vertical bridge arm. The fifth switching device 21 and the sixth switching device 22 are connected in series to form the second vertical bridge arm. The first bus capacitor 15 and the second bus capacitor 16 are connected in series to form the capacitor bridge arm. The common point of the second switching device 12 and the third switching device 13 is used as the AC terminal. The common point of the first bus capacitor 15 and the second bus capacitor 16 is used as the midpoint O. The two free ends of the first vertical bridge arm are connected in parallel with the two free ends of the capacitor bridge arm. One free end of the second vertical bridge arm is connected to the common point of the first switching device 11 and the second switching device 12. The other free end of the second vertical bridge arm is connected to the common point of the third switching device 13 and the fourth switching device 14. The common point of the fifth switching device 21 and the sixth switching device 22 is connected to the midpoint O.

[0078] The second switching device 12, the third switching device 13, the fifth switching device 21, and the sixth switching device 22 are all freewheeling switches, while the first switching device 11 and the fourth switching device 14 are both main switching devices. The first level channel refers to the channel from the free end of the first bus capacitor 15, the first switching device 11, and the second switching device 12 to the AC terminal. The second level channel is the channel from the free end of the second bus capacitor 16, the fourth switching device 14, and the third switching device 13 to the AC terminal. The mid-level channel is the channel from the midpoint O, the fifth switching device 21, and the second switching device 12 to the AC terminal, or the channel from the AC terminal, the third switching module 13, and the sixth switching device 22 to the midpoint O. The reverse freewheeling circuit is the freewheeling channel flowing through the parasitic diodes of the first switching device 11 and the second switching device 12, or the freewheeling channel flowing through the parasitic diodes of the third switching device 13 and the fourth switching device 14.

[0079] Please see Figure 5 The intermediate freewheeling circuit refers to the electrical path between the first bus capacitor 15, the second bus capacitor 16, the fifth switching device 21, and the sixth switching device 22; the electrical path between the fifth switching device 21, the first switching device 11, and the second switching device 12; and the electrical path between the sixth switching device 22, the third switching device 13, and the fourth switching device 14. This electrical path can be divided into four segments: ①, ②, and ③. There are two first metal regions 31. The first first metal region 31 is used to form the electrical path ① between the first switching device 11, the second switching device 12, and the fifth switching device 21. The second first metal region 31 is used to form the electrical path ① between the third switching device 13, the fourth switching device 14, and the sixth switching device 22. The second metal region 32 forms the electrical path ② between the second switching device 12 and the third switching device 13. The third metal region 33 and the fourth metal region 34 are connected in parallel to form the electrical path ③ between the first bus capacitor 15, the second bus capacitor 16, the fifth switching device 21, and the sixth switching device 22.

[0080] Specifically, please see Figure 6 (a)~ Figure 6 (c) illustrates the commutation operation of the multilevel circuit 10b after triggering the current limiting point during the positive half-cycle: Specifically:

[0081] Before switching: Before triggering the current limiting point, the current loop of the multilevel circuit 10b is as follows: Figure 6 As shown in (a), that is, the first level channel;

[0082] Sub-phase 1: After triggering the current limiting point, first shut off the vertical pipe, i.e., the first switching device 11. Please refer to [link to relevant documentation]. Figure 6 (b) At this time, the current loop switches to the mid-level channel, and the fifth switching device 21 and the second switching device 12 are turned on.

[0083] Sub-phase two: After the fifth switching device 21 is stably turned on, the second switching device 12 continues to be turned off. Please refer to [link to relevant documentation]. Figure 6 (c) The parasitic diodes of the third switching device 13 and the fourth switching device 14 are turned on, i.e., the second level channel.

[0084] Please see Figure 7 (a)~ Figure 7 (c) illustrates the commutation operation of the type-I topology multilevel circuit 10b after triggering the current-limiting point during the negative half-cycle: Specifically:

[0085] Before switching: Before triggering the current limiting point, the current loop of the multilevel circuit 10b is as follows: Figure 7 As shown in (a), this is the second level channel;

[0086] Sub-phase 1: After triggering the current limiting point, first shut off the vertical pipe, i.e., the fourth switching device 14. Please refer to [link / reference]. Figure 7 (b) At this time, the current loop switches to the middle level channel, and the third switching device 13 and the sixth switching device 22 are turned on.

[0087] Sub-phase two: After the sixth switching device 22 is stably turned on, continue to turn off the sixth switching device 22. Please refer to [link to relevant documentation]. Figure 7 (c) The parasitic diodes of the second switching device 12 and the first switching device 11 are turned on, i.e., the first level channel.

[0088] As can be seen from the above, regardless of whether it is sub-stage one or sub-stage two of the current limiting point triggered during the positive half-cycle, or sub-stage one or sub-stage two of the current limiting point triggered during the negative half-cycle, there is current in the middle freewheeling circuit (i.e., the path between the first bus capacitor 15, the second bus capacitor 16, the fifth switching device 21, the sixth switching device 22, the second switching device 12, the third switching device 13, the first switching device 11 and the fourth switching device 14, specifically path ① + path ①' + path ② + path ③).

[0089] On one hand, in the printed circuit board 30 corresponding to the multi-level circuit 10b, the first metal region 31 has multiple components. The first path ① (i.e., the electrical path between the first switching device 11, the second switching device 12, and the fifth switching device 21) is realized through the first first metal region 31, and the second path ①' (i.e., the electrical path between the third switching device 13, the fourth switching device 14, and the sixth switching device 22) is realized through the second first metal region 31; path ② (i.e., the electrical path between the second switching device 12 and the third switching device 13) is realized through the second metal region 32. In sub-stage one and sub-stage two after the current limiting point is triggered in the positive half-cycle, current exists simultaneously in both path ② and the first path ①, meaning the current magnetic fields on the first metal region 31 and the first second metal region 32 cancel each other out. In sub-stage one and sub-stage two after the current limiting point is triggered in the negative half-cycle, current exists simultaneously in both path ② and the second path ①', meaning the current magnetic fields on the first metal region 31 and the second second metal region 32 cancel each other out. Thus... During the entire cycle of current loop switching, the current magnetic fields on the first metal region 31 and the second metal region 32 cancel each other out, reducing stray inductance and thus reducing reverse peaks, extending the life of circuit devices.

[0090] On the other hand, in the printed circuit board 30 corresponding to the multi-level circuit 10b, path ③ (i.e., the electrical path between the first bus capacitor 15, the second bus capacitor 16, the fifth switching device 21 and the sixth switching device 22) is realized through the parallel third metal region 33 and the fourth metal region 34, so that the overall noise after the third metal region 33 and the fourth metal region 34 are connected in parallel is also smaller, and the life of the circuit device is extended.

[0091] The following description uses a five-level topology as an example to illustrate the structure of a printed circuit board 30.

[0092] Please see Figure 8 The printed circuit board 30 is specifically used to form a multilevel circuit 10c with a five-level topology. The multilevel circuit 10c includes eight switching devices and four bus capacitors. The first to fourth switching devices 14 are connected in series to form a vertical bridge arm, the fifth and sixth switching devices 21 and 22 are connected in series to form a horizontal bridge arm, and the first, second, fourth, and third bus capacitors 15a, 15b, 16a, and 16a are connected in series to form a capacitor bridge arm. The two free ends of the capacitor bridge arm and the two free ends of the vertical bridge arm are connected in parallel.

[0093] The common point of the second bus capacitor 15b and the fourth bus capacitor 16b is taken as the midpoint O. One free end of the horizontal tube bridge arm is connected to the midpoint O, and the other free end of the horizontal tube bridge arm is connected to the common point of the second switch device 12 and the third switch device 13. The common point of the second switch device 12 and the third switch device 13 forms an AC terminal. One end of the seventh switch device 27 is connected to the common point of the first switch device 11 and the second switch device 12, and the other end of the seventh switch device 27 is connected to the common point of the first bus capacitor 15a and the third bus capacitor 15b. One end of the eighth switch device 28 is connected to the common point of the third switch device 13 and the fourth switch device 14, and the other end of the eighth switch device 28 is connected to the common terminal of the fourth bus capacitor 16b and the third bus capacitor 16a.

[0094] The second switching device 12, the third switching device 13, the fifth switching device 21, and the sixth switching device 22 are all freewheeling switching devices, while the first switching device 11, the fourth switching device 14, the seventh switching device 27, and the eighth switching device 28 are all main switching devices.

[0095] Please see Figure 8 The intermediate freewheeling circuit refers to the electrical path between the second bus capacitor 15b and the fourth bus capacitor 16b, which is connected to the second switch device 12 and the third switch device 13 via the fifth switch device 21 and the sixth switch device 22. This electrical path can be divided into three segments: ①, ②, and ③. The first metal region 31 forms the electrical path ① between the fifth switch device 21 and the sixth switch device 22. The second metal region 32 forms the electrical path ② between the sixth switch device 22, the second switch device 12, and the third switch device 13. The third metal region 33 and the fourth metal region 34 are connected in parallel to form the electrical path ③ between the second bus capacitor 15b, the fourth bus capacitor 16b, and the fifth switch device 21.

[0096] The current loop switching process of multilevel circuit 10c after triggering the current limiting point can be understood by referring to the switching process of multilevel circuits 10a and 10b, and will not be elaborated here. Similarly, during the current loop switching process of multilevel circuit 10c after triggering the current limiting point, current exists in paths ①, ②, and ③. Therefore, the current magnetic fields on the first metal region 31 and the second metal region 32 cancel each other out. At the same time, since the third metal region 33 and the fourth metal region 34 together form path ③, the current density is even lower, which can also reduce the reverse peak.

[0097] Taking a T-type three-level circuit as an example, the various switching devices, bus capacitors, and other circuit components can be arranged in various ways on the circuit board, such as T-type, diamond-shaped, and rectangular layouts. It should be understood that topology connection describes the circuit principle connection structure of a multilevel circuit, such as T-type topology and I-type topology. Layout structure describes the position of each component in the multilevel circuit on the circuit board. A T-type topology can have T-type, diamond, and rectangular layouts, and similarly, an I-type topology can have T-type, diamond, and rectangular layouts.

[0098] The following is a T-type layout of a T-type three-level topology (please refer to...). Figure 2 The provided multilevel circuit 10a) is used as an example to illustrate the structure of a printed circuit board 30. For other layouts of the T-type three-level topology (such as rectangular layout, diamond layout) or other multilevel topologies, those skilled in the art can obtain the current path that satisfies the above embodiment according to the actual commutation path and set it as the first metal region 31 to the fourth metal region 34.

[0099] Please see Figure 9 On the printed circuit board 30 corresponding to the multi-level circuit 10a, the first switching device 11, the second switching device 12, the third switching device 13, and the fourth switching device 14 are arranged in a T-shape; the first switching device 11 and the fourth switching device 14 form the short side of the T-shape; the second switching device 12 and the third switching device 13 form the long side of the T-shape; the third switching device 13 is close to the short side of the T-shape, and the second switching device 12 is far away from the long side of the T-shape; one of the first bus capacitor 15 and the second bus capacitor 16 is placed on the side of the first switching device 11 that is far away from the fourth switching device 14, and the other of the first bus capacitor 15 and the second bus capacitor 16 is placed on the side of the fourth switching device 14 that is far away from the first switching device 11.

[0100] It should also be noted that the printed circuit board 30 is laid out in layers. In one specific embodiment, the printed circuit board 30 includes a bottom wiring layer arranged sequentially along a third direction (see [link to documentation]). Figure 10A ), second intermediate wiring layer (see Figure 10B ), First intermediate wiring layer (see Figure 10C ) and top-level routing layer (see Figure 10D The second metal area 32 (i.e., electrical path ②) and the third metal area 33 (i.e., electrical path ③) are both located in the bottom wiring layer, the fourth metal area 34 (i.e., electrical path ③) is located in the second intermediate wiring layer, and the first metal area 31 (i.e., electrical path ①) is located in the first intermediate wiring layer.

[0101] Please see Figure 10AThe bottom wiring layer also includes a fifth metal region 35, which is used to form an electrical path (i.e., electrical path ④) between the first switching device 11 and the first bus capacitor 15; the third metal region 33, the first metal region 31 and the fifth metal region 35 are arranged along the first direction;

[0102] The first intermediate wiring layer also includes a sixth metal region 36, which is used to form an electrical path between the first switching device 11 and the fourth switching device 14 (corresponding to a partial connection of electrical path ②, forming a complete electrical path ② between the first switching device 11, the fourth switching device 14, and the third switching device 13 with the second metal region 32); the second metal region 32 and the sixth metal region 36 are arranged along the first direction;

[0103] The top wiring layer includes a seventh metal region 37, which is used to form an electrical path (i.e., electrical path ⑤) between the fourth switching device 14 and the second bus capacitor 16.

[0104] Specifically, please see Figure 9 Each switching device includes multiple switching transistors; for example, each shaded box represents one switching transistor. Figures 10A to 10D In the diagram, three consecutive circular patterns at corresponding positions represent a switching transistor, and each circular pattern represents a pin of that switching transistor. The second switching device 12 includes four switching transistors, the third switching device 13 includes four switching transistors, the first switching device 11 includes three switching transistors, and the fourth switching device 14 includes three switching transistors.

[0105] Please see Figure 10A In the bottom wiring layer, the second metal region 32 is connected to one of the switches in the first switching device 11, and the fifth metal region 35 is connected to all the switches in the first switching device 11. In this way, the second metal region 32 is also connected to the first switching device 11, allowing the current between the first switching device 11 and the third switching device 13 to flow directly through the first switching device 11, greatly shortening the commutation path and avoiding wiring interference. Otherwise, if the second metal region 32 were not connected to the first switching device 11, the current between the first switching device 11 and the third switching device 13 would need to flow from the fifth metal region 35 (bottom wiring layer) to the sixth metal region 36 (first intermediate wiring layer) and then to the second metal region 32 (second intermediate wiring layer), significantly increasing the current path.

[0106] In some embodiments, the multilevel circuit further includes decoupling capacitors, each of which is connected between a freewheeling switch and a main switch, and one decoupling capacitor is connected in parallel with one of the bus capacitors. The decoupling capacitors are used to shorten the commutation path of the switching process of the current loop.

[0107] In other words, after the multilevel circuit triggers the current limiting point, at least one main switching device is turned off, so that the multilevel circuit switches from the current current loop to the intermediate freewheeling loop; and at least one freewheeling switching device is turned off, so that the multilevel circuit switches from the intermediate freewheeling loop to the reverse freewheeling loop through the decoupling capacitor.

[0108] For example, there are two decoupling capacitors: the first decoupling capacitor is connected in parallel with the first bus capacitor, and the second decoupling capacitor is connected in parallel with the second bus capacitor. This is just an example; the number of bus capacitors and decoupling capacitors can be selected according to actual usage requirements.

[0109] It should also be noted that on the printed circuit board corresponding to the multi-level circuit, the bus capacitor is relatively large and therefore needs to be placed independently, while the decoupling capacitor is smaller and can be placed between different switching devices. Specifically, for the multi-level circuit, multiple switching devices and multiple decoupling capacitors are all located within the core device area, while multiple bus capacitors are located outside the core device area.

[0110] Therefore, when the multi-level circuit switches from the intermediate freewheeling loop to the reverse freewheeling loop, the commutation path includes a first path through the decoupling capacitor and a second path through the bus capacitor, with the first path being shorter than the second path. In other words, compared to the bus capacitor, the decoupling capacitor is closer to the switching device, resulting in a shorter commutation path through the decoupling capacitor and reduced reverse peak current.

[0111] (1) When the multilevel circuit is a three-level T-type topology connection, please refer to Figure 11 The first decoupling capacitor 17 is connected across one free end of the vertical tube bridge arm and the first end of the horizontal tube bridge arm, and the second decoupling capacitor 18 is connected across the other free end of the vertical tube bridge arm and the first end of the horizontal tube bridge arm.

[0112] Correspondingly, on the printed circuit board 30 containing the first coupling capacitor 17 and the second coupling capacitor 18, the fifth metal region 35 is also connected to the second terminal of the first decoupling capacitor (i.e., Figure 11 The electrical path ⑦); the fourth metal region 34 is connected to the first terminal of the first decoupling capacitor and the first terminal of the second decoupling capacitor (i.e., the electrical path ⑦); Figure 11 The electrical paths ⑥ and ⑥' in the middle; the seventh metal region 37 is also connected to the second terminal of the second decoupling capacitor (i.e., electrical path ⑦').

[0113] Specifically, for the circuit switching process of the current-limiting current triggered during the positive half-cycle, please refer to [link to relevant documentation]. Figure 3 (a)~ Figure 3 (c);

[0114] Please see Figure 3(b) After the current limiting point is triggered during the positive half-cycle, the vertical tube, i.e. the first switching device 11, is turned off first. At this time, the current loop switches to the middle level channel, the horizontal tube, i.e. the second switching device 12, is turned on, and the parasitic diode of the third switching device 13 is turned on. At this time, the platform voltage that the first switching device 11 withstands is half of the bus voltage (e.g., 500V). If the withstand voltage of the first switching device 11 is 1200V, it is in a non-extreme operating condition.

[0115] Please see Figure 3 (c) After the second switching device 12 is stably turned on, the second switching device 12 is turned off again, and the parasitic diode of the fourth switching device 14 is turned on. At this time, the platform voltage that the first switching device 11 bears is the entire bus voltage (e.g., 1000V). Similarly, when the withstand voltage of the first switching device 11 is 1200V, there is only a margin of 200V. Once the induced voltage exceeds 200V, the reverse peak voltage formed by its superposition of the bus platform voltage exceeds 1200V, which exceeds the device withstand voltage and damages the switching device. This is the extreme operating condition.

[0116] Thus, in Figure 3 (b) To Figure 3 (c) During the switching process, without a decoupling capacitor, the commutation loop is the path from the mid-level channel to the second-level channel, i.e., the current loop from midpoint O, the horizontal bridge arm, and the AC terminal switches to midpoint O, the second bus capacitor 16, the fourth switching device 14, and the AC terminal. Because the bus capacitor has a large capacitance and volume, and a long path, it contains high stray inductance. Furthermore, large voltage / current changes acting on this stray inductance generate large reverse peaks, which may break down the switching device. Please refer to... Figure 11 Since this embodiment introduces a decoupling capacitor connected in parallel with the bus capacitor, and since the volume of the decoupling capacitor is smaller than that of the bus capacitor, it can be connected nearby between the first end of the horizontal tube bridge arm and the free end of the vertical tube bridge arm, resulting in a shorter path. Therefore, the commutation circuit also includes a path through the second decoupling capacitor 18 and the fourth switching device 14, significantly shortening the commutation circuit and reducing the stray inductance. This reduces the reverse peak borne by the first switching device 11 and improves the lifespan of the multilevel circuit 10.

[0117] Specifically, for the circuit switching process of the negative half-cycle trigger current-limiting current, please refer to [link to relevant documentation]. Figure 4 (a)~ Figure 4 (c) illustrates the commutation operation of the multilevel circuit 10 after triggering the current limiting point during the negative half-cycle: Specifically:

[0118] Please see Figure 4(b): After the current limiting point is triggered, the vertical tube, i.e. the fourth switching device 14, is turned off first. At this time, the current loop switches to the middle level channel, the horizontal tube, i.e. the third switching device 13, is turned on, and the parasitic diode of the second switching device 12 is turned on. At this time, the platform voltage of the fourth switching device 14 is half of the bus voltage (e.g., 500V). If the withstand voltage of the fourth switching device 14 is 1200V, it is in a non-extreme operating condition.

[0119] Please see Figure 4 (c): After the third switching device 13 has been stably turned on, continue to turn off the third switching device 13. Please refer to [link to relevant documentation]. Figure 4 (c) When the parasitic diode of the first switching device 11 is turned on, the platform voltage of the fourth switching device 14 is the entire bus voltage (e.g., 1000V). Similarly, the withstand voltage of the fourth switching device 14 is 1200V, leaving only a margin of 250V. Once the induced voltage exceeds 250V, the reverse peak voltage formed by its superposition with the bus platform voltage exceeds 1200V, exceeding the device withstand voltage and damaging the switching device, which is the extreme operating condition.

[0120] Thus, in Figure 4 (b) To Figure 4 (c) During the switching process, without setting a decoupling capacitor, the commutation loop is the path from the mid-level channel to the first-level channel, that is, the current loop from the endpoint O, the horizontal bridge arm, and the AC terminal switches to the midpoint O, the first bus capacitor 15, the first switching device 11, and the AC terminal. Because the bus capacitor has a large capacitance and volume, and a long path, it contains a high stray inductance. Furthermore, the large voltage / current change acts on the stray inductance, generating a large reverse peak, which may break down the switching device. Please refer to... Figure 11 Because this embodiment introduces a decoupling capacitor connected in parallel with the bus capacitor, and because the volume of the decoupling capacitor is smaller than the value of the bus capacitor, it can be connected nearby between the first end of the horizontal tube bridge arm and the free end of the vertical tube bridge arm. The path is shorter, so the commutation circuit also includes the path through the first decoupling capacitor 17 and the first switching device 11. The commutation circuit is significantly shortened, and the stray inductance is smaller, thereby reducing the reverse peak borne by the fourth switching device 14 and improving the lifespan of the multilevel circuit 10.

[0121] Generally, the positive and negative half-cycle waveforms of a multi-level circuit are symmetrical, and devices in symmetrical positions are usually selected with the same specifications. For example, the first switching device in the positive half-cycle and the second switching device in the negative half-cycle are both selected with a withstand voltage of 1200V. Both the positive and negative half-cycles may trigger current limiting protection. Therefore, it is generally necessary to set both the first and second decoupling capacitors. In some special cases, if the devices in the positive and negative half-cycles are selected with different specifications, such as the first switching device being a 1200V switch and the second switching device being a 2000V switch, since the second switching device has a larger withstand voltage margin and can withstand a larger reverse peak, only the second decoupling capacitor 18 needs to be set.

[0122] (2) In the case of a three-level type I topology connection in a multilevel circuit, please refer to Figure 12 In (a), the first decoupling capacitor 17 is connected between the free end of the first switching device 11 and the anode of the first diode (i.e., the fifth switching device 21), and the second decoupling capacitor 18 is connected between the free end of the fourth switching device 14 and the cathode of the second diode (i.e., the sixth switching device 22).

[0123] Alternatively, please see Figure 12 In (b), the first decoupling capacitor 17 is connected between the free end of the first switching device 11 and the cathode of the second diode (i.e., the sixth switching device 22), and the second decoupling capacitor 18 is connected between the free end of the fourth switching device 14 and the anode of the first diode (i.e., the fifth switching device 21). Compared to Figure 12 (a) shows the connection method of the decoupling capacitor. Figure 12 (b) The connection method of the decoupling capacitor can further shorten the commutation path and reduce the reverse peak.

[0124] (3) In the case of a five-level circuit, please refer to [the relevant documentation]. Figure 13 The first decoupling capacitor 17 is connected across one free end of the first vertical tube bridge arm and the first end of the horizontal tube bridge arm, and the second decoupling capacitor 18 is connected across the other free end of the first vertical tube bridge arm and the first end of the horizontal tube bridge arm. Both are used to shorten the commutation path and reduce reverse peaks.

[0125] In the above description, the capacitance value of the decoupling capacitor satisfies the following: the ripple distribution of the decoupling capacitor for the reverse peak current is greater than the current distribution of the decoupling capacitor for the power frequency ripple current, and the ripple distribution of the decoupling capacitor for the reverse peak current is greater than the current distribution of the decoupling capacitor for the switching frequency ripple.

[0126] It should be noted that there are three main types of ripple current in the multi-level circuit 10: (1) power frequency ripple current; (2) switching frequency ripple current; and (3) reverse peak ripple current (which can also be called commutation current). The frequencies of these three ripple currents are different. The frequency of the power frequency ripple is less than that of the switching frequency ripple, which is less than that of the reverse peak ripple (generally, the frequency of the power frequency ripple is 50Hz or 60Hz and its multiples, the frequency of the switching frequency ripple is 10kHz to 100kHz, and the frequency of the reverse peak ripple is 1MHz to 10MHz). Through experiments, it was found that different types and capacitance values ​​of capacitors have different throughput for the three different frequencies of ripple. The capacitor with a smaller capacitance value has a larger throughput for the higher switching frequency. The capacitance value of the decoupling capacitor needs to allow the reverse peak ripple current to pass through well, while allowing less throughput for the power frequency ripple current and the switching frequency ripple current. Therefore, the capacitance value of the decoupling capacitor cannot be too large, otherwise it will easily receive too much switching frequency current, leading to overheating of the capacitor.

[0127] In a specific scenario, the decoupling capacitor has a capacitance of 0.47 microfarads, and a film capacitor is recommended. For the bus capacitor absorbing the power frequency ripple current, a 470 microfarad electrolytic capacitor can be used. This larger capacitor is placed in a more peripheral area and can be composed of multiple capacitors connected in parallel. For the bus capacitor absorbing the switching frequency ripple current, a 12 microfarad capacitor can be used. This larger capacitor is also placed in a more peripheral area and can be composed of multiple capacitors connected in parallel. Experimental results show that the 0.47 microfarad film capacitor provides almost no current sharing for the power frequency ripple current, approximately 1% for the switching frequency ripple current, and approximately 99% for the reverse peak ripple current. The 12 microfarad bus capacitor shares approximately 95% of the switching frequency ripple current and approximately 1% of the reverse peak ripple current. The 0.47 microfarad film capacitor provides almost no current sharing for the reverse peak ripple current and approximately 99% for the power frequency ripple current. Therefore, it can be seen that the reverse peak ripple current (i.e., commutation current) mainly passes through the thin-film capacitor. The capacitance values ​​and experimental data above are merely a set of values ​​obtained by the inventors during the experimental process. They do not limit the sole range of capacitance values ​​in this application, nor do they limit the distribution of different ripple currents by different capacitors to the same extent as measured in the experiments. The understanding should return to the inventive concept of this invention.

[0128] In summary, the embodiments of this application provide a multi-level circuit that, by introducing a decoupling capacitor, can reduce the commutation path length during the switching process from the intermediate freewheeling circuit to the reverse freewheeling circuit, thereby reducing reverse peaks and extending device lifespan.

[0129] In other embodiments, the bus capacitor can be composed of multiple small capacitors connected in parallel, and their distribution can be flexibly selected. For example... Figure 9Each small square in the bus capacitor can be considered a small capacitor, and multiple small capacitors are connected in parallel to form the bus capacitor with a preset capacitance value. It should be noted that when the bus capacitor consists of multiple small capacitors connected in parallel, the volume of the aforementioned decoupling capacitor is smaller than the volume of the bus capacitor. This should not be interpreted as the volume of the decoupling capacitor being smaller than the volume of each small capacitor connected in parallel to form the bus capacitor. Rather, it should be understood that the volume of the capacitor used for decoupling (i.e., the decoupling capacitor) is smaller than the volume of the entire capacitor used for bus support (i.e., the bus capacitor).

[0130] In other embodiments, there are multiple multilevel circuits 10, each multilevel circuit constituting a core device region. The bus capacitors include multiple first bus capacitor arrays and multiple second bus capacitor arrays. Each bus capacitor array includes multiple capacitors (the number of capacitors included in each bus capacitor array may be different). The first bus capacitor array and the second bus capacitor array are respectively arranged on both sides of each multilevel circuit 10 (i.e., each core device region), and the first bus capacitor array and the second bus capacitor array are arranged alternately.

[0131] For example, please see Figure 14 The number of multi-level circuits 10 is three, thus forming a three-phase three-level inverter circuit. The three multi-level circuits 10 are arranged sequentially along the first direction, and a first bus capacitor array and a second bus capacitor array are respectively arranged on both sides of each multi-level circuit 10. In this embodiment, the number of capacitors included in each bus capacitor array is different; in other embodiments, the number of capacitors included in each bus capacitor array can be the same.

[0132] In this way, the bus capacitors can be arranged in different parts on the circuit board, with each multi-level circuit 10 having a commutation path of equal length and high current sharing. Simultaneously, the bus capacitors are implemented in parallel using multiple small-package capacitors, which have lower stray inductance compared to large capacitors, while also providing greater layout freedom for other components. Simulation results show that the stray inductance of the capacitors in this layout accounts for only 7% of the total stray inductance of the circuit.

[0133] In summary, this application provides a printed circuit board 30. On the one hand, during the switching operation of the current loop, current exists in both the first metal region and the second metal region, and the angle between the current directions is greater than 90 degrees. As a result, the current magnetic fields of the first metal region and the second metal region cancel each other out, reducing line stray inductance and reducing reverse peaks. On the other hand, during the switching operation of the current loop, the third metal region and the fourth metal region are connected in parallel to provide a partial section of the middle freewheeling loop, thereby reducing the current density and further reducing reverse peaks. Furthermore, the multilevel circuit also includes at least one decoupling capacitor, which is connected in parallel with the bus capacitor and is connected between two of the switching devices. The multilevel circuit has multiple selectively conducting current loops, and the decoupling capacitor is used to shorten the commutation path of the switching process from one current loop to another, reducing the stray inductance of the path during the commutation process, thereby reducing reverse peaks and improving device lifespan.

[0134] In another embodiment of this application, an inverter is provided that includes the aforementioned printed circuit board 30.

[0135] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application. It should be noted that in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A printed circuit board, characterized in that, The printed circuit board includes at least a plurality of wiring layers arranged along a third direction, wherein a first metal region is formed in one of the wiring layers and a second metal region is formed in another wiring layer. The projection of the first metal region along a third direction overlaps with the projection of the second metal region along a third direction; and the angle between the current direction of the first metal region corresponding to the overlapping region and the current direction of the second metal region corresponding to the overlapping region is greater than 90 degrees. The printed circuit board is used to form a multi-level circuit. After the multi-level circuit triggers the current limiting point, it performs a current loop switching operation. During the current loop switching operation, current exists in both the first metal area and the second metal area.

2. The printed circuit board according to claim 1, characterized in that, The output of the multilevel circuit includes a first level, a middle level, and a second level; after the multilevel circuit triggers the current limiting point, at least one main switching device is turned off, so that the multilevel circuit switches from the current current loop to the middle freewheeling loop; and at least one freewheeling switching device is turned off, so that the multilevel circuit switches from the middle freewheeling loop to the reverse freewheeling loop. Among them, the switching device located on the middle level channel is the freewheeling switching device, and the switching device located on the first level channel or the second level channel is the main switching device. When the current current loop is the first level channel, the reverse freewheeling loop is the freewheeling loop through the main switching device on the second level channel. When the current level path is the second level channel, the reverse freewheeling loop is the freewheeling loop through the main switching device on the first level channel. The intermediate freewheeling circuit refers to the circuit between the bus capacitor, the freewheeling switch device, and the main switch device. The first metal area is used to form the electrical path between the freewheeling switch devices, and the second metal area is used to form the electrical path between the AC terminal of the multilevel circuit and at least one of the switch devices.

3. The printed circuit board according to claim 2, characterized in that, In the printed circuit board, a third metal region is formed in one of the wiring layers, and a fourth metal region is formed in the other wiring layer; The third metal region and the fourth metal region are connected in parallel to form the electrical path between the bus capacitor and the freewheeling switch device, and the electrical path formed by the third metal region and the fourth metal region also belongs to the middle freewheeling circuit.

4. The printed circuit board according to claim 3, characterized in that, The multilevel circuit also includes decoupling capacitors. Each decoupling capacitor is connected between a freewheeling switch and a main switch, and one decoupling capacitor is connected in parallel with one bus capacitor. The decoupling capacitor is used to shorten the commutation path of the current loop switching process.

5. The printed circuit board according to claim 4, characterized in that, When the multilevel circuit is a T-type topology connection, the multilevel circuit includes four switching devices, two bus capacitors, and two decoupling capacitors. The first and fourth switching devices are connected in series to form a vertical bridge arm, the second and third switching devices are connected in series to form a horizontal bridge arm, the first and second bus capacitors are connected in series to form a capacitor bridge arm, the common point of the first and fourth switching devices serves as the AC terminal of the multilevel circuit, the common point of the first and second bus capacitors serves as the midpoint, the two free ends of the vertical bridge arm are connected in parallel with the two free ends of the capacitor bridge arm, the first end of the horizontal bridge arm is connected to the midpoint, and the second end is connected to the AC terminal; the first decoupling capacitor is connected across one free end of the vertical bridge arm and the first end of the horizontal bridge arm, and the second decoupling capacitor is connected across the other free end of the vertical bridge arm and the first end of the horizontal bridge arm; The first switching device and the fourth switching device are both main switching devices, and the second switching device and the third switching device are both freewheeling switching devices; the first metal region is used to form an electrical path between the second switching device and the third switching device, the second metal region is used to form an electrical path between the third switching device, the first switching device and the fourth switching device, and the third metal region and the fourth metal region are connected in parallel to form an electrical path between the first bus capacitor, the second bus capacitor and the second switching device.

6. The printed circuit board according to claim 4, characterized in that, When the multilevel circuit is a type I topology connection, the multilevel circuit includes 6 switching devices, 2 bus capacitors, and 2 decoupling capacitors. The first to fourth switching devices are connected in series to form a first vertical bridge arm, the fifth and sixth switching devices are connected in series to form a second vertical bridge arm, the first and second bus capacitors are connected in series to form a capacitor bridge arm, the common point of the second and third switching devices is used as the AC terminal, the common point of the first and second bus capacitors is used as the midpoint, the two free ends of the first vertical bridge arm are connected in parallel to the two free ends of the capacitor bridge arm, one free end of the second vertical bridge arm is connected to the common point of the first and second switching devices, and the other free end of the second vertical bridge arm is connected to the common point of the third and fourth switching devices; the common point of the fifth and sixth switching devices is connected to the midpoint; the first decoupling capacitor is connected across one free end of the first vertical bridge arm and the common end of the second vertical bridge arm, and the second decoupling capacitor is connected across the other free end of the first vertical bridge arm and the common end of the second vertical bridge arm. The second, third, fifth, and sixth switching devices are all freewheeling switching devices, and the first and fourth switching devices are both main switching devices. The number of first metal regions is 2. The first first metal region is used to form an electrical path between the first switching device, the second switching device and the fifth switching device, and the second first metal region is used to form an electrical path between the third switching device, the fourth switching device and the sixth switching device. The second metal region forms an electrical path between the second switching device and the third switching device; The third metal region and the fourth metal region are connected in parallel to form an electrical path between the first bus capacitor, the second bus capacitor, the fifth switching device, and the sixth switching device.

7. The printed circuit board according to claim 5, characterized in that, The printed circuit board includes a bottom wiring layer, a second intermediate wiring layer, a first intermediate wiring layer and a top wiring layer arranged sequentially along a third direction; the second metal region and the third metal region are both located on the bottom wiring layer, the fourth metal region is located on the second intermediate wiring layer, and the first metal region is located on the first intermediate wiring layer. The bottom wiring layer further includes a fifth metal region, which is used to form an electrical path between the first switching device and the first bus capacitor; the third metal region, the first metal region, and the fifth metal region are arranged along a first direction; The first intermediate wiring layer further includes a sixth metal region, which is used to form an electrical path between the first switching device and the fourth switching device; the second metal region and the sixth metal region are arranged along a first direction; The top wiring layer also includes a seventh metal region, which is used to form an electrical path between the fourth switching device and the second bus capacitor.

8. The printed circuit board according to claim 7, characterized in that, The first switching device includes multiple switching transistors; The second metal region is connected to one of the switching transistors in the first switching device, and the fifth metal region is connected to all the switching transistors in the first switching device.

9. The printed circuit board according to claim 7, characterized in that, The fifth metal region is also connected to the second terminal of the first decoupling capacitor; The fourth metal region is connected to the first terminal of the first decoupling capacitor and the first terminal of the second decoupling capacitor; The seventh metal region is also connected to the second terminal of the second decoupling capacitor.

10. An inverter, characterized in that, Including the printed circuit board as described in any one of claims 1-9.

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