Nitride-based semiconductor devices and their manufacturing methods

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, an n-type doped nitride-based semiconductor layer, a p-type doped nitride-based semiconductor layer, and an electrode. The first nitride-based semiconductor layer has a first portion and a second portion, wherein the thickness of the first portion is greater than the thickness of the second portion and is surrounded by the second portion. The second nitride-based semiconductor layer is disposed on the first portion and has a larger band gap than the first nitride-based semiconductor layer. The n-type doped nitride-based semiconductor layer is disposed on the second portion of the first nitride-based semiconductor layer. The p-type doped nitride-based semiconductor layer is disposed on and in contact with the n-type doped nitride-based semiconductor layer. The electrode extends through the p-type doped nitride-based semiconductor layer to contact the n-type doped nitride-based semiconductor layer.

Description

Technical Field

[0001] Generally, the present invention relates to nitride-based semiconductor devices. More specifically, the present invention relates to nitride-based semiconductor devices having an n+ doped GaN layer for low contact resistance. Background Technology

[0002] In recent years, research on high electron mobility transistors (HEMTs) has become increasingly popular, especially for high-power switching and high-frequency applications. Group III nitride-based HEMTs utilize heterojunction interfaces between two materials with different band gaps to form quantum well-like structures that accommodate two-dimensional electron gas (2DEG) regions to meet the demands of high-power / frequency devices. Besides HEMTs, examples of devices with heterostructures include heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs), and modulation-doped FETs (MODFETs). Summary of the Invention

[0003] In one aspect, the present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, an n-type doped nitride-based semiconductor layer, a p-type doped nitride-based semiconductor layer, and an electrode. The first nitride-based semiconductor layer has a first portion and a second portion, wherein the thickness of the first portion is greater than the thickness of the second portion and is surrounded by the second portion. The second nitride-based semiconductor layer is disposed on the first portion and has a larger band gap than the first nitride-based semiconductor layer. The n-type doped nitride-based semiconductor layer is disposed on the second portion of the first nitride-based semiconductor layer. The p-type doped nitride-based semiconductor layer is disposed on and in contact with the n-type doped nitride-based semiconductor layer. The electrode extends through the p-type doped nitride-based semiconductor layer to contact the n-type doped nitride-based semiconductor layer.

[0004] In another aspect, the present invention provides a method for manufacturing a nitride-based semiconductor device. The method includes the steps of: forming a first nitride-based semiconductor layer having a first portion and a second portion, wherein the thickness of the first portion is greater than the thickness of the second portion and is surrounded by the second portion; forming a second nitride-based semiconductor layer on the first portion of the first nitride-based semiconductor layer; forming an n-type doped nitride-based semiconductor layer on the second portion of the first nitride-based semiconductor layer; forming a blanket-type p-type doped nitride-based semiconductor layer to cover the n-type doped nitride-based semiconductor layer and the second nitride-based semiconductor layer; performing a patterning process on the blanket-type p-type doped nitride-based semiconductor layer such that some portions of the blanket-type p-type doped nitride-based semiconductor layer remain on the n-type doped nitride-based semiconductor layer; forming vias in the portions of the blanket-type p-type doped nitride-based semiconductor layer; and forming a plurality of electrodes in the vias such that the bottom of each electrode is covered by both the n-type doped nitride-based semiconductor layer and the p-type doped nitride-based semiconductor layer.

[0005] In another aspect, the present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, an n-type doped nitride-based semiconductor layer, and a p-type doped nitride-based semiconductor layer. The first nitride-based semiconductor layer has a first portion and a second portion, wherein the thickness of the first portion is greater than the thickness of the second portion and is surrounded by the second portion. The second nitride-based semiconductor layer is disposed on the first portion and has a larger band gap than the first nitride-based semiconductor layer. The n-type doped nitride-based semiconductor layer is disposed on the second portion of the first nitride-based semiconductor layer and extends vertically from the second portion of the first nitride-based semiconductor layer to a position above the interface between the first and second nitride-based semiconductor layers. The p-type doped nitride-based semiconductor layer is disposed on and in contact with the n-type doped nitride-based semiconductor layer.

[0006] With the above structure, the sidewalls of the electrode adjacent to the top surface of the n-type doped nitride-based semiconductor layer are covered by a p-type doped nitride-based semiconductor layer. The resistance of the p-type doped nitride-based semiconductor layer can block leakage current from the electrode. Attached Figure Description

[0007] Various aspects of the invention can be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, for clarity, the dimensions of the various features may be arbitrarily increased or decreased. Embodiments of the invention are described in more detail below with reference to the accompanying drawings, wherein:

[0008] Figure 1This is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present invention;

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D Different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present invention are illustrated.

[0010] Figure 3 This is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present invention;

[0011] Figure 4 This is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present invention;

[0012] Figure 5 These are vertical cross-sectional views of nitride-based semiconductor devices according to some embodiments of the present invention; and

[0013] Figure 6 This is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0014] The same reference numerals are used in the accompanying drawings and detailed description to denote the same or similar parts. Embodiments of the invention will be readily understood from the following detailed description in conjunction with the accompanying drawings.

[0015] Spatial descriptions such as "up," "down," "left," "right," "top," "bottom," "vertical," "horizontal," "side," "higher," and "lower" are specified relative to a particular component or group of components, or a plane of a component or group of components, for the orientation of the components shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and specific implementations of the structures described herein can be arranged in space in any orientation or manner, provided that such arrangement does not depart from the spirit of the invention.

[0016] Furthermore, it should be noted that, due to limitations in device manufacturing conditions, the actual shapes of various structures depicted as approximately rectangular in actual devices may be curved, have rounded corners, or have slightly uneven thicknesses, etc. Straight lines and right angles are used only for convenience in representing layers and features.

[0017] In the following description, semiconductor devices / dies / packages and methods for manufacturing them are set forth as preferred examples. It will be apparent that modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid confusion. However, the purpose of this invention is to enable those skilled in the art to practice its teachings without excessive experimentation.

[0018] Figure 1 This is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present invention. The nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14 and 16, a doped III-V semiconductor layer 20, a gate 22, n-type doped nitride-based semiconductor layers 30 and 32, p-type doped nitride-based semiconductor layers 34 and 36, electrodes 40 and 42, and a passivation layer 50.

[0019] Substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)), or other suitable substrate materials. In some embodiments, substrate 10 may include (but is not limited to) group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, substrate 10 may include (but is not limited to) one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.

[0020] A buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 16. The buffer layer 12 is configured to reduce lattice and thermal mismatch between the substrate 10 and the nitride-based semiconductor layer 16, thereby overcoming defects caused by mismatch / difference. The buffer layer 12 may include a III-V compound. The III-V compound may include, but is not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Therefore, exemplary materials for the buffer layer 12 may further include, but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

[0021] In some embodiments, semiconductor device 1A may further include a nucleation layer (not shown). The nucleation layer may be formed between substrate 10 and buffer layer 12. The nucleation layer is configured to provide a transition to accommodate mismatch / difference between the group III nitride layers of substrate 10 and buffer layer 12. Exemplary materials for the nucleation layer may include, but are not limited to, AlN or any alloy thereof.

[0022] A nitride-based semiconductor layer 14 may be disposed on the buffer layer 12. A nitride-based semiconductor layer 16 may be disposed on the nitride-based semiconductor layer 14. Exemplary materials for the nitride-based semiconductor layer 14 may include, but are not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1-x-y) N(x+y≤1), or Al x Ga (1-x)N (x≤1). Exemplary materials for the nitride-based semiconductor layer 16 may include, but are not limited to, nitrides or III-V compounds, such as GaN, AlN, In. x Al y Ga (1-x-y) N(x+y≤1), or Al y Ga (1-y) N(y≤1).

[0023] The exemplary materials of nitride-based semiconductor layers 14 and 16 are chosen such that the band gap (i.e., bandgap width) of nitride-based semiconductor layer 16 is larger than that of nitride-based semiconductor layer 14, thereby creating different electron affinities and forming a heterojunction therebetween. For example, when nitride-based semiconductor layer 14 is an undoped GaN layer with a band gap of approximately 3.4 eV, nitride-based semiconductor layer 16 can be selected as a GaN layer with a band gap of approximately 4.0 eV. Thus, nitride-based semiconductor layers 14 and 16 can be used as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the bonding interface between the channel and barrier layers, causing electrons to accumulate in the triangular wells, thereby creating a two-dimensional electron gas (2DEG) region 15 adjacent to or along the heterojunction. Therefore, semiconductor device 1A can be used to include at least one GaN-based high electron mobility transistor (HEMT).

[0024] Furthermore, the nitride-based semiconductor layer 14 has a portion 142 and a portion 144 connected to the portion 142. The portion 142 is surrounded by the portion 144. The thickness T1 of the portion 142 is greater than the thickness T2 of the portion 144. The nitride-based semiconductor layer 16 on the nitride-based semiconductor layer 14 may be confined within the portion 144 of the nitride-based semiconductor layer 14.

[0025] A doped III-V semiconductor layer 20 is disposed on the nitride-based semiconductor layer 16. The doped III-V semiconductor layer 20 may be in contact with the nitride-based semiconductor layer 16. Through the doped III-V semiconductor layer 20, the nitride-based semiconductor device 1A enters an enhancement mode. The doped III-V semiconductor layer 20 may be a p-type doped III-V semiconductor layer. Exemplary materials for p-type doped III-V semiconductor layers may include, but are not limited to, p-doped III-V group nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, p-doped materials are achieved by using p-type impurities (e.g., Be, Zn, Cd, and Mg).

[0026] Gate 22 is disposed on the doped III-V semiconductor layer 20. Gate 22 may be formed as a single layer or a multilayer with the same or different compositions. Exemplary materials of metals or metal compounds may include, but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metal compounds.

[0027] n-type doped nitride-based semiconductor layers 30 and 32 are disposed on a portion 144 of nitride-based semiconductor layer 14. A portion 142 of nitride-based semiconductor layer 14 is located between n-type doped nitride-based semiconductor layers 30 and 32. The conductivity types of n-type doped nitride-based semiconductor layers 30 and 32 include "n+", "n-", and "n". The n+ doped portion has a higher doping concentration than the n-doped portion; and the n-doped portion has a higher doping concentration than the n-doped portion. In some embodiments, n-type doped nitride-based semiconductor layers 30 and 32 may be n+ doped III-V semiconductor layers. Exemplary materials for n-type doped nitride-based semiconductor layers 30 and 32 may include, but are not limited to, n-doped III-V group nitride semiconductor materials, such as n-type GaN, n-type AlGaN, n-type InN, n-type AlInN, n-type InGaN, n-type AlInGaN, or combinations thereof. In some embodiments, the n-doped material is achieved by using n-type impurities such as Si, C, Ge, Se, and Te. The n-type doped nitride-based semiconductor layers 30 and 32 are configured to improve the contact resistance of the conductor relative to the semiconductor.

[0028] n-type doped nitride-based semiconductor layers 30 and 32 may abut against nitride-based semiconductor layers 14 and 16. For example, a portion 142 of nitride-based semiconductor layer 14 may extend horizontally to abut against the side surfaces of n-type doped nitride-based semiconductor layers 30 and 32. n-type doped nitride-based semiconductor layers 30 and 32 are connected to nitride-based semiconductor layers 14 and 16. n-type doped nitride-based semiconductor layers 30 and 32 may extend vertically from a portion 144 of nitride-based semiconductor layer 14 to a position above the interface between nitride-based semiconductor layers 14 and 16.

[0029] P-type doped nitride-based semiconductor layers 34 and 36 are disposed on n-type doped nitride-based semiconductor layers 30 and 32, respectively. The p-type doped nitride-based semiconductor layers 34 and 36 can contact the n-type doped nitride-based semiconductor layers 30 and 32, respectively. The p-type doped nitride-based semiconductor layers 34 and 36 are completely located above the nitride-based semiconductor layers 14 and 16. At a location above the interface between the nitride-based semiconductor layers 14 and 16, the n-type doped nitride-based semiconductor layers 30 and 32 can form interfaces with the p-type doped nitride-based semiconductor layers 34 and 36, respectively. In some embodiments, the thickness of the n-type doped nitride-based semiconductor layers 30 and 32 is greater than the thickness of the p-type doped nitride-based semiconductor layers 34 and 36.

[0030] In some embodiments, the doping concentration of each of the n-type doped nitride-based semiconductor layers 30 and 32 is greater than the doping concentration of each of the p-type doped nitride-based semiconductor layers 34 and 36. For example, the n-type doped nitride-based semiconductor layers 30 and 32 can be used as "n+" nitride-based semiconductor layers, while the p-type doped nitride-based semiconductor layers 34 and 36 can be used as "p" nitride-based semiconductor layers.

[0031] Exemplary materials for the p-type doped nitride-based semiconductor layers 34 and 36 may include, but are not limited to, p-type doped III-V group nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is achieved by using p-type impurities (e.g., Be, Zn, Cd, and Mg). In some embodiments, the doped III-V semiconductor layer 20 and the p-type doped nitride-based semiconductor layers 34 and 36 have the same material. In some embodiments, the doped III-V semiconductor layer 20 and the p-type doped nitride-based semiconductor layers 34 and 36 are formed by patterning a single blanket-like p-type doped nitride-based semiconductor layer.

[0032] Electrode 40 is disposed on n-type doped nitride-based semiconductor layer 30 and p-type doped nitride-based semiconductor layer 34. Electrode 40 can penetrate the p-type doped nitride-based semiconductor layer 34 to contact the n-type doped nitride-based semiconductor layer 30. Electrode 40 can extend downward such that its bottom surface is lower than the bottom surface of the p-type doped nitride-based semiconductor layer 34. The bottom surface of electrode 40 is within the thickness range of the n-type doped nitride-based semiconductor layer 30. The bottom surface of electrode 40 is positioned higher than the nitride-based semiconductor layer 16. Electrode 40 has a side surface that contacts the inner surfaces of the p-type doped semiconductor layer 34 and the n-type doped nitride-based semiconductor layer 30.

[0033] Electrode 42 is disposed on n-type doped nitride-based semiconductor layer 32 and p-type doped nitride-based semiconductor layer 36. Electrode 42 can penetrate the p-type doped nitride-based semiconductor layer 36 to contact the n-type doped nitride-based semiconductor layer 32. Electrode 42 can extend downward such that the bottom surface of electrode 42 is lower than the bottom surface of p-type doped nitride-based semiconductor layer 36. The bottom surface of electrode 42 is within the thickness range of n-type doped nitride-based semiconductor layer 32. The bottom surface of electrode 42 is located higher than nitride-based semiconductor layer 16. Electrode 42 has a side surface that contacts the inner surfaces of p-type doped semiconductor layer 36 and n-type doped nitride-based semiconductor layer 32.

[0034] Each electrode 40 and 42 can be used as either a source or a drain. For example, electrode 40 is a source and electrode 42 is a drain. In some embodiments, electrodes 40 and 42 can be referred to as ohmic electrodes. Electrodes 40, 42 and gate 22 can constitute an enhancement-mode HEMT.

[0035] In some embodiments, electrodes 40 and 42 may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductive materials, or combinations thereof. Exemplary materials for electrodes 40 and 42 may include, but are not limited to, Ti, AlSi, TiN, or combinations thereof. Electrodes 40 and 42 may be a single layer or multiple layers of the same or different compositions. In some embodiments, electrodes 40 and 42 may form an ohmic contact with the nitride-based semiconductor layer 16. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to electrodes 40 and 42.

[0036] In some embodiments, each electrode 40 and 42 is formed of at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer include, but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. Exemplary materials for the conductive filler may include, but are not limited to, AlSi, AlCu, or combinations thereof.

[0037] The p-type doped nitride-based semiconductor layers 34 and 36 define the carrier inlets for electrodes 40 and 42. Electrodes 40 and 42 extend through the p-type doped nitride-based semiconductor layers 34 and 36 to inject carriers into the n-type doped nitride-based semiconductor layers 30 and 32. The sidewalls of electrodes 40 and 42 adjacent to the top surfaces of the n-type doped nitride-based semiconductor layers 30 and 32 are covered by the p-type doped nitride-based semiconductor layers 34 and 36. The resistance of the p-type doped nitride-based semiconductor layers 34 and 36 blocks leakage current from electrodes 40 and 42. In other cases, if the sidewalls of the electrodes adjacent to the top surfaces of the n-type doped nitride-based semiconductor layers are covered by a dielectric, interface defects between the electrodes and the dielectric may lead to leakage current. Furthermore, due to the resistance of the p-type doped nitride-based semiconductor layers 34 and 36, electrodes 40 and 42 need to completely extend through the p-type doped nitride-based semiconductor layers 34 and 36.

[0038] Furthermore, this structure is compatible with the process of forming p-type doped nitride-based semiconductor layers 34 and 36 after forming n-type doped nitride-based semiconductor layers 30 and 32. Therefore, once the p-type doped nitride-based semiconductor layer is formed on the channel layer before the formation of the n-type doped nitride-based semiconductor layer, the dopant in the p-type doped nitride-based semiconductor layer diffuses into the channel layer during the formation of the n-type doped nitride-based semiconductor layer, resulting in a decrease in channel mobility and carrier concentration.

[0039] A passivation layer 50 is disposed on the nitride-based semiconductor layer 16. The passivation layer 50 covers n-type doped nitride-based semiconductor layers 30 and 32 and p-type doped nitride-based semiconductor layers 34 and 36. Exemplary materials for the passivation layer 50 may include, but are not limited to, SiN. x SiO x The passivation layer 50 may be a multilayer structure, such as a composite dielectric layer of Al2O3 / SiN, Al2O3 / SiO2, AlN / SiN, AlN / SiO2, or a combination thereof. In some embodiments, the passivation layer 50 may be a multilayer structure, such as a composite dielectric layer of Al2O3 / SiN, Al2O3 / SiO2, AlN / SiN, AlN / SiO2, or a combination thereof.

[0040] As described below, Figure 2A , Figure 2B , Figure 2C and Figure 2D Different stages of a method for fabricating a nitride-based semiconductor device 1A are illustrated. In the following, deposition techniques may include (but are not limited to) atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other processes.

[0041] Reference Figure 2A A buffer layer 12 is formed on substrate 10. Nitride-based semiconductor layers 14 and 16 (i.e., channel layer and barrier layer) are formed on buffer layer 12. Nitride-based semiconductor layer 14 has portions 142 and 144 as described above. n-type doped nitride-based semiconductor layers 30 and 32 are formed on portion 144 of nitride-based semiconductor layer 14. The formation of n-type doped nitride-based semiconductor layers 30 and 32 includes epitaxial growth. Prior to epitaxial growth, a mask layer is provided to cover nitride-based semiconductor layer 16 and expose portion 144 of nitride-based semiconductor layer 14. Therefore, the formation of n-type doped nitride-based semiconductor layers 30 and 32 is selective epitaxial growth.

[0042] refer to Figure 2B A p-type doped nitride-based semiconductor layer 60 is formed to cover n-type doped nitride-based semiconductor layers 30 and 32 and nitride-based semiconductor layer 16.

[0043] Reference Figure 2C A patterning process is performed on a blanket-coated p-type doped nitride-based semiconductor layer 60. This removes at least a portion of the blanket-coated p-type doped nitride-based semiconductor layer 60. The patterning process may include at least one etching stage. After the patterning process, the doped nitride-based semiconductor layer 20 remains on the nitride-based semiconductor layer 16, and the p-type doped nitride-based semiconductor layers 34 and 36 remain on the n-type doped nitride-based semiconductor layers 30 and 32. In some embodiments, dopants in the p-type doped nitride-based semiconductor layers 34 and 36 may diffuse into the n-type doped nitride-based semiconductor layers 30 and 32, allowing for variations in the thickness of the n-type doped nitride-based semiconductor layers 30 and 32. At least one n-type feature in a portion of the n-type doped nitride-based semiconductor layers 30 and 32 may be weakened.

[0044] Since the n-type doped nitride-based semiconductor layers 30 and 32 are formed before the formation of the doped nitride-based semiconductor layer 20 and the p-type doped nitride-based semiconductor layers 34 and 36, the risk of dopants in the p-type doped nitride-based semiconductor layers 34 and 36 diffusing into the channel layer during the formation of the n-type doped nitride-based semiconductor layers 30 and 32 is minimal. This avoids a potential reduction in channel mobility and carrier concentration.

[0045] refer to Figure 2DA passivation layer 50 is formed on the nitride-based semiconductor layer 16. Subsequently, a portion of the passivation layer 50 is removed to expose the p-type doped nitride-based semiconductor layers 34 and 36. A removal process is performed on the p-type doped nitride-based semiconductor layers 34 and 36 to form vias within them. The removal process may include at least one etching stage. Since the n-type doped nitride-based semiconductor layers 30 and 32 and the p-type doped nitride-based semiconductor layers 34 and 36 have the same or similar materials, it is difficult to avoid removing the n-type doped nitride-based semiconductor layers 30 and 32 during the removal process. Therefore, a portion of the n-type doped nitride-based semiconductor layers 30 and 32 is removed to form recesses within them. Electrodes and gates, as described above, are then formed, with the electrodes formed in the vias, thereby obtaining... Figure 1 The structure shown.

[0046] Figure 3 This is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present invention. The nitride-based semiconductor device 1B is similar to... Figure 1 The nitride-based semiconductor device 1A is different from the nitride-based semiconductor device 1B, which has a dual-channel design.

[0047] The nitride-based semiconductor device 1B includes III-V layers 70 and 72 disposed alternately with stacked sub-portions SP1 and SP2 of a nitride-based semiconductor layer 14 along a vertical direction. III-V layer 70 is located between sub-portions SP1 and SP2 of the nitride-based semiconductor layer 14. III-V layer 70 contacts sub-portion SP1 of the nitride-based semiconductor layer 14 to form a heterojunction therebetween having a 2DEG region 15A. III-V layer 72 is located between sub-portion SP2 of the nitride-based semiconductor layer 14 and a nitride-based semiconductor layer 16. III-V layer 72 contacts nitride-based semiconductor layer 16 to form a heterojunction therebetween having a 2DEG region 15B. III-V layers 70 and 72 overlap with the thickness range of n-type doped nitride-based semiconductor layers 30 and 32, thereby forming a dual-channel completely located between the n-type doped nitride-based semiconductor layers 30 and 32. In some embodiments, each III-V layer 70 and 72 includes an aluminum nitride layer. This design can be adapted to the requirements of RF devices.

[0048] Figure 4 This is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present invention. The nitride-based semiconductor device 1C is similar to... Figure 3The nitride-based semiconductor device 1B differs in that it has only one III-V layer 74. The III-V layer 74 is located between sub-portions SP1 and SP2 of the nitride-based semiconductor layer 14. The III-V layer 74 contacts the sub-portion SP1 of the nitride-based semiconductor layer 14 to form a heterojunction therebetween having a 2DEG region 15C. The nitride-based semiconductor layer 16 may contact the nitride-based semiconductor layer 14 to form a heterojunction therebetween having a 2DEG region 15D. In some embodiments, the configuration can be achieved by adjusting the bandgap of the materials applied to the nitride-based semiconductor layers 14 and 16 and the III-V layer 74. In some embodiments, the configuration can be achieved by selecting the materials used for the nitride-based semiconductor layers 14 and 16 and the III-V layer 74.

[0049] Figure 5 This is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present invention. The nitride-based semiconductor device 1D is similar to... Figure 1 The nitride-based semiconductor device 1A differs in that the n-type doped nitride-based semiconductor layers 30 and 32 are replaced by n-type doped nitride-based semiconductor layers 30D and 32D. The n-type doped nitride-based semiconductor layers 30D and 32D have different thicknesses. The n-type doped nitride-based semiconductor layer 32D can extend downwards to a depth deeper than the n-type doped nitride-based semiconductor layer 30D. This configuration is considered because the n-type doped nitride-based semiconductor layer 32D can be used to improve the drain contact resistance. During high-voltage operation, excessive resistance can generate heat, leading to power loss. Therefore, this configuration can mitigate this defect.

[0050] In some embodiments, to enhance the improvement of drain contact resistance, the n-type doped nitride-based semiconductor layers 30D and 32D may have different doping concentrations. For example, the doping concentration of the n-type doped nitride-based semiconductor layer 32D is greater than the doping concentration of the n-type doped nitride-based semiconductor layer 30D.

[0051] Figure 6 This is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present invention. The nitride-based semiconductor device 1E is similar to... Figure 1The nitride-based semiconductor device 1A differs in that the p-type doped nitride-based semiconductor layers 34 and 36 are replaced by p-type doped nitride-based semiconductor layers 34D and 36D. The p-type doped nitride-based semiconductor layers 34D and 36D can further cover the sidewalls of the n-type doped nitride-based semiconductor layers 30 and 32. This coverage of the n-type doped nitride-based semiconductor layers 30 and 32 by the p-type doped nitride-based semiconductor layers 34D and 36D can prevent the n-type doped nitride-based semiconductor layers 30 and 32 from being etched during the patterning process of the p-type doped nitride-based semiconductor layers 34D and 36D.

[0052] These embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the intended particular use.

[0053] As used herein and unless otherwise defined, the terms “substantially,” “essentially,” “approximately,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the term can include both cases where the event or situation occurred precisely and cases where the event or situation occurred approximately. For example, when used with numerical values, these terms can cover a range of variation less than or equal to ±10% of that value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces placed within a micrometer-scale distance along the same plane, such as two surfaces placed within a 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm distance along the same plane.

[0054] As used herein, the singular terms “an,” “an,” and “the” may include plural indicators unless the context clearly indicates otherwise. In the description of some embodiments, a component positioned “on another component” or “above another component” may cover a situation where the preceding component is directly positioned on the following component (e.g., in physical contact with the following component), and a situation where one or more intermediate components are located between the preceding and following components.

[0055] While the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations are not necessarily drawn to scale. Artistic representations of the invention may differ from actual devices due to manufacturing processes and tolerances. Furthermore, it should be understood that actual devices and layers may deviate from the rectangular layer depicted in the drawings due to manufacturing processes such as conformal deposition, etching, etc., and may include corner surfaces or edges, rounded corners, etc. Other embodiments of the invention may exist that are not specifically shown. The specification and drawings are intended to be illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are included within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limiting.

Claims

1. A semiconductor device, characterized in that, include: A first nitride-based semiconductor layer has a first portion and a second portion, wherein the thickness of the first portion is greater than the thickness of the second portion and is surrounded by the second portion; A second nitride-based semiconductor layer is disposed on the first portion and has a larger band gap than the first nitride-based semiconductor layer; An n-type doped nitride-based semiconductor layer is disposed on the second portion of the first nitride-based semiconductor layer; A p-type doped nitride-based semiconductor layer is disposed on and in contact with the n-type doped nitride-based semiconductor layer. as well as An electrode that penetrates the p-type doped nitride-based semiconductor layer to contact the n-type doped nitride-based semiconductor layer; A p-type doped nitride-based semiconductor layer covers the sidewalls of an n-type doped nitride-based semiconductor layer.

2. The semiconductor device according to claim 1, characterized in that, The electrode extends downwards such that the bottom surface of the electrode is lower than the bottom surface of the p-type doped nitride-based semiconductor layer.

3. The semiconductor device according to claim 1, characterized in that, The side surface of the electrode is in contact with the inner surfaces of the p-type doped nitride-based semiconductor layer and the n-type doped nitride-based semiconductor layer.

4. The semiconductor device according to claim 1, characterized in that, The doping concentration of the n-type doped nitride-based semiconductor layer is greater than that of the p-type doped nitride-based semiconductor layer.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the n-type doped nitride-based semiconductor layer is greater than the thickness of the p-type doped nitride-based semiconductor layer.

6. The semiconductor device according to claim 1, characterized in that, The electrode has a bottom surface located at a position higher than the second nitride-based semiconductor layer.

7. The semiconductor device according to claim 1, characterized in that, It further includes a gate p-type doped nitride-based semiconductor layer disposed on the second nitride-based semiconductor layer.

8. The semiconductor device according to claim 7, characterized in that, The material of the gate p-type doped nitride-based semiconductor layer is the same as the material of the p-type doped nitride-based semiconductor layer.

9. The semiconductor device according to claim 1, characterized in that, The first nitride-based semiconductor layer is in contact with the second nitride-based semiconductor layer to form a heterojunction therebetween having a two-dimensional electron gas (2DEG) region.

10. The semiconductor device according to claim 1, characterized in that, It further includes a plurality of III-V layers arranged alternately with a plurality of stacked sub-parts of the first nitride-based semiconductor layer in a vertical direction, wherein each of the III-V layers contacts a corresponding sub-part of the first nitride-based semiconductor layer to form a heterojunction therebetween having a two-dimensional electron gas (2DEG) region.

11. The semiconductor device according to claim 10, characterized in that, Each of the III-V layers contains an aluminum nitride layer.

12. The semiconductor device according to claim 10, characterized in that, The III-V layer is within the thickness range of the n-type doped nitride-based semiconductor layer.

13. The semiconductor device according to claim 1, characterized in that, The first portion of the first nitride-based semiconductor layer extends horizontally to abut against the side surface of the n-type doped nitride-based semiconductor layer.

14. A method for manufacturing a semiconductor device, characterized in that, include: A first nitride-based semiconductor layer is formed having a first portion and a second portion, wherein the thickness of the first portion is greater than the thickness of the second portion and is surrounded by the second portion; A second nitride-based semiconductor layer is formed on the first portion of the first nitride-based semiconductor layer; An n-type doped nitride-based semiconductor layer is formed on the second portion of the first nitride-based semiconductor layer; A blanket-type p-type doped nitride-based semiconductor layer is formed to cover the n-type doped nitride-based semiconductor layer and the second nitride-based semiconductor layer; A patterning process is performed on the blanket-covered p-type doped nitride-based semiconductor layer, such that a portion of the blanket-covered p-type doped nitride-based semiconductor layer remains on the n-type doped nitride-based semiconductor layer. Through-holes are formed in the portion of the blanket-coated p-type doped nitride-based semiconductor layer; as well as Multiple electrodes are formed in the vias, such that the bottom of each electrode is covered by the n-type doped nitride-based semiconductor layer and the p-type doped nitride-based semiconductor layer. A p-type doped nitride-based semiconductor layer covers the sidewalls of an n-type doped nitride-based semiconductor layer.

15. The manufacturing method according to claim 14, characterized in that, Before forming the n-type doped nitride-based semiconductor layer, a mask layer is provided to cover the second nitride-based semiconductor layer and expose the second portion of the first nitride-based semiconductor layer.

16. The manufacturing method according to claim 14, characterized in that, The n-type doped nitride-based semiconductor layer is formed such that the side surface of the n-type doped nitride-based semiconductor layer is in contact with the side surfaces of the first portion and the second portion of the first nitride-based semiconductor layer.

17. The manufacturing method according to claim 14, characterized in that, After the patterning process, at least a portion of the blanket-coated p-type doped nitride-based semiconductor layer is further retained on the second nitride-based semiconductor layer.

18. The manufacturing method according to claim 14, characterized in that, The doping concentration of the n-type doped nitride-based semiconductor layer is greater than that of the blanket-type p-type doped nitride-based semiconductor layer.

19. A semiconductor device, characterized in that, include: A first nitride-based semiconductor layer has a first portion and a second portion, wherein the thickness of the first portion is greater than the thickness of the second portion and is surrounded by the second portion; A second nitride-based semiconductor layer is disposed on the first portion and has a larger band gap than the first nitride-based semiconductor layer; An n-type doped nitride-based semiconductor layer is disposed on the second portion of the first nitride-based semiconductor layer and extends vertically from the second portion of the first nitride-based semiconductor layer to a position above the interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer; as well as A p-type doped nitride-based semiconductor layer is disposed on and in contact with the n-type doped nitride-based semiconductor layer. An electrode that penetrates the p-type doped nitride-based semiconductor layer to contact the n-type doped nitride-based semiconductor layer; the p-type doped nitride-based semiconductor layer covers the sidewalls of the n-type doped nitride-based semiconductor layer.

20. The semiconductor device according to claim 19, characterized in that, At a location above the interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer, the n-type doped nitride-based semiconductor layer and the p-type doped nitride-based semiconductor layer form an interface.

21. The semiconductor device according to claim 19, characterized in that, The doping concentration of the n-type doped nitride-based semiconductor layer is greater than that of the p-type doped nitride-based semiconductor layer.

22. The semiconductor device according to claim 19, characterized in that, The thickness of the n-type doped nitride-based semiconductor layer is greater than the thickness of the p-type doped nitride-based semiconductor layer.

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