Chip design method and chip design system

Abstract

The present invention provides a chip design method and a chip design system. The chip design method includes: reading a netlist; identifying multiple interfaces of a submodule in a chip based on the netlist; confirming the interface position of at least one designated interface among the multiple interfaces; determining the location of an interface unit based on the interface position of the at least one designated interface and a designated spacing; and determining the location of a decoupling capacitor based on the location of the interface unit. The chip design method and chip design system of the present invention can automatically and efficiently design the location of the interface unit and the decoupling capacitor in a chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a chip design method and a chip design system. Background Art

[0002] In traditional chip design, due to the large design scale of circuit layouts in advanced processes, for example, static timing analysis (STA) takes a long time. Therefore, timing issues related to the interfaces of multiple sub-modules in the chip need to be avoided in advance during the chip design process to avoid wasting design time. However, the current implementation method is to manually modify and edit layout data, which has the problems of low design efficiency and prone to human error. Summary of the Invention

[0003] The present invention is directed to a chip design method and a chip design system, which can provide effective and convenient chip design effects.

[0004] According to an embodiment of the present invention, the chip design method of the present invention includes: reading a netlist; identifying multiple interfaces of a sub-module in a chip based on the netlist; confirming the interface position of at least one specified interface among the multiple interfaces; determining the setting position of an interface unit based on the interface position of at least one specified interface and a specified spacing; and determining the setting position of a decoupling capacitor based on the setting position of the interface unit.

[0005] In one embodiment of the present invention, the plurality of interfaces include an input interface, an output interface, and a clock interface.

[0006] In one embodiment of the present invention, the at least one designated interface is an input interface.

[0007] In one embodiment of the present invention, the interface unit is a buffer unit.

[0008] In one embodiment of the present invention, the step of confirming the interface position of at least one designated interface among the plurality of interfaces includes: designating a name of an interface that does not require an interface unit to be set.

[0009] In one embodiment of the present invention, the distance between the aforementioned interface position and the location where the interface unit is disposed meets the minimum physical distance requirement of the design constraint.

[0010] In one embodiment of the present invention, a first preset spacing distance is provided between two adjacent interface units in the submodule in the first direction, and the first preset spacing distance is equal to the height of one interface unit.

[0011] In one embodiment of the present invention, a second preset spacing distance exists between two adjacent interface units in the submodule in the second direction. The first direction is perpendicular to the second direction.

[0012] In one embodiment of the present invention, the interface units corresponding to the designated interfaces and the decoupling capacitors in the submodule are arranged in an alternating manner.

[0013] In an embodiment of the present invention, the plurality of interface units are of the same predetermined size, and / or the plurality of decoupling capacitors are of the same predetermined size.

[0014] In one embodiment of the present invention, at least one side of each of the plurality of interface units is connected to at least one side of at least one of the plurality of decoupling capacitors.

[0015] According to an embodiment of the present invention, a chip design system includes a storage device and a processing device. The storage device is used to store a netlist. The processing device is coupled to the storage device and is used to read the netlist. The processing device identifies multiple interfaces of a submodule in the chip based on the netlist and confirms the interface position of at least one designated interface among the multiple interfaces. The processing device determines the location of an interface unit based on the interface position of the at least one designated interface and a designated spacing, and the processing device determines the location of a decoupling capacitor based on the location of the interface unit.

[0016] Based on the above, the chip design method and chip design system of the present invention can automatically and effectively design the locations of interface units and decoupling capacitors in a chip.

[0017] The present invention will be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of simplicity, many of the figures herein depict only portions of the display device, and certain components in the figures are not drawn to scale. Furthermore, the number and dimensions of components in the figures are for illustration only and are not intended to limit the scope of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a chip design system according to an embodiment of the present invention;

[0019] Figure 2 is a circuit diagram of a submodule in a chip according to an embodiment of the present invention;

[0020] Figure 3 is a flow chart of a chip design method according to an embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of the layout of submodules in a chip according to an embodiment of the present invention;

[0022] Figure 5 It is a schematic diagram of the layout of submodules in a chip according to an embodiment of the present invention.

[0023] Description of Reference Numerals

[0024] 100: Chip design system;

[0025] 110: processing device;

[0026] 120: storage device;

[0027] 121: Netlist;

[0028] 210, 220: submodule;

[0029] 211, 212: logic circuits;

[0030] 213: Input interface;

[0031] 214: output interface;

[0032] 215, 216, 401-404: interface unit;

[0033] 221: drive unit;

[0034] 222: load capacitance;

[0035] 400: Local circuit layout;

[0036] 411~415, 421~425: decoupling capacitors;

[0037] D1: first direction;

[0038] D2: second direction;

[0039] H1: first preset interval distance;

[0040] W1: second preset interval distance;

[0041] S310~S350: steps. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0043] Figure 1 Schematic diagram of a chip design system according to an embodiment of the present invention. Figure 1The chip design system 100 includes a processing device 110 and a storage device 120. The processing device 110 is coupled to the storage device 120. The storage device 120 can store data related to a netlist 121. In this embodiment, the processing device 110 can read the storage device 120 to obtain the netlist 121. The processing device 110 can execute a script programmed in the Tool Command Language (TCL) to implement the design of an integrated circuit (IC) chip on any tool platform. In this embodiment, the processing device 110 can identify the netlist 121 according to the script and perform corresponding circuit layout design.

[0044] In this embodiment, the processing device 110 may be, for example, a central processing unit (CPU), other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers (PCIs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), other similar processing devices, or a combination of these devices. The storage device 120 may be, for example, dynamic random access memory (DRAM), flash memory, or non-volatile random access memory (NVRAM). The storage device 120 may store a netlist 121 and the software, programs, and algorithms required to implement the present invention, and provide the processing device 110 with the execution thereof.

[0045] Figure 2 Schematic diagram of the circuit of the submodule in the chip of the embodiment of the present invention. Figure 2 The chip of the present invention may include multiple sub-modules, and one of the multiple sub-modules may be as follows Figure 2The architecture of the submodule 210 shown. In this embodiment, the submodule 210 may, for example, include logic circuits 211, 212, an input interface (port) 213, and an output interface 214. In one embodiment, the input interface 213 and / or the output interface 214 may also be a clock interface. In the process of designing the circuit layout of the submodule 210, an analogy can be made to the submodule 220 connected thereto based on the design constraints, wherein the submodule 220 includes a driving unit 221 and a load capacitor 222. The driving unit 221 and the load capacitor 222 can be used to specify the thrust size and output load of the external driving unit. The driving unit 221 can be coupled to the input interface 213, and the load capacitor 222 can be coupled to the output interface 214.

[0046] In this regard, if the driving force of the driver unit 221 is weak and / or the distance between the load capacitor 222 and the output interface 214 is far, signal transmission problems, such as excessive signal delay, may occur. Therefore, the processing device 110 of the present invention can automatically identify the interfaces 213 and 214 through the netlist 121 and can add interface units 215 and 216 between the logic circuit 211 and the input interface 213 and between the logic circuit 212 and the output interface 214 in the submodule 220, respectively. This prevents the aforementioned hypothetical signal transmission problems from occurring during the chip implementation phase during the circuit design phase. In this embodiment, the interface units 215 and 216 can be buffer units.

[0047] Figure 3 FIG. 1 is a flow chart of a chip design method according to an embodiment of the present invention. Figure 1 as well as Figure 3 In view of the above Figure 2In this embodiment, the processing device 110 may perform the following steps S310 to S350 to implement automated chip design. In step S310, the processing device 110 may read the netlist 121 from the storage device 120. In step S320, the processing device 110 may identify multiple interfaces of the submodules in the chip based on the netlist 121. In this embodiment, the multiple interfaces may include input interfaces, output interfaces, and clock interfaces. In step S330, the processing device 110 may determine the interface location of at least one designated interface among the multiple interfaces. In this embodiment, a user may input a command to designate an interface, so that the script executed by the processing device 110 may automatically determine the interface location of the corresponding designated interface based on the corresponding physical location information. In one embodiment, the at least one designated interface may be an input interface. In other words, the processing device 110 may designate the addition of interface units only for input interfaces, but the present invention is not limited to this. In another embodiment, the user may input a command to specify that no interface units are required, so that the processing device 110 may specify the interface names for which no interface units are required, for example, not adding interface units to output interfaces. In this way, the script executed by the processing device 110 can automatically exclude the interfaces that do not need to be configured with the interface unit during the above confirmation process.

[0048] In step S340, processing device 110 may determine the location of the interface unit based on the interface location of the at least one designated interface and the designated spacing. The at least one designated interface may be a buffer unit. In this embodiment, the location of the interface unit must be close to the interface location of the corresponding designated interface. To this end, the distance between the interface location of the designated interface and the location of the interface unit may meet the minimum physical distance requirement of the design constraints.

[0049] In step S350, the processing device 110 may determine the location of a decoupling capacitor based on the location of the interface unit. In this embodiment, the processing device 110 may further add decoupling capacitors between the multiple buffer units set in the previous step to improve the dynamic voltage drop problem caused by the simultaneous voltage level flipping of a large number of buffer units. In this embodiment, the processing device 110 may modify the netlist 121 to configure the interface unit based on the location of the interface unit defined above, and to configure the decoupling capacitor based on the location of the decoupling capacitor defined above. After completing the modification, the processing device 110 may store the modified netlist 121 in the storage device 120.

[0050] Figure 4 It is a schematic diagram of the layout of submodules in a chip according to an embodiment of the present invention. Figure 5 Schematic diagram of the layout of the submodules in the chip of the embodiment of the present invention. Figure 1 as well as Figure 4 , the processing device 110 can read the netlist 121 and identify multiple interfaces of the submodules in the chip. The netlist 121 can, for example, describe Figure 4 The local circuit layout 400 of the submodule shown. In this embodiment, the processing device 110 can determine the setting position of the interface units 401 to 404 according to the interface position of the specified interface and the specified spacing. The specified spacing may include a first preset spacing distance H1 between two adjacent interface units 401 and 404 in the first direction D1 in the submodule, and the first preset spacing distance H1 is equal to the height of one interface unit. In addition, the specified spacing may also include a second preset spacing distance W1 between two adjacent interface units 402 and 403 in the second direction D2 in the submodule, wherein the first direction D1 is perpendicular to the second direction D2. As Figure 4 As shown, the interface units 401 - 404 may be arranged in a staggered manner. In this embodiment, appropriate spacing may be maintained between the interface units 401 - 404 to effectively avoid IR violations.

[0051] Next, refer to Figure 1 as well as Figure 5 , the processing device 110 can further determine the setting positions of the decoupling capacitors 411 to 415 and 421 to 425 according to the setting positions of the interface units 401 to 404. In this embodiment, the processing device 110 can automatically determine the setting positions of the interface units 401 to 404, and further set the decoupling capacitors 411 to 415 and 421 to 425 in the intervals between the interface units 401 to 404. It should be noted that at least one side of each of the interface units 401 to 404 can be connected to at least one side of at least one of the decoupling capacitors 411 to 415 and 421 to 425, so that it can be used to decouple the corresponding interface unit. To this end, the interface units 401 to 404 corresponding to multiple designated interfaces in the sub-module and the decoupling capacitors 411 to 415 and 421 to 425 can be staggered. It should be noted that the positions of the multiple designated interfaces may be adjacent to each other, so that the interface units corresponding to the multiple designated interfaces may also need to be arranged adjacent to each other and arranged in a staggered manner to achieve the most effective utilization of the layout space.

[0052] Therefore, if Figure 5As shown, the processing device 110 can automatically place the interface units 401-404 and the decoupling capacitors 411-415, 421-425 in locations adjacent to one or more corresponding interfaces within the submodule. Furthermore, in subsequent chip design stages, if IR violations occur in the interface units 401-404, the reserved sufficient spacing and a certain number of decoupling capacitors 411-415, 421-425 effectively avoid the need for the user to manually modify the buffer units, thereby significantly reducing design execution time.

[0053] In addition, in this embodiment, the interface units 401 to 404 may be of the same preset size. For example, the size of the buffer unit is, for example, positively correlated to the thrust size, wherein the thrust size may be, for example, divided into X1 to X8. The buffer thrust size used in the physical implementation of the chip design may be one of X1 to X8. In this regard, the user or the processing device 110 may choose to use a buffer unit with a buffer thrust size of X4, but the present invention is not limited to this. In this embodiment, the decoupling capacitors 411 to 415 may be of the same preset size, and the decoupling capacitors 421 to 425 may be of the same another preset size. However, in one embodiment, the decoupling capacitors 411 to 415 and 421 to 425 may also be of the same preset size.

[0054] In summary, the chip design method and chip design system of the present invention can automatically design the locations of interface units and decoupling capacitors in the chip circuit layout by identifying relevant description information in the netlist, thereby achieving effective and automated chip design functions.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip design method, characterized in that: include: Read the netlist; identifying a plurality of interfaces of a submodule in the chip according to the netlist; confirming an interface location of at least one designated interface among the plurality of interfaces; determining a setting position of an interface unit according to the interface position and the specified spacing of the at least one specified interface, wherein the interface unit is added between a logic circuit and an interface in the submodule, wherein a plurality of interface units corresponding to a plurality of specified interfaces in the submodule are staggered, wherein a first preset spacing distance is provided between two adjacent interface units in a first direction in the submodule, and the first preset spacing distance is equal to a height of one interface unit, and wherein a second preset spacing distance is provided between two adjacent interface units in a second direction in the submodule, and the second preset spacing distance is greater than a width of one interface unit, wherein the first direction is perpendicular to the second direction; and Determining the location of the decoupling capacitor according to the location of the interface unit, wherein the interface units corresponding to the plurality of designated interfaces in the submodule are staggered with the plurality of decoupling capacitors, and at least one side of each of the plurality of interface units is connected to at least one side of at least one of the plurality of decoupling capacitors; The multiple interfaces include an input interface, and the input interface is coupled to a driving unit in another submodule docked with the submodule.

2. The chip design method according to claim 1, characterized in that: The multiple interfaces further include an output interface and a clock interface.

3. The chip design method according to claim 2, characterized in that: The at least one designated interface is the input interface.

4. The chip design method according to claim 1, wherein: The interface unit is a buffer unit.

5. The chip design method according to claim 1, wherein: The step of confirming the interface position of the at least one designated interface among the multiple interfaces includes: Specifies the interface name for which the interface unit does not need to be configured.

6. The chip design method according to claim 1, wherein: The distance between the interface position and the setting position of the interface unit meets the minimum physical distance requirement of the design constraint.

7. The chip design method according to claim 1, wherein: The plurality of interface units have the same preset size, and / or the plurality of decoupling capacitors have the same preset size.

8. A chip design system, characterized in that: include: a storage device for storing a netlist; as well as a processing device coupled to the storage device and configured to read the netlist, wherein the processing device identifies a plurality of interfaces of the submodule in the chip according to the netlist, and the processing device confirms the interface position of at least one specified interface among the plurality of interfaces, wherein the processing device determines a setting position of an interface unit according to the interface position and a specified spacing of the at least one specified interface, wherein the interface unit is added between a logic circuit and an interface in the submodule, wherein a plurality of interface units corresponding to a plurality of specified interfaces in the submodule are staggered, wherein a first preset spacing distance is provided between two adjacent interface units in a first direction in the submodule, and the first preset spacing distance is equal to the height of one interface unit, and a second preset spacing distance is provided between two adjacent interface units in a second direction in the submodule, and the second preset spacing distance is greater than the width of one interface unit, wherein the first direction is perpendicular to the second direction; and the processing device determines a setting position of a decoupling capacitor according to the setting position of the interface unit, wherein a plurality of interface units corresponding to a plurality of specified interfaces in the submodule and a plurality of decoupling capacitors are staggered, and at least one side of each of the plurality of interface units is connected to at least one side of at least one of the plurality of decoupling capacitors; The multiple interfaces include an input interface, and the input interface is coupled to a driving unit in another submodule docked with the submodule.

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