Static built-in self-test circuit for high-precision ADC

Abstract

The high-precision ADC provided by this invention has a built-in self-test circuit for its static characteristics, comprising: in the sample-and-hold phase, sampling the input external common-mode signal Vcm to obtain a sampled common-mode signal; in the first quantization phase, sampling and amplifying the sampled common-mode signal based on the positive input signal Vip, and reducing the output impedance to obtain a first amplified common-mode signal; in the second quantization phase, sampling and amplifying the sampled common-mode signal based on the negative input signal Vin, and reducing the output impedance to obtain a second amplified common-mode signal; wherein the positive input signal Vip and the negative input signal Vin are a pair of differential signals; both the first amplified common-mode signal and the second amplified common-mode signal are quantized, and the quantization results of the two are averaged to obtain a high-precision test signal. In this invention, the sampling common-mode signal is quantized based on a pair of differential signals, and the results of the two quantizations are summed, thus eliminating sampling thermal noise.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a high-precision ADC with built-in self-test circuit for static characteristics. Background Technology

[0002] Traditional built-in self-test circuits require input of high linearity test signals; for example, an 18-bit ADC under test requires the linearity of a 21-bit test signal.

[0003] Most existing mainstream solutions employ traditional error elimination testing algorithms, which can alleviate the linearity requirements of the input signal of the ADC under test. However, traditional solutions also place high demands on the linearity of the voltage offset between the two input signals when testing high-precision ADCs. Furthermore, when testing the static characteristics of high-precision ADCs, traditional methods typically require test signals with higher precision compared to testing ordinary-precision ADCs. For example, testing a 24-bit high-precision ADC requires... 24 The test involves 16,777,215 code value intervals. Each interval contains 10 samples, requiring over 160 million samples in total. Furthermore, the ADC under test needs to be sampled dozens of times for each sampling point to reduce the impact of noise on the histogram test results. Clearly, traditional testing methods require enormous storage space and testing time when testing high-precision ADCs, making implementation difficult and incurring significant resource overhead.

[0004] Therefore, existing built-in self-test circuits have technical problems such as high requirements for the linearity of the test signal and large data storage space. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a built-in self-test circuit for the static characteristics of a high-precision ADC.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] This invention provides a built-in self-test circuit for the static characteristics of a high-precision ADC, comprising:

[0008] During the sample-and-hold phase, the input external common-mode signal Vcm is sampled to obtain the sampled common-mode signal;

[0009] In the first quantization stage, the sampled common-mode signal is sampled and amplified according to the positive input signal Vip, and the output impedance is reduced to obtain the first amplified common-mode signal;

[0010] In the second quantization stage, the sampled common-mode signal is sampled and amplified based on the negative input signal Vin, and the output impedance is reduced to obtain the second amplified common-mode signal; wherein, the positive input signal Vip and the negative input signal Vin are a pair of differential signals; both the first amplified common-mode signal and the second amplified common-mode signal are quantized, and the quantization results of the two are summed to obtain the high-precision test signal.

[0011] Optionally, the built-in self-test circuitry for static characteristics includes: a noise cancellation circuit, an operational amplifier circuit, a negative capacitor circuit, a load circuit, a clock signal generation module, and a signal redistribution module;

[0012] The clock signal generation module is used for periodic quantization control of the built-in self-test circuit for static characteristics;

[0013] The noise cancellation circuit is used to reset the voltage of the sampling capacitor and periodically sample the external common-mode signal Vcm under the condition of voltage reset of the sampling capacitor to obtain the sampled common-mode signal; under periodic quantization control, the sampled common-mode signal is subtracted from the external fully differential sine signal to obtain the voltage difference signal;

[0014] Negative capacitor circuits are used for gain compensation in operational amplifier circuits;

[0015] Operational amplifier circuits are used to amplify differential voltage signals under gain compensation to obtain amplified fully differential signals;

[0016] The signal redistribution module is used to distribute the amplified fully differential signal into sub-amplified fully differential signals and input the sub-amplified fully differential signals into the branches of the load circuit;

[0017] The load circuit is used to cancel noise in the sub-amplified fully differential signal and to sample and average the sub-amplified common-mode signal in each period in each branch. Then, the sampled and averaged sub-amplified common-mode signals in multiple branches are summed to obtain a high-precision test signal. The load circuit cancels noise in the sub-amplified fully differential signal by controlling the bandwidth of the input.

[0018] Optionally, the bandwidth of the negative capacitor circuit is less than the bandwidth of the operational amplifier circuit.

[0019] Optionally, the first output terminal of the noise cancellation circuit is connected to the first input terminal of the operational amplifier circuit and the input terminal of the negative capacitor circuit, respectively; the second output terminal of the noise cancellation circuit is connected to the second input terminal of the operational amplifier circuit and the input terminal of the negative capacitor circuit, respectively; the first output terminal of the operational amplifier circuit is connected to the first input terminal of the signal redistribution module; the second output terminal of the operational amplifier circuit is connected to the second input terminal of the signal redistribution module; the first input terminal of the signal redistribution module is connected to the first input terminal of the load circuit; the second input terminal of the signal redistribution module is connected to the second input terminal of the load circuit; and the clock signal generation module is connected to the input terminals of all switches in the static characteristic built-in self-test circuit.

[0020] Optionally, the noise cancellation circuit includes: a switch S 11 Switch S 12 Switch S 21 Switch S 22 Switch S 31 Switch S 32 Switch S 41 Switch S 42 Switches CTL1, CTL2, CH1, CH2, CHb1, CHb2, and capacitor C S1 Capacitor C S2 Capacitor C OS1 and capacitor C OS2 ;

[0021] One end of switch CH1, the positive input signal Vip, and one end of switch CHb2 are connected to each other; the other end of switch CH1, the other end of switch CHb1, and switch S 21 one end and capacitor C S1 The upper plates of switch CH2 are connected to each other; the other end of switch CHb2, the other end of switch S, and switch S 22 The other end and capacitor C S2 The upper plates are connected to each other; one end of switch CH2, the negative input signal Vin, and one end of switch CHb1 are connected to each other; switch S 21 The other end, the common-mode signal Vcm, and the switch S 22 One end of the switch is connected to the other; switch S 11 The other end, the common-mode signal Vcm, and the switch S 12 One end of the capacitor is connected to the other end; capacitor C S1 The lower electrode plate, switch S 11 One end of switch S, the other end of switch CTL1, the first input terminal of the operational amplifier circuit, and the input terminal of the negative capacitor circuit are connected to each other; switch S 31 One end of switch S is connected to the power supply voltage Vref; 41 One end is connected to the common-mode signal Vcm; switch S31 The other end, switch S 41 The other end and capacitor C OS1 The upper plates of the capacitor are connected to each other; capacitor C OS1 The lower plate is connected to one end of switch CTL1; capacitor C S2 The lower electrode plate, switch S 12 The other end, one end of switch CTL2, the second input terminal of the operational amplifier circuit, and the input terminal of the negative capacitor circuit are connected to each other.

[0022] Optionally, the operational amplifier circuit includes: operational amplifier A1 and switch S. 23 Switch S 24 Capacitor C f11 and capacitor C f12 ;

[0023] Capacitor C f11 The upper plate of capacitor C and the negative input terminal of operational amplifier A1 are both connected to the first input terminal of the operational amplifier circuit; capacitor C f12 The upper plate of the amplifier and the positive input terminal of the operational amplifier A1 are both connected to the second input terminal of the operational amplifier circuit.

[0024] Capacitor C f11 The lower electrode plate, switch S 23 The other end, the negative output of operational amplifier A1, and the first input of the signal redistribution module are connected to each other; capacitor C f12 The lower electrode plate, switch S 24 The other end, the positive output of operational amplifier A1, and the second input of the signal redistribution module are connected to each other; switch S 23 One end and switch S 24 One end of each is connected to the common-mode signal Vcm.

[0025] Optionally, the signal redistribution module includes: switch CH3, switch CH4, switch CHb3, and switch CHb4;

[0026] The first input terminal of the signal redistribution module is connected to one end of switch CH3 and one end of switch CHb3 respectively; the second input terminal of the signal redistribution module is connected to one end of switch CH4 and one end of switch CHb4 respectively; the other ends of switch CH3, the other ends of switch CHb4 and the first input terminal of the load circuit are interconnected; the other ends of switch CH4, the other ends of switch CHb3 and the second input terminal of the load circuit are interconnected.

[0027] Optionally, the load circuit includes: switch S 51 Switch S 52 Capacitor C sar1 Capacitor C sar2Resistor R1, Resistor R2, Switch S 61 and switch S 62 ;

[0028] The first input terminal of the load circuit and switch S 51 One end is connected; switch S 51 The other end is connected to capacitor C sar1 Upper plate connection; capacitor C sar1 The lower electrode plate, switch S 61 One end of the switch and one end of the resistor R1 are connected together; switch S 61 The other end of the circuit and the other end of resistor R1 are both grounded; the second input terminal of the load circuit is connected to switch S. 52 One end is connected; switch S 52 The other end is connected to capacitor C sar2 Upper plate connection; capacitor C sar2 The lower electrode plate, switch S 62 One end of switch S is connected to one end of resistor R2; switch S 62 The other end of the resistor R1 and the other end of the resistor R2 are both grounded.

[0029] Optionally, the clock signal generation module is specifically used to generate: a first periodic quantization clock signal, a second periodic quantization clock signal, a third periodic quantization clock signal, a fourth periodic quantization clock signal, a fifth periodic quantization clock signal, a sixth periodic quantization clock signal, a seventh periodic quantization clock signal, and an eighth periodic quantization clock signal.

[0030] The first periodic quantization clock signal is used to control switch S. 11 and switch S 12 The second periodic quantization clock signal is used to control switch S. 21 -S 24 The third periodic quantization clock signal is used to control switch S. 31 and switch S 32 The fourth periodic quantization clock signal is used to control switch S. 41 and switch S 42 The fifth periodic quantization clock signal is used to control switch S. 51 and switch S 52 The sixth periodic quantization clock signal is used to control switch S. 61 and switch S 62 The seventh periodic quantization clock signal is used to control switches CH1-CH4; the eighth periodic quantization clock signal is used to control switches CHb1-CHb4.

[0031] Optionally, capacitor C sar1 The collected test signals are:

[0032]

[0033] Where Vout1 represents the capacitance C sar1 The acquired test signal, where Vref represents the power supply voltage and Vnsp represents the capacitance C. S1 The noise voltage is fixed on the lower electrode plate.

[0034] This invention provides a built-in self-test circuit for the static characteristics of a high-precision ADC, comprising: in a sample-and-hold phase, sampling an input external common-mode signal Vcm to obtain a sampled common-mode signal; in a first quantization phase, sampling and amplifying the sampled common-mode signal based on the positive input signal Vip, and reducing the output impedance to obtain a first amplified common-mode signal; in a second quantization phase, sampling and amplifying the sampled common-mode signal based on the negative input signal Vin, and reducing the output impedance to obtain a second amplified common-mode signal; wherein the positive input signal Vip and the negative input signal Vin are a pair of differential signals; both the first amplified common-mode signal and the second amplified common-mode signal are quantized, and the quantization results of the two are averaged to obtain a high-precision test signal. In this invention, firstly, the sampled common-mode signal is quantized based on a pair of differential signals, and the results of the two quantizations are summed to eliminate sampling thermal noise; secondly, to address the thermal noise of the operational amplifier, the noise during the amplification process is reduced by lowering the output impedance, ultimately improving the accuracy of the acquired test signal; furthermore, the reduction in thermal noise significantly reduces the number of sampling points, thereby reducing the amount of data stored and alleviating the technical problem of large data storage space requirements.

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0036] Figure 1 A schematic diagram of a built-in self-test circuit for the static characteristics of a high-precision ADC provided in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram illustrating the implementation principle of the negative capacitor circuit 3 provided in an embodiment of the present invention;

[0038] Figure 3 The circuit timing diagram provided for embodiments of the present invention;

[0039] Figure 4 The diagram shows the sampling thermal noise cancellation effect of the built-in self-test circuit of the high-precision ADC provided in the embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0041] To improve the accuracy of test signals while alleviating the technical problem of large data storage space requirements, this invention provides a high-precision ADC with a built-in self-test circuit for static characteristics, including:

[0042] During the sample-and-hold phase, the input external common-mode signal Vcm is sampled to obtain the sampled common-mode signal;

[0043] In the first quantization stage, the sampled common-mode signal is sampled and amplified according to the positive input signal Vip, and the output impedance is reduced to obtain the first amplified common-mode signal;

[0044] In the second quantization stage, the sampled common-mode signal is sampled and amplified based on the negative input signal Vin, and the output impedance is reduced to obtain the second amplified common-mode signal; wherein, the positive input signal Vip and the negative input signal Vin are a pair of differential signals; both the first amplified common-mode signal and the second amplified common-mode signal are quantized, and the quantization results of the two are summed to obtain the high-precision test signal.

[0045] This invention provides a built-in self-test circuit for the static characteristics of a high-precision ADC, comprising: in a sample-and-hold phase, sampling an input external common-mode signal Vcm to obtain a sampled common-mode signal; in a first quantization phase, sampling and amplifying the sampled common-mode signal based on the positive input signal Vip, and reducing the output impedance to obtain a first amplified common-mode signal; in a second quantization phase, sampling and amplifying the sampled common-mode signal based on the negative input signal Vin, and reducing the output impedance to obtain a second amplified common-mode signal; wherein the positive input signal Vip and the negative input signal Vin are a pair of differential signals; both the first amplified common-mode signal and the second amplified common-mode signal are quantized, and the quantization results of the two are averaged to obtain a high-precision test signal. In this embodiment of the invention, firstly, the sampled common-mode signal is quantized based on a pair of differential signals, and the results of the two quantizations are summed to eliminate sampling thermal noise; secondly, to address the thermal noise of the operational amplifier, the noise during the amplification process is reduced by lowering the output impedance, ultimately improving the accuracy of the acquired test signal; furthermore, the reduction in thermal noise significantly reduces the number of sampling points, thereby reducing the amount of data stored and alleviating the technical problem of large data storage space requirements.

[0046] It should be specifically explained that the summation of the two quantization results eliminates noise because the differential signal obtained by the ADC under test (load circuit 5) is noise-free. Both positive and negative branch outputs have noise, but the test signal sent to the ADC under test is the difference between the two output signals, which is the differential output of the entire circuit. Therefore, since the noise terms in the positive and negative branches are of the same magnitude, the differential signal after summation is free of noise, achieving noise cancellation.

[0047] Figure 1 This is a schematic diagram of a high-precision ADC with a built-in self-test circuit for static characteristics, provided as an embodiment of the present invention. Figure 1 As shown, it includes:

[0048] Noise cancellation circuit 1, operational amplifier circuit 2, negative capacitor circuit 3, load circuit 5, clock signal generation module 6, and signal redistribution module 4;

[0049] Clock signal generation module 6 is used for periodic quantization control of the built-in self-test circuit for static characteristics;

[0050] The noise cancellation circuit 1 is used to perform voltage reset processing on the sampling capacitor, and periodically sample the external common-mode signal Vcm to obtain the sampled common-mode signal when the sampling capacitor voltage is reset; under periodic quantization control, the sampled common-mode signal is subtracted from the external fully differential sine signal to obtain the voltage difference signal;

[0051] The negative capacitor circuit 3 is used for gain compensation of the operational amplifier circuit 2;

[0052] Operational amplifier circuit 2 is used to amplify the differential voltage signal under gain compensation to obtain an amplified fully differential signal;

[0053] The signal redistribution module 4 is used to redistribute the amplified fully differential signal into sub-amplified fully differential signals and input the sub-amplified fully differential signals into the branch of the load circuit 5;

[0054] The load circuit 5 is used to eliminate noise in the sub-amplified fully differential signal and to sample and average the sub-amplified common-mode signal in each period in each branch. Then, the sampled and averaged sub-amplified common-mode signals in multiple branches are summed to obtain a high-precision test signal. The load circuit 5 eliminates noise in the sub-amplified fully differential signal by controlling the bandwidth of the input.

[0055] In this embodiment, a negative capacitor circuit 3 is used to compensate for the gain of the operational amplifier circuit 2, which significantly improves the linearity of the output test signal.

[0056] It should be noted that, in this invention, both the first amplified common-mode signal and the second amplified common-mode signal include a sub-amplified common-mode signal.

[0057] This invention proposes a built-in self-test circuit for the static characteristics of a high-precision ADC, employing sampling thermal noise cancellation technology to address the problem of sampling thermal noise. Through a simple switching mechanism, sampling thermal noise of opposite polarity but equal magnitude is quantized twice within one cycle of the ADC under test, thus achieving summation and cancellation in the digital domain. By reducing noise power, the amount of sampled data is reduced by a factor of 10, significantly saving space and time consumed in data storage.

[0058] Optionally, the bandwidth of the negative capacitor circuit 3 is less than the bandwidth of the operational amplifier circuit 2.

[0059] Optionally, the first output terminal of the noise cancellation circuit 1 is connected to the first input terminal of the operational amplifier circuit 2 and the input terminal of the negative capacitor circuit 3, respectively; the second output terminal of the noise cancellation circuit 1 is connected to the second input terminal of the operational amplifier circuit 2 and the input terminal of the negative capacitor circuit 3, respectively; the first output terminal of the operational amplifier circuit 2 is connected to the first input terminal of the signal redistribution module 4; the second output terminal of the operational amplifier circuit 2 is connected to the second input terminal of the signal redistribution module 4; the first input terminal of the signal redistribution module 4 is connected to the first input terminal of the load circuit 5; the second input terminal of the signal redistribution module 4 is connected to the second input terminal of the load circuit 5; and the clock signal generation module 6 is connected to the input terminals of all switches in the static characteristic built-in self-test circuit.

[0060] Optionally, the noise cancellation circuit 1 includes: a switch S 11 Switch S 12 Switch S 21 Switch S 22 Switch S 31 Switch S 32 Switch S 41 Switch S 42 Switches CTL1, CTL2, CH1, CH2, CHb1, CHb2, and capacitor C S1 Capacitor C S2 Capacitor C OS1 and capacitor C OS2 ;

[0061] One end of switch CH1, the positive input signal Vip, and one end of switch CHb2 are connected to each other; the other end of switch CH1, the other end of switch CHb1, and switch S 21 one end and capacitor C S1 The upper plates of switch CH2 are connected to each other; the other end of switch CHb2, the other end of switch S, and switch S 22 The other end and capacitor C S2 The upper plates are connected to each other; one end of switch CH2, the negative input signal Vin, and one end of switch CHb1 are connected to each other; switch S 21 The other end, the common-mode signal Vcm, and the switch S 22 One end of the switch is connected to the other; switch S 11 The other end, the common-mode signal Vcm, and the switch S 12 One end of the capacitor is connected to the other end; capacitor C S1 The lower electrode plate, switch S 11One end of switch S, the other end of switch CTL1, the first input terminal of operational amplifier circuit 2, and the input terminal of negative capacitor circuit 3 are connected to each other; switch S 31 One end of switch S is connected to the power supply voltage Vref; 41 One end is connected to the common-mode signal Vcm; switch S 31 The other end, switch S 41 The other end and capacitor C OS1 The upper plates of the capacitor are connected to each other; capacitor C OS1 The lower plate is connected to one end of switch CTL1; capacitor C S2 The lower electrode plate, switch S 12 The other end, one end of switch CTL2, the second input terminal of operational amplifier circuit 2, and the input terminal of negative capacitor circuit 3 are interconnected.

[0062] Optionally, the operational amplifier circuit 2 includes: operational amplifier A1 and switch S. 23 Switch S 24 Capacitor C f11 and capacitor C f12 ;

[0063] Capacitor C f11 The upper plate of the capacitor and the negative input terminal of operational amplifier A1 are both connected to the first input terminal of operational amplifier circuit 2; capacitor C f12 The upper plate of the circuit and the positive input terminal of the operational amplifier A1 are both connected to the second input terminal of the operational amplifier circuit 2.

[0064] Capacitor C f11 The lower electrode plate, switch S 23 The other end, the negative output terminal of operational amplifier A1, and the first input terminal of signal redistribution module 4 are interconnected; capacitor C f12 The lower electrode plate, switch S 24 The other end, the positive output of operational amplifier A1, and the second input of signal redistribution module 4 are interconnected; switch S 23 One end and switch S 24 One end of each is connected to the common-mode signal Vcm.

[0065] Optionally, the signal redistribution module 4 includes: switch CH3, switch CH4, switch CHb3, and switch CHb4;

[0066] The first input terminal of the signal redistribution module 4 is connected to one end of switch CH3 and one end of switch CHb3 respectively; the second input terminal of the signal redistribution module 4 is connected to one end of switch CH4 and one end of switch CHb4 respectively; the other ends of switch CH3, the other ends of switch CHb4 and the first input terminal of load circuit 5 are interconnected; the other ends of switch CH4, the other ends of switch CHb3 and the second input terminal of load circuit 5 are interconnected.

[0067] Optionally, the load circuit 5 includes: a switch S 51 Switch S 52 Capacitor C sar1 Capacitor C sar2 Resistor R1, Resistor R2, Switch S 61 and switch S 62 ;

[0068] The first input terminal of load circuit 5 and switch S 51 One end is connected; switch S 51 The other end is connected to capacitor C sar1 Upper plate connection; capacitor C sar1 The lower electrode plate, switch S 61 One end of the switch and one end of the resistor R1 are connected together; switch S 61 The other end of the circuit and the other end of resistor R1 are both grounded; the second input terminal of load circuit 5 is connected to switch S. 52 One end is connected; switch S 52 The other end is connected to capacitor C sar2 Upper plate connection; capacitor C sar2 The lower electrode plate, switch S 62 One end of switch S is connected to one end of resistor R2; switch S 62 The other end of the resistor R1 and the other end of the resistor R2 are both grounded.

[0069] Optionally, the clock signal generation module 6 is specifically used to generate: a first periodic quantized clock signal, a second periodic quantized clock signal, a third periodic quantized clock signal, a fourth periodic quantized clock signal, a fifth periodic quantized clock signal, a sixth periodic quantized clock signal, a seventh periodic quantized clock signal, and an eighth periodic quantized clock signal.

[0070] The first periodic quantization clock signal is used to control switch S. 11 and switch S 12 The second periodic quantization clock signal is used to control switch S. 21 -S 24 The third periodic quantization clock signal is used to control switch S. 31 and switch S 32 The fourth periodic quantization clock signal is used to control switch S.41 and switch S 42 The fifth periodic quantization clock signal is used to control switch S. 51 and switch S 52 The sixth periodic quantization clock signal is used to control switch S. 61 and switch S 62 The seventh periodic quantization clock signal is used to control switches CH1-CH4; the eighth periodic quantization clock signal is used to control switches CHb1-CHb4.

[0071] In this invention, the on-state of switches controlled by the same periodic quantization clock signal changes synchronously.

[0072] For ease of description, S1 will be used to uniformly represent switch S in the following text. 11 and switch S 12 S2 uniformly represents switch S 21 -S 24 S3 uniformly represents switch S 31 and switch S 32 S4 uniformly represents switch S 41 and switch S 42 S5 uniformly represents switch S 51 and switch S 52 S6 uniformly represents switch S 61 and switch S 62 CH uniformly represents switches CH1-CH4, CHb uniformly represents CHb1-CHb4, and CTL uniformly represents switches CTL1 and CTL2.

[0073] Furthermore, due to the symmetry of the fully differential circuit, the capacitance C S1 and C S2 The capacitance values ​​are equal, and the capacitor C OS1 and C OS2 With equal capacitance values, capacitor C f11 and C f12 With equal capacitance values, capacitor C sar1 and C sar2 The capacitance values ​​are equal; they will be referred to as C throughout the text. S C os C f1 and C sar To express.

[0074] Corresponding to Figure 1 Due to the capacitor C S Looking at the operational amplifier circuit 2 from the lower plate, the input node is a high-impedance node, thus satisfying the law of charge conservation. With the opening of switch S1, the noise charge contained in the sample is fixed at the input node of operational amplifier circuit 2. Subsequently, S2 and S3 are disconnected, and the charge is fixed at C. OS and C SThe pressure differences are as follows:

[0075] ΔVos=Vref-Vcm+Vns;

[0076] ΔVs=Vcm-Vcm+Vns=Vns;

[0077] Where Vns represents C when connected to the positive input terminal. S The corresponding noise voltage or when connected to the negative input terminal C S The corresponding noise voltage; next, the first quantization stage is performed. Switches S4 and CH are closed, and the external positive input signal Vip is connected. At the same time, switches S5 and S6 are closed to acquire the signal amplified at the output of operational amplifier circuit 2. Here, switch S6 bypasses the resistor, resulting in a larger bandwidth for the operational amplifier, allowing for faster setup. It should be noted that the conduction time of switch S6 is only 1 / 3 of that of switch S5. During its off-state, the resistor and C... sar The series connection increases the output impedance of the op-amp and reduces its bandwidth. By opening and closing switch S6, the circuit achieves rapid signal establishment at the op-amp output and reduces op-amp noise.

[0078] Taking the negative input terminal of the operational amplifier as an example, during the first quantization stage, the law of conservation of charge at the input node of operational amplifier circuit 2 is as follows:

[0079] (Vref-Vcm+Vnsp)Cos+VnspCs=(Vip-Vcm)Cs+(Vout1-Vcm)Cf1;

[0080] The sampling capacitance C of the ADC under test is obtained by sorting. sar1 The test signal Vout1 acquired during the first quantization phase:

[0081]

[0082] The voltage offset between two input test signals;

[0083] This represents the voltage difference amplification signal between the external input signal and the common-mode signal, where V... ref V of the ADC under test ref It uses the same power supply voltage. Vnsp indicates that C is connected to the negative input terminal. S The corresponding noise voltage.

[0084] As can be seen, the accuracy of both the search voltage offset term and the external input signal amplification term is affected by sampling thermal noise. Switch S5 is open, ending the sampling operation of the ADC under test. Then CH is opened, ending the first quantization stage. Immediately following is a reset operation of the op-amp output level. Switch S4 is open, then switch S2 is closed again. According to the law of conservation of charge, it is easy to see that both the input and output terminals of the op-amp are reset to V. cm This ensures that the op-amp has the same initial operating state at the start of the second quantization phase as it did in the first quantization phase.

[0085] When switch S4 closes again, and switches CHb, S5, and S6 are also closed, the second quantization phase begins. Still taking the negative input terminal of the op-amp as an example, capacitor CS samples the external negative input signal Vin, which is then amplified and sampled by the sampling capacitor Csar2 of the ADC under test. Similarly, capacitor C... sar1 The test signal collected in the second quantization phase is as follows:

[0086]

[0087] Vnsn indicates that C is connected to the positive input terminal. S The corresponding noise voltage.

[0088] Due to the symmetry of the differential structure, the test signals sampled by capacitor Csar2 in both quantization stages also contain the same noise amplification term.

[0089] After the two quantization stages are completed, the results of the two quantization stages can be summed in the digital domain to eliminate the sampling thermal noise introduced during the sample-and-hold stage.

[0090] It should be noted that during the duty cycle when no constant bias voltage is applied to the output, the CTL switch remains open. When a constant bias voltage needs to be applied to the test signal, the CTL switch remains closed. The working principle of the negative capacitor circuit 3 is briefly described below using the duty cycle when the CTL switch is open as an example.

[0091] because Figure 1 The open-loop gain of operational amplifier circuit 2 is limited, and the signal V at the output terminal of operational amplifier circuit 2 is used alone. out It is not precise; its error term is related to the open-loop gain A1, and is expressed by the following formula:

[0092]

[0093] For simplicity, β represents C. f1 / (C s +C f1 ).

[0094] From the above equation, it can be concluded that the open-loop gain A1 of operational amplifier circuit 2 is a finite value, and the larger A1 is, the larger the output voltage V of operational amplifier circuit 2 becomes. out The more precise the amplification, the better, depending on the change in the negative input signal Vin. Therefore, the negative capacitor circuit 3 is used to assist the operational amplifier circuit 2 in completing the precise amplification process and improve the linearity of the output signal.

[0095] While operational amplifier circuit 2 (main op-amp) performs its amplification function, negative capacitor circuit 3 (auxiliary op-amp) is also amplifying the input signal. In the design, the bandwidth BW of the auxiliary op-amp is... a Set to a bandwidth BW smaller than that of the main operational amplifier. p (BW a <BW p This ensures the stability of the entire circuit. Once the output signal of the auxiliary operational amplifier is fully established, the amplitude of the input signal is less than the amplitude of the output signal. At this point, looking from the input node, the feedback capacitor C... f2 It is equivalent to a negative capacitor. If the capacitance ratio of each capacitor and the open-loop gain of the auxiliary operational amplifier are designed properly, the residual voltage at the input terminal of operational amplifier circuit 2 can be eliminated. Figure 2 This is a schematic diagram illustrating the implementation principle of the negative capacitor circuit 3 provided in an embodiment of the present invention. Figure 2 Figure (a) shows the output signal of circuit 3 without adding negative capacitor, where Figure 2 Figure (b) shows the output signal of the circuit with added negative capacitor 3. Specifically, Figure 3 The Negative-C circuit, i.e., the negative capacitor C, is not used in diagram (a). f2 The input node X is not connected. If noise charge is temporarily ignored, the column charge conservation theorem for node X yields VinCs = -VxCs + (Vy - Vx)C f1 Therefore, rearranging, we get Vy = 2Vin + (1 + 2)Vx. Where Vx represents the expression due to... Figure 3 In diagram (a), the open-loop gain is not infinite, resulting in a residual voltage at the input node after the op-amp has fully built up. To improve linearity, Figure 3 A Negative-C circuit (auxiliary op-amp) has been added to Figure (b). Here, the Negative-C circuit can be equivalent to a negative capacitor (1-A2)C. f2 A2 represents the open-loop gain of the auxiliary operational amplifier in the Negative-C circuit corresponding to Figure (b). Let Cs: C f1 :C f2 Since the ratio is 2:1:3 and A2 equals 2, the negative capacitance can be simplified to -3C. f1 Applying the charge conservation theorem again to node X, we obtain VinCs = -VxCs + (Vy - Vx)C f1 -Vx(1-A2)Cf2 Substituting the proportional relationships and rearranging, we get Vy = 2Vin + (1 + 2)Vx - 3Vx = 2Vin. That is, the addition of the negative capacitor eliminates the linearity degradation problem caused by insufficient open-loop gain of the op-amp, effectively eliminating the residual voltage V. X .

[0096] It should be noted that the feedback capacitor of the auxiliary operational amplifier is an adjustable capacitor. The capacitance value of Cf2 is different during the working cycle when CTL is closed or open, in order to meet the requirements of negative capacitor technology. Figure 3 The circuit timing diagram provided for the embodiments of the present invention.

[0097] Optionally, capacitor C sar1 The collected test signals are:

[0098]

[0099] Where Vout1 represents the capacitance C sar1 The acquired test signal, where Vref represents the power supply voltage and Vnsp represents the capacitance C. S1 The noise voltage is fixed on the lower electrode plate.

[0100] The high-precision ADC designed in this invention has a built-in self-test circuit for measuring the integral nonlinearity of the high-precision ADC. The circuit was designed using a 180nm standard CMOS process and simulated for verification. The entire circuit operates at a power supply voltage of 1.8V, a sampling frequency of 1MS / s, and an output test signal with a fully differential swing of 1.2V. By simultaneously using thermal noise cancellation technology, the noise performance of the output test signal is significantly improved under different capacitance conditions. Specifically, by using a negative capacitor circuit, the noise performance of the output test signal is significantly improved under different capacitance conditions. S =2pF, C f11 =1Pf, C f12 With a gain of 3pF and an auxiliary operational amplifier open-loop gain of 2x, the total harmonic power was reduced by 24.5dB. Specifically, Figure 4 The diagram illustrates the sampling thermal noise cancellation effect of the built-in self-test circuit for the static characteristics of the high-precision ADC provided in this embodiment of the invention. In summary, the circuit designed and implemented in this invention simultaneously improves the accuracy and linearity of the output test signal from the built-in self-test circuit. This test signal generation circuit avoids the need for dozens of samplings of a single code value during testing to suppress noise, reducing testing time and data storage requirements. Furthermore, with an input swing of 200mV and a magnification of 2x, the linearity of the test signal reaches -113.5dB, an improvement of 24.5dB compared to when negative capacitor technology is not used.

[0101] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0102] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0103] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-precision ADC with a built-in self-test circuit for static characteristics, characterized in that, include: During the sample-and-hold phase, the input external common-mode signal Vcm is sampled to obtain the sampled common-mode signal; In the first quantization stage, the sampled common-mode signal is sampled and amplified according to the positive input signal Vip, and the output impedance is reduced to obtain the first amplified common-mode signal; In the second quantization stage, the sampled common-mode signal is sampled and amplified based on the negative input signal Vin, and the output impedance is reduced to obtain the second amplified common-mode signal; wherein, the positive input signal Vip and the negative input signal Vin are a pair of differential signals; both the first amplified common-mode signal and the second amplified common-mode signal are quantized, and the quantization results of the two are summed to obtain a high-precision test signal; The built-in self-test circuit for static characteristics includes: a noise cancellation circuit, an operational amplifier circuit, a negative capacitor circuit, a load circuit, a clock signal generation module, and a signal redistribution module. The clock signal generation module is used for periodic quantization control of the built-in self-test circuit of the static characteristics; The noise cancellation circuit is used to perform voltage reset processing on the sampling capacitor, and periodically sample the external common-mode signal Vcm to obtain the sampled common-mode signal under the voltage reset condition of the sampling capacitor; under periodic quantization control, the sampled common-mode signal is subtracted from the external fully differential sine signal to obtain the voltage difference signal; The negative capacitor circuit is used for gain compensation of the operational amplifier circuit; The operational amplifier circuit is used to amplify the differential pressure signal under gain compensation to obtain an amplified fully differential signal. The signal redistribution module is used to distribute the amplified fully differential signal into sub-amplified fully differential signals, and input the sub-amplified fully differential signals into the branches of the load circuit; The load circuit is used to perform noise cancellation on the sub-amplified fully differential signal, and to perform sampling and averaging processing on the sub-amplified common-mode signal in each period in each branch, and then summing the sub-amplified common-mode signals after sampling and averaging processing in multiple branches to obtain a high-precision test signal; wherein, the load circuit performs noise cancellation on the sub-amplified fully differential signal by controlling the access bandwidth.

2. The static characteristic built-in self-test circuit of a high-precision ADC according to claim 1, characterized in that, The bandwidth of the negative capacitor circuit is less than the bandwidth of the operational amplifier circuit.

3. The static characteristic built-in self-test circuit of a high-precision ADC according to claim 1, characterized in that, The first output terminal of the noise cancellation circuit is connected to the first input terminal of the operational amplifier circuit and the input terminal of the negative capacitor circuit, respectively; the second output terminal of the noise cancellation circuit is connected to the second input terminal of the operational amplifier circuit and the input terminal of the negative capacitor circuit, respectively; the first output terminal of the operational amplifier circuit is connected to the first input terminal of the signal redistribution module; the second output terminal of the operational amplifier circuit is connected to the second input terminal of the signal redistribution module; the first input terminal of the signal redistribution module is connected to the first input terminal of the load circuit; the second input terminal of the signal redistribution module is connected to the second input terminal of the load circuit; the clock signal generation module is connected to the input terminals of all switches in the static characteristic built-in self-test circuit.

4. The static characteristic built-in self-test circuit of a high-precision ADC according to claim 1, characterized in that, The noise cancellation circuit includes: a switch S 11 Switch S 12 Switch S 21 Switch S 22 Switch S 31 Switch S 32 Switch S 41 Switch S 42 Switches CTL1, CTL2, CH1, CH2, CHb1, CHb2, and capacitor C S1 Capacitor C S2 Capacitor C OS1 and capacitor C OS2 ; One end of switch CH1, the positive input signal Vip, and one end of switch CHb2 are interconnected; the other end of switch CH1, the other end of switch CHb1, and switch S 21 one end and the capacitor C S1 The upper plates of the switch CH2 are connected to each other; the other end of the switch CH2, the other end of the switch CHb2, and the switch S 22 The other end and capacitor C S2 The upper plates are interconnected; one end of switch CH2, the negative input signal Vin, and one end of switch CHb1 are interconnected; switch S 21 The other end, the external common-mode signal Vcm, and the switch S 22 One end of the switch is connected to the other end; the switch S 11 The other end, the external common-mode signal Vcm, and the switch S 12 One end of the capacitor is connected to the other; the capacitor C S1 The lower electrode plate, switch S 11 One end of the switch S, the other end of the switch CTL1, the first input terminal of the operational amplifier circuit, and the input terminal of the negative capacitor circuit are interconnected; the switch S 31 One end of the switch S is connected to the power supply voltage Vref; 41 One end of the switch S is connected to the external common-mode signal Vcm; 31 The other end, the switch S 41 The other end and the capacitor C OS1 The upper plates of the capacitor C are connected to each other; OS1 The lower electrode plate is connected to one end of the switch CTL1; the capacitor C S2 The lower electrode plate, switch S 12 The other end, one end of switch CTL2, the second input terminal of the operational amplifier circuit, and the input terminal of the negative capacitor circuit are connected to each other.

5. The static characteristic built-in self-test circuit of a high-precision ADC according to claim 4, characterized in that, The operational amplifier circuit includes: operational amplifier A1 and switch S. 23 Switch S 24 Capacitor C f11 and capacitor C f12 ; The capacitor C f11 The upper plate of the capacitor and the negative input terminal of the operational amplifier A1 are both connected to the first input terminal of the operational amplifier circuit; the capacitor C f12 The upper plate of the circuit and the positive input terminal of the operational amplifier A1 are both connected to the second input terminal of the operational amplifier circuit. The capacitor C f11 The lower electrode plate, switch S 23 The other end, the negative output terminal of operational amplifier A1, and the first input terminal of the signal redistribution module are interconnected; the capacitor C f12 The lower electrode plate, switch S 24 The other end, the positive output of operational amplifier A1, and the second input of the signal redistribution module are connected to each other; switch S 23 One end and switch S 24 One end of each is connected to the external common-mode signal Vcm.

6. The static characteristic built-in self-test circuit of a high-precision ADC according to claim 5, characterized in that, The signal redistribution module includes: switch CH3, switch CH4, switch CHb3, and switch CHb4; The first input terminal of the signal redistribution module is connected to one end of switch CH3 and one end of switch CHb3, respectively; the second input terminal of the signal redistribution module is connected to one end of switch CH4 and one end of switch CHb4, respectively; the other end of switch CH3, the other end of switch CHb4 and the first input terminal of the load circuit are interconnected; the other end of switch CH4, the other end of switch CHb3 and the second input terminal of the load circuit are interconnected.

7. The static characteristic built-in self-test circuit of a high-precision ADC according to claim 6, characterized in that, The load circuit includes: switch S 51 Switch S 52 Capacitor C sar1 Capacitor C sar2 Resistor R1, Resistor R2, Switch S 61 and switch S 62 ; The first input terminal of the load circuit is connected to the switch S 51 One end is connected; the switch S 51 The other end is connected to the capacitor C sar1 The upper electrode plate is connected; the capacitor C sar1 The lower electrode plate, switch S 61 One end of the switch and one end of the resistor R1 are connected together; switch S 61 The other end of the resistor R1 and the other end of the load circuit are both grounded; the second input terminal of the load circuit is connected to the switch S. 52 One end is connected; the switch S 52 The other end is connected to the capacitor C sar2 The upper electrode plate is connected; the capacitor C sar2 The lower electrode plate, switch S 62 One end of switch S is connected to one end of resistor R2; switch S 62 The other end of the resistor R1 and the other end of the resistor R2 are both grounded.

8. The static characteristic built-in self-test circuit of a high-precision ADC according to claim 7, characterized in that, The clock signal generation module is specifically used to generate: a first periodic quantized clock signal, a second periodic quantized clock signal, a third periodic quantized clock signal, a fourth periodic quantized clock signal, a fifth periodic quantized clock signal, a sixth periodic quantized clock signal, a seventh periodic quantized clock signal, and an eighth periodic quantized clock signal. The first periodic quantization clock signal is used to control switch S 11 and switch S 12 The second periodic quantization clock signal is used to control switch S. 21 -S 24 The third periodic quantization clock signal is used to control switch S. 31 and switch S 32 The fourth periodic quantization clock signal is used to control switch S. 41 and switch S 42 The fifth periodic quantization clock signal is used to control switch S. 51 and switch S 52 The sixth periodic quantization clock signal is used to control switch S. 61 and switch S 62 The seventh periodic quantization clock signal is used to control switches CH1-CH4; the eighth periodic quantization clock signal is used to control switches CHb1-CHb4.

9. The static characteristic built-in self-test circuit of a high-precision ADC according to claim 7, characterized in that, The capacitor C sar1 The collected test signals are: ； in, Indicates capacitance C sar1 The collected test signals, Indicates the power supply voltage. Indicates capacitance C S1 The noise voltage is fixed on the lower electrode plate.

Images