A low power fast transient response LDO circuit without off-chip capacitor

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a low-power fast transient response LDO circuit without off-chip capacitor. The LDO circuit comprises an LDO main circuit, a first comparator COMP1, a second comparator COMP2, an HL pulse generating circuit, an HL pulse delay circuit, an LH pulse generating circuit, an LH pulse delay circuit, a heavy load jump light load charging PMOS transistor M HL , a light load jump heavy load discharging PMOS transistor M LH , a charging shielding MOS transistor M PHL , and a discharging shielding MOS transistor M PLH . The comparators detect load jump and output level signals to the pulse generating circuit for further processing. The LDO power transistor gate voltage is rapidly changed by turning on the charging or discharging PMOS transistor, so that the load jump is responded in an instant. The pulse delay circuit generates a wide negative pulse to shield the opening of another PMOS transistor according to the narrow negative pulse output by the pulse generating circuit. The circuit proposed in the application can be widely applied to power management systems, reduces system power consumption, reduces system area, and enhances load transient response.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a low dropout regulator (LDO) circuit with no external capacitor and low power consumption and fast transient response. BACKGROUND

[0002] The LDO is a power management chip widely used in on-chip system power supply, which uses a bandgap reference to cooperate with an error amplifier (EA) to clamp the output voltage and drive a power tube to output a certain load current as a stable power supply for a subsequent system. In a certain scenario, the power load may jump instantaneously, causing an overshoot of the LDO output voltage, which may lead to a running failure of the subsequent system.

[0003] Using an external large output capacitor can reduce the output overshoot, but using an external load capacitor means an increase in area, which is not conducive to the high-density integration of the system, especially for portable small devices. Increasing the bandwidth of the EA can improve the transient response rate of the circuit, but the trade-off is increased power consumption. The current widely used method to speed up the transient response is to increase the slew rate enhancement path to provide a fast channel for the output voltage feedback, but the additional current branch also increases the power consumption of the circuit. SUMMARY

[0004] The application aims to solve the above problems and provides an LDO circuit with no external capacitor, low power consumption and fast transient response.

[0005] To achieve the above purpose, the application adopts the following technical scheme:

[0006] The LDO circuit with no external capacitor, low power consumption and fast transient response comprises an LDO main circuit, a first comparator COMP1, a second comparator COMP2, an HL pulse generation circuit, an HL pulse delay circuit, an LH pulse generation circuit, an LH pulse delay circuit, a heavy load jump light load charging PMOS tube M HL , a light load jump heavy load discharging PMOS tube M LH , a charging shield MOS tube M PHL and a discharging shield MOS tube M PLH . The circuit does not need an external load capacitor to weaken the output voltage overshoot caused by the load jump, and the LDO circuit based on the low power consumption design can also ensure fast transient load response.

[0007] The two input ends of the first comparator COMP1 detect the output ends V A and V B of the error amplifier in the LDO main circuit, and the output end V HL1The input end of the HL pulse generating circuit; the two input ends of the second comparator COMP2 detect the output end V B and V A of the error amplifier in the LDO main circuit respectively LH1 The input end of the LH pulse generating circuit; the output end V HL of the HL pulse generating circuit HL The gate of the heavy load jump light load charging PMOS tube M PHL The input end of the HL pulse delay circuit and the drain of the charging shield MOS tube M LH The output end V LH of the LH pulse generating circuit PLH The gate of the light load jump heavy load discharging PMOS tube M PB The input end of the LH pulse delay circuit and the drain of the discharging shield MOS tube M PLH The output end V PA of the HL pulse delay circuit PHL The gate of the charging shield MOS tube M PHL The source of the charging shield MOS tube M IN Connects the input voltage V PLH of the LDO; the source of the discharging shield MOS tube M IN Connects the input voltage V HL of the LDO; the source of the heavy load jump light load charging PMOS tube M IN The drain of the light load jump heavy load discharging PMOS tube M LH The source of the power tube M P The gate V G of the LDO main circuit; the drain of the light load jump heavy load discharging PMOS tube M LH Grounded.

[0008] The first comparator COMP1 and the second comparator COMP2 are consistent in structure, and the output is reversed when the difference between the positive phase input voltage and the inverted input voltage exceeds a certain threshold value, and the change of the output load is judged by comparing the difference between the positive output V A and the negative output V B of the error amplifier in the LDO main loop. Specifically, the first comparator COMP1 and the second comparator COMP2 include a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4. In the first comparator COMP1, the gate of the first MOS tube M1 and the gate of the second MOS tube M2 are connected, and this node is the positive phase input end V BThe drain of the first MOS transistor M1 is connected to the gate of the third MOS transistor M3, and the source of the first MOS transistor M1 is connected to the inverting input terminal V A of the first comparator COMP1 IN The source of the second MOS transistor M2 is connected to the input voltage V IN of the LDO LH1 The source of the fourth MOS transistor M4 is connected to the ground, and the gate of the fourth MOS transistor M4 is connected to the bias voltage V BIAS The non-inverting input terminal of the second comparator COMP2 is V A , the inverting input terminal is V B , and the output terminal is V HL1 .

[0009] The LH pulse generating circuit outputs a negative pulse of a certain pulse width to control the on-off of the discharge PMOS transistor M LH by the output level signal of the front-stage second comparator COMP2, so as to weaken the instantaneous undershoot of the LDO output voltage HL The HL pulse generating circuit outputs a negative pulse to control the on-off of the charge PMOS transistor M LH1 by the signal of the front-stage first comparator COMP1, so as to weaken the instantaneous overshoot of the LDO output voltage. Specifically, the LH pulse generating circuit and the HL pulse generating circuit comprise a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first NAND gate NAND1, and a first capacitor C1. In the LH pulse generating circuit, the first inverter INV1, the third inverter INV3, and the fourth inverter INV4 are connected in sequence and end to end, the input terminal of the first inverter INV1 is the input terminal V LH of the LH pulse generating circuit, the output terminal of the third inverter INV3 is connected to the ground through the capacitor C1, and the output terminal of the fourth inverter INV4 is connected to one input terminal of the first NAND gate NAND1; the input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and the output terminal of the second inverter INV2 is connected to the other input terminal of the first NAND gate NAND1; the output terminal of the first NAND gate NAND1 is the output terminal V HL1 of the pulse generating circuit HL .

[0010] The LH pulse delay circuit generates a wide negative pulse by delaying the short negative pulse output by the front-stage LH pulse generating circuit, so as to control the on-off of the charge shielding MOS transistor M PHL , and shield the charge PMOS transistor M HLthe opening of the discharge shield MOS transistor M PLH the opening of the discharge shield MOS transistor M LH the opening of the discharge shield MOS transistor M. Specifically, the LH pulse delay circuit comprises a fifth inverter INV5, a sixth inverter INV6, a first NOR gate NOR1, a fifth MOS transistor M5, and a second capacitor C2. In the LH pulse delay circuit, an input end of the fifth inverter INV5, i.e., an input end V LH of the LH pulse delay circuit, is connected to the gate of the fifth MOS transistor M5 and one input end of the first NOR gate NOR1; the drain of the fifth MOS transistor M5 is connected to the tail end of a bias current source I BIAS , and is connected to the input end of the sixth inverter INV6, and is grounded through the second capacitor C2, and the source is grounded; the output end of the sixth inverter INV6 is connected to the other input end of the first NOR gate NOR1; the output end of the first NOR gate NOR1, i.e., the output end V PA of the LH pulse delay circuit, is connected to the output end of the comparator. HL The input end of the HL pulse delay circuit is V PB , and the output end is V

[0011] Compared with the prior art, the present application has the beneficial effects that: the present application proposes a low-power-consumption fast transient response LDO circuit without off-chip capacitor, two fast response paths for load jump from heavy load to light load and load jump from light load to heavy load are introduced respectively, fast response to load jump is made, and output overshoot is reduced. Load jump is detected by a comparator, and a control pulse is output. A pulse generation circuit is used for further processing, the gate voltage of the LDO power transistor is quickly changed by opening the charging or discharging PMOS transistor, so as to respond to load jump in an instant. A pulse delay circuit is used to generate a wide pulse to shield the opening of the other fast response path. In addition, the transistors in the circuit of the present application work in the sub-threshold region, which reduces the system power consumption. No off-chip load capacitor is used in the circuit of the present application, which reduces the system area while also quickly responding to load jump. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 It is a fast transient LDO overall block diagram proposed by the present application;

[0013] Figure 2 It is a circuit diagram of one implementation of the comparator of the present application in the embodiment;

[0014] Figure 3 It is a structure diagram of the pulse generation circuit;

[0015] Figure 4 It is a structure diagram of the pulse delay circuit;

[0016] Figure 5 The key node waveform diagram of the LDO proposed in the application when the load jumps. DETAILED DESCRIPTION

[0017] A low-power fast transient response LDO circuit without off-chip capacitor, comprising an LDO main circuit, a first comparator COMP1, a second comparator COMP2, an HL pulse generating circuit, an HL pulse delay circuit, an LH pulse generating circuit, an LH pulse delay circuit, a heavy load jump light load charging PMOS M HL , a light load jump heavy load discharging PMOS M LH , a charging shield MOS M PHL and a discharging shield MOS M PLH . The circuit does not require an off-chip load capacitor to weaken the output voltage overshoot caused by load jump, and can also ensure fast transient load response based on the LDO circuit under low-power design.

[0018] The two input ends of the first comparator COMP1 detect the output ends V A and V B of the error amplifier in the LDO main circuit, and the output end V HL1 of the first comparator COMP1 is connected to the input end of the HL pulse generating circuit; the two input ends of the second comparator COMP2 detect the output ends V B and V A of the error amplifier in the LDO main circuit, and the output end V LH1 of the second comparator COMP2 is connected to the input end of the LH pulse generating circuit; the output end V HL of the HL pulse generating circuit is connected to the gate of the heavy load jump light load charging PMOS M HL , the input end of the HL pulse delay circuit and the drain of the charging shield MOS M PHL ; the output end V LH of the LH pulse generating circuit is connected to the gate of the light load jump heavy load discharging PMOS M LH , the input end of the LH pulse delay circuit and the drain of the discharging shield MOS M PLH ; the output end V PB of the HL pulse delay circuit is connected to the gate of the discharging shield MOS M PLH ; the output end V PA of the LH pulse delay circuit is connected to the gate of the charging shield MOS M PHL ; the source of the charging shield MOS M PHL is connected to the input voltage V IN of the LDO; and the source of the discharging shield MOS M PLHThe source of the LDO input voltage V IN The source of the LDO input voltage V HL The source of the LDO input voltage V IN The source of the LDO input voltage V LH The source of the LDO input voltage V P The source of the LDO input voltage V G The source of the LDO input voltage V LH The source of the LDO input voltage V

[0019] As shown in Figure 5 , the comparator detects two output terminals of the error amplifier in the LDO main loop, and generates a negative pulse signal by using the pulse generation circuit to control the charging or discharging of the power tube gate, while using the pulse delay circuit to generate a wide pulse to shield the opening of another path MOS tube. Its working principle is as follows: at t1, when the LDO load current I OUT jumps from light load to heavy load, the output voltage V OUT starts to produce undershoot, and the EA in the LDO main loop responds accordingly, and the positive output voltage V A starts to drop, and the reverse output voltage V B starts to rise; at t2, the output V B of the EA and V A reach the flip-flop threshold, the output V LH1 of the second comparator COMP2 generates a pulse, which is further processed by the LH pulse generation circuit, and the output V LH generates a pulse, quickly turning on the charging tube M LH to lower the power tube gate potential to adapt to the heavy load working condition, and almost at the same time, the output V PA of the LH pulse delay circuit starts to generate a wide negative pulse until t4, turning on the discharge shielding MOS tube M PLH to pull up the gate of the light load jump heavy load discharge PMOS tube M LH , which is used to shield the output voltage V OUT from the rebound overshoot, causing the output V HL of the LH pulse generation circuit to generate a pulse; until t3, the LDO output voltage V OUT stabilizes.

[0020] From t5 to t8, it is the process of heavy load jump light load, which is similar to the foregoing process: at t5, when the LDO load current I OUT jumps from heavy load to light load, the output voltage V OUT starts to produce overshoot, and the EA in the LDO main loop responds accordingly, and the positive output voltage V AThe voltage begins to rise, and the reverse output voltage V B It begins to decrease; at time t6, the output V of EA... A With V B The difference reaches the flip threshold, activating the output V of the first comparator COMP1. HL1 A pulse is generated, which is further processed by the HL pulse generation circuit, resulting in an output V. HL A negative pulse is then generated, quickly activating the charging tube M. HL Raising the gate potential of the power transistor to adapt to light-load operating conditions, almost simultaneously the output V of the HL pulse delay circuit... PB A wide pulse is generated until time t8, at which point the charging shielded MOSFET M is turned on. PHL To pull up the charging PMOS transistor M under heavy load and switch to light load HL The gate is used to shield the output voltage V. OUT The output V of the LH pulse generation circuit caused by the rebound and downward impulse in the middle LH The generated pulse; until the LDO output voltage V at time t7. OUT Stablize.

[0021] In summary, this invention proposes a low-power, fast transient response LDO circuit that requires no external capacitors. It compares the output of an error amplifier using two comparators and generates pulses via digital circuitry to rapidly adjust the gate voltage of the power transistors, thereby reducing output voltage overshoot. The MOSFETs in the proposed LDO circuit operate primarily in the subthreshold region and do not require external load capacitors, thus reducing system power consumption, minimizing system area, and enhancing load transient response.

Claims

1. A low power fast transient response LDO circuit without off-chip capacitance, characterized in that, The LDO main circuit, the first comparator, the second comparator, the HL pulse generating circuit, the HL pulse delay circuit, the LH pulse generating circuit, the LH pulse delay circuit, the heavy load jump light load charging PMOS tube, the light load jump heavy load discharging PMOS tube, the charging shield MOS tube and the discharging shield MOS tube are included. The two input ends of the first comparator detect the two output ends of the error amplifier in the LDO main circuit respectively, and the output end is connected with the input end of the HL pulse generating circuit; the two input ends of the second comparator detect the output ends of the error amplifier in the LDO main circuit respectively in reverse, and the output end is connected with the input end of the LH pulse generating circuit; the output end of the HL pulse generating circuit is connected with the gate of the heavy load jump light load charging PMOS tube, the input end of the HL pulse delay circuit and the drain of the charging shield MOS tube; the output end of the LH pulse generating circuit is connected with the gate of the light load jump heavy load discharging PMOS tube, the input end of the LH pulse delay circuit and the drain of the discharging shield MOS tube; the output end of the HL pulse delay circuit is connected with the gate of the discharging shield MOS tube; the output end of the LH pulse delay circuit is connected with the gate of the charging shield MOS tube; the source of the charging shield MOS tube is connected with the input voltage of the LDO; the source of the discharging shield MOS tube is connected with the input voltage of the LDO; the source of the heavy load jump light load charging PMOS tube is connected with the input voltage of the LDO, and the drain is connected with the source of the light load jump heavy load discharging PMOS tube and the gate of the power tube in the LDO main circuit; the drain of the light load jump heavy load discharging PMOS tube is grounded.

2. The low power consumption fast transient response LDO circuit without off-chip capacitance according to claim 1, characterized in that: The first comparator judges the change of the output load by comparing the difference between the positive outputs of the error amplifier in the LDO main loop, and the second comparator judges the change of the output load by comparing the difference between the negative outputs of the error amplifier in the LDO main loop; the first comparator and the second comparator flip the output when the difference between the positive phase input voltage and the inverse phase input voltage exceeds a certain threshold; the first comparator and the second comparator are the same structure, including the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube; the gate of the first MOS tube and the gate of the second MOS tube are connected, and the connection node is the positive phase input end of the comparator; the drain of the first MOS tube and the drain of the second MOS tube are connected with the gate of the third MOS tube, and the source of the first MOS tube is connected with the inverse phase input end of the comparator; the source of the second MOS tube is connected with the input voltage of the LDO; the source of the third MOS tube is connected with the input voltage of the LDO, and the drain is connected with the drain of the fourth MOS tube, and the connection node is the output end of the comparator; the source of the fourth MOS tube is grounded, and the gate is connected with the bias voltage.

3. The low power consumption fast transient response LDO circuit without off-chip capacitor according to claim 1, characterized in that: The LH pulse generation circuit outputs a negative pulse control on-off of the discharging PMOS tube through the output level signal of the front stage second comparator, to weaken the instantaneous undershoot of the output, the HL pulse generation circuit outputs a negative pulse control on-off of the charging PMOS tube through the signal of the front stage first comparator, to weaken the instantaneous overshoot of the output, the LH pulse generation circuit and the HL pulse generation circuit are the same in structure, comprising a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, a first capacitor; the first inverter, the third inverter and the fourth inverter are connected in sequence in a head-tail mode, the input end of the first inverter is the input end of the pulse generation circuit, the output end of the third inverter is connected to the ground through the first capacitor, and the output end of the fourth inverter is connected to one input end of the first NAND gate; the input end of the second inverter is connected to the output end of the first inverter, and the output end of the second inverter is connected to the other input end of the first NAND gate; the output end of the first NAND gate is the output end of the pulse generation circuit.

4. The low power consumption fast transient response LDO circuit without off-chip capacitor of claim 1, wherein, The LH pulse delay circuit delays a short negative pulse output by the front stage LH pulse generation circuit to generate a wide negative pulse, to control on-off of the charging shield MOS tube, and shield the opening of the charging PMOS tube in the light load to heavy load jump; the HL pulse delay circuit delays a short negative pulse output by the front stage HL pulse generation circuit to generate a wide negative pulse, to control on-off of the discharging shield MOS tube, and shield the opening of the discharging PMOS tube in the heavy load to light load jump; the LH pulse delay circuit and the HL pulse delay circuit are the same in structure, comprising a fifth inverter, a sixth inverter, a first NOR gate, a fifth MOS tube and a second capacitor; the input end of the fifth inverter is the input end of the pulse delay circuit, and the output end is connected to the gate of the fifth MOS tube and one input end of the first NOR gate; the drain of the fifth MOS tube is connected to the tail end of a bias current source and the input end of the sixth inverter, and is connected to the ground through the second capacitor, and the source of the fifth MOS tube is grounded; the output end of the sixth inverter is connected to the other input end of the first NOR gate; the output end of the first NOR gate is the output end of the pulse delay circuit.

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