Three-dimensional semiconductor structure and preparation method thereof

Abstract

The present application provides a three-dimensional semiconductor structure and a preparation method thereof, which relates to the field of semiconductor technology and is used to solve the technical problem of the difficulty of characterizing the uniformity of the film thickness of a storage capacitor. The three-dimensional semiconductor structure includes a substrate, a stacked structure, a contact pad, and a test structure. The stacked structure is located on the substrate, the contact pad is located on the surface of the stacked structure facing away from the substrate, and the contact pad is electrically connected to the first electrode array in the capacitor structure; the test structure is located on the surface of the stacked structure facing away from the substrate, the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the contact pad, and the plurality of second test pads are respectively electrically connected to the corresponding second electrodes in the capacitor structure, and the test structure is configured to test the voltage of the capacitor structure. The present application can reduce the difficulty of characterizing the uniformity of the capacitor film thickness and improve the test accuracy. At the same time, it can also simulate and test the performance of multiple parallel capacitors and simplify the preparation process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device consisting of many repetitive memory cells. Each memory cell typically includes a transistor and a capacitor. The transistor's gate is connected to a word line (WL), its drain is connected to a bit line (BL), and its source is connected to a capacitor.

[0003] With the continuous development of semiconductor chips, their critical dimensions are constantly decreasing, and the thickness of the capacitor film material (dielectric layer) in the capacitor is getting thinner and thinner. The leakage of the capacitor is exponentially related to the thickness of the capacitor film. A small thickness difference of the capacitor film will lead to a large leakage difference. Therefore, the characterization of the thickness uniformity of the capacitor film is particularly important.

[0004] However, in the related art, it is difficult to characterize the thickness uniformity of storage capacitor films. Summary of the Invention

[0005] In view of the above problems, the embodiments of the present application provide a three-dimensional semiconductor structure and a preparation method thereof, which can reduce the difficulty of characterizing the uniformity of the thickness of the capacitor film at different heights and improve the test accuracy. At the same time, it can also simulate and test the performance of multiple parallel capacitors and simplify the preparation process.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] A first aspect of an embodiment of the present application provides a three-dimensional semiconductor structure, comprising:

[0008] substrate;

[0009] A stacked structure located on the substrate, wherein the stacked structure comprises a capacitor structure, wherein the capacitor structure comprises a first electrode array and a plurality of second electrodes, wherein the first electrode array comprises a plurality of first electrodes arranged in an array, a dielectric layer being provided between each first electrode and the second electrode, wherein each first electrode extends along a first direction; and the plurality of second electrodes are stacked and spaced apart along the first direction, with a support layer being provided between any two adjacent second electrodes; and wherein the first direction is the thickness direction of the substrate;

[0010] a contact pad located on a surface of the stacked structure facing away from the substrate, and electrically connected to each of the first electrodes; wherein one first electrode array corresponds to one contact pad;

[0011] A test structure is located on a surface of the stacked structure facing away from the substrate, the test structure includes a first test pad and multiple second test pads, the first test pad is electrically connected to the contact pad, and the multiple second test pads are respectively electrically connected to their corresponding second electrodes, and the test structure is configured to test the voltage of the capacitor structure.

[0012] In some optional embodiments, the plurality of first electrodes are arranged in a rectangular array.

[0013] In some optional embodiments, the projection of the contact pad in the first direction covers the projection of the first electrode array in the first direction.

[0014] In some optional embodiments, the contact pad is a titanium nitride contact pad.

[0015] In some optional embodiments, a contact structure is further included, which includes a first contact plug and a plurality of second contact plugs, wherein the first contact plug is electrically connected between the contact pad and the first test pad; and each second contact plug is electrically connected between the second electrode corresponding thereto and the second test pad.

[0016] In some optional embodiments, the stack structure is provided with a plurality of first channels penetrating the stack structure along the first direction, and each of the first electrodes is respectively provided in the first channel corresponding thereto;

[0017] The dielectric layer is located between the first electrode and the inner wall of the first channel;

[0018] The plurality of second electrodes are sequentially stacked and spaced apart in a step-like manner from close to the substrate to far away from the substrate, and each of the second electrodes is connected to the dielectric layer.

[0019] In some optional embodiments, a first barrier layer is further provided between the dielectric layer and the first electrode; and / or a second barrier layer is provided between the second electrode and the support layer.

[0020] In some optional embodiments, there are multiple capacitor structures, and the multiple capacitor structures are spaced apart along the second direction, and an isolation wall is provided between any two adjacent capacitor structures; wherein the second direction is perpendicular to the first direction.

[0021] In some optional embodiments, a plurality of the capacitor structures are arranged in parallel.

[0022] A second aspect of the embodiments of the present application further provides a method for preparing a three-dimensional semiconductor structure, comprising:

[0023] providing a substrate;

[0024] A stacked structure is formed on the substrate; a capacitor structure is formed in the stacked structure, the capacitor structure including a first electrode array and a plurality of second electrodes, the first electrode array including a plurality of first electrodes arranged in an array, a dielectric layer being provided between each first electrode and the second electrode, wherein each first electrode extends along a first direction; the plurality of second electrodes are stacked and spaced apart along the first direction, a support layer being provided between any two adjacent second electrodes; the first direction being a thickness direction of the substrate;

[0025] forming a contact pad on a surface of the stacked structure facing away from the substrate, wherein the contact pad is located on the surface of the stacked structure facing away from the substrate and is electrically connected to the first electrode array;

[0026] A test structure is formed on a surface of the stacked structure facing away from the substrate; the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the contact pad, and the plurality of second test pads are respectively electrically connected to their corresponding second electrodes, and the test structure is configured to test the voltage of the capacitor structure.

[0027] In some optional embodiments, before the step of forming the stacked structure on the substrate and after the step of providing the substrate, the method includes:

[0028] forming a plurality of predetermined layers stacked on the substrate;

[0029] The plurality of preset layers include supporting layers and sacrificial layers that are alternately stacked in sequence.

[0030] In some optional embodiments, the step of forming a stacked structure on the substrate includes:

[0031] forming a plurality of first channels arranged in an array in the preset layer; the first channels extending along the first direction and penetrating the preset layer;

[0032] A dielectric layer, a barrier layer, and a first electrode are sequentially formed in the first trench; wherein the barrier layer is disposed around an outer sidewall of the first electrode; and the dielectric layer is located between the barrier layer and an inner sidewall of the first trench;

[0033] removing the sacrificial layer in the preset layer and forming a first slit;

[0034] A second electrode is formed in the first slit.

[0035] In some optional implementations, before removing the sacrificial layer in the preset layer, the method further includes:

[0036] removing portions of the supporting layer and the sacrificial layer on two opposite sides of the predetermined layer along the third direction to expose a surface of each supporting layer facing away from the substrate, so that the remaining adjacent supporting layers and sacrificial layers are arranged in a step-like manner from close to away from the substrate;

[0037] forming a first oxide layer on the remaining support layer and the sacrificial layer;

[0038] forming a plurality of second slits spaced apart along a second direction on the first oxide layer, wherein the second slits penetrate the preset layer, and the first electrode array and the second slits are sequentially spaced apart along the second direction;

[0039] The third direction, the second direction and the first direction are perpendicular to each other; in some optional embodiments, the step of forming the second electrode in the first slit specifically includes:

[0040] sequentially filling a second barrier layer and a second electrode in the first slit;

[0041] removing the second barrier layer and the second electrode in the second slit;

[0042] The second slit is filled with an isolation material to form an isolation wall.

[0043] In some optional embodiments, the step of forming a contact pad on the stacked structure specifically includes:

[0044] removing a portion of the first oxide layer to expose a surface of the first electrode array facing away from the substrate; wherein the remaining surface of the first oxide layer facing away from the substrate is a flat surface;

[0045] Contact pads are formed on the first electrode array so as to electrically connect the contact pads to the first electrodes in the first electrode array.

[0046] In some optional embodiments, the step of forming a test structure on the stacked structure includes:

[0047] forming a second oxide layer on the first oxide layer and the contact pad;

[0048] forming a second channel and a plurality of third channels on the second oxide layer, wherein the second channel exposes the contact pad, and the third channel exposes the surface of the second electrode; wherein one third channel corresponds to one second electrode;

[0049] Depositing a conductive material on the second oxide layer, the conductive material filling the second trench and the third trench while covering the surface of the second oxide layer; the conductive material filled in the second trench forms a first contact plug, and the conductive material filled in the third trench forms a second contact plug;

[0050] A portion of the conductive material is removed, and the conductive material covering the first contact plug and the second contact plug is retained; wherein the conductive material covering the first contact plug is formed into a first test pad; the conductive material covering the second contact plug is formed into a second test pad; and the first test pad and the second test pad are formed into the test structure.

[0051] In the three-dimensional semiconductor structure and its preparation method provided by the embodiment of the present application, a test structure is set on the stacked structure, so that the first test pad in the test structure is electrically connected to the first electrode array in the capacitor structure through the contact pad, and the second test pad in the test structure is electrically connected to its corresponding second electrode. The leakage conditions at different positions of the capacitor structure are tested by the test structure, so that the uniformity of the film thickness in the capacitor structure is characterized by the leakage magnitude at different positions of the capacitor structure. The structure and characterization method are simple and easy to implement. In addition, the first electrode array in the capacitor structure includes multiple first electrodes, so that while simulating the performance of multiple parallel capacitors, the leakage current signal of the capacitor structure can also be amplified, thereby improving the test accuracy of the test structure for leakage current phenomena and improving the characterization accuracy of the film thickness of the capacitor structure. Moreover, a first electrode array is connected to the first test pad through a contact pad, and each first electrode does not need to be electrically connected to the first test pad by making a contact plug, thereby simplifying the preparation process.

[0052] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the three-dimensional semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0054] Figure 1A schematic diagram of a half-section structure of a three-dimensional semiconductor structure provided in an embodiment of the present application;

[0055] Figure 2 for Figure 1 A partial enlarged schematic diagram of point A in the middle;

[0056] Figure 3 A schematic flow chart of a method for preparing a three-dimensional semiconductor structure provided in an embodiment of the present application;

[0057] Figures 4 to 15 Schematic diagram of the preparation process of the three-dimensional semiconductor structure provided in an embodiment of the present application.

[0058] Reference numerals:

[0059] 100-three-dimensional semiconductor structure; 10-substrate; 20-stacked structure; 21-capacitor structure;

[0060] 211 - first electrode array; 2111 - first electrode; 212 - second electrode; 213 - dielectric layer;

[0061] 22-preset layer; 221-support layer; 222-sacrificial layer; 223-second slit;

[0062] 23 - first channel; 24 - contact pad; 25 - contact structure; 251 - first contact plug;

[0063] 252 - second contact plug; 26 - first oxide layer; 27 - second oxide layer;

[0064] 28 - second channel; 29 - third channel; 30 - test structure; 301 - first test pad;

[0065] 302 - second test pad; 31 - isolation wall; 40 - first mask layer; 41 - second mask layer;

[0066] 42 - a third mask layer; 43 - a fourth mask layer. DETAILED DESCRIPTION

[0067] As described in the background technology, in the related art, the uniformity of the film thickness at the top and bottom ends of the capacitor structure is usually analyzed by means of transmission electron microscopy, etc. However, as the critical dimensions of semiconductor structures continue to decrease, the thickness of DRAM capacitor film materials is very thin, resulting in the difficulty in characterizing the uniformity of the thickness of the films at the top and bottom ends of the capacitor structure by means of transmission electron microscopy, etc.

[0068] In view of this, an embodiment of the present application provides a three-dimensional semiconductor structure and a preparation method thereof, wherein a test structure is set on a stacked structure, a first test pad in the test structure is electrically connected to a first electrode array in a capacitor structure through a contact pad, and a second test pad in the test structure is electrically connected to its corresponding second electrode, and leakage conditions at different positions of the capacitor structure are tested through the test structure, so that the uniformity of the film thickness in the capacitor structure is characterized by the leakage size at different positions of the capacitor structure. The structure and characterization method are simple and easy to implement; in addition, the first electrode array in the capacitor structure includes multiple first electrodes, so that while simulating the performance of multiple parallel capacitors, the leakage current signal of the capacitor structure can also be amplified, thereby improving the test accuracy of the test structure for leakage current phenomena and improving the characterization accuracy of the film thickness of the capacitor structure; and a first electrode array is connected to the first test pad through a contact pad, and each first electrode does not need to be electrically connected to the first test pad by making a contact plug, thereby simplifying the preparation process.

[0069] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0070] Example 1

[0071] An embodiment of the present application provides a three-dimensional semiconductor structure, which can be a memory device or a non-memory device. The memory device may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM). The non-memory device may be a logic device (such as a microprocessor, a digital signal processor, or a microcontroller) or a device similar thereto. The embodiment of the present application is described using a DRAM memory device as an example.

[0072] Figure 1 A schematic diagram of a half-section structure of a three-dimensional semiconductor structure provided in an embodiment of the present application; Figure 2 for Figure 1 A local enlarged schematic diagram of point A in the middle. Figure 1 A schematic structural diagram of a three-dimensional semiconductor structure provided in an embodiment of the present application; Figure 2 This is a partial cross-sectional diagram of a three-dimensional semiconductor structure provided in an embodiment of the present application. Figure 1 and Figure 2 As shown, the three-dimensional semiconductor structure 100 includes a substrate 10 and a stacked structure 20 disposed on the substrate 10 .

[0073] The substrate 10 may provide a supporting foundation for the structure on the substrate 10. The substrate 10 may be made of a crystalline semiconductor material, for example, a silicon (Si) substrate. The substrate 10 may also be a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, etc. The substrate 10 may be a single-layer structure or a multi-layer composite structure. The structure may be adaptively designed according to actual needs and is not specifically limited here. In the embodiment of the present application, the substrate 10 is described as a silicon substrate.

[0074] In some embodiments, the stacked structure 20 has a capacitor structure 21, and the capacitor structure 21 includes a first electrode array 211 and a plurality of second electrodes 212. Exemplarily, the first electrode array 211 includes a plurality of first electrodes 2111 arranged in an array, for example, the plurality of first electrodes 2111 are arranged in a rectangular array, and each first electrode 2111 extends along the first direction; the plurality of second electrodes 212 are stacked at intervals along the first direction, and a support layer 221 is provided between any two adjacent second electrodes 212. The support layer 221 can achieve electrical isolation between adjacent second electrodes 212 to avoid mutual interference between adjacent second electrodes 212, wherein the first direction is the thickness direction of the substrate 10.

[0075] A dielectric layer 213 is provided between each first electrode 2111 and the second electrode 212 . The dielectric layer 213 can be understood as a thin film structure in the capacitor structure 21 . The material of the dielectric layer 213 may include a high dielectric constant material, such as aluminum oxide, zirconium oxide, and the like.

[0076] In the embodiment of the present application, since each first electrode array 211 includes multiple first electrodes 2111 arranged in an array, a capacitor structure 21 can be understood as including multiple sub-capacitor structures 21, that is, a first electrode 2111 in a first electrode array 211 can be respectively formed with multiple second electrodes 212 and a dielectric layer 213 spaced apart in the vertical direction to form a sub-capacitor structure 21. Therefore, multiple first electrodes 2111 can be respectively formed with the dielectric layer 213 and multiple second electrodes 212 to form multiple sub-capacitor structures 21. In this way, the performance of multiple parallel capacitors can be simulated and tested, and the leakage signal of the capacitor structure 21 can also be amplified.

[0077] Please continue to refer to Figure 1 and Figure 2 The three-dimensional semiconductor structure 100 provided in the embodiment of the present application further includes a contact pad 24, which is located on the surface of the stacked structure 20 on the side facing away from the substrate 10, and the contact pad 24 is electrically connected to each first electrode array 211, so that each first electrode array 211 can be electrically connected to an external device through its corresponding contact pad 24. In this way, there is no need to make a contact plug for each first electrode 2111 to be electrically connected to an external device, thereby simplifying the structure and making the process simpler.

[0078] In some embodiments, the projection of the contact pad 24 on the stacked structure 20 covers the projection of the first electrode array 211 on the stacked structure 20, so that the contact pad 24 is electrically connected to each first electrode 2111. In this way, the first electrode array 211 can be electrically connected to an external device through the contact pad 24. In this way, there is no need to make a contact plug for external connection for each first electrode 2111, thereby simplifying the structure and making the process simpler. The compactness of the three-dimensional semiconductor structure 100 can be improved, thereby achieving the purpose of optimizing the size of the three-dimensional semiconductor structure 100.

[0079] In some embodiments, the material of the contact pad 24 may include but is not limited to titanium nitride, and may also be titanium or other conductive materials, which is not specifically limited in the embodiment of the present application.

[0080] In addition, in order to facilitate the characterization of the thickness uniformity of the thin film in the capacitor structure 21 (such as the dielectric layer 213 in the capacitor structure 21), please continue to refer to Figure 1 and Figure 2In an embodiment of the present application, the three-dimensional semiconductor structure 100 also includes a test structure 30, which is located on the stacked structure 20. The test structure 30 includes a first test pad 301 and multiple second test pads 302. The first test pad 301 is electrically connected to the contact pad 24, and the multiple second test pads 302 are respectively electrically connected to their corresponding second electrodes 212, that is, one second test pad 302 is electrically connected to one second electrode 212. The test structure 30 is used to test the voltage of the capacitor structure 21, and to determine the leakage current of the capacitor structure 21 by the voltage at different positions in the capacitor structure 21 obtained by the test structure 30, and to characterize the uniformity of the film thickness in the capacitor structure 21 through the leakage current. The structure and characterization method are simple and easy to implement.

[0081] In addition, a contact pad 24 is electrically connected to the corresponding first test pad 301 to achieve electrical connection between each first electrode 2111 in the first electrode array 211 in the capacitor structure 21 and the first test pad 301. There is no need to make a contact plug to electrically connect each first electrode 2111 to the first test pad 301, thereby simplifying the preparation process and simplifying the structure.

[0082] In a specific implementation, a ground voltage can be applied to the first test pad 301 electrically connected to the first electrode 2111, and a test voltage can be applied to each second test pad 302 electrically connected to each second electrode 212 to charge each capacitor structure 21. Then, the actual voltage value between the first electrode 2111 and each second electrode 212 is obtained through the first test pad 301 and each second test pad 302, and the actual voltage value obtained is compared with the preset voltage value previously preset. If there is a voltage difference between the detected actual voltage value and the preset voltage value, it means that the capacitor structure 21 has a leakage condition, and the magnitude of the voltage difference can characterize the magnitude of the leakage at different height positions of the capacitor structure 21. Since the magnitude of the leakage of the capacitor structure 21 is exponentially related to the thickness of the film of the capacitor structure 21, the thickness uniformity of the film of the capacitor structure 21 at different height positions can be characterized by the magnitude of the leakage at different height positions of the capacitor structure 21. The structure is simple and easy to implement, thereby reducing the difficulty of characterizing the thickness uniformity of the film of the capacitor structure 21.

[0083] Please continue to refer to Figure 1 and Figure 2The three-dimensional semiconductor structure 100 provided in the embodiment of the present application also includes a contact structure 25, which includes a first contact plug 251 and a plurality of second contact plugs 252. The first contact plug 251 is electrically connected between the contact pad 24 and the first test pad 301, and each second contact plug 252 is electrically connected between the corresponding second electrode 212 and the second test pad 302. An isolation structure is provided between any two adjacent second contact plugs 252 to achieve electrical isolation between the two adjacent second contact plugs 252 through the isolation structure.

[0084] In the above scheme, an electrical connection is achieved between the contact pad 24 and the first test pad 301 through a first contact plug 251, so that the first electrode array 211 in the capacitor structure 21 is electrically connected to the first test pad 301. It is not necessary for each first electrode 2111 to require a first contact plug 251 to be electrically connected to the first test pad 301, thereby simplifying the preparation process; and the second contact plug 252 achieves an electrical connection between the second test pad 302 and the second electrode 212, so as to test the leakage conditions of the capacitor structure 21 at different height positions through the test structure 30, thereby realizing the characterization of the film thickness uniformity of the capacitor structure 21 according to the leakage current of the capacitor structure 21, thereby reducing the difficulty of characterizing the film thickness uniformity in the capacitor structure 21.

[0085] Please continue to refer to Figure 1 and Figure 2 , each second contact plug 252 can extend along the first direction, so that each second contact plug 252 is vertically connected to its corresponding second electrode 212; the first contact plug 251 can be set on the contact pad 24 and can also extend along the first direction. In this way, by respectively extending the first contact plug 251 and the second contact plug 252 along the first direction, the space occupied by the contact structure 25 in the stacked structure can be reduced, the space utilization rate is improved, the volume is reduced, and it is beneficial to increase the number of arrangements of the capacitor structure 21, thereby improving the storage density of the three-dimensional semiconductor structure 100.

[0086] In some embodiments, a plurality of first channels 23 extending along a first direction and penetrating the stacked structure 20 may be provided on the stacked structure 20, the dielectric layer 213 and the corresponding first electrode 2111 may be located in the first channel 23, and the dielectric layer 213 is located between the side wall of the first electrode 2111 and the inner wall of the first channel 23.

[0087] It can be understood that the dielectric layer 213 is a thin film structure formed on the inner wall of the first channel 23, and then the first electrode 2111 fills the first channel 23 with the dielectric layer 213, so that the dielectric layer 213 is wrapped around the outer wall of the first electrode 2111. In this way, the arrangement between the first electrode 2111 and the dielectric layer 213 can be better, and the volume of the capacitor structure 21 can be smaller, which is conducive to improving space utilization, thereby improving the storage density of the three-dimensional semiconductor structure 100.

[0088] In some embodiments, a first barrier layer is further provided between the dielectric layer 213 and the first electrode 2111 . The material of the first barrier layer may include but is not limited to titanium or titanium nitride. The first barrier layer may prevent ion diffusion from occurring in the first electrode 2111 .

[0089] In some embodiments, a second barrier layer may be provided between the second electrode 212 and the support layer 221 to prevent ion diffusion between the second electrode 212 and the support layer 221. The material of the second barrier layer may include but is not limited to titanium or titanium nitride.

[0090] In some embodiments, the edges of the plurality of second electrodes 212 are sequentially stacked and spaced apart in a step-like manner from close to the substrate 10 to far away from the substrate 10 (eg, Figure 1 and Figure 2 ), and each second electrode 212 is connected to its corresponding dielectric layer 213.

[0091] For example, the edges of the plurality of second electrodes 212 are stepped from bottom to top along the first direction. Therefore, the distance between the connection point of each second electrode 212 and its corresponding second contact plug 252 and the first electrode 2111 decreases successively.

[0092] It can be understood that by arranging the edges of the multiple second electrodes 212 in a stepped manner, on the one hand, each second electrode 212 can be exposed while preventing each second contact plug 252 from being electrically connected to the corresponding second electrode 212 and other second electrodes 212, thereby improving the connection reliability of the electrical connection between the second contact plug 252 and the corresponding second electrode 212; on the other hand, the space occupied by the multiple second electrodes 212 can be reduced, which is beneficial to reducing the characteristic size of the three-dimensional semiconductor structure 100 while improving the storage density of the three-dimensional semiconductor structure 100.

[0093] In some embodiments, there may be multiple capacitor structures 21, and the multiple capacitor structures 21 are spaced apart along the second direction in the stacked structure 20, and isolation walls 31 are provided between adjacent capacitor structures 21, so that adjacent capacitor structures 21 are electrically isolated by the isolation walls 31.

[0094] The second direction is perpendicular to the first direction. For example, in a three-dimensional coordinate system, the first direction may be the Z direction, and the second direction may be the X direction or the Y direction. Figure 1 and Figure 2 In the embodiment, a plurality of capacitor structures 21 are arranged at intervals along the Y direction. Of course, the second direction may also be a direction having an inclined angle with the X direction or the Y direction, and the adaptive design is carried out according to actual needs.

[0095] It can be understood that multiple capacitor structures 21 are arranged at intervals along the second direction in the stacked structure 20. This arrangement can make the arrangement of the capacitor structures 21 more compact, so that the arrangement form of the multiple capacitor structures 21 in the stacked structure 20 is better, and the volume they occupy is smaller, which is conducive to increasing the number of arranged capacitor structures 21, thereby improving the storage density of the three-dimensional semiconductor structure 100.

[0096] In some embodiments, as Figure 1 and Figure 2 As shown, multiple capacitor structures 21 are arranged in parallel along the Y direction. It can be understood that since the leakage difference between the two ends of a single capacitor structure 21 in the first direction is small, if the signal collected by a single capacitor structure 21 is represented by i, by arranging multiple capacitor structures 21 in parallel, for example, N capacitor structures 21 are arranged in parallel, then the total collected signal (represented by I) is: I=Nxi, thereby maximizing the resolution.

[0097] Example 2

[0098] An embodiment of the present application provides a method for preparing a three-dimensional semiconductor structure. The method for preparing a three-dimensional semiconductor structure can be used to prepare the three-dimensional semiconductor structure 100 in the above embodiment.

[0099] Figure 3 This is a flow chart of a method for preparing a three-dimensional semiconductor structure provided in an embodiment of the present application. Figure 3 As shown, the method for preparing the three-dimensional semiconductor structure includes:

[0100] Step S101: providing a substrate.

[0101] Combine Figure 4 As shown, in the embodiment of the present application, the substrate 10 includes a silicon substrate 10 and an oxide layer formed on the silicon substrate 10, and the silicon substrate 10 is insulated and protected by the oxide layer.

[0102] Step S102: forming a plurality of preset layers stacked on a substrate.

[0103] Specifically, a plurality of stacked preset layers 22 can be sequentially formed on the substrate 10 by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process, wherein the plurality of preset layers 22 include a support layer 221 and a sacrificial layer 222 alternately stacked in sequence along a first direction, and the preset layer 22 close to the silicon substrate 10 can be, for example, a sacrificial layer 222, such as Figure 4 As shown in FIG, a plurality of preset layers 22 are provided on the substrate 10 so as to form a stacked structure 20 on the preset layers 22 in a subsequent process.

[0104] In some embodiments, the material of the sacrificial layer 222 can be a material such as silicon nitride (SiN), and the material of the support layer 221 can be an insulating material such as oxide, so as to achieve electrical isolation between adjacent second electrodes 212 in the stacked structure 20 formed by subsequent processes through the support layer 221 to avoid mutual interference of signals between adjacent second electrodes 212.

[0105] Step S103: forming a stacked structure on the substrate.

[0106] In which, a capacitor structure 21 is formed in the stacked structure 20, and the capacitor structure 21 includes a first electrode array 211 and multiple second electrodes 212. The first electrode array 211 includes multiple first electrodes 2111 arranged in an array. The multiple first electrodes 2111 can be arranged in a rectangular array, for example, wherein each first electrode 2111 extends along a first direction, and the multiple second electrodes 212 are stacked at intervals along the first direction, and a support layer 221 is provided between any two adjacent second electrodes 212; and a dielectric layer 213 is provided between each first electrode 2111 and the second electrode 212; the first direction is the thickness direction of the substrate 10.

[0107] It can be understood that the capacitor structure 21 is formed by multiple sub-capacitor structures 21, that is, a first electrode 2111, a dielectric layer 213 and multiple second electrodes 212 together form a sub-capacitor structure 21, and the first electrode array 211 in the capacitor structure 21 includes multiple first electrodes 2111. Therefore, the multiple first electrodes 2111 respectively form multiple sub-capacitor structures 21 with their corresponding dielectric layers 213 and multiple second electrodes 212. In this way, the performance of multiple parallel capacitors can be simulated and tested. In addition, the leakage signal of the capacitor structure 21 can be amplified to facilitate the measurement of the leakage current of the capacitor structure 21 in subsequent processes.

[0108] In addition, each first electrode 2111 is equivalent to a common electrode of the sub-capacitor structure 21 . In this way, the spatial arrangement of the sub-capacitor structure 21 can be optimized, and the storage density of the three-dimensional semiconductor structure 100 can be improved.

[0109] In some embodiments, the step of forming the stacked structure 20 on the substrate 10 specifically includes:

[0110] Step S1031 : forming a plurality of first channels arranged in an array in a predetermined layer, wherein the first channels extend along a first direction and penetrate the predetermined layer.

[0111] For details, please refer to Figure 5 As shown, a first mask layer 40 is first formed on the preset layer 22, and the first mask layer 40 is patterned by exposure, development, etc., and the patterned first mask layer 40 is used as a mask to etch part of the preset layer 22, and a plurality of first channels 23 are formed on the preset layer 22 that penetrate the preset layer 22 and are arranged in an array, so that the first channels 23 expose the substrate 10 (for example, expose the oxide layer on the silicon substrate); a first electrode 2111 can be formed in each first channel 23 in a subsequent process, so that a plurality of first electrodes 2111 arranged in an array together form a first electrode array 211, and the formed first electrode array 211 can be multiple.

[0112] The cross-sectional shape of the first channel 23 can be circular, elliptical, rectangular or square.

[0113] like Figure 6 As shown, after the first trench 23 is formed, the first mask layer 40 is removed to expose the surface of the top predetermined layer 22 .

[0114] Step S1032: forming a dielectric layer, a first barrier layer and a first electrode in sequence in the first trench; wherein the first barrier layer is arranged around the outer sidewall of the first electrode, and the dielectric layer is located between the first barrier layer and the inner sidewall of the first trench.

[0115] For details, please refer to Figure 6 After removing the first mask layer 40 on the surface of the preset layer 22 , a thin film structure can be formed on the preset layer 22 by a chemical deposition process or a physical deposition process, and the thin film structure covers the inner wall of the first channel 23 .

[0116] After the thin film structure is formed on the inner wall of the first trench 23, the thin film structure on the surface of the preset layer 22 can be removed by chemical mechanical polishing (CMP) or etching, and the surface of the preset layer 22 is exposed, while the thin film structure covering the inner wall of the first trench 23 is retained to form the dielectric layer 213 of the capacitor structure 21.

[0117] The dielectric layer 213 may be made of a high-K gate dielectric material, which may include nitrides, metal oxides, and the like, such as aluminum oxide and zirconium oxide. By making the dielectric layer 213 of the high-K gate dielectric material, the electron tunneling effect can be effectively suppressed, thereby reducing leakage of the capacitor structure 21. It will be understood that K is the dielectric constant.

[0118] In some embodiments, after forming a dielectric layer 213 on the inner wall of each first channel 23, a first barrier layer is formed on the preset layer 22 by a chemical vapor deposition process or a physical vapor deposition process, and the first barrier layer is attached to the surface of the dielectric layer 213, wherein the first barrier layer can be a titanium layer or a titanium nitride layer.

[0119] After forming the dielectric layer 213 on the inner wall of each first trench 23, a conductive material can be deposited on the preset layer 22 by a chemical deposition process or a physical deposition process so that the conductive material fills the first trench 23, so that the conductive material filled in the first trench 23 forms a first electrode layer.

[0120] The first electrode layer may be formed of a material such as a metal having conductive properties. For example, the first electrode layer may be made of a material with low resistance such as W, TiN, TaN, Al, Ru or Cu.

[0121] After the first electrode layer fills the first trench 23, the first electrode layer on the surface of the preset layer 22 can be removed by chemical mechanical polishing (CMP) or etching, and the surface of the preset layer 22 is exposed, and the first electrode layer in the first trench 23 is retained. The first electrode layer retained in the first trench 23 forms the first electrode 2111 of the capacitor structure 21, as shown in FIG. Figure 1 and Figure 2 As shown in , the first barrier layer is wrapped around the outer wall of the first electrode 2111 , and the dielectric layer 213 is wrapped around the outer wall of the first barrier layer, so that the dielectric layer 213 is located between the outer wall of the first barrier layer and the inner wall of the first channel 23 .

[0122] In some embodiments, after the dielectric layer 213, the first barrier layer, and the first electrode 2111 are sequentially formed in the first trench 23, a mask block is formed on the preset layer 22, and the mask block is used as a mask to remove portions of the support layer 221 and the sacrificial layer 222 on two opposite sides of the preset layer 22 along the third direction to expose the surface of each support layer 221 facing away from the substrate 10, and the above process is repeated to arrange the remaining adjacent support layers 221 and sacrificial layers 222 in a step-like arrangement from close to away from the substrate 10, as shown in FIG. Figure 7As shown in ; wherein the third direction, the second direction and the first direction are perpendicular to each other. For example, in an embodiment of the present application, the first direction may be the Z direction, the second direction may be the Y direction, and the third direction may be the X direction.

[0123] Afterwards, a first oxide layer 26 is formed on the retained support layer 221 and the sacrificial layer 222, wherein the sidewalls of the first oxide layer 26 are flush with the sidewalls of the substrate 10, and the upper surface of the first oxide layer 26 covers the upper surface of the preset layer 22; wherein the material of the first oxide layer 26 may include but is not limited to silicon dioxide, etc.

[0124] Step S1033: removing the sacrificial layer in the preset layer and forming a first slit.

[0125] Before forming the first slits, a plurality of second slits 223 spaced apart along the second direction are formed on the first oxide layer 26 . The second slits 223 penetrate the preset layer 22 , and the first electrode array 211 and the second slits 223 are sequentially spaced apart along the second direction.

[0126] Specifically, a portion of the preset layer 22 is removed to form Figure 7 After the structure in FIG. 1 is formed, a second mask layer 41 is formed on the first oxide layer 26, and the second mask layer 41 is patterned by exposure, development, etc., and the patterned second mask layer 41 is used as a mask to remove part of the preset layer 22 by a wet etching process or a dry etching process, and the area where the preset layer 22 is removed is formed into a second slit 223 (such as Figure 8 ), wherein the second slit 223 extends along the first direction and exposes the substrate 10.

[0127] After removing part of the preset layer 22 to form the second slit 223, each sacrificial layer 222 in the preset layer 22 is removed through the second slit 223 to form the first slit. Then, the second mask layer 41 is removed to expose the surface of the preset layer 22. Figure 9 As shown in .

[0128] Specifically, each sacrificial layer 222 in the preset layer 22 may be removed through the second slits 223 by wet etching or other processes, and the supporting layers 221 in the preset layer 22 may be retained, so that first slits are formed between adjacent supporting layers 221 .

[0129] Step S1034: forming a second electrode in the first slit.

[0130] Combine Figure 10As shown, after the first slit is formed between adjacent supporting layers 221, the second blocking layer and the second electrode 212 are sequentially formed through the second slit 223 into the first slit by chemical vapor deposition process, physical vapor deposition process, etc., so that the second blocking layer and the second electrode 212 fill the first slit, and the second blocking layer is wrapped on the outer wall of the second electrode 212.

[0131] After the second barrier layer and the second electrode 212 are sequentially filled in the first slit, the second barrier layer and the second electrode 212 in the second slit 223 can be removed by an etching process, that is, the second slit 223 is etched back so that the second slit 223 exposes the substrate 10. Figure 11 As shown in , thereafter, an isolation material is filled into the second slit 223 to form an isolation wall 31 . It can be understood that the isolation wall 31 is used to achieve electrical isolation between adjacent capacitor structures 21 .

[0132] Please refer to Figure 12 As shown, after the isolation material is filled in the second slit 223 to form the isolation wall 31, part of the first oxide layer 26 is removed to expose the surface of the first electrode array 211 facing away from the substrate 10; wherein, the surface of the retained first oxide layer 26 facing away from the substrate 10 is a flat surface.

[0133] Step S104: forming contact pads on a surface of the stack structure facing away from the substrate, wherein the contact pads are electrically connected to the first electrodes.

[0134] Specific, combined Figure 13 As shown, a metal conductive material can be deposited on the surface of the stacked structure 20 facing away from the substrate 10 by chemical vapor deposition, atomic layer deposition, physical vapor deposition and other processes to form a metal conductive layer covering the surface of the first oxide layer 26 facing away from the substrate 10, wherein the material of the metal conductive layer can be a conductive material such as W, TiN, TaN, Al, Ru or Cu.

[0135] A patterned fourth mask layer 43 is formed on the metal conductive layer, and the fourth mask layer 43 is used as a mask, such as Figure 13 As shown in , part of the metal conductive layer is removed, and the metal conductive layer in the area corresponding to each first electrode array 211 is retained to form a contact pad 24, so that the formed contact pad 24 is electrically connected to each first electrode 2111 in the first electrode array 211, wherein one contact pad 24 is provided corresponding to one electrode array.

[0136] Step S105 : forming a test structure on a surface of the stack structure facing away from the substrate.

[0137] The test structure 30 includes a first test pad 301 and multiple second test pads 302. The first test pad 301 is electrically connected to the contact pad 24, and the multiple second test pads 302 are respectively electrically connected to their corresponding second electrodes 212. The test structure 30 is configured to test the voltage of the capacitor structure 21.

[0138] The step of forming the test structure 30 on the stack structure 20 specifically includes:

[0139] Combine Figure 14 As shown, a second oxide layer 27 covering the first oxide layer 26 and the contact pad 24 is formed on the first oxide layer 26 and the contact pad 24, and the surface of the second oxide layer 27 facing away from the substrate 10 is a flat surface, and a third mask layer 42 is formed on the second oxide layer 27, the third mask layer 42 is patterned, and a portion of the second oxide layer 27 is removed using the patterned third mask layer 42 as a mask to form a second channel 28 exposing the contact pad 24 and a third channel 29 exposing the second electrode 212. It can be understood that the second channel 28 and the third channel 29 both extend along the first direction. In this way, space can be reasonably utilized, which is beneficial to reducing the characteristic size of the three-dimensional semiconductor structure 100 while improving the storage density of the three-dimensional semiconductor structure 100.

[0140] It is understandable that the second oxide layer 27 retained between two adjacent third trenches 29 forms an isolation structure, and the isolation structure can be used to electrically isolate two adjacent second contact plugs 252 formed in subsequent processes.

[0141] The cross-sectional shape of the second channel 28 and the third channel 29 can be any shape such as circular, elliptical, rectangular, square, etc.

[0142] Combine Figure 15 As shown, after the second trench 28 and the third trench 29 are formed on the second oxide layer 27, the third mask layer 42 is removed, and the surface of the second oxide layer 27 is exposed, and a conductive material is deposited on the second oxide layer 27. The conductive material fills the second trench 28 and the third trench 29 and covers the surface of the second oxide layer 27. In this way, the conductive material filled in the second trench 28 is formed into a first contact plug 251, and the conductive material filled in the third trench 29 is formed into a second contact plug 252.

[0143] The conductive material formed on the surface of the second oxide layer 27 covers the entire surface of the second oxide layer 27. Thereafter, a patterned fifth mask layer is formed on the conductive material on the surface of the second oxide layer 27, and the fifth mask layer is used as a mask to remove part of the conductive material, retaining the conductive material covering the first contact plug 251 and the second contact plug 252, wherein the conductive material covering the first contact plug 251 is formed into a first test pad 301; the conductive material covering the second contact plug 252 is formed into a second test pad 302. It can be understood that the first test pad 301 and the second test pad 302 are independent structures, and there are multiple second test pads 302 formed, and the multiple second test pads 302 are also independent structures. In this way, the first test pad 301 and the second test pad 302 form a test structure 30.

[0144] It can be seen that in the above solution, the test structure 30 and the first contact plug 251 and the second contact plug 252 can be formed by an integrated molding process, which can reduce the number of manufacturing processes and thus reduce the manufacturing cost.

[0145] It can be understood that the material of the test structure 30 and the first contact plug 251 and the second contact plug 252 can be a material with low resistance such as W, TiN, TaN, Al, Ru or Cu; of course, the material of the test structure 30 and the first contact plug 251 and the second contact plug 252 can be the same or different. In the embodiment of the present application, the material of the test structure 30 and the first contact plug 251 and the second contact plug 252 is the same, and is formed through an integrated molding process, thereby reducing the preparation process.

[0146] That is, the first contact plug 251 electrically connected to the contact pad 24 in each capacitor structure 21 and the first test pad 301 are an integral structure, and each second contact plug 252 electrically connected to the second electrode 212 corresponding to the same height position in each capacitor structure 21 and its corresponding second test pad 302 are an integral structure, wherein the first test pad 301 can be a strip structure extending along the second direction, and the second test pad 302 can also be a strip structure extending along the second direction. Since there are multiple second electrodes 212 in each capacitor structure 21, the second test pads 302 corresponding to the second electrodes 212 at different height positions are different, and the multiple second test pads 302 can be arranged at intervals along the third direction, forming a three-dimensional semiconductor structure 100 as shown in FIG. Figure 1 and Figure 2 As shown in .

[0147] When characterizing the uniformity of the film thickness in each capacitor structure 21, first, a ground voltage is applied to the first test pad 301, and a test voltage is applied to each second test pad 302 to charge each capacitor structure 21. Then, the actual voltage values ​​of the first electrode 2111 and each second electrode 212 are obtained through the first test pad 301 and each second test pad 302, and the actual voltage values ​​obtained are compared with the preset voltage values. If there is a voltage difference between the actual voltage value and the preset voltage value, it means that the capacitor structure 21 has leakage, and the magnitude of the voltage difference can characterize the magnitude of leakage at different height positions of the capacitor structure 21. Since the magnitude of leakage of the capacitor structure 21 is exponentially related to the thickness of the film of the capacitor structure 21, the thickness uniformity of the film of the capacitor structure 21 at different height positions can be characterized by the magnitude of leakage at different height positions of the capacitor structure 21. The structure is simple and easy to implement, thereby reducing the difficulty of characterizing the uniformity of the film thickness of the capacitor structure 21.

[0148] In the three-dimensional semiconductor structure and its preparation method provided by the embodiment of the present application, a test structure is set on the stacked structure, so that the first test pad in the test structure is electrically connected to the first electrode array in the capacitor structure through the contact pad, and the second test pad in the test structure is electrically connected to its corresponding second electrode. The leakage conditions at different positions of the capacitor structure are tested by the test structure, so that the uniformity of the film thickness in the capacitor structure is characterized by the leakage magnitude at different positions of the capacitor structure. The structure and characterization method are simple and easy to implement. In addition, the first electrode array in the capacitor structure includes multiple first electrodes, so as to simulate the performance of multiple parallel capacitors and amplify the leakage current signal of the capacitor structure, thereby improving the test accuracy of the test structure for leakage current phenomena and improving the characterization accuracy of the film thickness of the capacitor structure. Moreover, a first electrode array is connected to the first test pad through a contact pad, and each first electrode does not need to be electrically connected to the first test pad by making a contact plug, thereby simplifying the preparation process.

[0149] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0150] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A three-dimensional semiconductor structure, characterized in that include: substrate; A stacked structure located on the substrate, wherein the stacked structure comprises a capacitor structure, wherein the capacitor structure comprises a first electrode array and a plurality of second electrodes, wherein the first electrode array comprises a plurality of first electrodes arranged in an array, a dielectric layer being provided between each first electrode and the second electrode, wherein each first electrode extends along a first direction; and the plurality of second electrodes are stacked and spaced apart along the first direction, with a support layer being provided between any two adjacent second electrodes; and wherein the first direction is the thickness direction of the substrate; a contact pad, located on a surface of the stacked structure facing away from the substrate, and electrically connected to the first electrode array; A test structure is located on a surface of the stacked structure facing away from the substrate, the test structure includes a first test pad and multiple second test pads, the first test pad is electrically connected to the contact pad, and the multiple second test pads are respectively electrically connected to their corresponding second electrodes, and the test structure is configured to test the voltage of the capacitor structure.

2. The three-dimensional semiconductor structure according to claim 1, wherein: The plurality of first electrodes are arranged in a rectangular array.

3. The three-dimensional semiconductor structure according to claim 2, wherein: The projection of the contact pad in the first direction covers the projection of the first electrode array in the first direction.

4. The three-dimensional semiconductor structure according to claim 3, wherein: The contact pad is a titanium nitride contact pad.

5. The three-dimensional semiconductor structure according to any one of claims 1 to 4, characterized in that: It also includes a contact structure, which includes a first contact plug and multiple second contact plugs. The first contact plug is electrically connected between the contact pad and the first test pad; each second contact plug is electrically connected between the corresponding second electrode and the second test pad.

6. The three-dimensional semiconductor structure according to any one of claims 1 to 4, wherein: The stack structure is provided with a plurality of first channels penetrating the stack structure along the first direction, and each of the first electrodes is respectively provided in the first channel corresponding thereto; The dielectric layer is located between the first electrode and the inner wall of the first channel; The plurality of second electrodes are sequentially stacked and spaced apart in a step-like manner from close to the substrate to far away from the substrate, and each of the second electrodes is connected to the dielectric layer.

7. The three-dimensional semiconductor structure according to claim 6, wherein: A first barrier layer is further provided between the dielectric layer and the first electrode; and / or a second barrier layer is provided between the second electrode and the support layer.

8. The three-dimensional semiconductor structure according to any one of claims 1 to 4, characterized in that: There are multiple capacitor structures, and the multiple capacitor structures are arranged at intervals along the second direction, and an isolation wall is provided between any two adjacent capacitor structures; wherein the second direction is perpendicular to the first direction.

9. The three-dimensional semiconductor structure according to claim 8, wherein: A plurality of the capacitor structures are arranged in parallel.

10. A method for preparing a three-dimensional semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate; A capacitor structure is formed in the stacked structure, comprising a first electrode array and a plurality of second electrodes, wherein the first electrode array comprises a plurality of first electrodes arranged in an array, wherein each first electrode extends along a first direction; a plurality of second electrodes are stacked and spaced apart along the first direction, a support layer is provided between any two adjacent second electrodes; and a dielectric layer is provided between the first electrode and the second electrode; and the first direction is the thickness direction of the substrate; forming a contact pad on a surface of the stacked structure facing away from the substrate, wherein the contact pad is electrically connected to the first electrode array; A test structure is formed on a surface of the stacked structure facing away from the substrate; the test structure includes a first test pad and a plurality of second test pads, the first test pad is electrically connected to the contact pad, and the plurality of second test pads are respectively electrically connected to their corresponding second electrodes, and the test structure is configured to test the voltage of the capacitor structure.

11. The method for preparing a three-dimensional semiconductor structure according to claim 10, wherein: Before the step of forming a stacked structure on the substrate and after the step of providing the substrate, the method includes: forming a plurality of predetermined layers stacked on the substrate; The plurality of preset layers include supporting layers and sacrificial layers that are alternately stacked in sequence.

12. The method for preparing a three-dimensional semiconductor structure according to claim 11, wherein: The step of forming a stacked structure on the substrate includes: forming a plurality of first channels arranged in an array in the preset layer; the first channels extending along the first direction and penetrating the preset layer; A dielectric layer, a first barrier layer, and a first electrode are sequentially formed in the first trench; wherein the first barrier layer is disposed around an outer sidewall of the first electrode; and the dielectric layer is located between the first barrier layer and an inner sidewall of the first trench; removing the sacrificial layer in the preset layer and forming a first slit; A second electrode is formed in the first slit.

13. The method for preparing a three-dimensional semiconductor structure according to claim 12, wherein: Before removing the sacrificial layer in the preset layer, the method further includes: removing portions of the supporting layer and the sacrificial layer on two opposite sides of the predetermined layer along the third direction to expose a surface of each supporting layer facing away from the substrate, so that the remaining adjacent supporting layers and sacrificial layers are arranged in a step-like manner from close to away from the substrate; forming a first oxide layer on the remaining support layer and the sacrificial layer; forming a plurality of second slits spaced apart along a second direction on the first oxide layer, wherein the second slits penetrate the preset layer, and the first electrode array and the second slits are sequentially spaced apart along the second direction; The third direction, the second direction and the first direction are perpendicular to each other.

14. The method for preparing a three-dimensional semiconductor structure according to claim 13, wherein: The step of forming the second electrode in the first slit specifically includes: sequentially filling a second barrier layer and a second electrode in the first slit; removing the second barrier layer and the second electrode in the second slit; The second slit is filled with an isolation material to form an isolation wall.

15. The method for preparing a three-dimensional semiconductor structure according to claim 14, wherein: The step of forming contact pads on the stacked structure specifically includes: removing a portion of the first oxide layer to expose a surface of the first electrode array facing away from the substrate; wherein the remaining surface of the first oxide layer facing away from the substrate is a flat surface; Contact pads are formed on the first electrode array so as to electrically connect the contact pads to the first electrodes in the first electrode array.

16. The method for preparing a three-dimensional semiconductor structure according to claim 15, wherein: The step of forming a test structure on the stacked structure includes: forming a second oxide layer on the first oxide layer and the contact pad; forming a second channel and a plurality of third channels on the second oxide layer, wherein the second channel exposes the contact pad, and the third channel exposes the surface of the second electrode; wherein one third channel corresponds to one second electrode; Depositing a conductive material on the second oxide layer, the conductive material filling the second trench and the third trench while covering the surface of the second oxide layer; the conductive material filled in the second trench forms a first contact plug, and the conductive material filled in the third trench forms a second contact plug; Part of the conductive material is removed, and the conductive material covering the first contact plug and the second contact plug is retained; wherein the conductive material covering the first contact plug is formed into a first test pad; the conductive material covering the second contact plug is formed into a second test pad; the first test pad and the second test pad form the test structure.

Images