Semiconductor structures and semiconductor devices

Abstract

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a semiconductor device. The semiconductor structure comprises at least: a gate structure region and a source region and a drain region respectively located on both sides of the gate structure region; wherein the gate structure region comprises at least: a channel region and a gate region arranged from the inside out, the channel region enveloping the inner cavity of the gate region, and the channel region respectively adheres to the source region, the drain region and the gate region; the drain region, the source region and the channel region are ion-doped of the same type. A semiconductor structure with body conduction, a non-inversion electron layer, a small tunneling effect, low gate leakage, low power consumption, a higher electron or hole drift velocity, and a higher carrier migration efficiency is provided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a semiconductor device. Background Art

[0002] With the rapid advancement of semiconductor technology, the scale of CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuits, a key component of the modern electronic information industry, continues to grow. This is primarily due to the continuous reduction in the feature size of CMOS devices, with the most advanced 5nm semiconductor process now entering mass production. However, with the continuous increase in integration density, the continued increase in power consumption of integrated circuit chips has become a major challenge in the development of integrated circuits.

[0003] In addition to the increasing demands for process precision, another significant influencing factor is short channel effects (SCE). SCE refers to the effects that occur in metal oxide semiconductor field-effect transistors (MOSFETs) when the conductive channel length is reduced to tens of nanometers or even a few nanometers. SCE primarily includes: a decrease in threshold voltage with decreasing channel length, a lower drain-induced barrier, carrier surface scattering, and velocity saturation. The presence of SCE prevents further reduction in the feature size of current semiconductor devices. To mitigate SCE, the industry is currently adopting specialized device structures. For example, at the 14nm node, FinFETs (Fin Field-Effect Transistors) and gate-all-around FETs were introduced, while at the 5nm node, GAA (Gate-All-Around) devices were introduced to mitigate the impact of SCE on devices. While GAA devices are currently more widely used, they still have PN junctions, which means they still face issues such as dopant diffusion, limiting device size. In addition, since it is a surface channel device, there are still problems such as surface mobility and hot carrier effect.

[0004] Therefore, there is an urgent need for a semiconductor device that can further break through the feature size. Summary of the Invention

[0005] In order to solve the above technical problems, a semiconductor structure and a semiconductor device are provided in the embodiments of the present application.

[0006] A first aspect of an embodiment of the present application provides a semiconductor structure, comprising at least:

[0007] A gate structure region and a source region and a drain region respectively located on both sides of the gate structure region; wherein the gate structure region at least includes:

[0008] The channel region and the gate region are arranged from the inside out, the channel region is covered in the inner cavity of the gate region, and the channel region is respectively attached to the source region, the drain region and the gate region; the drain region, the source region and the channel region are ion doped with the same type.

[0009] In an optional embodiment of the present application, the gate structure region further includes:

[0010] The dielectric layer is disposed between the gate region and the channel region, and is respectively adhered to the gate region, the channel region, the drain region, and the source region.

[0011] In an optional embodiment of the present application, the gate structure region further includes:

[0012] The buffer barrier region is located between the channel region and the dielectric layer, and is respectively in contact with the dielectric layer, the channel region, the drain region, and the source region.

[0013] In an optional embodiment of the present application, the ion doping concentration of the buffer barrier region is not greater than 1e17 / cm 3 .

[0014] In an optional embodiment of the present application, the ion doping concentration of the buffer barrier region is less than the ion doping concentration of the drain region and the source region; and / or, the ion doping concentration of the buffer barrier region is one order of magnitude less than the ion doping concentration of the channel region.

[0015] In an optional embodiment of the present application, the thickness of the buffer barrier region is 0.3 to 5 nanometers.

[0016] In an optional embodiment of the present application, the ion doping concentration of the gate region is 1e16 / cm 3 ~1e20 / cm 3 ; and / or, the ion doping concentration of the channel region is 1e17 / cm 3 ~5e19 / cm 3 ; and / or, the ion doping concentration of the drain region and the source region is 1e18 / cm 3 ~5e20 / cm 3 .

[0017] In an optional embodiment of the present application, the ion doping concentrations of the drain region, the source region, and the channel region are equal.

[0018] In an optional embodiment of the present application, the ion doping concentration of the drain region, the source region, and the channel region is not less than 1e17 / cm 3 .

[0019] In an optional embodiment of the present application, the drain region, the source region and the channel region are manufactured as one piece.

[0020] In an optional embodiment of the present application, the semiconductor structure is an N-type device, and the gate region is a metal with a metal work function of 4.5 eV-5.2 eV; or,

[0021] If the semiconductor structure is a P-type device, the gate region is a metal having a metal work function of 4.0 eV-4.5 eV.

[0022] In an optional embodiment of the present application, the semiconductor structure is a FinFET device or a GAA device.

[0023] According to a second aspect of the embodiments of the present application, a semiconductor device is provided, including:

[0024] A semiconductor structure as described in any one of the above items.

[0025] In an optional embodiment of the present application, there are multiple semiconductor structures; and the conductivity types of the multiple semiconductor structures are not completely the same.

[0026] In an optional embodiment of the present application, a first semiconductor structure and a second semiconductor structure are stacked on the surface of a substrate layer in a vertical direction, wherein the first semiconductor structure includes a plurality of semiconductor structures of a first conductive type, and the second semiconductor structure includes a plurality of semiconductor structures of a second conductive type; the first conductive type is different from the second conductive type.

[0027] In an optional embodiment of the present application, the semiconductor device further includes:

[0028] An insulating layer is disposed between the first semiconductor structure and the second semiconductor structure, and the insulating layer passes through the gate region.

[0029] First, the drain region, source region, and channel region in the embodiments of the present application are all doped with the same type of ions, forming a homojunction device structure. There is no interface effect between the regions, and the traditional interface conduction is converted to body conduction. The electron or hole drift velocity is higher, and the carrier migration efficiency is higher, thereby obtaining a higher electron or hole drift velocity, further improving the working efficiency and device reliability of the semiconductor structure;

[0030] Secondly, the drain region, source region and channel region in the embodiments of the present application are all doped with the same type of ions, converting the traditional interface conduction into body conduction, and the channel region is directly controlled by the gate region.

[0031] When no voltage is applied to the gate region or zero voltage is applied, due to the energy band difference between the gate region and the channel region (the electron affinity of silicon devices (the difference between the bottom of the conduction band and the vacuum energy level) is 4.05eV), the channel region of the device is self-depleted due to the influence of the gate region, forming a self-depleted non-inversion semiconductor structure. That is, only when a voltage is applied to the gate region does the current flow from the highly doped region of the drain region through the channel region to the source region, that is, the channel region is open. When no voltage is applied to the gate region, the channel region is in a closed state, forming a normally closed device structure, which consumes less energy than traditional normally open devices.

[0032] Thirdly, the semiconductor structure provided in the embodiment of the present application is body-conducting, and the device does not have a PN junction structure. The absence of a PN junction depletion layer can eliminate the effect of lowering the threshold voltage due to the PN junction structure, that is, the characteristic size of the device can be further reduced. Experiments show that the current device channel length can meet the requirements of less than 10nm.

[0033] Fourthly, the semiconductor structure provided by the embodiments of the present application is body-conducting, and the conduction current is far away from the interface, which does not cause the problem of reduced interface mobility. At the same time, the conduction current away from the interface can also reduce the tunneling current, reduce gate leakage, and improve the reliability and stability of the device structure;

[0034] Fifthly, the semiconductor structure of the embodiment of the present application is a non-inversion device, and the electrons in the channel region do not flow in the surface inversion layer, thus avoiding device gate leakage. At the nanoscale, the tunneling current caused by the tunneling effect is the main source of gate leakage. The thickness of the device gate dielectric is limited, and High-k dielectric technology has been developed. After adopting High-k dielectric, the gate dielectric thickness can be thickened without reducing the gate control capability. The semiconductor structure provided by the embodiment of the present application can reduce the tunneling current because the current no longer flows in the surface inversion layer, and at the same time, it is possible to avoid the use of high-k dielectric, proposing a new technical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0036] Figure 1 This is the process flow chart of traditional GAA;

[0037] Figure 2A schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of a simulation structure of a semiconductor structure provided in an embodiment of the present application;

[0039] Figure 4 A schematic cross-sectional view of a gate structure region in a semiconductor structure provided in an embodiment of the present application;

[0040] Figure 5 A data diagram showing the electron density simulation results of the vertical channel region of the semiconductor structure provided by an embodiment of the present application in the on state;

[0041] Figure 6 When the semiconductor structure provided in the embodiment of the present application is an N-type device, the energy band and electron distribution diagram of the buffer barrier region and the channel region of the device in the off state;

[0042] Figure 7 When the semiconductor structure provided in the embodiment of the present application is an N-type device, the transfer characteristic curve and gate leakage current curve of a 1mm total gate width device;

[0043] Figure 8 When the semiconductor structure provided in the embodiment of the present application is an N-type device, the transfer characteristic curves of a 1mm total gate width device under different Vd;

[0044] Figure 9 When the semiconductor structure provided in the embodiment of the present application is a P-type device, the energy band and electron distribution diagram of the buffer barrier region and the channel region of the device in the off state;

[0045] Figure 10 When the semiconductor structure provided in the embodiment of the present application is a P-type device, the transfer characteristic curve and gate leakage current curve of a 1mm total gate width device;

[0046] Figure 11 When the semiconductor structure provided in the embodiment of the present application is a P-type device, the transfer characteristic curves of a 1mm total gate width device under different Vd;

[0047] Figure 12 A schematic diagram of the semiconductor device structure provided in an embodiment of the present application.

[0048] in:

[0049] 10. Semiconductor structure; 100. Channel region; 200. Gate region; 300. Source region; 400. Drain region; 600. Buffer barrier region; 500: Dielectric layer; 30. Gate structure region;

[0050] 20. Semiconductor device; 21. Substrate layer; 22. Insulation layer; 23. First semiconductor structure; 24. Second semiconductor structure. DETAILED DESCRIPTION

[0051] With the rapid advancement of semiconductor technology, the scale of CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuits, a key component of the modern electronic information industry, continues to grow. This is primarily due to the continuous reduction in the feature size of CMOS devices, with the most advanced 5nm semiconductor process now entering mass production. However, with the continuous increase in integration density, the continued increase in power consumption of integrated circuit chips has become a major challenge in the development of integrated circuits.

[0052] In addition to the increasingly high requirements for process preparation precision, another important influencing factor is the short channel effect (SCE). The short channel effect refers to the effect that occurs in the transistor when the conductive channel length of the metal oxide semiconductor field effect transistor is reduced to a dozen nanometers or even a few nanometers. The short channel effect mainly includes: the threshold voltage decreases with the decrease in channel length, the drain barrier decreases, the carrier surface scattering, the velocity saturation effect, etc. The existence of the short channel effect makes it impossible to further reduce the feature size of current semiconductor devices. In order to reduce the short channel effect, the industry currently adopts special device structures. For example, at the 14nm node, FinFET (Fin Field-Effect Transistor) and all-around gate field effect transistor were proposed, and at the 5nm node, GAA (Gate-All-Around, transistors with surround gate technology, called all-around gate transistors) devices were introduced to improve the impact of the short channel effect on the device.

[0053] Currently, GAA devices are more widely used, but they still have PN junctions, which means they still have problems such as doping diffusion, and their device size is limited. In addition, because they are surface channel devices, they also have problems such as surface mobility and hot carrier effects. For example, current GAA devices still have the following defects:

[0054] (1) There are short channel effect and narrow channel effect that affect the threshold voltage

[0055] When the channel length is reduced to a certain extent, the proportion of the source and drain depletion regions in the entire channel increases, and the amount of charge required to form a surface inversion layer on the silicon surface below the gate decreases, thereby reducing the threshold voltage. At the same time, the charge in the depletion region in the substrate that extends laterally along the channel width increases the threshold voltage. When the channel width is reduced to the same order of magnitude as the depletion layer width, the threshold voltage reduction becomes very significant. The threshold voltage of short-channel devices is very sensitive to changes in channel length.

[0056] (2) Mobility field-related effect and carrier velocity saturation effect

[0057] Under low electric fields, mobility is constant, and carrier velocity increases linearly with the electric field. Under high electric fields, mobility decreases, carrier velocity reaches saturation, and is no longer dependent on the electric field. Current devices have a surface inversion layer when on, and the electron layer exists at the device interface, which is affected by interface scattering. Interface mobility determines the device's drain saturation current characteristics. On the semiconductor surface, mobility is reduced by surface scattering and Coulomb scattering, which also reduces the device's surface carrier saturation velocity. Furthermore, the gate's extremely strong electric field perpendicular to the interface further reduces carrier mobility.

[0058] (3) Subthreshold characteristics degrade, and the device clamps continuously

[0059] Subthreshold leakage current degrades the off-state characteristics of MOSFET devices and increases static power consumption. It can also cause logic state confusion in dynamic circuits and memory cells. Therefore, the drain-induced barrier lowering (DIBL) effect, caused by a short channel, has become a fundamental physical effect that determines the size limit of short-channel MOS devices. The DIBL effect occurs when a high voltage is applied to the drain. Due to the short gate, the source is also affected by the drain electric field, lowering the source junction barrier. Simultaneously, the drain depletion layer expands, even connecting to the source depletion region, rendering the device unable to turn off. The drain voltage affects the gate's turn-off potential. While increasing the drain voltage will not affect the drain voltage after normal shutdown, the short-channel effect increases the drain current as the drain voltage changes.

[0060] (4) Device gate dielectric layer tunneling and gate leakage

[0061] In microelectronics, tunneling current refers to the current generated by the quantum tunneling effect of charge carriers when the thickness of a semiconductor barrier or silicon dioxide film is reduced to a value comparable to the wavelength of the carrier's de Broglie wave. As device dimensions shrink to nanometers, the tunneling current through the gate oxide layer caused by this effect can no longer be ignored, becoming a significant factor affecting device miniaturization. In inversion devices, the charge carriers reside at the device interface and are highest there, resulting in a very strong tunneling current.

[0062] (5) 3D integration and annealing process

[0063] The device process requires ion implantation and annealing, which are incompatible with low-temperature processes. Temperature creates two issues: diffusion, as the diffusion of the PN junction prevents scaling to small dimensions; and high-temperature processes cannot be used after the metal and silicide processes, as they damage the silicide and metal structures.

[0064] (6) GAA process flow Figure 1 , the overall process is relatively complicated.

[0065] Therefore, there is an urgent need for a semiconductor device that can further break through the feature size.

[0066] To address the above-mentioned issues, embodiments of the present application provide a semiconductor structure and a semiconductor device. To further clarify the objectives, technical solutions, and advantages of this application, the following further describes a semiconductor structure and a semiconductor device of the present application through embodiments and in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are intended only to explain this application and are not intended to limit this application.

[0067] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application include direct and indirect connections (couplings) unless otherwise specified. In the description of this application, it should be understood that the orientations or positional relationships indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.

[0068] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0069] Please also see Figure 2-Figure 4 , an embodiment of the present application provides a semiconductor structure 10, comprising at least:

[0070] See Figure 2 and Figure 3 , Figure 2 Schematic diagram of the three-dimensional structure of the semiconductor structure 10 according to an embodiment of the present application. Figure 3This is a simulated structural diagram of the semiconductor structure 10 according to an embodiment of the present application, including an x-direction extending along a plane, a y-direction along a longitudinal direction, and a z-direction along a vertical direction (or a depth direction or a height direction). It includes a gate structure region 30 and a source region 300 and a drain region 400 located on either side of the gate structure region 30; Figure 4 For the Figure 3 The gate structure region 30 at least includes:

[0071] The channel region 100 and the gate 200 are arranged from the inside out, and the channel region 100 is covered in the inner cavity of the gate region 200, and the channel region 100 is respectively adhered to the source region 300, the drain region 400 and the gate region 200; the drain region 400, the source region 300 and the channel region 100 are ion-doped of the same type.

[0072] The gate region 200 may be a metal gate or a first ion doping type, which is not specifically limited in the present embodiment. The gate region 200 may include a top gate and a bottom gate, for example Figure 4 Both the top gate and the bottom gate are located on the surface of the channel region 100. The bottom gate and the top gate can be fabricated simultaneously, simplifying the process. The source region 300 and the drain region 400 can be highly doped regions to improve the conduction electron flow or hole mobility performance. The first ion doping type and the second ion doping type are different. That is, the first ion doping type is N-type doping and the second ion doping type is P-type doping, or the first ion doping type is P-type doping and the second ion doping type is N-type doping.

[0073] First, the drain region 400, the source region 300 and the channel region 100 in the embodiment of the present application are all doped with the same type of ions and are a homojunction device structure. There is no interface effect between the regions, and the traditional interface conduction is converted into body conduction. The electron or hole drift velocity is higher, and the carrier migration efficiency is higher, thereby obtaining a higher electron or hole drift velocity, further improving the working efficiency and device reliability of the semiconductor structure 10; wherein, body conduction refers to the conduction of electrons or holes along the internal layer of the device, which is different from the interface conduction of the electric field formed at the interface or the inversion electron layer.

[0074] Secondly, the drain region 400, the source region 300 and the channel region 100 in the embodiment of the present application are all doped with the same type of ions, converting the traditional interface conduction into body conduction, and the channel region 100 is directly controlled by the gate region.

[0075] When no voltage is applied to the gate region or zero voltage is applied, due to the energy band difference between the gate region and the channel region 100 (the electron affinity of silicon devices (the difference between the bottom of the conduction band and the vacuum energy level) is 4.05 eV), the device channel region 100 is self-depleted due to the influence of the gate region, forming a self-depleted non-inversion semiconductor structure 10. That is, only when a voltage is applied to the gate region does current flow from the highly doped region of the drain region 400 through the channel region 100 to the source region 300, that is, the channel region 100 is open. When no voltage is applied to the gate region, the channel region 100 is in a closed state, forming a normally closed device structure, which consumes less energy than traditional normally open devices.

[0076] Thirdly, the semiconductor structure 10 provided in the embodiment of the present application is body-conducting, and the device does not have a PN junction structure. The absence of a PN junction depletion layer can eliminate the effect of lowering the threshold voltage due to the PN junction structure, that is, the characteristic size of the device can be further reduced. Experiments show that the current device channel length can meet the requirements of less than 10nm.

[0077] Fourthly, the semiconductor structure 10 provided in the embodiment of the present application is body-conducting, and the conduction current is far away from the interface, which does not cause the problem of reduced interface mobility. At the same time, the conduction current away from the interface can also reduce the tunneling current, reduce gate leakage, and improve the reliability and stability of the device structure;

[0078] Fifthly, the semiconductor structure 10 of the embodiment of the present application is a non-inversion device. The electrons in the channel region 100 do not flow in the surface inversion layer, thus avoiding device gate leakage. At the nanoscale, the tunneling current caused by the tunneling effect is the main source of gate leakage. The thickness of the device gate dielectric is limited, and High-k dielectric technology has been developed. After adopting High-k dielectric, the gate dielectric thickness can be thickened without reducing the gate control capability. The semiconductor structure 10 provided in the embodiment of the present application can reduce the tunneling current because the current no longer flows in the surface inversion layer. At the same time, it is possible to avoid the use of high-k dielectrics, thus proposing a new technical direction.

[0079] Please continue to see Figure 2 and Figure 4 In an optional embodiment of the present application, the gate structure region 30 further includes:

[0080] The dielectric layer 500 is disposed between the gate region 200 and the channel region 100 and is respectively adhered to the gate region 200 , the channel region 100 , the drain region 400 and the source region 300 . The gate region 200 is located in different dielectric layers 500 .

[0081] The dielectric layer 500 can be made of an insulating material such as silicon dioxide. The dielectric layer 500 completely wraps the gate region 200 inside it, that is, there is a thin layer of dielectric between the gate region 200 and the channel region 100. Similarly, there is also a thin layer of dielectric between the bottom gate region and the channel. This structure forms a fully enclosed gate structure, that is, the channel region 100 is doped and annularly wrapped by the dielectric layer 500, exposing only the portion electrically connected to the source region 300 and the drain region 400.

[0082] Please continue to see Figure 2 and Figure 4 In an optional embodiment of the present application, the gate structure region 30 further includes a buffer barrier region 600, wherein:

[0083] The buffer barrier region 600 is located between the channel region 100 and the dielectric layer 500 , and is respectively aligned with the dielectric layer 500 , the channel region 100 , the drain region 400 , and the source region 300 .

[0084] The buffer barrier region 600 is used to isolate the gate region 200 from the channel region 100, and / or to isolate the bottom gate region from the channel region 100. The buffer barrier region 600 can be a low-doped region, that is, its ion doping concentration is less than the ion doping concentration of the drain region 400 and the source region 300. By setting the buffer barrier region 600, the device will not form a surface inversion electron layer at the contact interface between the channel region 100 and the gate region 200, thereby avoiding performance loss caused by a decrease in surface mobility. It can also effectively prevent the occurrence of electron tunneling, reduce the gate region current, prevent interface scattering, and improve device reliability and stability.

[0085] That is, a buffer barrier region 600 is provided between the gate region 200 and the channel region 100, so that the device does not form a surface inversion electron layer at the contact interface between the channel region 100 and the gate region 200, thereby avoiding the performance loss caused by the reduction of surface mobility. It can also effectively prevent the occurrence of electron tunneling, reduce the gate region current, prevent interface scattering, and further improve the reliability and stability of the device.

[0086] That is, the buffer barrier region 600 and the channel region 100, the drain region 400 and the source region 300 are of the same ion doping type and can be grown and formed simultaneously, reducing process complexity while avoiding traditional thermal processes such as annealing, thereby improving the yield of device structure preparation, as well as the performance reliability and stability of the finished device.

[0087] In an optional embodiment of the present application, the ion doping concentration of the buffer barrier region 600 is less than the ion doping concentration of the drain region 400 and the source region 300; and / or, the ion doping concentration of the buffer barrier region 600 is one order of magnitude less than the ion doping concentration of the channel region 100.

[0088] That is, the drain region 400 and the source region 300 are high ion doping regions, and the buffer barrier region 600 is a low ion doping region, forming an ion concentration difference between the two, thereby preventing the electron flow formed between the source region 300 and the drain region 400 from scattering from the channel region 100 to the buffer barrier region 600, thereby further ensuring the reliability of the device structure and the performance stability.

[0089] In an optional embodiment of the present application, the ion doping concentration of the buffer barrier region 600 is not greater than 1e17 / cm 3 , is a low-concentration doping region, the thickness of the buffer barrier region 600 is 0.3nm~5nm, and the buffer barrier region 600 is made of silicon material.

[0090] See Figure 5 , Figure 5 Taking the channel region 100 width of 1nm and the buffer barrier layer 600 thickness of 0.5nm as an example, the electron density simulation result data graph of the vertical channel region 100 when the device structure is in the open state is shown. The horizontal axis is the position along the vertical direction of the channel, in microns, where the 0 coordinate point is the center position of the channel, and the vertical axis is the electron concentration, in / cm 3 It can be seen that the electrons in the device channel in the on state are concentrated inside the device channel region 100, while the electron concentration in the buffer barrier region 600 of the device is reduced by more than an order of magnitude, proving that the device is in an internal conduction state.

[0091] In an optional embodiment of the present application, the ion doping concentration of the gate region 200 is 1e16 / cm 3 ~1e20 / cm 3 ; and / or, the ion doping concentration of the channel region 100 is 1e17 / cm 3 ~5e19 / cm 3 and / or, the ion doping concentration of the drain region 400 and the source region 300 is 1e18 / cm 3 ~5e20 / cm 3 .

[0092] The device structure obtained within the above concentration parameter range has better self-depletion effect, better body conduction performance, and smaller other negative effects, which can further improve the stability and reliability of the device structure.

[0093] In an optional embodiment of the present application, the ion doping concentrations of the drain region 400 , the source region 300 , and the channel region 100 are equal.

[0094] That is, the channel region 100, the drain region 400 and the source region 300 are of the same ion doping type and can be grown and formed simultaneously, reducing process complexity while avoiding traditional thermal processes such as annealing, thereby improving the yield of device structure preparation and the performance reliability and stability of the finished device.

[0095] In an optional embodiment of the present application, the ion doping concentration of the drain region 400, the source region 300 and the channel region 100 is not less than 1e17 / cm 3 .

[0096] That is, the channel region 100, the drain region 400 and the source region 300 are made of the same material, and the required ions are implanted into the initial material. No additional ion doping is required during the preparation process, and the channel region 100, the drain region 400 and the source region 300 can be grown and formed at the same time, reducing the process complexity and avoiding traditional thermal processes such as annealing, thereby improving the yield of device structure preparation and the performance reliability and stability of the finished device.

[0097] In an optional embodiment of the present application, the drain region 400, the source region 300 and the channel region 100 are made as one piece. That is, the channel region 100, the drain region 400 and the source region 300 are grown and formed at the same time, which simplifies the process and reduces the complexity of the process. At the same time, it avoids traditional thermal processes such as annealing, improves the yield rate of device structure preparation, and the performance reliability and stability of the finished device. In addition, by converting the traditional interface conduction to body conduction, there is no interface effect between the regions, the electron or hole drift velocity is higher, and the surface migration efficiency of the carrier is higher, thereby obtaining a higher electron or hole drift velocity, further improving the working efficiency and device reliability of the semiconductor structure 10.

[0098] In an optional embodiment of the present application, the semiconductor structure 10 is an N-type device, and the gate region 200 is a metal with a metal work function of 4.5 eV-5.2 eV.

[0099] See Figure 6 , Figure 6 When the N-type device is turned off, the metal work function of the gate region 200 is 4.5eV-5.2eV, and the energy band and electron distribution diagram of the buffer barrier region 600 and the channel region are shown. Figure 6 (a) is the energy band diagram. The horizontal axis is the position along the vertical direction of the channel, in micrometers, where the 0 coordinate point is the center of the channel, and the vertical axis is the electron concentration, in cm 3 , Figure 6 (b) is the electron distribution diagram of the buffer barrier region 600 and the channel region. The horizontal axis is the position along the vertical direction of the channel, in micrometers, where the 0 coordinate point is the center of the channel, and the vertical axis is the channel electron concentration. Figure 6(a) and Figure 6 (b) It can be seen that when the metal work function of the gate region 200 is 4.5eV-5.2eV, the Fermi level of the semiconductor layer is located in the middle position. In silicon material, as shown in the figure, the Fermi level is close to 0.5eV from the conduction band and the valence band. At this time, there are very few electrons and holes in the semiconductor layer, the device is completely turned off, and the device performance is excellent.

[0100] See Figure 7 , Figure 7 This is the simulation result of an N-type device with a channel width of 7nm and a gate width of 1mm. Figure 7 (a) is the transfer characteristic curve, the horizontal axis is the gate voltage, the vertical axis is the drain current, Figure 7 (b) is the gate leakage IgVg diagram, the horizontal axis is the gate voltage, the vertical axis is the gate current, Figure 7 (a) and Figure 7 (b) It can be seen that the channel current changes by 6 orders of magnitude in the on and off states of the device structure, while the gate leakage current of the device is controlled below 100uA, and the device performance is excellent.

[0101] See Figure 8 , Figure 8 This is the IdVg curve of the N-type device under different Vd, Figure 8 It can be seen that the current difference of the device is small under different drain voltages, and it can be seen that the device has good DIBL (drain-induced barrier lowering) characteristics.

[0102] In an optional embodiment of the present application, the semiconductor structure 10 is a P-type device, and the gate region 200 is a metal with a metal work function of 4.0 eV-4.5 eV.

[0103] See Figure 9 , Figure 9 When the P-type device is turned off, the metal work function of the gate region 200 is 4.0eV-4.5eV, and the energy band and hole distribution diagram of the buffer barrier region 600 and the channel region are shown. Figure 9 (a) is the energy band diagram, the horizontal axis is the position along the vertical direction of the channel, the unit is micrometer, where the 0 coordinate point is the center of the channel, and the vertical axis is the electron concentration, the unit is cm^-3, Figure 9 (b) is a diagram of hole distribution in the buffer barrier region 600 and the channel region. The horizontal axis is the position along the vertical direction of the channel, in micrometers, where the 0 coordinate point is the center of the channel, and the vertical axis is the hole concentration in the channel. Figure 9 (a) and Figure 9 (b) It can be seen that when the metal work function of the gate region 200 is 4.0eV-4.5eV, in the off state, the Fermi level is located in the center of the band gap, there are very few holes, the device is completely turned off, and the device performance is excellent.

[0104] See Figure 10 , Figure 10 This is the simulation result of a P-type device with a channel width of 7nm and a gate width of 1mm. Figure 10 (a) is the transfer characteristic curve, the horizontal axis is the gate voltage, the vertical axis is the drain current, Figure 10 (b) is the gate leakage IgVg diagram, the horizontal axis is the gate voltage, the vertical axis is the gate current, Figure 10 (a) and Figure 10 (b) It can be seen that the channel current changes by 5 orders of magnitude when the device structure is on and off, while the gate leakage current of the device is controlled below 100uA, and the device performance is excellent.

[0105] See Figure 11 , Figure 11 It is the IdVg curve of P-type device and N-type device under different Vd. Figure 11 It can be seen that the current difference of the device is small under different drain voltages, and it can be seen that the device has good DIBL (drain-induced barrier lowering) characteristics.

[0106] In an optional embodiment of the present application, the semiconductor structure 10 is a FinFET device or a GAA device.

[0107] Please refer to the description of the beneficial effects of the semiconductor structure 10 above. The embodiment of the present application can provide a semiconductor device 20 with body conduction, non-inversion electron layer, small tunneling effect, low gate leakage, low power consumption, higher electron or hole drift velocity, higher carrier migration efficiency, small characteristic size, and breaking through the current device size limit.

[0108] See Figure 12 One embodiment of the present application provides a semiconductor device 20, including:

[0109] The semiconductor structure 10 as described in any one of the above items.

[0110] Please refer to the above description of the beneficial effects of the semiconductor structure 10. The embodiment of the present application can provide a semiconductor structure 10 with body conduction, non-inversion electron layer, small tunneling effect, low gate leakage, low power consumption, higher electron or hole drift velocity, higher carrier migration efficiency, small characteristic size, and breaking through the current device size limit.

[0111] like Figure 12 As shown, in an optional embodiment of the present application, there are multiple semiconductor structures 10; the conductivity types of the multiple semiconductor structures 10 are not completely the same, and the multiple semiconductor structures 10 are insulated by an insulating layer 22. It should be explained that in an actual product, multiple semiconductor devices 10 can be stacked or arranged in any direction. Figure 12It does not constitute a specific limitation on the structure of the semiconductor device 20 and the arrangement of the semiconductor structure 10 provided in the embodiments of the present application.

[0112] That is, both N-type and P-type semiconductor devices 20 can be realized in the same device at the same time. For example, a three-dimensional integrated complementary FET device can be made through 3D integration to form a logic unit that can realize logical functions. On the one hand, the embodiment of the present application integrates both N-type and P-type semiconductor devices 20 in the same three-dimensional structure, which can improve the integration level and reduce the area; on the other hand, it can reduce the delay caused by the connection and improve the device performance. Figure 10 Taking the example of devices being divided into two categories, the first conductive type device is between the bottom insulating layer 22 of the substrate layer 21 and the middle insulating layer 22, and the first conductive type device is above the middle insulating layer 22. The two types of devices are complementary NFETs and PFETs. The number of NFETs and PFETs can be multiple, and the metal layers of the NFETs and PFETs are metal layers with different work functions.

[0113] Please refer to the description of the beneficial effects of the semiconductor structure 10 above. The embodiment of the present application can provide a complementary FET device or GAA device with body conduction, non-inversion electron layer, small tunneling effect, low gate leakage, low power consumption, higher electron or hole drift velocity, higher carrier migration efficiency, small characteristic size, and breaking through the current device size limit.

[0114] In an optional embodiment of the present application, the semiconductor device 20 includes:

[0115] A first semiconductor structure 23 and a second semiconductor structure 24 are stacked vertically on the surface of the substrate layer 21. The first semiconductor structure includes multiple semiconductor structures of a first conductivity type, and the second semiconductor structure includes multiple semiconductor structures of a second conductivity type. The first conductivity type and the second conductivity type are different. For example, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0116] As described in the above embodiments, through this structure, the embodiments of the present application can provide an N-type and P-type complementary semiconductor device with body conduction, non-inversion electron layer, small tunneling effect, low gate leakage, low power consumption, higher electron or hole drift velocity, higher carrier migration efficiency, small characteristic size, and breaking through the current device size limit.

[0117] In an optional embodiment of the present application, the semiconductor device 20 further includes:

[0118] An insulating layer 22 is disposed between the first semiconductor structure 23 and the second semiconductor structure 24 and extends through the gate region 200. The insulating layer 22 isolates the first semiconductor structure 23 from the second semiconductor structure 24, ensuring their relative independence and preventing mutual interference, thereby improving device stability and reliability.

[0119] It should be understood that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0120] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that At least: A gate structure region and a source region and a drain region respectively located on both sides of the gate structure region; wherein the gate structure region at least includes: The channel region and gate region are arranged from the inside out, the channel region covers the middle position of the gate region cavity, the gate region is distributed on both sides of the channel region in the vertical direction, the source region and the drain region are respectively located on both sides of the channel region in the horizontal direction, and the channel region is respectively attached to and connected to the source region, the drain region and the gate region; the drain region, the source region and the channel region are ion-doped with the same type, forming a homojunction device structure; the drain region, the source region and the channel region are manufactured as a whole; a dielectric layer, disposed between the gate region and the channel region, and respectively adhered to the gate region, the channel region, the drain region, and the source region, wherein the gate region is completely covered by the dielectric layer; A buffer barrier region is located between the channel region and the dielectric layer and is respectively aligned with the dielectric layer, the channel region, the drain region, and the source region; the ion doping concentration of the buffer barrier region is not greater than 1e17 / cm 3 , the ion doping concentration of the buffer barrier region is less than the ion doping concentration of the drain region and the source region.

2. The semiconductor structure according to claim 1, wherein: The ion doping concentration of the buffer barrier region is one order of magnitude lower than the ion doping concentration of the channel region.

3. The semiconductor structure according to claim 1, wherein: The thickness of the buffer barrier region is 0.3 to 5 nanometers.

4. The semiconductor structure according to claim 1, wherein: The ion doping concentration of the gate region is 1e16 / cm 3 ~1e20 / cm 3 ; and / or, the ion doping concentration of the channel region is 1e17 / cm 3 ~5e19 / cm 3 ; and / or, the ion doping concentration of the drain region and the source region is 1e18 / cm 3 ~5e20 / cm 3 .

5. The semiconductor structure according to claim 1, wherein: The ion doping concentrations of the drain region, the source region, and the channel region are equal.

6. The semiconductor structure according to claim 5, wherein: The ion doping concentration of the drain region, the source region, and the channel region is not less than 1e17 / cm 3 .

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure is an N-type device, and the gate region is a metal with a metal work function of 4.5eV-5.2eV; or, If the semiconductor structure is a P-type device, the gate region is a metal having a metal work function of 4.0 eV-4.5 eV.

8. The semiconductor structure according to claim 1, wherein: The semiconductor structure is a FinFET device or a GAA device.

9. A semiconductor device, characterized in that: include: The semiconductor structure according to any one of claims 1 to 7.

10. The semiconductor device according to claim 9, wherein There are multiple semiconductor structures; and the conductivity types of the multiple semiconductor structures are not completely the same.

11. The semiconductor device according to claim 9, wherein include: A first semiconductor structure and a second semiconductor structure are stacked vertically on the surface of a substrate layer, wherein the first semiconductor structure includes a plurality of semiconductor structures of a first conductivity type, and the second semiconductor structure includes a plurality of semiconductor structures of a second conductivity type; the first conductivity type is different from the second conductivity type.

12. The semiconductor device according to claim 11, wherein Also includes: The insulating layer is disposed between the first semiconductor structure and the second semiconductor structure, and the insulating layer passes through the gate region in the semiconductor structure.

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