Semiconductor structure and its fabrication method

Abstract

This disclosure relates to a semiconductor structure and its fabrication method. The structure includes: a substrate; a first contact layer disposed on the substrate; a conductive channel disposed on the first contact layer; a gate metal layer disposed around the conductive channel; a gate dielectric layer disposed between the gate metal layer and the conductive channel; an insulating layer disposed inside the conductive channel and in direct contact with the conductive channel; a second contact layer disposed on the insulating layer; and a work function layer located inside the insulating layer. This reduces the work function difference between the conductive channel and the gate metal layer, avoids boundary carrier accumulation between the conductive channel and the gate dielectric layer, helps reduce leakage current in the off-state of the semiconductor structure, improves the control capability of the gate metal layer over the conductive channel, and reduces the off-state current of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, integrated circuits are moving towards miniaturization, which requires higher integration density and smaller feature size. This means that as many semiconductor devices as possible should be placed on a smaller substrate to achieve higher performance.

[0003] However, the miniaturization of semiconductor devices has reached its limit, and further reduction in size is constrained by many factors. Furthermore, miniaturization may affect the performance of semiconductor devices. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a semiconductor structure, including:

[0006] Substrate;

[0007] A first contact layer is disposed on the substrate;

[0008] A conductive channel is disposed on the first contact layer;

[0009] A gate metal layer is disposed around the conductive channel;

[0010] A gate dielectric layer is disposed between the gate metal layer and the conductive channel;

[0011] An insulating layer is disposed on the inner side of the conductive channel and is in direct contact with the conductive channel;

[0012] A second contact layer is disposed on the insulating layer;

[0013] The work function layer is located inside the insulating layer.

[0014] Optionally, the work function layer includes a first work function layer and a second work function layer located inside the first work function layer, wherein the work function of the second work function layer is greater than the work function of the first work function layer.

[0015] Optionally, the outer wall and top surface of the first work function layer and the top surface of the second work function layer are in direct contact with the insulating layer.

[0016] Optionally, the surface of the work function layer is in contact with the insulating layer, and the work function layer is separated from the insulating layer, the conductive channel, and the second contact layer.

[0017] Optionally, the material of the work function layer may be selected from at least one of the following materials: conductive metal, conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal carbonitride, or conductive doped semiconductor material.

[0018] Optionally, the top surface of the insulating layer is not lower than the top surface of the gate metal layer, and the top surface of the insulating layer is lower than the top surface of the conductive channel.

[0019] Optionally, the insulating layer comprises:

[0020] The first insulating layer is in direct contact with the bottom wall and part of the side wall of the work function layer;

[0021] The second insulating layer is in direct contact with the top surface of the work function layer and another part of the sidewall, and the sidewall of the second insulating layer is in contact with the sidewall of the first insulating layer.

[0022] Secondly, this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0023] Provide substrate;

[0024] A first contact layer is formed on the substrate;

[0025] A gate metal layer is formed above the first contact layer, the gate metal layer being penetrated by a channel via which the channel exposes the first contact layer;

[0026] A gate dielectric layer is formed, the gate dielectric layer covering the sidewall of the channel hole;

[0027] A channel layer is deposited to form a conductive channel in the channel hole, the conductive channel directly contacting the gate dielectric layer and the first contact layer;

[0028] A first insulating layer is formed, which covers the bottom wall and at least part of the inner sidewall of the conductive channel;

[0029] A work function layer is formed, which covers the first insulating layer;

[0030] A second insulating layer is formed, and the second insulating layer is connected to the first insulating layer to form an insulating layer;

[0031] A second contact layer is formed on the insulating layer.

[0032] Optionally, a function layer is formed, including:

[0033] A first work function layer is deposited to form a first work function layer, which covers the first insulating layer;

[0034] A second work function layer is deposited to form a second work function layer, which covers the first work function layer and fills the space inside the conductive channel;

[0035] The first work function layer, the second work function layer, and the first insulating layer are etched back, and the remaining first work function layer and second work function layer together form the work function layer.

[0036] Optionally, after forming the second insulating layer, the second insulating layer is etched back to a preset height, and the etched and retained second insulating layer and the first insulating layer together form the insulating layer. The preset height is not lower than the top surface of the gate metal layer and the preset height is lower than the top surface of the conductive channel.

[0037] The sidewall of the second insulating layer is in contact with the sidewall of the first insulating layer.

[0038] The semiconductor structure and fabrication method disclosed herein can reduce the work function difference between the conductive channel and the gate metal layer by embedding a work function layer in the insulating layer inside the conductive channel, avoid the accumulation of boundary carriers between the conductive channel and the gate dielectric layer, reduce the leakage current of the semiconductor structure in the off-state, improve the control capability of the gate metal layer over the conductive channel, and reduce the off-state current of the semiconductor structure. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment.

[0041] Figure 2 This is a schematic diagram of a semiconductor structure provided in another embodiment.

[0042] Figure 3 This is a schematic diagram of a semiconductor structure provided in another embodiment.

[0043] Figure 4 This is a schematic diagram of a semiconductor structure provided in another embodiment.

[0044] Figure 5 This is a process flow diagram of a method for fabricating a semiconductor structure provided in one embodiment.

[0045] Figure 6 This is a schematic diagram of the structure after the first contact layer, gate metal layer, channel via and gate dielectric layer are formed on the substrate in one embodiment.

[0046] Figure 7 This is a schematic diagram of the structure after the channel layer is formed in one embodiment.

[0047] Figure 8 This is a schematic diagram of the structure after the first insulating layer is formed in one embodiment.

[0048] Figure 9 This is a schematic diagram of the structure after the first work function layer is formed in one embodiment.

[0049] Figure 10 This is a schematic diagram of the structure after the second work function layer is formed in one embodiment.

[0050] Figure 11 This is a schematic diagram of the structure after the first work function layer, the second work function layer, and the first insulating layer are etched back in one embodiment, and the remaining first work function layer and second work function layer together form the work function layer.

[0051] Figure 12 This is a schematic diagram of the structure after the second insulating layer is formed in one embodiment.

[0052] Figure 13 This is a schematic diagram of the structure after the second insulating layer is etched back to a preset height in one embodiment, and the etched and retained second insulating layer and the first insulating layer together form an insulating layer.

[0053] Figure 14 This is a schematic diagram of the structure after the second contact material layer is formed in one embodiment.

[0054] Figure 15 This is a schematic diagram of the structure after the second contact layer is formed in one embodiment.

[0055] Figure 16 This is a schematic diagram of the structure after the second electrode is formed on the second contact layer in one embodiment.

[0056] Figure label:

[0057] 10. Substrate; 20. First contact layer; 30. Conductive channel; 30a. Channel layer; 40. Second contact layer; 50. Gate metal layer; 51. Gate dielectric layer; 60. Insulating layer; 160. First insulating layer; 260. Second insulating layer; 70. Work function layer; 70. Work function layer; 170. First work function layer; 270. Second work function layer; 80. Channel via; 91. Dielectric layer; 92. First conductor; 921. First diffusion barrier layer; 922. First conductive layer; 923. Second diffusion barrier layer; 93. Interlayer dielectric layer; 94. Isolation layer; 941. First isolation layer; 942. Second isolation layer; 95. Second electrode; 951. Third diffusion barrier layer; 952. Second conductive layer; 953. Fourth diffusion barrier layer; 96. Metal plug. Detailed Implementation

[0058] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0060] According to an exemplary embodiment, this exemplary embodiment provides a semiconductor structure, which can be a memory chip. (Refer to...) Figure 1 , Figure 2 , Figure 3 , Figure 4 The semiconductor structure includes: a substrate 10, a first contact layer 20, a conductive channel 30, a gate metal layer 50, a gate dielectric layer 51, an insulating layer 60, a second contact layer 40, and a work function layer 70; the first contact layer 20 is disposed on the substrate 10; the conductive channel 30 is disposed on the first contact layer 20; the gate metal layer 50 is disposed around the conductive channel 30; the gate dielectric layer 51 is disposed between the gate metal layer 50 and the conductive channel 30; the insulating layer 60 is disposed inside the conductive channel and is in direct contact with the conductive channel 30; the second contact layer 40 is disposed on the insulating layer 60; and the work function layer 70 is located inside the insulating layer 60.

[0061] In this embodiment, a dielectric layer 91 is also formed on the substrate 10. The dielectric layer 91 can be a stacked structure composed of different material layers, such as a stacked structure composed of an oxide layer and a nitride layer, or it can be a single material layer, such as an oxide layer or a nitride layer, and is not limited thereto.

[0062] Furthermore, a first conductive line 92 is also disposed on the substrate 10. The first conductive line 92 extends on the dielectric layer 91, and the bottom of the first conductive line 92 penetrates the dielectric layer 91 and is electrically connected to the substrate 10 through a metal plug 96. The first conductive line 92 includes a first diffusion barrier layer 921, a first conductive layer 922, and a second diffusion barrier layer 923 stacked sequentially. The materials of the first diffusion barrier layer 921 and the second diffusion barrier layer 923 both include titanium nitride, and the material of the first conductive layer 922 includes tungsten.

[0063] The first contact layer 20 is disposed on and in contact with the first conductor 92. The material of the first contact layer 20 may include polysilicon.

[0064] An interlayer dielectric layer 93 is further disposed on the first contact layer 20, and the material of the interlayer dielectric layer 93 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0065] The gate metal layer 50 is disposed on the interlayer dielectric layer 93 and located above the first contact layer 20. The material of the gate metal layer 50 may include tungsten.

[0066] Furthermore, the semiconductor structure also includes an isolation layer 94, which is filled between the gate metal layers 50 and the conductive channels 30 to isolate adjacent gate metal layers 50 and conductive channels 30 and prevent adjacent devices from short-circuiting.

[0067] Furthermore, the isolation layer 94 includes a first isolation layer 941 filled between the gate metal layers 50 and a second isolation layer 942 filled between the conductive channels 30. The material of the first isolation layer 941 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide, and the material of the second isolation layer 942 includes at least one of silicon nitride, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0068] The first isolation layer 941 and the second isolation layer 942 may include the same material or different materials; this embodiment does not limit this. In one example, the first isolation layer 941 and the second isolation layer 942 are made of the same material, both including silicon oxide. In another example, the first isolation layer 941 is made of silicon oxide, and the second isolation layer 942 is made of silicon carbide.

[0069] The via 80 penetrates the second isolation layer 942, the gate metal layer 50, and the interlayer dielectric layer 93, exposing a portion of the top surface of the first contact layer 20. A gate dielectric layer 51 is disposed within the via 80, covering the sidewalls of the via 80. The material of the gate dielectric layer 51 may include silicon oxide.

[0070] A conductive channel 30 is disposed in the channel via 80. The projection of the conductive channel 30 onto a plane perpendicular to the substrate 10 is U-shaped, with the opening of the U-shape facing away from the substrate 10. The conductive channel 30 covers the gate dielectric layer 51 and the first contact layer 20, and is in contact with the first contact layer 20. The conductive channel 30 is separated from the gate metal layer 50 by the gate dielectric layer 51. The material of the conductive channel 30 may include doped polysilicon.

[0071] An insulating layer 60 is disposed in the conductive channel 30 and is in contact with the conductive channel 30. The material of the insulating layer 60 may include silicon oxide.

[0072] The work function layer 70 is embedded in the insulating layer 60 and is separated from the conductive channel 30 by the insulating layer 60. The material of the work function layer 70 can be selected from any material or combination thereof with a work function greater than that of the conductive channel 30. The work function layer 70 can be a single-layer structure or a multi-layer structure; this embodiment does not impose any restrictions on this.

[0073] In one example, refer to Figure 1 The work function layer 70 is a single-layer structure. In another example, refer to... Figure 2 The work function layer 70 has a two-layer structure. In another example, refer to... Figure 4 The work function layer 70 has a three-layer structure.

[0074] The second contact layer 40 is disposed on the insulating layer 60, and the second contact layer 40 is connected to the top of the conductive channel 30 and connected to the first contact layer 20 through the conductive channel 30. The material of the second contact layer 40 may include polycrystalline silicon.

[0075] Furthermore, a second electrode 95 is provided on the second contact layer 40, and the second electrode 95 is connected to the second contact layer 40. The second electrode 95 includes a third diffusion barrier layer 951, a second conductive layer 952 and a fourth diffusion barrier layer 953 stacked sequentially. The materials of the third diffusion barrier layer 951 and the fourth diffusion barrier layer 953 are both titanium nitride, and the material of the second conductive layer 952 is tungsten.

[0076] In this embodiment, the semiconductor structure, by embedding a work function layer 70 in the insulating layer 60 inside the conductive channel 30, can reduce the work function difference between the conductive channel 30 and the gate metal layer 50, avoid the accumulation of boundary carriers between the conductive channel 30 and the gate dielectric layer 51, which is beneficial to reduce the leakage current of the semiconductor structure in the off-state state, improve the control capability of the gate metal layer 50 over the conductive channel 30, and reduce the off-state current of the semiconductor structure.

[0077] In one embodiment, refer to Figures 1-4The material of the work function layer 70 may be selected from at least one of the following materials: conductive metal, conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal carbonitride, or conductively doped semiconductor materials.

[0078] In one example, the material of the work function layer 70 may be selected from at least one of the following materials: titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt), ruthenium (Ru), metal silicide, metal nitride, and metal carbide.

[0079] In other examples, the material of the work function layer 70 may be selected from conductively doped semiconductor materials, such as conductively doped silicon, conductively doped polysilicon, or conductively doped germanium.

[0080] In yet another example, the material of the work function layer 70 may include a stack of conductive metals, conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal carbonitrides, and conductive doped semiconductor materials.

[0081] In some embodiments, refer to Figure 2 , Figure 3 The work function layer 70 includes a first work function layer 170 and a second work function layer 270 located inside the first work function layer 170. The work function of the second work function layer 270 is greater than that of the first work function layer 170. Thus, from the conductive channel 30 towards the work function layer 70, the work functions of the conductive channel 30, the first work function layer 170, and the second work function layer 270 increase sequentially. When the semiconductor structure is in the off-state, the energy band of the conductive channel 30 bends more towards the work function layer 70, further preventing carrier accumulation at the boundary between the conductive channel 30 and the gate dielectric layer 51, reducing the leakage current of the semiconductor structure in the off-state, improving the control capability of the gate metal layer 50 over the conductive channel 30, and reducing the off-state current of the semiconductor structure.

[0082] For example, the first work function layer 170 is a tungsten layer, and the second work function layer 270 is a titanium nitride layer. Alternatively, the first work function layer 170 is a tungsten silicide layer, and the second work function layer 270 is a titanium nitride layer. Alternatively, the first work function layer 170 is a silicon tungsten nitride layer, and the second work function layer 270 is a tungsten nitride layer. Alternatively, the first work function layer 170 is a conductive doped silicon layer, and the second work function layer 270 is a conductive doped silicon layer, wherein the doping concentration of conductive ions in the second work function layer 270 is greater than the doping concentration of conductive ions in the first work function layer 170.

[0083] Furthermore, refer to Figure 2 , Figure 3 The outer sidewall and top surface of the first work function layer 170, and the top surface of the second work function layer 270, are in direct contact with the insulating layer 60. Thus, the first work function layer 170 and the second work function layer 270 are separated from the conductive channel 30 and the second contact layer 40 by the insulating layer 60, ensuring that the insulating layer 60 has good electrical isolation, preventing short circuits between the second contact layer 40 and the first contact layer 20, and ensuring good electrical performance of the semiconductor structure.

[0084] In one example, refer to Figure 2 The top surface height of the second work function layer 270 is higher than the top surface height of the first work function layer 170, and the top surfaces of the first work function layer 170 and the second work function layer 270 are connected to form a convex surface that protrudes away from the substrate 10. In another example, refer to... Figure 3 The top surface height of the first work function layer 170 is the same as the top surface height of the second work function layer 270, and the top surface of the work function layer 70 is a plane.

[0085] In some embodiments, refer to Figure 2 , Figure 3 The surface of the work function layer 70 is in contact with the insulating layer 60, and the work function layer 70 is separated from the conductive channel 30 and the second contact layer 40 by the insulating layer 60. That is, regardless of whether the work function layer 70 is a single-layer structure or a multi-layer structure, the work function layer 70 is embedded in the insulating layer 60 to avoid short circuit between the second contact layer 40 and the first contact layer 20.

[0086] In some embodiments, the top surface of the insulating layer 60 is not lower than the top surface of the gate metal layer 50, and the top surface of the insulating layer 60 is lower than the top surface of the conductive channel 30. This helps to reduce the parasitic capacitance of the semiconductor structure and improve the response speed of the semiconductor structure.

[0087] In some embodiments, refer to Figure 2 , Figure 3The insulating layer 60 includes a first insulating layer 160 and a second insulating layer 260. The first insulating layer 160 is in direct contact with the bottom wall and part of the sidewalls of the work function layer 70, and the second insulating layer 260 is in direct contact with the top surface and another part of the sidewalls of the work function layer 70. The sidewalls of the second insulating layer 260 are in contact with the sidewalls of the first insulating layer 160. In this way, the outer surface of the work function layer 70 is completely covered by the insulating layer 60, preventing the work function layer 70 from contacting the second contact layer 40 and ensuring that the semiconductor structure has good electrical performance.

[0088] The material of the first insulating layer 160 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide; the material of the second insulating layer 260 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. The material of the first insulating layer 160 may be the same as or different from the material of the second insulating layer 260.

[0089] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments. Figure 5 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown, such as... Figure 5 The present disclosure provides a method for fabricating a semiconductor structure according to an exemplary embodiment, comprising the following steps:

[0090] Step S10: Provide a substrate.

[0091] Step S20: Form a first contact layer on the substrate.

[0092] Step S30: A gate metal layer is formed above the first contact layer, the gate metal layer is penetrated by a channel hole, and the channel hole exposes the first contact layer.

[0093] Step S40: Form a gate dielectric layer that covers the sidewalls of the channel via.

[0094] Step S50: Deposit a channel layer to form a conductive channel in the channel hole, the conductive channel directly contacting the gate dielectric layer and the first contact layer.

[0095] Step S60: Form a first insulating layer that covers the bottom wall and at least part of the inner sidewall of the conductive channel.

[0096] Step S70: Form a power function layer, which covers the first insulating layer.

[0097] Step S80: Form a second insulating layer, which is connected to the first insulating layer to form an insulating layer.

[0098] Step S90: Form a second contact layer on the insulating layer.

[0099] The semiconductor structure fabrication method of this embodiment forms a work function layer inside the insulating layer inside the conductive channel, which can reduce the work function difference between the conductive channel and the gate metal layer, avoid the accumulation of boundary carriers between the conductive channel and the gate dielectric layer, help reduce the leakage current of the semiconductor structure in the off-state, improve the control capability of the gate metal layer over the conductive channel, and reduce the off-state current of the semiconductor structure.

[0100] The following is combined Figures 6-16 The process of fabricating semiconductor structures is explained in detail, including... Figures 6-16 This is a schematic diagram of the semiconductor structure in the fabrication process of an embodiment of the present invention.

[0101] In step S10, refer to Figure 6 The substrate 10 provided may be a semiconductor substrate. A dielectric layer 91 is formed on the substrate 10, and the material of the dielectric layer 91 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0102] In step S20, before forming the first contact layer 20 on the substrate 10, the method further includes forming a first conductive line 92 on the substrate 10. In this embodiment, forming the first conductive line 92 and the first contact layer 20 on the substrate 10 may specifically include the following steps.

[0103] Reference Figure 6 A first diffusion barrier layer 921, a first conductive layer 922, a second diffusion barrier layer 923, and a first contact layer 20 are sequentially deposited on the dielectric layer 91 using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes.

[0104] Etching removes a portion of the first diffusion barrier layer 921, the first conductive layer 922, the second diffusion barrier layer 923, and the first contact layer 20 on the dielectric layer 91, leaving the remaining first diffusion barrier layer 921, the first conductive layer 922, the second diffusion barrier layer 923, and together they form the first conductive wire 92. The remaining first contact layer 20 covers the first conductive wire 92.

[0105] The first diffusion barrier layer 921 and the second diffusion barrier layer 923 are both made of titanium nitride, and the first conductive layer 922 is made of tungsten. The first contact layer 20 is made of doped polycrystalline silicon.

[0106] In step S30, in this embodiment, a gate metal layer is formed above the first contact layer, and the gate metal layer is penetrated by a channel hole, which exposes the first contact layer. Specifically, the steps may include the following.

[0107] First, refer to Figure 6A first isolation layer 941 is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The first isolation layer 941 fills the spaces between and covers the first contact layers 20. The material of the first isolation layer 941 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0108] Then, refer to Figure 6 The first isolation layer 941 is etched to form a gate trench (not shown in the figure). A gate metal layer 50 is deposited in the gate trench using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The material of the gate metal layer 50 may include tungsten.

[0109] Next, refer to Figure 6 A second isolation layer 942 covering the first isolation layer 941 and the gate metal layer 50 is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The material of the second isolation layer 942 includes at least one of silicon nitride, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0110] Next, refer to Figure 6 The second isolation layer 942, the gate metal layer 50 and the interlayer dielectric layer 93 are etched layer by layer to form a channel hole 80 that penetrates the gate metal layer 50. The channel hole 80 exposes part of the top surface of the first contact layer 20 and is higher than the gate metal layer 50.

[0111] In step S40, refer to Figure 6 A gate dielectric layer 51 is deposited into the channel via 80 using atomic layer deposition (ALD). Then, the gate dielectric layer 51 covering the first contact layer 20 is etched away, and the remaining gate dielectric layer 51 covers the sidewall of the channel via 80.

[0112] In step S50, refer to Figure 7 A channel layer 30a is deposited using atomic layer deposition (ALD) technology. The channel layer 30a covers the top surface of the gate dielectric layer 51, the exposed first contact layer 20, and the second isolation layer 942. The channel layer 30a located within the channel via 80 forms a conductive channel 30, which contacts the gate dielectric layer 51 and the first contact layer 20. The material of the conductive channel 30 may include doped polysilicon.

[0113] In step S60, refer to Figure 8 A first insulating layer 160 is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process, and the first insulating layer 160 covers the conductive channel 30. The material of the first insulating layer 160 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0114] Specifically, forming the first insulating layer 160 also includes the step of etching the first insulating layer 160 back into the channel hole 80, which can be etched back together with the work function layer 70 in subsequent steps.

[0115] In step S70, in this embodiment, a power function layer is formed, which covers the first insulating layer. Specifically, the steps may include the following.

[0116] First, refer to Figure 9 , Figure 10 A work function layer 70 is deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. The work function layer 70 covers the first insulating layer 160 and fills the channel holes 80.

[0117] Then, refer to Figure 11 The common back-etched work function layer 70 and the first insulating layer 160 are then inserted into the channel hole 80.

[0118] After the etch is reversed, the top surfaces of the work function layer 70 and the first insulating layer 160 are flush; or, after the etch is reversed, the heights of the work function layer 70 and the first insulating layer 160 are different, with the top surface height of the work function layer 70 being higher than the top surface height of the first insulating layer 160.

[0119] The material of the work function layer 70 may be selected from at least one of the following materials: conductive metal, conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal carbonitride, or conductively doped semiconductor materials.

[0120] In one example, the material of the work function layer 70 may be selected from at least one of the following materials: titanium (Ti), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt), ruthenium (Ru), metal silicide, metal nitride, and metal carbide.

[0121] In other examples, the material of the work function layer 70 may be selected from conductively doped semiconductor materials, such as conductively doped silicon, conductively doped polysilicon, or conductively doped germanium.

[0122] In yet another example, the material of the work function layer 70 may include a stack of conductive metals, conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal carbonitrides, and conductive doped semiconductor materials.

[0123] In step S80, refer to Figure 12 A second insulating layer 260 is deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD). The second insulating layer 260 covers the top surface of the first insulating layer 160 and the top surface of the work function layer 70 and fills the channel holes 80.

[0124] The material of the second insulating layer 260 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. The material of the first insulating layer 260 may be the same as or different from the material of the second insulating layer 260, and this embodiment does not impose any restrictions on this.

[0125] In some embodiments, after the second insulating layer 260 is formed in step S80, refer to Figure 13 The second insulating layer 260 is etched back to a predetermined height. The etched-retained second insulating layer 260 and the first insulating layer 160 together form an insulating layer 60. The predetermined height is not lower than the top surface of the gate metal layer 50 and is lower than the top surface of the conductive channel 30. The sidewalls of the second insulating layer 260 and the sidewalls of the first insulating layer 160 are in contact connection. In this way, the insulating layer 60 has a good electrical isolation effect, which helps to reduce the parasitic capacitance of the semiconductor structure and improve the response speed of the semiconductor structure.

[0126] In step S90, in this embodiment, a second contact layer is formed on the insulating layer, which may specifically include the following steps.

[0127] Reference Figure 14 The second contact layer 40 is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The second contact layer 40 covers the top surface of the second insulating layer 260 and fills the unfilled area inside the conductive channel 30.

[0128] Reference Figure 15 The second contact layer 40 deposited on the outside of the conductive channel 30 is removed by etching, leaving the second contact layer 40 located on the inside of the conductive channel 30. The insulating layer 60 and the remaining second contact layer 40 are arranged sequentially in the conductive channel 30 in a direction away from the substrate 10.

[0129] Furthermore, after forming the second contact layer 40, refer to Figure 16 It also includes: forming a second electrode 95 on the second contact layer 40, and the second electrode 95 being connected to the second contact layer 40. The second electrode 95 includes a third diffusion barrier layer 951, a second conductive layer 925 and a fourth diffusion barrier layer 953 stacked sequentially. The materials of the third diffusion barrier layer 951 and the fourth diffusion barrier layer 953 both include titanium nitride, and the material of the second conductive layer 952 includes tungsten.

[0130] In some embodiments, after the second contact layer 40 is formed, refer to Figure 15The channel layer 30a located on the top surface of the second isolation layer 942 is etched away, leaving only the channel layer 30a located in the channel hole 80 as the conductive channel 30.

[0131] In some other embodiments, the trench layer 30a may be etched off the top surface of the second isolation layer 942 after the trench layer 30a has been formed.

[0132] In some embodiments, step S70, forming the function layer, includes:

[0133] Step S71: Deposit to form a first work function layer, the first work function layer covering the first insulating layer.

[0134] Step S72: Deposit to form a second work function layer, which covers the first work function layer and fills the space inside the conductive channel.

[0135] Step S73: Etch back the first work function layer, the second work function layer, and the first insulating layer. The remaining first work function layer and the second work function layer together form the work function layer.

[0136] Reference Figure 9 A first work function layer 170 is deposited using atomic layer deposition (ALD) to cover the first insulating layer 160. Then, referring to... Figure 10 A second work function layer 270 is deposited to cover the first work function layer 170 and fill the channel holes 80 using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes.

[0137] In this configuration, the work function of the second work function layer 270 is greater than that of the first work function layer 170. For example, the first work function layer 170 is a tungsten layer, and the second work function layer 270 is a titanium nitride layer. Alternatively, the first work function layer 170 is a tungsten silicide layer, and the second work function layer 270 is a titanium nitride layer. Alternatively, the first work function layer 170 is a tungsten silicon nitride layer, and the second work function layer 270 is a tungsten nitride layer. Alternatively, the first work function layer 170 is a conductive doped silicon layer, and the second work function layer 270 is a conductive doped silicon layer, where the doping concentration of conductive ions in the second work function layer 270 is greater than that in the first work function layer 170.

[0138] Thus, the work function layer 70 includes a first work function layer 170 and a second work function layer 270 located inside the first work function layer 170. From the conductive channel 30 to the work function 70, the work functions of the conductive channel 30, the first work function layer 170, and the second work function layer 270 increase sequentially. When the semiconductor structure is in the off state, the energy band of the conductive channel 30 bends more towards the work function 70, further avoiding the accumulation of charge carriers at the boundary between the conductive channel 30 and the gate dielectric layer 51, reducing the leakage current of the semiconductor structure in the off state, improving the control capability of the gate metal layer 50 over the conductive channel 30, and reducing the off-state current of the semiconductor structure.

[0139] In some embodiments, in step S73, referencing Figure 3 In the step of re-etching the first work function layer 170, the second work function layer 270, and the first insulating layer 160, the etching rates of the first work function layer 170, the second work function layer 270, and the first insulating layer 160 are the same, and the top surfaces of the first work function layer 170, the second work function layer 270, and the first insulating layer 160 are flush after re-etching.

[0140] In some embodiments, in step S73, referencing Figure 11 In the step of etching back the first work function layer 170, the second work function layer 270, and the first insulating layer 160, the etching rate of the second work function layer 270 is less than the etching rate of the first work function layer 170, which is less than the etching rate of the first insulating layer 160. After etching back, the top surface of the second work function layer 270 is higher than the top surface of the first work function layer 170, which is higher than the top surface of the first insulating layer 160. The top surface of the first work function layer 170 and the top surface of the second work function layer 270 are connected to form a convex surface that protrudes in a direction away from the substrate 10.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first contact layer is disposed on the substrate; A conductive channel is disposed on the first contact layer; A gate metal layer is disposed around the conductive channel; A gate dielectric layer is disposed between the gate metal layer and the conductive channel; An insulating layer is disposed on the inner side of the conductive channel and is in direct contact with the conductive channel; A second contact layer is disposed on the insulating layer; The work function layer is located inside the insulating layer.

2. The semiconductor structure according to claim 1, characterized in that, The work function layer includes a first work function layer and a second work function layer located inside the first work function layer, wherein the work function of the second work function layer is greater than the work function of the first work function layer.

3. The semiconductor structure according to claim 2, characterized in that, The outer wall and top surface of the first work function layer and the top surface of the second work function layer are in direct contact with the insulating layer.

4. The semiconductor structure according to claim 1, characterized in that, The surface of the work function layer is in contact with the insulating layer, and the work function layer is separated from the conductive channel and the second contact layer by the insulating layer.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The material of the work function layer is selected from at least one of the following materials: conductive metal, conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal carbonitride, or conductive doped semiconductor material.

6. The semiconductor structure according to any one of claims 1-4, characterized in that, The top surface of the insulating layer is not lower than the top surface of the gate metal layer, and the top surface of the insulating layer is lower than the top surface of the conductive channel.

7. The semiconductor structure according to any one of claims 1-4, characterized in that, The insulating layer includes: The first insulating layer is in direct contact with the bottom wall and part of the side wall of the work function layer; The second insulating layer is in direct contact with the top surface of the work function layer and another part of the sidewall, and the sidewall of the second insulating layer is in contact with the sidewall of the first insulating layer.

8. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first contact layer is formed on the substrate; A gate metal layer is formed above the first contact layer, the gate metal layer being penetrated by a channel via which the channel exposes the first contact layer; A gate dielectric layer is formed, the gate dielectric layer covering the sidewall of the channel hole; A channel layer is deposited to form a conductive channel in the channel hole, the conductive channel directly contacting the gate dielectric layer and the first contact layer; A first insulating layer is formed, which covers the bottom wall and at least part of the inner sidewall of the conductive channel; A work function layer is formed, which covers the first insulating layer; A second insulating layer is formed, and the second insulating layer is connected to the first insulating layer to form an insulating layer; A second contact layer is formed on the insulating layer.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Form a function layer, including: A first work function layer is deposited to form a first work function layer, which covers the first insulating layer; A second work function layer is deposited to form a second work function layer, which covers the first work function layer and fills the space inside the conductive channel; The first work function layer, the second work function layer, and the first insulating layer are etched back, and the remaining first work function layer and second work function layer together form the work function layer.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, After the second insulating layer is formed, the second insulating layer is etched back to a preset height. The etched and retained second insulating layer and the first insulating layer together form the insulating layer. The preset height is not lower than the top surface of the gate metal layer and the preset height is lower than the top surface of the conductive channel. The sidewall of the second insulating layer is in contact with the sidewall of the first insulating layer.

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