A PIN diode and its manufacturing method

Abstract

The present application discloses a PIN diode and a preparation method thereof, relating to the technical field of semiconductor devices. The PIN diode of the present application includes a substrate, a P-type structure, and a drift layer disposed on the substrate. Among them, the P-type structure is embedded in the top of the drift layer. The P-type structure includes a P layer and a junction diffusion region surrounding the periphery of the P layer. The P layer includes a P well layer and a P heavily doped layer sequentially disposed on the drift layer. The doping concentration of the junction diffusion region is less than that of the P heavily doped layer. The PIN diode and the preparation method thereof provided by the present application can improve the breakdown voltage of the PIN device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a PIN diode and a method for manufacturing the same. Background Art

[0002] A PIN diode (Positive-Intrinsic-Negative Diode) is a special semiconductor device, and its name comes from its internal structure, that is, it consists of three layers of P-type semiconductor, I-type (Intrinsic, that is, intrinsic semiconductor) and N-type semiconductor. There is a layer of lightly doped intrinsic semiconductor region sandwiched between the P-type and N-type semiconductors. The resistivity of this region is relatively high and the carrier concentration is low. As a commonly used voltage-resistant device, PIN diodes are currently widely used in power electronic circuits.

[0003] However, the existing PIN diodes are fabricated using a planar process, that is, deposited layer by layer and impurity diffusion is performed at the required positions. Due to the anisotropy of impurity diffusion, impurities will diffuse laterally while diffusing longitudinally in the semiconductor. For example, the lateral expansion of impurities in the silicon layer is about 85% of the longitudinal diffusion, which will make the curvature at the edge and apex of the diffusion window larger, causing the edge of the PN junction to bend. When the PIN diode is in use, at the location with a large curvature, the local electric field is too concentrated and it is easy to break down prematurely here, thus reducing the breakdown voltage of the PIN diode. Summary of the Invention

[0004] The purpose of the present application is to provide a PIN diode and a method for manufacturing the same, which can improve the breakdown voltage of the PIN device.

[0005] An embodiment of the present application provides a PIN diode, including a substrate, a P-type structure, and a drift layer disposed on the substrate. The P-type structure is embedded in the top of the drift layer. The P-type structure includes a P layer and a junction diffusion region surrounding the periphery of the P layer. The P layer includes a P well layer and a P heavily doped layer disposed on the drift layer in sequence. The doping concentration of the junction diffusion region is less than that of the P heavily doped layer.

[0006] As an implementable manner, the junction diffusion region includes a plurality of regions arranged in sequence outward along the P layer, and along the outward direction of the P layer, the doping concentrations of the plurality of junction diffusion regions gradually decrease.

[0007] As an implementable manner, the junction diffusion region includes two regions arranged in sequence outward along the P layer. Along the outward direction of the P layer, the two junction diffusion regions are the first junction diffusion region and the second junction diffusion region respectively.

[0008] As an implementable manner, the doping concentration of the first junction diffusion region is 6*e 13 -5*e17 Between them, the doping concentration of the second junction diffusion region is between 6*e 13 -5*e 15 .

[0009] As an implementable way, an induced defect is formed on the side of the P-well layer close to the P heavily doped layer to form a recombination center layer on the upper surface of the P-well layer.

[0010] As an implementable way, proton irradiation is used to form induced defects on one side of the P-well layer.

[0011] As an implementable way, the depth that the P layer extends into the drift layer is less than the depth that the junction diffusion region extends into the drift layer. Along the direction outward from the P layer, the depths that multiple junction diffusion regions extend into the drift layer gradually increase.

[0012] As an implementable way, along the hierarchical direction upward, the doping concentration of the junction diffusion region gradually increases.

[0013] As an implementable way, along the direction outward from the P layer, the ring widths of multiple junction diffusion regions gradually increase.

[0014] On the other hand, an embodiment of the present application provides a method for manufacturing a PIN diode for manufacturing the above PIN diode, including: providing a substrate and forming a drift layer on the substrate; doping the drift layer from one side of the substrate to form an N-type heavily doped layer; doping the drift layer from the side of the drift layer away from the substrate to form a P-well; heavily doping the surface of the P-well to form a P heavily doped layer, wherein the undoped part of the P-well forms a P-well layer; doping the drift layer outside the periphery of the P-well to form a junction diffusion region, and the doping concentration of the junction diffusion region is less than the doping concentration of the P heavily doped layer.

[0015] The beneficial effects of the embodiments of the present application include:

[0016] The PIN diode provided by the present application includes a substrate, a P-type structure, and a drift layer disposed on the substrate. Among them, the P-type structure is embedded at the top of the drift layer. The substrate is N-type heavily doped and serves as the n layer, and the drift layer is lightly doped and serves as the I layer. The P-type structure includes a P layer and a junction diffusion region surrounding the periphery of the P layer. The P layer includes a P well layer and a P-type heavily doped layer sequentially disposed on the drift layer, serving as the P layer, thus forming a PIN diode. Among them, the doping concentration of the junction diffusion region is less than that of the P-type heavily doped layer. The junction diffusion region is located on the periphery of the P layer and is in contact with the P layer. The P layer is formed by impurity diffusion in the drift layer. When the PIN diode is in the reverse bias state, the junction diffusion region is located between the P layer and the I layer. The reverse electric field depletes all the holes in the junction diffusion region, leaving immovable negative charges, which is equivalent to introducing negative charges into the space charge region of the drift layer. These negative charges cause the space charge region near the PI junction to expand outward, thereby reducing the curvature of the edge of the PI junction, reducing the electric field at the edge of the PI junction, and increasing the breakdown voltage of the PIN diode. Description of the Drawings

[0017] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 One of the structural schematic diagrams of a PIN diode provided by an embodiment of the present application;

[0019] Figure 2 Another structural schematic diagram of a PIN diode provided by an embodiment of the present application;

[0020] Figure 3 Another structural schematic diagram of a PIN diode provided by an embodiment of the present application;

[0021] Figure 4 A performance comparison diagram of a PIN diode provided by an embodiment of the present application and a PIN diode in the prior art;

[0022] Figure 5 A flowchart of a preparation method of a PIN diode provided by an embodiment of the present application;

[0023] Figure 6 One of the state diagrams of a PIN diode provided by an embodiment of the present application;

[0024] Figure 7 Another state diagram of a PIN diode provided by an embodiment of the present application;

[0025] Figure 8 This is the third state diagram of a PIN diode provided by an embodiment of the present application;

[0026] Figure 9 This is the fourth state diagram of a PIN diode provided by an embodiment of the present application;

[0027] Figure 10 This is the fifth state diagram of a PIN diode provided by an embodiment of the present application.

[0028] Icons: 100 - PIN diode; 110 - substrate; 120 - P-type structure; 121 - P layer; 122 - P well layer; 123 - P heavily doped layer; 124 - junction diffusion region; 125 - first junction diffusion region; 126 - second junction diffusion region; 127 - recombination center layer; 130 - drift layer; 141 - cathode electrode; 142 - anode electrode; 151 - passivation layer; 161 - buffer layer; 162 - N-type heavily doped layer; 163 - P well. Detailed implementation manners

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0031] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0032] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "center", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, terms such as "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0033] The PIN diode is different from the ordinary P-N junction diode. In the PIN diode, an intrinsic layer (lightly doped layer) is added between the P+ and N+ at both ends, and the whole structure is divided into three parts: the P+ region, the intrinsic region (i-region), and the N+ region. Like the P-N junction diode, both electrons and holes in the PIN diode participate in transport and it belongs to a bipolar device. In the prior art, the P+ region is usually formed by diffusing impurity ions in the drift layer. During the diffusion process, due to the anisotropy of impurity diffusion, the curvature at the edge and apex of the diffusion window is too large, so that the electric field at the edge and apex of the PIN diode is too concentrated, and the PIN diode is prone to premature breakdown at this place.

[0034] An embodiment of the present application provides a PIN diode 100, as Figure 1 shown, which includes a substrate 110, a P-type structure 120, and a drift layer 130 disposed on the substrate 110. Among them, the P-type structure 120 is embedded in the top of the drift layer 130. The P-type structure 120 includes a P layer 121 and a junction diffusion region 124 disposed around the outer periphery of the P layer 121. The P layer 121 includes a P well layer 122 and a P heavily doped layer 123 disposed in sequence on the drift layer 130. The doping concentration of the junction diffusion region 124 is less than the doping concentration of the P heavily doped layer 123.

[0035] In the PIN diode 100 provided by the embodiment of the present application, the substrate 110 is N+, the drift layer 130 serves as the I layer, and the P layer 121 serves as the P+ to form the PIN diode 100. When the PIN diode 100 is in the forward bias state, that is, the P layer 121 is connected to the positive voltage and the substrate 110 is connected to the negative voltage, the current starts to flow. In this case, the current flowing from the P end to the N end is mainly composed of carriers (holes and electrons).

[0036] When the PIN diode 100 is in the reverse bias state, that is, the P layer 121 is connected to the negative voltage and the substrate 110 is connected to the positive voltage, a reverse electric field is formed. The reverse electric field strengthens the built-in electric field within the PIN device, that is, the space charge region at the I-N becomes wider, such that electrons and holes need to overcome a larger space charge region when moving in the I layer under reverse bias. At the same time, all the holes in the junction diffusion region 124 are depleted, leaving immobile negative charges, which is equivalent to introducing negative charges into the space charge region of the drift layer 130. These negative charges cause the space charge region near the PI junction to expand outward, thereby reducing the curvature of the edge of the PI junction, and thus reducing the electric field at the edge of the PI junction. Therefore, the setting of the junction diffusion region 124 in the embodiments of the present application causes the electric field lines concentrated at the edge of the PI junction to terminate within the junction diffusion region 124, alleviating the electric field concentration at the edge of the PI junction, thereby reducing the electric field peak value and increasing the breakdown voltage of the PIN diode 100.

[0037] It can be understood that when the PIN diode 100 is forward biased or reverse biased, a voltage needs to be applied between the substrate 110 and the P layer 121. Therefore, in practical applications, electrodes are respectively provided on the outer sides of the substrate 110 and the P layer 121. Specifically, as Figure 1 and Figure 2 shown, a positive electrode 142 is provided on the outer side of the P layer 121, and a negative electrode 141 is provided on the outer side of the substrate 110. Additionally, in order to isolate the P layer 121 and the drift layer 130 from the external environment and prevent ions or water vapor in the external environment from affecting their performance, as Figure 1 shown, a passivation layer 151 is provided on the end face of the PIN diode 100, and the positive electrode 142 is exposed through the passivation layer 151. Among them, the specific material of the passivation layer 151 is not limited in the embodiments of the present application. By way of example, it can be silicon oxide, silicon nitride, or other organic passivation materials.

[0038] In addition, in order to enable lattice matching and thermal matching between the substrate 110 and the drift layer 130, a buffer layer 161 can be provided between the drift layer 130 and the substrate 110. When the materials of the substrate 110, the buffer layer 161, and the drift layer 130 are the same, the doping concentrations of the substrate 110, the buffer layer 161, and the drift layer 130 are different. Specifically, the doping concentration of the substrate 110 is greater than that of the buffer layer 161, and the doping concentration of the buffer layer 161 is greater than that of the drift layer 130.

[0039] The PIN diode 100 provided by the present application includes a substrate 110, a P-type structure 120, and a drift layer 130 disposed on the substrate 110. Among them, the P-type structure 120 is embedded in the top of the drift layer 130. The substrate 110 is N-fold doped and serves as the n layer, and the drift layer 130 is lightly doped and serves as the I layer. The P-type structure 120 includes a P layer 121 and a junction diffusion region 124 disposed around the outer periphery of the P layer 121. The P layer 121 includes a P well layer 122 and a P heavily doped layer 123 disposed in sequence on the drift layer 130, serving as the P layer, to form the PIN diode 100. Among them, the doping concentration of the junction diffusion region 124 is less than that of the P heavily doped layer 123. The junction diffusion region 124 is located on the outer periphery of the P layer 121 and is in contact with the P layer 121. The P layer 121 is formed by impurity diffusion in the drift layer 130. When the PIN diode 100 is in the reverse bias state, the junction diffusion region 124 is located between the P layer and the I layer. The reverse electric field depletes all the holes in the junction diffusion region 124, leaving immovable negative charges, which is equivalent to introducing negative charges into the space charge region of the drift layer 130. These negative charges cause the space charge region near the PI junction to expand outward, thereby reducing the curvature of the edge of the PI junction, reducing the electric field at the edge of the PI junction, and increasing the breakdown voltage of the PIN diode 100.

[0040] Optionally, as Figure 1 and Figure 2 shown, the junction diffusion region 124 includes a plurality of regions sequentially disposed outward along the P layer 121, and along the outward direction of the P layer 121, the doping concentrations of the plurality of junction diffusion regions 124 gradually decrease.

[0041] The P layer 121 and the junction diffusion region 124 are formed by diffusing impurities on the drift layer 130. Among them, the P layer 121 can be located at the center of the drift layer 130 as Figure 1 shown, or can be located at the edge of the drift layer 130 as Figure 2 shown. When the P layer 121 is located at the center of the drift layer 130, the plurality of junction diffusion regions 124 are sequentially disposed around the outer periphery of the P layer 121 to form an annular junction diffusion region 124. When the P layer 121 is located at the edge of the drift layer 130, the plurality of junction diffusion regions 124 are sequentially disposed around the outer periphery of the P layer 121 to form a semi-annular or quarter-annular diffusion region.

[0042] By disposing a plurality of junction diffusion regions 124 outward along the P layer 121 and the doping concentrations of the plurality of junction diffusion regions 124 gradually decreasing, when the PIN diode 100 is in the reverse bias state, the plurality of junction diffusion regions 124 can cause the space charge region to further expand outward, thereby further reducing the region at the edge of the PI junction and further increasing the breakdown voltage of the PIN diode 100.

[0043] In an implementable manner of the embodiment of the present application, asFigure 1 and Figure 2 As shown in Figure 2 , the junction diffusion region 124 includes two arranged in sequence outward along the P layer 121. Along the direction outward along the P layer 121, the two junction diffusion regions 124 are respectively a first junction diffusion region 125 and a second junction diffusion region 126.

[0044] When the number of junction diffusion regions 124 is set to more than two, the improvement of the breakdown voltage of the PIN diode 100 is limited. Moreover, multiple diffusion junctions will increase the manufacturing difficulty of the PIN diode 100. Considering the above two aspects, in the embodiments of the present application, the junction diffusion region 124 is set to two.

[0045] Optionally, as Figure 1 and Figure 2 shown, the doping concentration of the first junction diffusion region 125 is between 6*e 13 -5*e 17 and the doping concentration of the second junction diffusion region 126 is between 6*e 13 -5*e 15

[0046] The doping concentration of the P heavily doped layer 123 is between 5*e 18 -6*e 18 so that the doping concentrations of the P heavily doped layer 123, the first junction diffusion region 125, and the second junction diffusion region 126 gradually decrease.

[0047] In an achievable manner of the embodiments of the present application, as Figure 3 shown, on the side of the P well layer 122 close to the P heavily doped layer 123, induced defects are formed to form a recombination center layer 127 on the upper surface of the P well layer 122.

[0048] In the PIN diode 100 of the prior art, the carrier lifetime is large, the conductance modulation effect is obvious, and the forward conduction characteristic of the device is optimized. However, the large carrier lifetime will also cause the problem of excessive reverse peak current, deteriorating the reverse recovery characteristics of the device, including reverse peak current, reverse recovery time, turn-off loss, and softness factor. In the embodiments of the present application, a recombination center layer 127 is formed on the side of the P well layer 122 close to the P heavily doped layer 123. When the PIN diode 100 is made of silicon material, the recombination center layer 127 mainly introduces oxygen vacancy pairs and divacancy pairs in silicon. The oxygen vacancy pairs control the large injection lifetime, and the divacancy pairs control the small injection lifetime and the carrier generation lifetime. Therefore, the carrier lifetime at the recombination center layer 127 is reduced to a suitable value. In this way, both the current-voltage oscillation caused by the large carrier lifetime value at the recombination center layer 127 can be avoided, and the reverse recovery time can be reduced, the reverse recovery peak current can be decreased, and the softness factor can be optimized.

[0049] Optionally, as Figure 3 ​As shown, proton irradiation is used to form induced defects on one side of the P-well layer 122.

[0050] Proton irradiation is to irradiate one side of the P-well layer 122 with a high-energy electron beam. Induced defects are introduced as recombination centers on the side of the P-well layer 122 close to the P+ heavily doped layer 123, thereby reducing the carrier lifetime. Since the proton has a large mass, the defect position can be precisely controlled, and only a defect peak will be formed at the end of the range without changing the overall carrier lifetime. Since proton irradiation can reduce the carrier lifetime only at the defect peak position without changing the carrier lifetime. This carrier lifetime control is also called local carrier lifetime control.

[0051] In an achievable way of the embodiment of the present application, as Figure 1 and Figure 2 shown, the depth that the P-layer 121 extends into the drift layer 130 is less than the depth that the junction diffusion region 124 extends into the drift layer 130. Along the outward direction of the P-layer 121, the depths that multiple junction diffusion regions 124 extend into the drift layer 130 gradually increase.

[0052] The depth that the junction diffusion region 124 extends into the drift layer 130 is greater than the depth that the P-layer 121 extends into the drift layer 130, so that the junction diffusion region 124 can better surround the vertex of the P-layer 121, thereby improving the improvement effect of the junction diffusion region 124 on the breakdown voltage. Similarly, along the outward direction of the P-layer 121, the depths that multiple junction diffusion regions 124 extend into the drift layer 130 gradually increase, further improving the improvement effect of the junction diffusion region 124 on the breakdown voltage.

[0053] Optionally, along the upward direction of the layer, the doping concentration of the junction diffusion region 124 gradually increases.

[0054] At the top corner and edge of the P-layer 121, the curvature at the top corner is the largest, and along the upward direction of the layer, the curvature gradually decreases. Based on this, in the embodiment of the present application, the doping concentration of the junction diffusion region 124 is gradually increased to improve the improvement effect on the breakdown voltage.

[0055] In an achievable way of the embodiment of the present application, as Figure 1 and Figure 2 shown, along the outward direction of the P-layer 121, the ring widths of multiple junction diffusion regions 124 gradually increase.

[0056] In order to further verify the beneficial effects of the PIN diode 100 of the embodiment of the present application, the applicant tested the performance of the PIN diode 100 in the prior art and the PIN diode 100 of the embodiment of the present application. The test results are as Figure 4As shown, the breakdown voltage of the PIN diode 100 according to the embodiment of the present application reaches 2185V, which is three times that of the PIN diode 100 in the prior art, and the forward conduction characteristics and reverse recovery characteristics are also greatly optimized.

[0057] The embodiment of the present application also discloses a preparation method of a PIN diode 100, as Figure 5 shown, for preparing the above PIN diode 100, including:

[0058] S10: As Figure 6 shown, provide a substrate 110 and form a drift layer 130 on the substrate 110;

[0059] Among them, the specific material of the substrate 110 is not limited in the embodiment of the present application. By way of example, it can be silicon, silicon carbide, etc. The drift layer 130 is formed on the substrate 110 by an epitaxial process. Specifically, a N-type drift layer 130 can be formed on the substrate 110 by chemical vapor deposition or physical vapor deposition.

[0060] S20: As Figure 7 and Figure 8 shown, dope the drift layer 130 from one side of the substrate 110 to form a N-type heavily doped layer 162;

[0061] Among them, the drift layer 130 can be doped with phosphorus elements from one side of the substrate 110 to form a N-type heavily doped layer 162, wherein the doping concentration is between 3*e 18 -5*e 18 . Among them, the N-type doped layer serves as the N layer of the PIN diode 100. When the substrate 110 is also heavily doped, the N-type heavily doped layer 162 and the substrate 110 are used as a whole as the substrate 110 of the PIN diode 100.

[0062] Having the same structure as the PIN diode 100, in order to enable lattice matching and thermal matching between the substrate 110 and the drift layer 130, a buffer layer 161 can be provided between the drift layer 130 and the substrate 110. When the PIN diode 100 includes the buffer layer 161, a buffer layer 161 can be first formed by lightly doping phosphorus from one side of the substrate 110, and then heavily doped with phosphorus on the side of the buffer layer 161 close to the substrate 110 to form a N-type heavily doped layer 162.

[0063] S30: As Figure 9 shown, dope the drift layer 130 from the side of the drift layer 130 away from the substrate 110 to form a P well 163;

[0064] Specifically, boron can be selected as the doping element, wherein the P well layer 122 has a relatively light doping concentration and serves as the space charge region together with the drift layer 130.

[0065] S40: As shown in Figure 9 FIG. [FIG. number not provided], a P heavily doped layer 123 is formed by heavily doping the surface of the P well 163. Among them, the undoped part of the P well 163 forms a P well layer 122;

[0066] Specifically, boron can be selected as the doping element, and the P heavily doped layer 123 has a relatively high doping concentration.

[0067] S50: As shown in Figure 10 FIG. [FIG. number not provided], the drift layer 130 outside the P well 163 is doped to form a junction diffusion region 124, and the doping concentration of the junction diffusion region 124 is less than that of the P heavily doped layer 123.

[0068] When there are multiple junction diffusion regions 124, the junction diffusion region 124 close to the P well 163 can be doped first, and then, in the direction away from the P well 163, the multiple junction diffusion regions 124 can be doped in sequence. Specifically, the drift layer 130 can be doped by means of aluminum ion implantation.

[0069] Before doping the drift layer 130 outside the P well 163 to form the junction diffusion region 124, a blocking layer can be formed on the drift layer 130. The blocking layer forms an implantation window by photolithography at the place where ion implantation is required, and ions are implanted into the drift layer 130 through the implantation window to form the junction diffusion region 124.

[0070] Same as the structure of the PIN diode 100, electrodes are respectively arranged outside the substrate 110 and the P layer 121. Specifically, as shown in Figure 1 and Figure 2 FIG. [FIG. number not provided], an anode electrode 142 is arranged outside the P layer 121, and a cathode electrode 141 is arranged outside the substrate 110. A passivation layer 151 is arranged on the end face of the PIN diode 100. Specifically, the passivation layer 151 can be formed by the method of in-situ growth.

[0071] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A PIN diode, characterized in that, It includes a substrate, a P-type structure, and a drift layer disposed on the substrate. Among them, the P-type structure is embedded in the top of the drift layer. The P-type structure includes a P-level and a junction diffusion region surrounding the periphery of the P-level. The P-level includes a P-well layer and a P-heavily doped layer disposed on the drift layer in sequence. The doping concentration of the junction diffusion region is less than that of the P-heavily doped layer; An induced defect is formed on the side of the P-well layer close to the P-heavily doped layer, so as to form a recombination center layer on the upper surface of the P-well layer; Proton irradiation is used to form an induced defect on one side of the P-well layer.

2. The PIN diode according to claim 1, characterized in that The junction diffusion region includes a plurality of regions disposed in sequence outward along the P-level, and the doping concentration of the plurality of junction diffusion regions gradually decreases outward along the P-level.

3. The PIN diode according to claim 2, wherein The junction diffusion region includes two regions disposed in sequence outward along the P-level. In the direction outward along the P-level, the two junction diffusion regions are respectively a first junction diffusion region and a second junction diffusion region.

4. The PIN diode according to claim 3, characterized in that, The doping concentration of the first junction diffusion region is between 6*e 13 -5*e 17 , and the doping concentration of the second junction diffusion region is between 6*e 13 -5*e 15 .

5. The PIN diode according to claim 2, characterized in that, The depth of the P-level extending into the drift layer is less than the depth of the junction diffusion region extending into the drift layer. In the direction outward along the P-level, the depth of the plurality of junction diffusion regions extending into the drift layer gradually increases.

6. The PIN diode according to claim 1, characterized in that, In the upward direction along the level direction, the doping concentration of the junction diffusion region gradually increases.

7. The PIN diode according to claim 1, characterized in that, In the direction outward along the P-level, the ring width of the plurality of junction diffusion regions gradually increases.

8. A method for preparing a PIN diode, characterized in that, For manufacturing the PIN diode according to any one of claims 1-7, it includes: Providing a substrate and forming a drift layer on the substrate; Doping the drift layer from one side of the substrate to form an N-type heavily doped layer; Doping the center of the drift layer from the side of the drift layer away from the substrate to form a P-well; Performing heavy doping on the surface of the P-well to form a P-heavily doped layer, wherein the part of the P-well that is not heavily doped forms a P-well layer; Doping the drift layer outside the P-well to form a junction diffusion region, and the doping concentration of the junction diffusion region is less than that of the P-heavily doped layer.

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