A method for eliminating DC bias of capacitor voltage using virtual space vector modulation

Abstract

The present invention discloses a method for eliminating a capacitor voltage DC bias of a virtual space vector modulation, comprising: comparing the size of a three-phase dual modulation wave to obtain a positive maximum value, a negative minimum value, a positive middle value, and a negative middle value of the three-phase dual modulation wave. According to the size relationship between the positive maximum value, the negative minimum value, the positive middle value, and the negative middle value, eight types of DC bias elimination areas are divided, and the maximum value of the dual modulation wave upward shift and the maximum value of the dual modulation wave downward shift are calculated respectively. By judging the direction of the product of the capacitor current and the DC bias, the dual modulation wave displacement flag is obtained. Combining the dual modulation wave displacement flag and the maximum value of the dual modulation wave upward shift and the maximum value of the dual modulation wave downward shift, the displacement values ​​of the positive maximum value, the negative minimum value, the positive middle value, and the negative middle value are determined. A specific dual modulation wave is moved based on the displacement value to eliminate the capacitor voltage DC bias. The method of the present invention improves the reliability of virtual space vector modulation and has the advantage of simple calculation.

Description

Technical Field

[0001] The invention belongs to the field of capacitor voltage DC bias elimination methods, and in particular relates to a capacitor voltage DC bias elimination method using virtual space vector modulation. Background Art

[0002] Figure 1 This is the main circuit topology of the three-level neutral point clamped inverter. Compared with the two-level inverter, the voltage stress of each power device of the three-level inverter is lower and the current harmonic performance is better; and compared with the cascaded H-bridge inverter, the three-level inverter has a simpler structure and is more convenient to control. Based on the above advantages, the three-level inverter has been widely used in industrial automation, photovoltaic energy storage, rail transportation and other fields.

[0003] Capacitor voltage balance control is the core issue of three-level inverters. The literature "An Extended DPWM Strategy With Unconditional Balanced Neutral Point Voltage for Neutral Point Clamped Three-Level Converter" (Chen K[J].IEEE Transactions on Industrial Electronics, 2019, 66(11):8402-8413.) points out that capacitor voltage imbalance will aggravate output voltage distortion, increase device shutdown voltage, reduce system reliability and increase low-frequency harmonics output by the inverter. Therefore, it is necessary to balance the capacitor voltage of the three-level inverter.

[0004] Figure 2 is the voltage vector diagram of the three-level inverter. According to the amplitude and level state, each voltage vector can be classified into zero vector, P-type small vector, N-type small vector, medium vector and large vector. The specific classification of each voltage vector is shown in Table 1.

[0005] Table 1 Voltage vector types of three-level NPC converter

[0006]

[0007]

[0008] Among the space vectors of the three-level inverter, only the middle vector and the small vector will affect the capacitor voltage. The literature "A Carrier-based Implementation of Three-Level Neutral-Point-Clamped Converter Zero-Vector Initial SVPWM Method" (Gao Zhan. [J]. Transactions of the Chinese Society of Electrotechnical Engineering, 2020, 35(10): 2194-2205.) points out that the P-type small vector and the N-type small vector with the same position have opposite effects on the capacitor voltage. Therefore, under normal circumstances, the capacitor voltage of the three-level inverter can be controlled to restore balance by redistributing the action time of the P-type small vector and the N-type small vector.

[0009] The document "Research on Midpoint Potential Balance Problem Based on Dual Modulation Wave Carrier PWM Strategy" (Tian Kai [D]. Harbin: Harbin Institute of Technology, 2010) analyzes the relationship between capacitor voltage and small vector action time, and points out that under special conditions such as high modulation ratio or low power factor, the small vector action time is too short and its impact on the capacitor voltage is small, and it is impossible to control the capacitor voltage balance by reallocating the small vector action time.

[0010] In order to control the capacitor voltage balance under special conditions such as high modulation ratio or low power factor, the paper "Virtual space vector pulse width modulation method of diode clamped three-level inverter based on carrier" (Jiang Weidong. [J]. Transactions of China Electrotechnical Society, 2016, 31(12): 153-160.) proposed the principle as follows Figure 3 Virtual space vector modulation. When the initial voltages of the upper and lower capacitors are equal, the virtual space vector with an average capacitor current of zero is used to synthesize the reference voltage. The virtual space vector modulation can control the capacitor voltage balance at any modulation ratio and power factor.

[0011] Virtual space vector modulation overcomes the defects of traditional capacitor voltage balance control methods, but the document "Interval adjustable hybrid carrier modulation strategy for NPC three-level inverter" (Gu Xin. [J]. New Technology of Electrical Engineering and Energy, 2022, 41(10): 11-19.) points out that virtual space vector modulation can only eliminate the influence of AC component on capacitor voltage, and it cannot curb DC bias. Under the action of virtual space vector modulation, the capacitor voltage will continue to shift and eventually lead to capacitor voltage imbalance.

[0012] In order to improve the practicability and reliability of virtual space vector modulation, it is necessary to study the capacitor voltage DC offset elimination method applicable to virtual space vector modulation. Summary of the invention

[0013] In order to improve the practicality and reliability of virtual space vector modulation, the present invention proposes a method for eliminating the DC bias of capacitor voltage of virtual space vector modulation. The method of the present invention can eliminate the DC bias of capacitor voltage under any modulation ratio and power factor, thereby overcoming the defect that virtual space vector modulation cannot curb the DC bias, and will not cause output current distortion and will not increase the switching frequency. In addition, the method of the present invention only needs to obtain the displacement value of the modulation wave through simple calculation, and it also has the advantages of easy calculation and convenient implementation.

[0014] To achieve the above object, the present invention provides the following solutions:

[0015] A method for eliminating a capacitor voltage DC bias using virtual space vector modulation comprises the following steps:

[0016] Compare the size of the virtual space vector modulation three-phase dual modulation wave to obtain the positive maximum value VS of the three-phase dual modulation wave maxP , negative minimum VS minN , positive middle value VS midP and negative intermediate values ​​VS midN ;

[0017] Compare the maximum values ​​SIN of the three-phase sine waves max and the minimum absolute value SIN minabs , and combined with the positive maximum value VS maxP , the negative minimum value VS minN , the positive middle value VS midP , the negative intermediate value VS midN The DC bias elimination regions are divided into eight categories according to the size relationship of

[0018] Based on different DC bias elimination areas, the maximum value UP of the dual modulation wave is calculated respectively. max The maximum value DN of the double modulation wave downshift max ;

[0019] By determining the direction of the product of the capacitor current and the capacitor voltage DC bias, the dual modulation wave displacement flag VSflag is obtained;

[0020] According to the dual modulation wave displacement flag VSflag, each dual modulation wave shifts up to the maximum value UP max And each dual modulation wave downshift maximum DN max , determine the positive maximum value VS maxP The displacement value, the negative minimum value VS minN The displacement value, the positive middle value VS midP The displacement value and the negative intermediate value VS midN The displacement value of

[0021] Based on the positive maximum value VSmaxP The displacement value, the negative minimum value VS minN The displacement value, the positive middle value VS midP The displacement value and the negative intermediate value VS midN The displacement value moves the specific dual modulation wave and eliminates the DC offset of the capacitor voltage.

[0022] Preferably, the size of the virtual space vector modulation three-phase dual modulation wave is compared to obtain the positive maximum value VS of the three-phase dual modulation wave maxP , negative minimum VS minN , positive middle value VS midP and negative intermediate values ​​VS midN The methods include:

[0023] When the three-level inverter uses virtual space vector modulation, set the modulation wave on phase A of the virtual space vector modulation to VS AP , the modulation wave in phase A is VS AN , the modulation wave on phase B is VS BP , the modulation wave in phase B is VS BN , the modulation wave on phase C is VS CP , the modulation wave in phase C is VS CN ;

[0024] When VS AP ≥VS BP , and VS AP ≥VS CP When, let the positive maximum value VS maxP =VS AP ; Otherwise when VS BP ≥VS AP , and VS BP ≥VS CP When, let the positive maximum value VS maxP =VS BP ; Otherwise, let the positive maximum value VS maxP =VS CP ;

[0025] When VS AN <VS BN , and VS AN <VS CN When, let the negative minimum value VS minN =VS AN ; Otherwise when VS BN <VS AN , and VS BN <VS CN When, let the negative minimum value VS minN =VS BN ; Otherwise, let the negative minimum value VS minN =VSCN ;

[0026] When VS AP <Positive maximum value VS maxP , and VS AN > Negative minimum VS minN When, let the middle value VS midP =VS AP , negative intermediate value VS midN =VS AN ; Otherwise when VS BP <Positive maximum value VS maxP , and VS BN > Negative minimum VS minN When, let the middle value VS midP =VS BP , negative intermediate value VS midN =VS BN ; Otherwise, let the middle value VS midP =VS CP , negative intermediate value VS midN =VS CN .

[0027] Preferably, compare the maximum value SIN of the three-phase sine wave max and the minimum absolute value SIN minabs , and combined with the positive maximum value VS maxP , the negative minimum value VS minN , the positive middle value VS midP , the negative intermediate value VS midN The method of dividing the eight types of DC bias elimination areas includes:

[0028] When the maximum value SIN max ≥Minimum absolute value SIN minabs hour:

[0029] When the negative minimum value VS minN +1 ≥ the positive maximum value VS maxP , the current region is divided into the first type of DC bias elimination region; otherwise, when the negative intermediate value VS midN +1 ≥ the positive maximum value VS maxP , divide the current area into the second type of DC bias elimination area; otherwise, when the negative minimum value VS minN +1 ≥ the positive median value VS midP , the current area is divided into the third type of DC bias elimination area; otherwise, the current area is divided into the fourth type of DC bias elimination area;

[0030] When the maximum value SIN max <Minimum absolute value SIN minabs hour:

[0031] When the negative minimum value VS minN +1 ≥ the positive maximum value VS maxP , the current region is divided into the fifth type of DC bias elimination region; otherwise, when the negative minimum value VS minN +1 ≥ the positive median value VS midP , the current region is divided into the sixth type of DC bias elimination region; otherwise, when the negative intermediate value VS midN +1 ≥ the positive maximum value VS maxP , the current area is divided into the seventh category of DC bias elimination area; otherwise, the current area is divided into the eighth category of DC bias elimination area.

[0032] Preferably, compare the maximum value SIN of the three-phase sine wave max and the minimum absolute value SIN minabs The methods include:

[0033] Set the A-phase sine wave of the virtual space vector modulation to SIN A , the B-phase sine wave is SIN B , the C phase sine wave is SIN C ;

[0034] When SIN A ≥SIN B , and SIN A ≥SIN C When the maximum value SIN max =SIN A ; Otherwise when SIN B ≥SIN A , and SIN B ≥SIN C When the maximum value SIN max =SIN B ; Otherwise, let the maximum value SIN max =SIN C ;

[0035] When SIN A <SIN B , and SIN A <SIN C When the minimum absolute value SIN minabs =1+SIN A ; Otherwise when SIN B <SIN A , and SIN B <SIN C When the minimum absolute value SIN minabs =1+SIN B ; Otherwise, let the minimum absolute value SINminabs =1+SIN C .

[0036] Preferably, based on different DC bias elimination regions, the maximum upshift value UP of the dual modulation wave is calculated respectively. max The maximum value DN of the double modulation wave downshift max The methods include:

[0037] For the first type of DC bias elimination area, let the dual modulation wave shift up to the maximum value UP max =-VS midN , double modulation wave downshift maximum value DN max =VS maxP -VS midP ;

[0038] For the second type of DC bias elimination area, let the dual modulation wave shift up to the maximum value UP max =-VS midN , double modulation wave downshift maximum value DN max =1+VS minN -VS midP ;

[0039] For the third type of DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1-VS maxP , double modulation wave downshift maximum value DN max =1+VS minN -VS midP ;

[0040] For the fourth and eighth types of DC offset elimination regions, the dual modulation wave is shifted up to the maximum value UP max =1-VS maxP , double modulation wave downshift maximum value DN max =1+VS minN ;

[0041] For the fifth type of DC bias elimination area, let the dual modulation wave shift up to the maximum value UP max =VS midN -VS minN , double modulation wave downshift maximum value DN max =VS midP ;

[0042] For the sixth type of DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1+VS midN -VS maxP , double modulation wave downshift maximum value DN max =VS midP ;

[0043] For the seventh category DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1+VS midN -VS maxP , double modulation wave downshift maximum value DN max =1+VS minN .

[0044] Preferably, the method for obtaining the dual modulation wave displacement flag VSflag by determining the direction of the product of the capacitor current and the capacitor voltage DC bias comprises:

[0045] Set the capacitor current to I cap , capacitor voltage DC bias is U caperr ;

[0046] When I cap with U caperr When the product of is greater than zero, set VSflag = 1; otherwise, when I cap with U caperr When the product is less than zero, set VSflag = -1.

[0047] Preferably, the capacitor current I cap The method is:

[0048] Set the output current of phase A to I A , the output current of phase B is I B , the output current of phase C is I C ;

[0049] When the maximum value SIN max ≥Minimum absolute value SIN minabs hour:

[0050] When SIN A ≥0, let I cap =I A ; Otherwise when SIN B ≥0, let I cap =I B Otherwise, let I cap =I C ;

[0051] When the maximum value SIN max <Minimum absolute value SIN minabs hour:

[0052] When SIN A <0, let I cap =-I A ; Otherwise when SIN B <0, let I cap =-I B Otherwise, let I cap =-IC ;

[0053] Determine the capacitor voltage DC bias U caperr The method is:

[0054] Set the upper capacitor voltage to U capup , the lower capacitor voltage is U capdn ;

[0055] When(U capup -U capdn )≥0, let U caperr =1; otherwise, when (U capup -U capdn )<0, let U caperr =-1.

[0056] Preferably, according to the dual modulation wave displacement flag VSflag, each dual modulation wave shift up maximum value UP max And each dual modulation wave downshift maximum DN max , determine the positive maximum value VS maxP The displacement value, the negative minimum value VS minN The displacement value, the positive middle value VS midP The displacement value and the negative intermediate value VS midN Methods for finding displacement values ​​include:

[0057] When the dual modulation wave shift flag VSflag=1, the dual modulation wave shifts up to the maximum value UP max Determine the displacement value, specifically:

[0058] Let the positive maximum value VS maxP and the negative minimum value VS minN The displacement value is the maximum value of the double modulation wave UP max ;

[0059] When 1+the negative minimum value vs minN ≥ the positive median value VS midP , and the maximum value SIN max ≥Minimum absolute value SIN minabs When the negative intermediate value VS midN The displacement value is the maximum value of the double modulation wave UP max , the positive middle value VS midP The displacement value of is 0;

[0060] When 1+the negative minimum value vs minN ≥ the positive median value VS midP , and the maximum value SIN max <Minimum absolute value SIN minabs When the positive intermediate value VSmidP The displacement value is the maximum value of the double modulation wave UP max , the negative intermediate value VS midN The displacement value of is 0;

[0061] When 1+the negative minimum value vs minN <The positive middle value VS midP When the positive intermediate value VS midP and the negative intermediate value VS midN The displacement value is the maximum value of the double modulation wave UP max / 2;

[0062] When the dual modulation wave shift flag VSflag = -1, the dual modulation wave is shifted down to the maximum value DN max Determine the displacement value, specifically:

[0063] Let the positive maximum value VS maxP and the negative minimum value VS minN The displacement value is -DN max ;

[0064] When 1+the negative middle value vs minN ≥ the positive median value VS midP , and the maximum value SIN max ≥Minimum absolute value SIN minabs When the negative intermediate value VS midN The displacement value is -DN max VS midP The displacement value of is 0;

[0065] When 1+the negative middle value vs minN ≥ the positive median value VS midP , and the maximum value SIN max <Minimum absolute value SIN minabs When the positive intermediate value VS midP The displacement value is -DN max , the negative intermediate value VS midN The displacement value of is 0;

[0066] When 1+the negative middle value vs minN <The positive middle value VS midP When the positive intermediate value VS midP and the negative intermediate value VS midN The displacement value is -DN max / 2.

[0067] Preferably, based on the positive maximum value VS maxP The displacement value, the negative minimum value VS minNThe displacement value, the positive middle value VS midP The displacement value and the negative intermediate value VS midN Methods for moving a specific dual modulation wave by a displacement value and eliminating the DC bias of the capacitor voltage include:

[0068] When the positive maximum value VS maxP =VS AP When, based on the positive maximum value VS maxP The displacement value of the move VS AP ; Otherwise when the negative intermediate value VS minN =VS AN When, based on the negative intermediate value VS minN The displacement value of the move VS AN ; Otherwise, based on the positive intermediate value VS midP and the negative intermediate value VS midN The displacement values ​​are respectively moved VS AP and VS AN ;

[0069] When the positive maximum value VS maxP =VS BP When, based on the positive maximum value VS maxP The displacement value of the move VS BP ; Otherwise when the negative intermediate value VS minN =VS BN When, based on the negative intermediate value VS minN The displacement value of the move VS BN ; Otherwise, based on the positive intermediate value VS midP and the negative intermediate value VS midN The displacement values ​​are respectively moved VS BP and VS BN ;

[0070] When the positive maximum value VS maxP =VS CP When, based on the positive maximum value VS maxP The displacement value of the move VS CP ; Otherwise when the negative intermediate value VS minN =VS CN When, based on the negative intermediate value VS minN The displacement value of the move VS CN ; Otherwise, based on the positive intermediate value VS midP and the negative intermediate value VS midN The displacement values ​​are respectively moved VS CP and VS CN .

[0071] Compared with the prior art, the present invention has the following beneficial effects:

[0072] When the three-level inverter uses virtual space vector modulation, the present invention first compares the size of the virtual space vector modulation three-phase dual modulation wave and obtains the positive maximum value VS of the three-phase dual modulation wave maxP , negative minimum VS minN and the positive middle value VS midP , negative intermediate value VS midN Then compare the maximum value SIN of the three-phase sine wave max and the minimum absolute value SIN minabs , and combined with VS maxP VS minN and VS midP VS midN According to the size relationship of , eight types of DC bias elimination regions are divided. For different DC bias elimination regions, the present invention calculates the maximum value UP of the dual modulation wave upward shift respectively. max The maximum value DN of the double modulation wave downshift max By determining the direction of the product of the capacitor current and the capacitor voltage DC bias, the present invention obtains the dual modulation wave displacement flag VSflag. max DN max The present invention further determines VS maxP VS minN and VS midP VS midN Finally, by moving a specific dual modulation wave based on the displacement value, the present invention can eliminate the DC bias of the capacitor voltage. The method of the present invention can eliminate the DC bias of the capacitor voltage under any modulation ratio and power factor, thereby overcoming the defect that the virtual space vector modulation cannot curb the DC bias, and will not cause output current distortion and will not increase the switching frequency. In addition, the method of the present invention only needs to obtain the displacement value of the modulation wave through simple calculation, and it also has the advantages of easy calculation and convenient implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0074] Figure 1 is a main circuit topology diagram of a three-level frequency converter in the background technology;

[0075] Figure 2 A voltage vector diagram of a three-level frequency converter in the background technology;

[0076] Figure 3It is a principle diagram of virtual space vector modulation in the background technology;

[0077] Figure 4 A specific implementation flow chart of the method for eliminating the capacitor voltage DC bias of virtual space vector modulation of the present invention;

[0078] Figure 5a , Figure 5b The upper capacitor voltage of the three-level inverter in the embodiment of the present invention is 700V, the lower capacitor voltage is 300V, the carrier frequency is 1500Hz, the modulation ratio is 0.3, the power factor is 0.8, and the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the virtual space vector modulation are not used. Wherein, Figure 5a is the simulation result of the whole process. Figure 5b This is the simulation result within a fundamental wave period;

[0079] Figure 6a , Figure 6b The upper capacitor voltage of the three-level inverter in the embodiment of the present invention is 700V, the lower capacitor voltage is 300V, the carrier frequency is 1500Hz, the modulation ratio is 0.3, and the power factor is 0.8. The method of the present invention is used to obtain the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the virtual space vector modulation; wherein, Figure 6a This is the simulation result of the whole process of DC bias elimination. Figure 6b This is the simulation result within one fundamental wave cycle during the DC bias elimination process;

[0080] Figure 7a , Figure 7b The upper capacitor voltage of the three-level inverter in the embodiment of the present invention is 300V, the lower capacitor voltage is 700V, the carrier frequency is 2000Hz, the modulation ratio is 0.6, the power factor is 0.4, and the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the virtual space vector modulation are not used. Wherein, Figure 7a is the simulation result of the whole process. Figure 7b This is the simulation result within a fundamental wave period;

[0081] Figure 8a , Figure 8b The upper capacitor voltage of the three-level inverter in the embodiment of the present invention is 300V, the lower capacitor voltage is 700V, the carrier frequency is 2000Hz, the modulation ratio is 0.6, and the power factor is 0.4. The method of the present invention is used to obtain the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the action of virtual space vector modulation; wherein, Figure 8a This is the simulation result of the whole process of DC bias elimination. Figure 8b This is the simulation result within one fundamental wave cycle during the DC bias elimination process;

[0082] Figure 9a, Figure 9b The upper capacitor voltage of the three-level inverter in the embodiment of the present invention is 550V, the lower capacitor voltage is 450V, the carrier frequency is 3000Hz, the modulation ratio is 0.98, the power factor is 0.2, and the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the virtual space vector modulation are not used. Wherein, Figure 9a is the simulation result of the whole process. Figure 9b This is the simulation result within a fundamental wave period;

[0083] Fig.10a , Fig.10b The upper capacitor voltage of the three-level inverter in the embodiment of the present invention is 550V, the lower capacitor voltage is 450V, the carrier frequency is 3000Hz, the modulation ratio is 0.98, and the power factor is 0.2. The method of the present invention is used to obtain the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the virtual space vector modulation; wherein, Fig.10a This is the simulation result of the whole process of DC bias elimination. Fig.10b This is the simulation result within one fundamental wave cycle during the DC bias elimination process. DETAILED DESCRIPTION

[0084] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0085] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0086] Embodiment 1

[0087] The present invention provides a method for eliminating a capacitor voltage DC bias of a virtual space vector modulation, comprising the following steps:

[0088] When the three-level inverter uses virtual space vector modulation, the size of the virtual space vector modulation three-phase dual modulation wave is compared to obtain the positive maximum value VS of the three-phase dual modulation wave. maxP , negative minimum VS minN , positive middle value VS midP and negative intermediate values ​​VS midN ;

[0089] Compare the maximum values ​​SIN of the three-phase sine waves max and the minimum absolute value SIN minabs , and combined with the positive maximum value VS maxP, negative minimum VS minN , positive middle value VS midP , negative intermediate value VS midN The DC bias elimination regions are divided into eight categories according to the size relationship of

[0090] Based on different DC bias elimination areas, the maximum value UP of the dual modulation wave is calculated respectively. max The maximum value DN of the double modulation wave downshift max ;

[0091] By determining the direction of the product of the capacitor current and the capacitor voltage DC bias, the dual modulation wave displacement flag VSflag is obtained;

[0092] According to the dual modulation wave displacement flag VSflag, each dual modulation wave shifts up to the maximum value UP max And each dual modulation wave downshift maximum DN max , determine the positive maximum value VS maxP Displacement value, negative minimum value VS minN Displacement value, positive middle value VS midP The displacement value and negative intermediate value VS midN The displacement value of

[0093] Based on positive maximum VS maxP Displacement value, negative minimum value VS minN Displacement value, positive middle value VS midP The displacement value and negative intermediate value VS midN The displacement value moves the specific dual modulation wave and eliminates the DC offset of the capacitor voltage.

[0094] In this embodiment, the magnitude of the virtual space vector modulated three-phase dual modulation wave is compared to obtain the positive maximum value VS of the three-phase dual modulation wave. maxP , negative minimum VS minN , positive middle value VS midP and negative intermediate values ​​VS midN The methods include:

[0095] When the three-level inverter uses virtual space vector modulation, compare the size of the virtual space vector modulation three-phase dual modulation wave. Set the modulation wave on phase A of the virtual space vector modulation to VS AP , the modulation wave in phase A is VS AN , the modulation wave on phase B is VS BP , the modulation wave in phase B is VS BN , the modulation wave on phase C is VS CP , the modulation wave in phase C is VS CN ;

[0096] When VS AP ≥VS BP , and VSAP ≥VS CP When, let the positive maximum value VS maxP =VS AP ; Otherwise when VS BP ≥VS AP , and VS BP ≥VS CP When, let the positive maximum value VS maxP =VS BP ; Otherwise, let the positive maximum value VS maxP =VS CP ;

[0097] When VS AN <VS BN , and VS AN <VS CN When, let the negative minimum value VS minN =VS AN ; Otherwise when VS BN <VS AN , and VS BN <VS CN When, let the negative minimum value VS minN =VS BN ; Otherwise, let the negative minimum value VS minN =VS CN ;

[0098] When VS AP <Positive maximum value VS maxP , and VS AN > Negative minimum VS minN When, let the middle value VS midP =VS AP , negative intermediate value VS midN =VS AN ; Otherwise when VS BP <Positive maximum value VS maxP , and VS BN > Negative minimum VS minN When, let the middle value VS midP =VS BP , negative intermediate value VS midN =VS BN ; Otherwise, let the middle value VS midP =VS CP , negative intermediate value VS midN =VS CN .

[0099] In this embodiment, the maximum values ​​SIN of the three-phase sine waves are compared. max and the minimum absolute value SIN minabs , and combined with the positive maximum value VS maxP , negative minimum VSminN , positive middle value VS midP , negative intermediate value VS midN The method of dividing the eight types of DC bias elimination areas includes:

[0100] When the maximum value SIN max ≥Minimum absolute value SIN minabs hour:

[0101] When the negative minimum VS minN +1 ≥ positive maximum value VS maxP , the current area is divided into the first type of DC bias elimination area; otherwise, when the negative intermediate value VS midN +1 ≥ positive maximum value VS maxP , divide the current area into the second type of DC bias elimination area; otherwise, when the negative minimum value VS minN +1≥Positive median VS midP , the current area is divided into the third type of DC bias elimination area; otherwise, the current area is divided into the fourth type of DC bias elimination area;

[0102] When the maximum value SIN max <Minimum absolute value SIN minabs hour:

[0103] When the negative minimum VS minN +1 ≥ positive maximum value VS maxP , the current area is divided into the fifth type of DC bias elimination area; otherwise, when the negative minimum value VS minN +1≥Positive median VS midP , the current area is divided into the sixth type of DC bias elimination area; otherwise, when the negative intermediate value VS midN +1 ≥ positive maximum value VS maxP , the current area is divided into the seventh category of DC bias elimination area; otherwise, the current area is divided into the eighth category of DC bias elimination area.

[0104] Specifically, compare the maximum value SIN of the three-phase sine wave max and the minimum absolute value SIN minabs The methods include:

[0105] Set the A-phase sine wave of the virtual space vector modulation to SIN A , the B-phase sine wave is SIN B , the C phase sine wave is SIN C ;

[0106] When SIN A ≥SIN B , and SIN A ≥SIN C When the maximum value SIN max=SIN A ; Otherwise when SIN B ≥SIN A , and SIN B ≥SIN C When the maximum value SIN max =SIN B ; Otherwise, let the maximum value SIN max =SIN C ;

[0107] When SIN A <SIN B , and SIN A <SIN C When the minimum absolute value SIN minabs =1+SIN A ; Otherwise when SIN B <SIN A , and SIN B <SIN C When the minimum absolute value SIN minabs =1+SIN B ; Otherwise, let the minimum absolute value SIN minabs =1+SIN C .

[0108] In this embodiment, based on different DC bias elimination regions, the maximum upshift value UP of the dual modulation wave is calculated respectively. max The maximum value DN of the double modulation wave downshift max The methods include:

[0109] For the first type of DC bias elimination area, let the dual modulation wave shift up to the maximum value UP max =-VS midN , double modulation wave downshift maximum value DN max =VS maxP -VS midP ;

[0110] For the second type of DC bias elimination area, let the dual modulation wave shift up to the maximum value UP max =-VS midN , double modulation wave downshift maximum value DN max =1+VS minN -VS midP ;

[0111] For the third type of DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1-VS maxP , double modulation wave downshift maximum value DN max =1+VS minN -VS midP;

[0112] For the fourth and eighth types of DC offset elimination regions, the dual modulation wave is shifted up to the maximum value UP max =1-VS maxP , double modulation wave downshift maximum value DN max =1+VS minN ;

[0113] For the fifth type of DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =VS midN -VS minN , double modulation wave downshift maximum value DN max =VS midP ;

[0114] For the sixth type of DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1+VS midN -VS maxP , double modulation wave downshift maximum value DN max =VS midP ;

[0115] For the seventh category DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1+VS midN -VS maxP , double modulation wave downshift maximum value DN max =1+VS minN .

[0116] In this embodiment, the method of obtaining the dual modulation wave displacement flag VSflag by determining the direction of the product of the capacitor current and the capacitor voltage DC bias includes:

[0117] Set the capacitor current to I cap , capacitor voltage DC bias is U caperr ;

[0118] When I cap with U caperr When the product of is greater than zero, set VSflag = 1; otherwise, when I cap with U caperr When the product is less than zero, set VSflag = -1.

[0119] Specifically, determine the capacitor current I cap The method is:

[0120] Set the output current of phase A to I A , the output current of phase B is I B , the output current of phase C is I C ;

[0121] When the maximum value SIN max ≥Minimum absolute value SIN minabs hour:

[0122] When SIN A ≥0, let I cap =I A ; Otherwise when SIN B ≥0, let I cap =I B Otherwise, let I cap =I C ;

[0123] When the maximum value SIN max <Minimum absolute value SIN minabs hour:

[0124] When SIN A <0, let I cap =-I A ; Otherwise when SIN B <0, let I cap =-I B Otherwise, let I cap =-I C ;

[0125] Determine the capacitor voltage DC bias U caperr The method is:

[0126] Set the upper capacitor voltage to U capup , the lower capacitor voltage is U capdn ;

[0127] When(U capup -U capdn )≥0, let U caperr =1; otherwise, when (U capup -U capdn )<0, let U caperr =-1.

[0128] In this embodiment, according to the dual modulation wave shift flag VSflag, each dual modulation wave shifts up to the maximum value UP max And each dual modulation wave downshift maximum DN max , determine the positive maximum value VS maxP Displacement value, negative minimum value VS minN Displacement value, positive middle value VS midP The displacement value and negative intermediate value VS midN Methods for finding displacement values ​​include:

[0129] When the dual modulation wave shift flag VSflag = 1, the dual modulation wave shifts up to the maximum value UP maxDetermine the displacement value, specifically:

[0130] Let the positive maximum value VS maxP and negative minimum VS minN The displacement value is the maximum value of the double modulation wave UP max ;

[0131] When 1+negative minimum VS minN ≥ positive median VS midP , and the maximum value SIN max ≥Minimum absolute value SIN minabs When the negative intermediate value VS midN The displacement value is the maximum value of the double modulation wave UP max , positive middle value VS midP The displacement value of is 0;

[0132] When 1+negative minimum VS minN ≥ positive median VS midP , and the maximum value SIN max <Minimum absolute value SIN minabs When, let the middle value VS midP The displacement value is the maximum value of the double modulation wave UP max , negative intermediate value VS midN The displacement value of is 0;

[0133] When 1+negative minimum VS minN <Positive middle value VS midP When, let the middle value VS midP and negative intermediate values ​​VS midN The displacement value is the maximum value of the double modulation wave UP max / 2;

[0134] When the dual modulation wave shift flag VSflag = -1, the dual modulation wave shifts down to the maximum value DN. max Determine the displacement value, specifically:

[0135] Let the positive maximum value VS maxP and negative minimum VS minN The displacement value is -DN max ;

[0136] When 1+negative intermediate value VS minN ≥ positive median VS midP , and the maximum value SIN max ≥Minimum absolute value SIN minabs When the negative intermediate value VS midN The displacement value is -DN max VS midP The displacement value of is 0;

[0137] When 1+negative intermediate value VS minN ≥ positive median VS midP , and the maximum value SIN max <Minimum absolute value SIN minabs When, let the middle value VS midP The displacement value is -DN max , negative intermediate value VS midN The displacement value of is 0;

[0138] When 1+negative intermediate value VS minN <Positive middle value VS midP When, let the middle value VS midP and negative intermediate values ​​VS midN The displacement value is -DN max / 2.

[0139] In this embodiment, based on the positive maximum value VS maxP Displacement value, negative minimum value VS minN Displacement value, positive middle value VS midP The displacement value and negative intermediate value VS midN Methods for moving a specific dual modulation wave by a displacement value and eliminating the DC bias of the capacitor voltage include:

[0140] When the positive maximum value VS maxP =VS AP When, based on the positive maximum value VS maxP The displacement value of the move VS AP ; Otherwise when the negative intermediate value VS minN =VS AN When based on the negative intermediate value VS minN The displacement value of the move VS AN ; Otherwise, based on the positive median VS midP and negative intermediate values ​​VS midN The displacement values ​​are respectively moved VS AP and VS AN ;

[0141] When the positive maximum value VS maxP =VS BP When, based on the positive maximum value VS maxP The displacement value of the move VS BP ; Otherwise when the negative intermediate value VS minN =VS BN When based on the negative intermediate value VS minN The displacement value of the move VS BN ; Otherwise, based on the positive median VS midP and negative intermediate values ​​VS midN The displacement values ​​are respectively moved VS BP and VS BN ;

[0142] When the positive maximum value VS maxP =VS CP When based on the positive maximum value VS maxP The displacement value of the move VS CP ; Otherwise when the negative intermediate value VS minN =VS CN When based on the negative intermediate value VS minN The displacement value of the move VS CN ; Otherwise, based on the positive median VS midP and negative intermediate values ​​VS midN The displacement values ​​are respectively moved VS CP and VS CN .

[0143] Embodiment 2

[0144] The specific implementation process of the method for eliminating the capacitor voltage DC bias of virtual space vector modulation of the present invention is as follows: Figure 4 shown.

[0145] In order to improve the practicality and reliability of virtual space vector modulation, the present invention proposes a method for eliminating the DC bias of capacitor voltage of virtual space vector modulation. The method of the present invention can eliminate the DC bias of capacitor voltage under any modulation ratio and power factor, thereby overcoming the defect that virtual space vector modulation cannot curb the DC bias, and will not cause output current distortion and will not increase the switching frequency. In addition, the method of the present invention only needs to obtain the displacement value of the modulation wave through simple calculation, and it also has the advantages of easy calculation and convenient implementation.

[0146] The specific embodiment of the method for eliminating the DC bias of capacitor voltage by virtual space vector modulation of the present invention is as follows:

[0147] The embodiment of the present invention uses PSIM software to build a three-level inverter model, and uses simulation to verify the effectiveness of the capacitor voltage DC offset elimination method of virtual space vector modulation of the present invention. The simulation conditions of the embodiment are: the simulation step size is set to 4us, the DC side voltage is set to 1000V, the current output frequency is set to 50Hz, and the modulation ratio, power factor, and carrier frequency can be freely adjusted.

[0148] Figure 5a , Figure 5b The capacitor voltage at the upper end of the level inverter of the third embodiment is 700V, the capacitor voltage at the lower end is 300V, the carrier frequency is 1500Hz, the modulation ratio is 0.3, the power factor is 0.8, and the method of the present invention is not used. The capacitor voltage DC bias, dual modulation wave, phase voltage and current under the virtual space vector modulation. Among them, Figure 5a is the simulation result of the whole process. Figure 5bis the simulation result within one fundamental wave cycle. The modulation ratio of 0.3 and the power factor of 0.8 correspond to the low modulation ratio and high power factor. Figure 5a It can be seen that when there is a DC bias greater than zero between the upper capacitor voltage and the lower capacitor voltage, under low modulation ratio and high power factor, if the method of the present invention is not used, the virtual space vector modulation cannot control the upper capacitor voltage and the lower capacitor voltage to restore balance. The DC bias of the capacitor voltage will cause the shutdown voltage of the device to increase and increase the low-frequency harmonics output by the inverter. In order to improve the practicality and reliability of virtual space vector modulation, an effective DC bias elimination method must be used for it.

[0149] Figure 6a , Figure 6b For the third embodiment, the upper capacitor voltage of the level inverter is 700V, the lower capacitor voltage is 300V, the carrier frequency is 1500Hz, the modulation ratio is 0.3, and the power factor is 0.8. The method of the present invention is used to simulate the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the action of space vector modulation. Among them, Figure 6a This is the simulation result of the whole process of DC bias elimination. Figure 6b This is the simulation result of a fundamental wave cycle during the DC bias elimination process. Figure 5a and Figure 6a , when there is a DC bias greater than zero between the upper capacitor voltage and the lower capacitor voltage, under low modulation ratio and high power factor, the method of the present invention can make the DC bias quickly approach zero by moving the dual modulation wave of virtual space vector modulation. Therefore, under low modulation ratio and high power factor, the method of the present invention overcomes the defect that virtual space vector modulation cannot curb DC bias. In addition, compared Figure 5b and Figure 6b In the process of eliminating the DC bias, the method of the present invention reduces the switching frequency from 1000 Hz to 900 Hz and reduces the current THD from 3.63% to 2.64%. Therefore, the method of the present invention does not increase the switching frequency and does not cause output current distortion.

[0150] Figure 7a , Figure 7b The capacitor voltage at the upper end of the level inverter of the third embodiment is 300V, the capacitor voltage at the lower end is 700V, the carrier frequency is 2000Hz, the modulation ratio is 0.6, the power factor is 0.4, and the method of the present invention is not used. The capacitor voltage DC bias, dual modulation wave, phase voltage and current under the virtual space vector modulation. Among them, Figure 7a is the simulation result of the whole process. Figure 7b The simulation results in one fundamental wave cycle are shown in Figure 2. The modulation ratio of 0.6 and the power factor of 0.4 correspond to the medium modulation ratio and medium power factor. Figure 7aIt shows that when there is a DC bias less than zero between the upper capacitor voltage and the lower capacitor voltage, under the conditions of medium modulation ratio and medium power factor, if the method of the present invention is not used, the virtual space vector modulation cannot control the upper capacitor voltage and the lower capacitor voltage to restore balance, thereby affecting the output performance of the three-level inverter.

[0151] Figure 8a , Figure 8b In the third embodiment, the upper capacitor voltage of the level inverter is 300V, the lower capacitor voltage is 700V, the carrier frequency is 2000Hz, the modulation ratio is 0.6, and the power factor is 0.4. The method of the present invention is used to simulate the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the action of space vector modulation. Figure 8a This is the simulation result of the whole process of DC bias elimination. Figure 8b This is the simulation result of a fundamental wave cycle during the DC bias elimination process. Figure 7a and Figure 8a , when there is a DC bias less than zero between the upper capacitor voltage and the lower capacitor voltage, under the condition of medium modulation ratio and medium power factor, the method of the present invention can make the DC bias quickly approach zero by moving the dual modulation wave of virtual space vector modulation. Therefore, under the condition of medium modulation ratio and medium power factor, the method of the present invention overcomes the defect that virtual space vector modulation cannot curb DC bias. In addition, compared Figure 7b and Figure 8b In the process of eliminating the DC bias, the method of the present invention reduces the switching frequency from 1350 Hz to 1200 Hz and reduces the current THD from 1.15% to 0.73%. Therefore, the method of the present invention does not increase the switching frequency and does not cause output current distortion.

[0152] Figure 9a , Figure 9b The capacitor voltage at the upper end of the level inverter of the third embodiment is 550V, the capacitor voltage at the lower end is 450V, the carrier frequency is 3000Hz, the modulation ratio is 0.98, the power factor is 0.2, and the method of the present invention is not used. The capacitor voltage DC bias, dual modulation wave, phase voltage and current under the virtual space vector modulation are shown. Among them, Figure 9a is the simulation result of the whole process. Figure 9b is the simulation result within one fundamental wave cycle. The modulation ratio of 0.98 and the power factor of 0.2 correspond to the high modulation ratio and low power factor. Figure 9a It is known that when there is a DC bias greater than zero between the upper capacitor voltage and the lower capacitor voltage, under the conditions of high modulation ratio and low power factor, if the method of the present invention is not used, the virtual space vector modulation cannot control the upper capacitor voltage and the lower capacitor voltage to restore balance, thereby affecting the output performance of the three-level inverter.

[0153] Fig.10a , Fig.10b In the third embodiment, the upper capacitor voltage of the level inverter is 550V, the lower capacitor voltage is 450V, the carrier frequency is 3000Hz, the modulation ratio is 0.98, and the power factor is 0.2. The method of the present invention is used to simulate the capacitor voltage DC bias, dual modulation wave, phase voltage and current under the action of space vector modulation. Fig.10a This is the simulation result of the whole process of DC bias elimination. Fig.10b This is the simulation result of a fundamental wave cycle during the DC bias elimination process. Figure 9a and Fig.10a , when there is a DC bias greater than zero between the upper capacitor voltage and the lower capacitor voltage, under the condition of high modulation ratio and low power factor, the method of the present invention can make the DC bias quickly approach zero by moving the dual modulation wave of virtual space vector modulation. Therefore, under the condition of high modulation ratio and high power factor, the method of the present invention overcomes the defect that virtual space vector modulation cannot curb DC bias. In addition, compared Figure 9b and Fig.10b In the process of eliminating DC bias, the method of the present invention reduces the switching frequency from 2000 Hz to 1925 Hz, and the current THD is 0.753% and 0.752% respectively. Therefore, the method of the present invention does not increase the switching frequency additionally and does not cause output current distortion.

[0154] Comprehensive analysis Figures 5a to 10b The results of the embodiment prove the effectiveness of the method for eliminating the capacitor voltage DC bias of the virtual space vector modulation of the present invention. Regardless of whether the DC bias is greater than zero or less than zero, under low modulation ratio, high power factor, or medium modulation ratio, medium power factor, or high modulation ratio, low power factor, the method of the present invention can make the DC bias quickly approach zero. Therefore, the method of the present invention can eliminate the capacitor voltage DC bias under any modulation ratio and power factor, and will not cause output current distortion and will not increase the switching frequency additionally, which significantly improves the practicality and reliability of the virtual space vector modulation. In addition, the method of the present invention eliminates the DC bias by moving the dual modulation wave, which also has the advantages of simple calculation and easy implementation.

[0155] The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A method for eliminating DC bias of capacitor voltage using virtual space vector modulation, characterized in that: The following steps are involved: Compare the size of the virtual space vector modulation three-phase dual modulation wave to obtain the positive maximum value VS of the three-phase dual modulation wave maxP , negative minimum VS minN , positive middle value VS midP and negative intermediate values ​​VS midN ; Compare the maximum values ​​SIN of the three-phase sine waves max and the minimum absolute value SIN minabs , and combined with the positive maximum value VS maxP , the negative minimum value VS minN , the positive middle value VS midP , the negative intermediate value VS midN The DC bias elimination regions are divided into eight categories according to the size relationship of Based on different DC bias elimination areas, the maximum value UP of the dual modulation wave is calculated respectively. max The maximum value DN of the double modulation wave downshift max ; By determining the direction of the product of the capacitor current and the capacitor voltage DC bias, the dual modulation wave displacement flag VSflag is obtained; According to the dual modulation wave displacement flag VSflag, each dual modulation wave shifts up to the maximum value UP max And each dual modulation wave downshift maximum DN max , determine the positive maximum value VS maxP The displacement value, the negative minimum value VS minN The displacement value, the positive middle value VS midP The displacement value and the negative intermediate value VS midN The displacement value of Based on the positive maximum value VS maxP The displacement value, the negative minimum value VS minN The displacement value, the positive middle value VS midP The displacement value and the negative intermediate value VS midN The displacement value moves the specific dual modulation wave to eliminate the DC bias of the capacitor voltage; Compare the maximum values ​​SIN of the three-phase sine waves max and the minimum absolute value SIN minabs , and combined with the positive maximum value VS maxP , the negative minimum value VS minN , the positive middle value VS midP , the negative intermediate value VS midN The method of dividing the DC bias elimination area into eight categories includes: When the maximum value SIN max ≥Minimum absolute value SIN minabs hour: When the negative minimum value VS minN +1 ≥ the positive maximum value VS maxP , the current region is divided into the first type of DC bias elimination region; otherwise, when the negative intermediate value VS midN +1 ≥ the positive maximum value VS maxP , divide the current area into the second type of DC bias elimination area; otherwise, when the negative minimum value VS minN +1 ≥ the positive median value VS midP , the current area is divided into the third type of DC bias elimination area; otherwise, the current area is divided into the fourth type of DC bias elimination area; When the maximum value SIN max <Minimum absolute value SIN minabs hour: When the negative minimum value VS minN +1 ≥ the positive maximum value VS maxP , the current region is divided into the fifth type of DC bias elimination region; otherwise, when the negative minimum value VS minN +1 ≥ the positive median value VS midP , the current region is divided into the sixth type of DC bias elimination region; otherwise, when the negative intermediate value VS midN +1 ≥ the positive maximum value VS maxP , the current area is divided into the seventh category of DC bias elimination area; otherwise, the current area is divided into the eighth category of DC bias elimination area; According to the dual modulation wave displacement flag VSflag, each dual modulation wave shifts up to the maximum value UP max And each dual modulation wave downshift maximum DN max , determine the positive maximum value VS maxP The displacement value, the negative minimum value VS minN The displacement value, the positive middle value VS midP The displacement value and the negative intermediate value VS midN Methods for finding displacement values ​​include: When the dual modulation wave shift flag VSflag=1, the dual modulation wave shifts up to the maximum value UP max Determine the displacement value, specifically: Let the positive maximum value VS maxP and the negative minimum value VS minN The displacement value is the maximum value of the double modulation wave UP max ; When 1+the negative minimum value VS minN ≥ the positive median value VS midP , and the maximum value SIN max ≥Minimum absolute value SIN minabs When the negative intermediate value VS midN The displacement value is the maximum value of the double modulation wave UP max , the positive middle value VS midP The displacement value of is 0; When 1+the negative minimum value VS minN ≥ the positive median value VS midP , and the maximum value SIN max <Minimum absolute value SIN minabs When the positive intermediate value VS midP The displacement value is the maximum value of the double modulation wave UP max , the negative intermediate value VS midN The displacement value of is 0; When 1+the negative minimum value VS minN <The positive middle value VS midP When the positive intermediate value VS midP and the negative intermediate value VS midN The displacement value is the maximum value of the double modulation wave UP max / 2; When the dual modulation wave shift flag VSflag = -1, the dual modulation wave is shifted down to the maximum value DN max Determine the displacement value, specifically: Let the positive maximum value VS maxP and the negative minimum value VS minN The displacement value is -DN max ; When 1+the negative middle value vs minN ≥ the positive median value VS midP , and the maximum value SIN max ≥Minimum absolute value SIN minabs When the negative intermediate value VS midN The displacement value is -DN max VS midP The displacement value of is 0; When 1+the negative middle value vs minN ≥ the positive median value VS midP , and the maximum value SIN max <Minimum absolute value SIN minabs When the positive intermediate value VS midP The displacement value is -DN max , the negative intermediate value VS midN The displacement value of is 0; When 1+the negative middle value vs minN <The positive middle value VS midP When the positive intermediate value VS midP and the negative intermediate value VS midN The displacement value is -DN max / 2.

2. The method for eliminating the capacitor voltage DC bias of virtual space vector modulation according to claim 1, characterized in that: Compare the size of the virtual space vector modulation three-phase dual modulation wave to obtain the positive maximum value VS of the three-phase dual modulation wave maxP , negative minimum VS minN , positive middle value VS midP and negative intermediate values ​​VS midN The methods include: When the three-level inverter uses virtual space vector modulation, set the modulation wave on phase A of the virtual space vector modulation to VS AP , the modulation wave in phase A is VS AN , the modulation wave on phase B is VS BP , the modulation wave in phase B is VS BN , the modulation wave on phase C is VS CP , the modulation wave in phase C is VS CN ; When VS AP ≥VS BP , and VS AP ≥VS CP When, let the positive maximum value VS maxP =VS AP ; Otherwise when VS BP ≥VS AP , and VS BP ≥VS CP When, let the positive maximum value VS maxP =VS BP ; Otherwise, let the positive maximum value VS maxP =VS CP ; When VS AN <VS BN , and VS AN <VS CN When the negative minimum value VS minN =VS AN ; Otherwise when VS BN <VS AN , and VS BN <VS CN When the negative minimum value VS minN =VS BN ; Otherwise, let the negative minimum value VS minN =VS CN ; When VS AP <Positive maximum value VS maxP , and VS AN > Negative minimum VS minN When, let the middle value VS midP =VS AP , negative intermediate value VS midN =VS AN ; Otherwise when VS BP <Positive maximum value VS maxP , and VS BN > Negative minimum VS minN When, let the middle value VS midP =VS BP , negative intermediate value VS midN =VS BN ; Otherwise, let the middle value VS midP =VS CP , negative intermediate value VS midN =VS CN .

3. The method for eliminating the capacitor voltage DC bias of virtual space vector modulation according to claim 1, characterized in that: Compare the maximum values ​​SIN of the three-phase sine waves max and the minimum absolute value SIN minabs The methods include: Set the A-phase sine wave of the virtual space vector modulation to SIN A , the B-phase sine wave is SIN B , the C phase sine wave is SIN C ; When SIN A ≥SIN B , and SIN A ≥SIN C When the maximum value SIN max =SIN A ; Otherwise when SIN B ≥SIN A , and SIN B ≥SIN C When the maximum value SIN max =SIN B ; Otherwise, let the maximum value SIN max =SIN C ; When SIN A <SIN B , and SIN A <SIN C When the minimum absolute value SIN minabs =1+SIN A ; Otherwise when SIN B <SIN A , and SIN B <SIN C When the minimum absolute value SIN minabs =1+SIN B ; Otherwise, let the minimum absolute value SIN minabs =1+SIN C .

4. The method for eliminating the capacitor voltage DC bias of virtual space vector modulation according to claim 1, characterized in that: Based on different DC bias elimination areas, the maximum value UP of the dual modulation wave is calculated respectively. max The maximum value DN of the double modulation wave downshift max The methods include: For the first type of DC bias elimination area, let the dual modulation wave shift up to the maximum value UP max =-VS midN , Double modulation wave downshift maximum value DN max =VS maxP -VS midP ; For the second type of DC bias elimination area, let the dual modulation wave shift up to the maximum value UP max =-VS midN , double modulation wave downshift maximum value DN max =1+VS minN -VS midP ; For the third type of DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1-VS maxP , double modulation wave downshift maximum value DN max =1+VS minN -VS midP ; For the fourth and eighth types of DC offset elimination regions, the dual modulation wave is shifted up to the maximum value UP max =1-VS maxP , double modulation wave downshift maximum value DN max =1+VS minN ; For the fifth type of DC bias elimination area, let the dual modulation wave shift up to the maximum value UP max =VS midN -VS minN , double modulation wave downshift maximum value DN max =VS midP ; For the sixth type of DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1+VS midN -VS maxP , double modulation wave downshift maximum value DN max =VS midP ; For the seventh category DC bias elimination area, let the dual modulation wave move up to the maximum value UP max =1+VS midN -VS maxP , double modulation wave downshift maximum value DN max =1+VS minN .

5. The method for eliminating the capacitor voltage DC bias of virtual space vector modulation according to claim 1, characterized in that: The method of obtaining the dual modulation wave displacement flag VSflag by determining the direction of the product of the capacitor current and the capacitor voltage DC bias includes: Set the capacitor current to I cap , capacitor voltage DC bias is U caperr ; When I cap with U caperr When the product of is greater than zero, set VSflag = 1; otherwise, when I cap with U caperr When the product is less than zero, set VSflag = -1.

6. The method for eliminating the capacitor voltage DC bias of virtual space vector modulation according to claim 5, characterized in that: Determine the capacitor current I cap The method is: Set the output current of phase A to I A , the output current of phase B is I B , the output current of phase C is I C ; When the maximum value SIN max ≥Minimum absolute value SIN minabs hour: This SIN A ≥0,Rei I cap =I A ; Otherwise when SIN B ≥0, let I cap =I B ;otherwise Order I cap =I C ; When the maximum value SIN max <Minimum absolute value SIN minabs hour: This SIN A <0, order I cap =-I A ; Otherwise when SIN B <0, let I cap =-I B ;otherwise Order I cap =-I C ; Determine the capacitor voltage DC bias U caperr The method is: Set the upper capacitor voltage to U capup , the lower capacitor voltage is U capdn ; U capup -U capdn )≥0 hours, U caperr = 1; Otherwise, when (U capup -U capdn )<0, let U caperr =-1.

7. The method for eliminating the capacitor voltage DC bias of virtual space vector modulation according to claim 2, characterized in that: Based on the positive maximum value VS maxP The displacement value, the negative minimum value VS minN The displacement value, the positive middle value VS midP The displacement value and the negative intermediate value VS midN Methods for moving a specific dual modulation wave by a displacement value and eliminating the DC bias of the capacitor voltage include: When the positive maximum value VS maxP =VS AP When, based on the positive maximum value VS maxP The displacement value of the move VS AP ; Otherwise when the negative intermediate value VS minN =VS AN When, based on the negative intermediate value VS minN The displacement value of the move VS AN ; Otherwise, based on the positive intermediate value VS midP and the negative intermediate value VS midN The displacement values ​​are respectively moved VS AP and VS AN ; When the positive maximum value VS maxP =VS BP When, based on the positive maximum value VS maxP The displacement value of the move VS BP ; Otherwise when the negative intermediate value VS minN =VS BN When, based on the negative intermediate value VS minN The displacement value of the move VS BN ; Otherwise, based on the positive intermediate value VS midP and the negative intermediate value VS midN The displacement values ​​are respectively moved VS BP and VS BN ; When the positive maximum value VS maxP =VS CP When, based on the positive maximum value VS maxP The displacement value of the move VS CP ; Otherwise when the negative intermediate value VS minN =VS CN When, based on the negative intermediate value VS minN The displacement value of the move VS CN ; Otherwise, based on the positive intermediate value VS midP and the negative intermediate value VS midN The displacement values ​​are respectively moved VS CP and VS CN .

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