A clock data recovery circuit, a clock signal adjustment method and a display chip

Abstract

The present invention discloses a clock data recovery circuit, a method for adjusting a clock signal, and a display chip. In the clock data recovery circuit, when a digital controller detects that the frequency of a data signal has changed, it outputs a mode selection switch signal according to the detection result, and generates a target frequency control signal based on the level state of the frequency adjustment mode signal; the current source circuit outputs a first current signal under the control of the mode selection switch signal and the target frequency control signal; the clock generation module generates a target clock signal according to the first current signal under the control of the switching control signal. Through the above method, the broadband output of the target clock signal can be achieved to adapt to different data transmission modes, and there is no need to set multiple groups of current source branches, which reduces the circuit area overhead and circuit power consumption.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a clock data recovery circuit, a clock signal adjustment method and a display chip. Background Art

[0002] In a serial communication display system, the transmitter generates a data signal according to a fixed transmission frequency and transmits the data signal to the receiver. After receiving the data signal, the receiver reads the data signal according to a clock signal synchronized with the transmission frequency of the transmitter to ensure the correctness of the data signal reading result. Therefore, a clock and data recovery circuit (CDR) is usually set in the receiver to recover the transmission frequency and clock signal of the transmitter to achieve correct reading of the data signal.

[0003] In order to reduce the area overhead and power consumption of the clock data recovery circuit, a clock data recovery circuit based on a single loop system is proposed in the related art. The clock data recovery circuit does not need to introduce an additional reference clock and can achieve frequency locking through the frequency of the input data signal.

[0004] However, a variety of data transmission modes are defined in the display system, and different data transmission modes correspond to different data signal transmission rates, which results in different frequencies of clock signals output by the clock data recovery circuit. If the frequency of the clock signal output by the clock data recovery circuit is to be matched with each data transmission mode, more current source branches are required in the clock data recovery circuit, which will increase the area overhead of the clock data recovery circuit and is not conducive to integration. Summary of the invention

[0005] The present invention provides a clock data recovery circuit, a clock signal adjustment method and a display chip, which are used to solve the problem of large circuit area overhead caused by matching multiple data transmission modes in the clock data recovery circuit in the prior art.

[0006] In a first aspect, an embodiment of the present invention provides a clock data recovery circuit, comprising:

[0007] A digital controller, for outputting a mode selection switch signal according to a detection result when a change in the frequency of the data signal is detected, and generating a target frequency control signal based on a level state of the frequency adjustment mode signal;

[0008] a current source circuit, configured to output a first current signal under the control of the mode selection switch signal and the target frequency control signal;

[0009] A clock generation module, used to generate a target clock signal according to the first current signal under the control of a switching control signal;

[0010] The switching control signal is generated by the digital controller after outputting the target frequency control signal, the frequency of the target clock signal matches the frequency of the data signal, and the phase of the target clock signal matches the phase of the data signal.

[0011] The clock data recovery circuit provided by the embodiment of the present invention detects the frequency change of the data signal through a digital controller, generates a mode selection switch signal, and outputs a first current signal through a current source circuit under the control of the mode selection switch signal and the target frequency control signal, so that the clock generation module generates a target clock signal according to the first current signal. Since the first current signal is generated under the joint control of the mode selection switch signal and the target frequency control signal, it is not necessary to set multiple groups of current source branches in the current source circuit, and multiple first current signals adapted to different data transmission modes can be output, thereby realizing broadband output of the target clock signal, reducing circuit area overhead and circuit power consumption.

[0012] In an optional embodiment, the current source circuit includes a reference current source module and a current generating module, wherein:

[0013] The reference current source module is electrically connected to the digital controller and the current generating module respectively, and the current generating module is also electrically connected to the digital controller and the clock generating module respectively;

[0014] The reference current source module is used to output a first reference current signal under the control of the mode selection switch signal;

[0015] The current generating module is configured to output the first current signal based on the first reference current signal under the control of the target frequency control signal;

[0016] The digital controller is specifically used for:

[0017] If it is detected that the frequency of the data signal increases, the level of the mode selection switch signal is increased to increase the current value of the first reference current signal;

[0018] If it is detected that the frequency of the data signal becomes smaller, then the level of the mode selection switch signal is reduced to reduce the current value of the first reference current signal;

[0019] The mode selection switch signal includes a plurality of levels, and the level of the mode selection switch signal is positively correlated with the current value of the first reference current signal.

[0020] In the above embodiment, by setting a reference current source module in the current source circuit, the reference current source outputs a first reference current signal under the control of the mode selection switch signal, and the first current signal can be generated under the control of the target frequency control signal with the first reference current signal as the reference. In addition, by setting a multi-level mode selection switch signal, and adjusting the level of the mode selection switch signal according to the frequency change direction of the detected data signal, the current value of the first reference current signal is increased or decreased accordingly, thereby realizing the adjustment of the first current value and the target clock signal, expanding the output frequency of the clock data recovery circuit, and realizing broadband output.

[0021] In an optional embodiment, the reference current source module includes a reference current source and a current source mirror branch, and the current generation module includes a first current source branch and a second current source branch, wherein:

[0022] The reference current source is electrically connected to the current source mirror branch, and the current source mirror branch is electrically connected to the first current source branch, the second current source branch and the digital controller respectively;

[0023] The first current source branch is also electrically connected to the digital controller and the clock generation module respectively, and the second current source branch is also electrically connected to the digital controller and the clock generation module respectively;

[0024] The reference current source is used to output a second reference current signal;

[0025] The current source mirror branch is used to adjust the number of mirror current sources working in the current source mirror branch under the control of the mode selection switch signal, and output the first reference current signal based on the second reference current signal;

[0026] The first current source branch is used to adjust the number of first current sources working in the first current source branch under the control of a first frequency control signal to output a first current sub-signal;

[0027] The second current source branch is used to adjust the number of second current sources working in the second current source branch under the control of a second frequency control signal to output a second current sub-signal;

[0028] Among them, the current value of the first reference current signal is a multiple of the current value of the second reference current signal, the target frequency control signal includes the first frequency control signal and the second frequency control signal, the first current signal is determined based on the first current sub-signal and the second current sub-signal, and the current value of the first current sub-signal is greater than the current value of the second current sub-signal.

[0029] In the above embodiment, under the control of the mode selection switch signal, at least one mirror current source in the current source mirror branch is turned on to make it work, and the second reference current signal output by the reference current source is used as the mirror reference of the working mirror current source to generate a first reference current signal, thereby realizing the adjustment of the first reference current signal. In addition, the current generating module adjusts the current value of the first current signal by coarse adjustment and fine adjustment to adjust the frequency of the clock signal generated by the clock generating module. Among them, the first current source branch adjusts the output first current sub-signal under the control of the first frequency control signal to change the frequency of the clock signal, that is, the frequency adjustment is performed by the coarse adjustment method, so that the frequency of the generated clock signal can quickly approach the frequency of the data signal. The second current source branch adjusts the output second current sub-signal under the control of the second frequency control signal to change the frequency of the clock signal, that is, the frequency adjustment is performed by the fine adjustment method, so that the frequency of the generated clock signal can accurately lock the frequency of the data signal, thereby realizing the frequency locking of the clock signal.

[0030] In an optional embodiment, the digital controller is specifically used for:

[0031] If the level state of the frequency adjustment mode signal is the first level state, outputting a preset target frequency control signal;

[0032] If the level state of the frequency adjustment mode signal is the second level state, generating the target frequency control signal according to the frequency of the data signal and the frequency of the first clock signal;

[0033] The first clock signal is generated by the clock generation module according to the first current signal when the clock generation module does not receive the switching control signal.

[0034] In the above embodiment, the frequency adjustment mode signal is set to select different target frequency control signal generation modes according to different level states of the frequency adjustment mode signal, thereby realizing flexible control of frequency adjustment.

[0035] In an optional embodiment, if the level state of the frequency adjustment mode signal is the second level state, the digital controller is specifically used to:

[0036] Detecting a first count value, wherein the first count value is used to represent the number of times the digital controller outputs the first frequency control signal;

[0037] If it is detected that the first count value is less than a first preset value, adjusting the level of the first frequency control signal according to the first frequency difference so that the first current sub-signal changes;

[0038] If it is detected that the first count value is greater than or equal to the first preset value, the first frequency difference is detected, and according to the detection result, the mode selection switch signal is adjusted, or the current first frequency control signal is locked, and the locked first frequency control signal is used as the target frequency signal;

[0039] The first frequency difference is the difference between the frequency of the data signal and the frequency of the current first clock signal, the first frequency control signal includes a plurality of levels, and the level of the first frequency control signal is positively correlated with the current value of the first current sub-signal.

[0040] In the above embodiment, the digital controller adjusts the first frequency control signal according to the first frequency difference. Specifically, if the first frequency difference is detected to be a positive value, it means that the frequency of the data signal is greater than the frequency of the current first clock signal, and the level of the first frequency control signal is increased to increase the first current signal, so that the frequency of the first clock signal increases rapidly. If the first frequency difference is detected to be a negative value, it means that the frequency of the data signal is less than the frequency of the current first clock signal, and the level of the first frequency control signal is reduced to reduce the first current signal, so that the frequency of the first clock signal decreases rapidly. In the above manner, the frequency of the adjusted first clock signal can be made closer to the frequency of the data signal, and the frequency can be rapidly approached.

[0041] In an optional embodiment, if it is detected that the first count value is greater than or equal to the first preset value, the digital controller is specifically configured to:

[0042] If it is detected that the first frequency difference is within a first preset threshold range, locking the current first frequency control signal, and using the locked first frequency control signal as the target frequency signal;

[0043] If it is detected that the first frequency difference is outside the first preset threshold range, the mode selection switch signal is adjusted.

[0044] In the above embodiment, when the digital controller outputs the first frequency control signal of the first preset value times, the first frequency difference is detected. If the numerical controller detects that the first frequency difference is within the first preset threshold range, it means that the frequency of the data signal is close to the frequency of the first clock signal, and the purpose of coarse adjustment is achieved, and the frequency locking operation can be performed. Otherwise, it means that the frequency of the data signal is still far from the frequency of the first clock signal, which exceeds the lockable range, and it is necessary to adjust the mode selection switch signal to change the reference for generating the first current signal, and perform coarse adjustment again. Rapid frequency approximation can be achieved in the above manner.

[0045] In an optional embodiment, the digital controller is further used for:

[0046] When it is detected that the first count value is greater than or equal to the first preset value and less than a second preset value, adjusting the first frequency control signal according to the first frequency difference, and continuously detecting the first frequency difference;

[0047] If it is detected that the first frequency difference is outside the first preset threshold range within a first time period, adjusting the mode selection switch signal;

[0048] If it is not detected that the first frequency difference is outside the first preset threshold range within the first time period, the current first frequency control signal is locked, and the locked first frequency control signal is used as the target frequency signal;

[0049] The first time duration is the time duration required for the first count value to change from the first preset value to the second preset value.

[0050] In the above embodiment, by continuously detecting the first frequency difference for a first time period, and when it is determined that the first frequency difference is within the first preset threshold range within the first time period, it can be determined that the frequency of the data signal and the frequency of the first clock signal remain stably close. At this time, the frequency is locked to avoid the occurrence of frequency mislock or loss of lock, thereby achieving precise frequency locking.

[0051] In an optional embodiment, after locking the first frequency control signal, the digital controller is specifically used to:

[0052] Detecting a second count value, wherein the second count value is used to represent the number of times the digital controller outputs the second frequency control signal;

[0053] If it is detected that the second count value is less than a third preset value, adjusting the level of the second frequency control signal according to the first frequency difference so that the second current sub-signal changes;

[0054] If it is detected that the second count value is greater than or equal to the third preset value, the first frequency difference is detected, and according to the detection result, the mode selection switch signal is adjusted, or the current second frequency control signal is locked, and the locked second frequency control signal is used as the target frequency signal;

[0055] The second frequency control signal includes a plurality of levels, and the level of the second frequency control signal is positively correlated with the current value of the second current sub-signal.

[0056] In the above embodiment, the digital controller adjusts the second frequency control signal according to the first frequency difference. Specifically, if the first frequency difference is detected to be a positive value, it means that the frequency of the data signal is greater than the frequency of the current first clock signal, and the level of the second frequency control signal is increased to increase the first current signal, so that the frequency of the first clock signal slowly increases. If the first frequency difference is detected to be a negative value, it means that the frequency of the data signal is less than the frequency of the current first clock signal, and the level of the second frequency control signal is reduced to reduce the first current signal, so that the frequency of the first clock signal slowly decreases. In the above manner, the frequency of the adjusted first clock signal can be made closer to the frequency of the data signal, thereby achieving accurate determination of the frequency.

[0057] In an optional embodiment, if it is detected that the second count value is greater than or equal to the third preset value, the digital controller is specifically configured to:

[0058] If it is detected that the second frequency difference is within the second preset threshold range, locking the current second frequency control signal, and using the locked second frequency control signal as the target frequency signal;

[0059] If it is detected that the second frequency difference is outside the second preset threshold range, adjusting the mode selection switch signal;

[0060] The first preset threshold range includes the second preset threshold range.

[0061] In the above embodiment, when the digital controller outputs the second frequency control signal of the third preset value times, the first frequency difference is detected. If the numerical controller detects that the first frequency difference is within the second preset threshold range, it means that the frequency of the data signal is close to the frequency of the first clock signal, that is, it is considered that the frequency of the data signal is consistent with the frequency of the first clock signal, and the purpose of fine adjustment is achieved, and the frequency locking operation can be performed. Otherwise, it means that the frequency of the data signal is still significantly different from the frequency of the first clock signal, which exceeds the lockable range, and it is necessary to adjust the mode selection switch signal to change the reference for generating the first current signal, and perform fine adjustment again. Accurate determination of the frequency can be achieved in the above manner.

[0062] In an optional embodiment, the digital controller is further used for:

[0063] When it is detected that the second count value is greater than or equal to the third preset value and less than a fourth preset value, adjusting the second frequency control signal according to the first frequency difference, and continuously detecting the first frequency difference;

[0064] If it is detected that the first frequency difference is outside the second preset threshold range within the second time period, adjusting the mode selection switch signal;

[0065] If it is not detected that the first frequency difference is outside the second preset threshold range within the second time period, the current second frequency control signal is locked, and the locked second frequency control signal is used as the target frequency signal;

[0066] The second time duration is the time duration required for the second count value to change from the third preset value to the fourth preset value.

[0067] In the above embodiment, by continuously detecting the first frequency difference for a second time period, and when it is determined that the first frequency difference is within the second preset threshold range within the second time period, it can be determined that the frequency of the data signal and the frequency of the first clock signal remain stably close. At this time, the frequency is locked to avoid the occurrence of frequency mislock or loss of lock, thereby achieving precise frequency locking.

[0068] In an optional embodiment, after locking the second frequency control signal, the digital controller is specifically used to:

[0069] outputting the switching control signal;

[0070] The clock generation module is specifically used for:

[0071] Under the control of the switching control signal, a second clock signal is generated according to the first current signal; the phase of the data signal is compared with the phase of the second clock signal, and the second clock signal is adjusted according to the comparison result; the adjusted second clock signal is used as the target clock signal.

[0072] In the above embodiment, after frequency locking is achieved by coarse adjustment plus fine adjustment, the clock generation module is used to adjust the phase of the second clock signal, and the second clock signal after the phase adjustment is completed is used as the target clock signal to determine the target clock signal. The frequency and phase of the target clock signal generated in the above manner are close to the frequency and phase of the data signal, so that the target clock signal can be considered to have the same frequency and phase as the data signal, so that the receiving end can read the data signal according to the target clock signal to ensure the correctness of the data signal reading result.

[0073] In an optional embodiment, the clock generation module is specifically used for:

[0074] detecting a third count value, wherein the third count value is used to represent the number of times the clock generation module adjusts the second clock signal;

[0075] If it is detected that the third count value is less than a fifth preset value, adjusting the phase of the second clock signal according to the first phase difference value;

[0076] If it is detected that the third count value is greater than or equal to the fifth preset value, the first phase difference value is detected, and according to the detection result, the mode selection switch signal is adjusted, or the current second clock signal is locked, and the locked second clock signal is used as the target clock signal;

[0077] The first phase difference is the difference between the phase of the data signal and the phase of the current second clock signal.

[0078] In the above embodiment, the phase of the second clock signal is adjusted by the clock generation module, and after the phase is adjusted a fifth preset value times, the first phase difference is detected to perform a phase locking operation according to the detection result.

[0079] In a second aspect, an embodiment of the present invention provides a method for adjusting a clock signal, which is applied to a clock data recovery circuit as described in any one of the embodiments of the first aspect above, and the method includes:

[0080] When a change in the frequency of the data signal is detected, a mode selection switch signal is output according to the detection result, and a target frequency control signal is generated based on the level state of the frequency adjustment mode signal;

[0081] Under the control of the mode selection switch signal and the target frequency control signal, outputting a first current signal;

[0082] Under the control of the switching control signal, generating a target clock signal according to the first current signal;

[0083] The switching control signal is generated after the target frequency control signal is output, the frequency of the target clock signal matches the frequency of the data signal, and the phase of the target clock signal matches the phase of the data signal.

[0084] In a third aspect, an embodiment of the present invention provides a display chip, comprising a clock data recovery circuit as described in any one of the embodiments in the first aspect above.

[0085] In a fourth aspect, an embodiment of the present invention provides a display device, comprising a display chip as described in any one of the embodiments in the third aspect above.

[0086] For the technical effects that may be achieved by the clock signal adjustment method disclosed in the second aspect, the display chip disclosed in the third aspect, and the display device disclosed in the fourth aspect, please refer to the technical effects that can be achieved by the first aspect or various possible schemes in the first aspect, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0088] Figure 1 A schematic diagram of the module structure of a clock data recovery circuit provided by an embodiment of the present invention;

[0089] Figure 2 A schematic diagram of a module structure of a current source circuit provided by an embodiment of the present invention;

[0090] Figure 3 A schematic diagram of the internal structure of a current source circuit provided by an embodiment of the present invention;

[0091] Figure 4 A schematic diagram of the internal structure of another current source circuit provided by an embodiment of the present invention;

[0092] Figure 5 A schematic diagram of a circuit structure of a current source circuit provided by an embodiment of the present invention;

[0093] Figure 6 A schematic diagram of the internal structure of a digital controller provided by an embodiment of the present invention;

[0094] Figure 7 A schematic diagram of the internal structure of a clock generation module provided by an embodiment of the present invention;

[0095] Figure 8 A schematic diagram of a working process of frequency regulation by a digital controller provided in an embodiment of the present invention;

[0096] Fig. 9 A schematic diagram of a working process of frequency regulation by another digital controller provided in an embodiment of the present invention;

[0097] Fig.10 A schematic diagram of a working process of phase adjustment of a clock generation module provided in an embodiment of the present invention;

[0098] Fig.11 A schematic diagram of the working process of a method for adjusting a clock signal provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0099] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0100] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0101] As mentioned above, a variety of data transmission modes are defined in the display system. Different data transmission modes correspond to different data signal transmission rates (ie, frequencies), which results in different frequencies of clock signals output by the clock data recovery circuit.

[0102] In the prior art, if a clock data recovery circuit based on a single loop system is to meet the requirements of various data transmission modes, it is necessary to output clock signals of various frequencies, which requires that multiple current source branches be set in the clock data recovery circuit to meet the current requirements for generating clock signals of various frequencies. However, this will increase the area overhead of the clock data recovery circuit, increase the cost, and be unfavorable for integration.

[0103] In addition, as the transmission rate of the data signal is continuously switched, the frequency of the clock signal jumps, and the frequency variation range is large and uncertain, which can easily lead to mis-locking or failure to lock.

[0104] Based on this, the embodiments of the present invention provide a clock data recovery circuit, a clock signal adjustment method and a display chip, so as to reduce circuit area overhead and facilitate integration while adapting to multiple data transmission modes.

[0105] The purpose, features and advantages of the present invention will be further described in conjunction with the embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0106] The clock data recovery circuit provided by the present invention is specifically introduced below in conjunction with the accompanying drawings:

[0107] Figure 1 A schematic diagram of the module structure of a clock data recovery circuit is shown. Figure 1 As shown, the clock data recovery circuit 10 includes a digital controller 11, a current source circuit 12 and a clock generation module 13;

[0108] The digital controller 11 is electrically connected to the current source circuit 12 and the clock generation module 13 respectively, and the current source circuit 12 is also electrically connected to the clock generation module 13, wherein:

[0109] The digital controller 11 is used to output a mode selection switch signal M_SEL according to the detection result when the frequency of the data signal Din is detected to change, and generate a target frequency control signal based on the level state of the frequency adjustment method signal F_Adjust_Method;

[0110] The current source circuit 12 is used to output a first current signal under the control of the mode selection switch signal M_SEL and the target frequency control signal;

[0111] The clock generation module 13 is used to generate a target clock signal DClk_1 according to the first current signal under the control of the switching control signal Mode_Switch;

[0112] The switching control signal Mode_Switch is generated by the digital controller 11 after outputting the target frequency control signal. The frequency of the target clock signal DClk_1 matches the frequency of the data signal Din, and the phase of the target clock signal DClk_1 matches the phase of the data signal Din.

[0113] It should be noted that, in the embodiment of the present invention, the frequency of the target clock signal DClk_1 matches the frequency of the data signal Din, indicating that the frequency difference between the frequency of the target clock signal DClk_1 and the frequency of the data signal Din is within the allowable error range. Similarly, the phase of the target clock signal DClk_1 matches the phase of the data signal Din, indicating that the phase difference between the phase of the target clock signal DClk_1 and the phase of the data signal Din is within the allowable error range.

[0114] In some embodiments, the data signal Din is sent externally, for example, by a transmitting end.

[0115] In some embodiments, the frequency adjustment method signal F_Adjust_Method may be externally input, or may be configured in advance in the digital controller 11 , and the embodiment of the present invention does not impose any limitation on this.

[0116] The clock data recovery circuit provided by the embodiment of the present invention detects the frequency change of the data signal through a digital controller, generates a mode selection switch signal, and outputs a first current signal through a current source circuit under the control of the mode selection switch signal and the target frequency control signal, so that the clock generation module generates a target clock signal according to the first current signal.

[0117] Since the first current signal is generated under the joint control of the mode selection switch signal and the target frequency control signal, there is no need to set multiple groups of current source branches in the current source circuit, so that a variety of first current signals adapted to different data transmission modes can be output, thereby realizing wide-band output of the target clock signal and reducing circuit area overhead and circuit power consumption.

[0118] First, the circuit structure of the clock data recovery circuit provided by the embodiment of the present invention is specifically introduced:

[0119] A specific example of the circuit structure of the current source circuit 12 provided in an embodiment of the present invention is given below:

[0120] like Figure 2 As shown, the current source circuit 12 provided in the embodiment of the present invention includes a reference current source module 121 and a current generating module 122, wherein:

[0121] The reference current source module 121 is electrically connected to the current generating module 122 and the digital controller 11 respectively, and the current generating module 122 is also electrically connected to the digital controller 11 and the clock generating module 13 respectively;

[0122] The reference current source module 121 is used to output a first reference current signal under the control of the mode selection switch signal M_SEL;

[0123] The current generating module 122 is used to output a first current signal based on a first reference current signal under the control of a target frequency control signal.

[0124] In some embodiments, the current source circuit 12 has the following two possible circuit structures:

[0125] Structure 1:

[0126] Figure 3 A schematic diagram of the internal structure of a current source circuit 12 is shown. Figure 3 As shown, the reference current source module 121 includes a reference current source 1211 and a current source mirror branch 1212, and the current generating module 122 includes a first current source branch 1221 and a second current source branch 1222, wherein:

[0127] The reference current source 1211 is electrically connected to the current source mirror branch 1212; the current source mirror branch 1212 is also electrically connected to the digital controller 11, the first current source branch 1221 and the second current source branch 1222 respectively; the first current source branch 1221 is also electrically connected to the digital controller 11 and the clock generation module 13 respectively; the second current source branch 1222 is also electrically connected to the digital controller 11 and the clock generation module 13 respectively.

[0128] In some embodiments, the reference current source 1211 is used to output a second reference current signal.

[0129] In a specific implementation, first, the reference current source 1211 outputs a second reference current signal to the current source mirror branch 1212, and the current source mirror branch 1212 uses the second reference current signal as a current reference and outputs a first reference current signal to the first current source branch 1221 and the second current source branch 1222 respectively;

[0130] Then, after receiving the first reference current signal, the first current source branch 1221 uses it as a current reference and outputs a first current sub-signal; similarly, after receiving the first reference current signal, the second current source branch 1222 also uses it as a current reference and outputs a second current sub-signal;

[0131] Finally, a current addition operation is performed on the first current sub-signal and the second current sub-signal to generate a first current signal and send it to the clock generation module 13; the clock generation module 13 generates a target clock signal according to the first current signal.

[0132] Structure 2:

[0133] Figure 4 A schematic diagram of the internal structure of a current source circuit 12 is shown. Figure 4 As shown, the reference current source module 121 includes a reference current source 1211 and a current source mirror branch 1212; the current generating module 122 includes a first current source branch 1221 and a second current source branch 1222, wherein:

[0134] The reference current source 1211 is electrically connected to the current source mirror branch 1212; the current source mirror branch 1212 is also electrically connected to the digital controller 11 and the first current source branch 1221 respectively; the first current source branch 1221 is also electrically connected to the second current source branch 1222, the digital controller 11 and the clock generation module 13 respectively; the second current source branch 1222 is also electrically connected to the digital controller 11 and the clock generation module 13 respectively.

[0135] In some embodiments, the reference current source 1211 is used to output a second reference current signal.

[0136] In a specific implementation, first, the reference current source 1211 outputs a second reference current signal to the current source mirror branch 1212, and the current source mirror branch 1212 uses the second reference current signal as a current reference and outputs a first reference current signal to the first current source branch 1221;

[0137] Then, after receiving the first reference current signal, the first current source branch 1221 uses it as a current reference and outputs a first current sub-signal to the second current source branch 1222; after receiving the first current sub-signal, the second current source branch 1222 uses it as a current reference and outputs a second current sub-signal;

[0138] Finally, a current addition operation is performed on the first current sub-signal and the second current sub-signal to generate a first current signal and send it to the clock generation module 13; the clock generation module 13 generates a target clock signal according to the first current signal.

[0139] The following embodiments are all based on Figure 3 The current source circuit 12 shown is used as an example for explanation:

[0140] The following is a detailed introduction to each part of the current source circuit 12:

[0141] In some embodiments, Figure 5 As shown, the current source mirror branch 1212 includes r mirror current sources (S01, S02, ..., S0r) and first switches (K01, K02, ..., K0r) connected to each mirror current source (S01, S02, ..., S0r) in a one-to-one correspondence, wherein:

[0142] One end of the mirror current source (S01, S02, ..., S0r) is electrically connected to the output end of the reference current source 1211, and the other end of the mirror current source (S01, S02, ..., S0r) is electrically connected to one end of the first switch (K01, K02, ..., K0r);

[0143] The other end of the first switch (K01, K02, ..., K0r) is used to output a first reference current signal, and the controlled end of the first switch (K01, K02, ..., K0r) is used to receive a mode selection switch signal M_SEL.

[0144] In some embodiments, the current source mirror branch 1212 is used to adjust the number of mirror current sources operating in the current source mirror branch 1212 under the control of the mode selection switch signal M_SEL, and output a first reference current signal based on the second reference current signal, wherein the current value of the first reference current signal is a multiple of the current value of the second reference current signal.

[0145] In some embodiments, the mirror current sources (S01, S02, . . . , S0r) are current sources proportional to the reference current source 1211, and the ratios between the mirror current sources and the reference current source 1211 may be the same or different.

[0146] For example, assuming that the reference current source 1211 is a 50 μA current source, if the mirror current source S01 is also a 50 μA current source, then the reference current source 1211 and the mirror current source S01 have a 1:1 mirror ratio. If the mirror current source S02 is a 100 μA current source, then the reference current source 1211 and the mirror current source S02 have a 1:2 mirror ratio.

[0147] In a specific implementation, under the control of the mode selection switch signal M_SEL, one or more of the first switches (K01, K02, ..., K0r) are selectively closed, and the mirror current source connected to the closed first switch outputs a corresponding current signal to form a first reference current signal.

[0148] For example, assuming that the current source mirror branch 1212 includes four mirror current sources (S01, S02, S03, S04), and each mirror current source is in a 1:1 mirror ratio with the reference current source 1211, and assuming that the reference current source 1211 is a 50 μA current source:

[0149] If the mode selection switch signal M_SEL output by the digital controller 11 is 0001, the first switch K01 is closed, and the first switches (K02, K03, K04) are all opened. At this time, only the mirror current source S01 works, and the other mirror current sources do not work, and the output first reference current signal is 50μA;

[0150] If the mode selection switch signal M_SEL output by the digital controller 11 is 0011, the first switch K01 and the first switch K02 are closed, and the first switches (K03, K04) are both disconnected. At this time, the mirror current source S01 and the mirror current source S02 work, and the other mirror current sources do not work, and the output first reference current signal is 50μA×2=100μA.

[0151] In the above embodiment, under the control of the mode selection switch signal, at least one mirror current source in the current source mirror branch is turned on to make it work, and the second reference current signal output by the reference current source is used as the mirror reference of the working mirror current source to generate a first reference current signal, thereby realizing the adjustment of the first reference current signal.

[0152] In some embodiments, Figure 5As shown, the first current source branch 1221 includes m first current sources (S11, S12, ..., S1m) and second switches (K11, K12, ..., K1m) connected to each first current source (S11, S12, ..., S1m) in a one-to-one correspondence, wherein:

[0153] One end of the first current source (S11, S12, ..., S1m) is electrically connected to the output end of the current source mirror branch 1212, and the other end of the first current source (S11, S12, ..., S1m) is electrically connected to one end of the second switch (K11, K12, ..., K1m);

[0154] The other end of the second switch (K11, K12, ..., K1m) is used to output the first current sub-signal, and the controlled end of the second switch (K11, K12, ..., K1m) is used to receive the target frequency control signal.

[0155] In some embodiments, Figure 5 As shown, the second current source branch 1222 includes n second current sources (S21, S22, ..., S2n) and third switches (K21, K22, ..., K2n) connected one-to-one with each second current source (S21, S22, ..., S2n), wherein:

[0156] One end of the second current source (S21, S22, ..., S2n) is electrically connected to the output end of the current source mirror branch 1212, and the other end of the second current source (S21, S22, ..., S2n) is electrically connected to one end of the third switch (K21, K22, ..., K2n);

[0157] The other end of the third switch (K21, K22, ..., K2n) is used to output the second current sub-signal, and the controlled end of the third switch (K21, K22, ..., K2n) is used to receive the target frequency control signal.

[0158] The embodiment of the present invention does not impose any restriction on the size relationship among r, m and n.

[0159] In some embodiments, Figure 5 As shown, the target frequency control signal includes a first frequency control signal CCTW and a second frequency control signal FCTW, wherein the first frequency control signal CCTW is used to control the first current source branch 1221 , and the second frequency control signal FCTW is used to control the second current source branch 1222 .

[0160] In some embodiments, the first current source branch 1221 is used to adjust the number of first current sources operating in the first current source branch 1221 under the control of the first frequency control signal CCTW to output a first current sub-signal.

[0161] In a specific implementation, under the control of the first frequency control signal CCTW, one or more of the second switches (K11, K12, ..., K1m) are selectively closed, and the first current source connected to the closed second switch outputs a corresponding current signal to form a first current sub-signal.

[0162] For example, assuming that the first reference current signal output by the current source mirror branch 1212 is 50 μA, and assuming that the first current source branch 1221 includes four first current sources (S11, S12, S13, S14), and each first current source is in a 1:1 mirror ratio with the mirror current source:

[0163] If the first frequency control signal CCTW output by the digital controller 11 is 0001, the second switch K11 is closed, and the second switches (K12, K13, K14) are all opened. At this time, only the first current source S11 works, and the other first current sources do not work, and the output first current sub-signal is 50μA;

[0164] If the first frequency control signal CCTW output by the digital controller 11 is 0101, the second switch K11 and the second switch K13 are closed, and the second switches (K12, K14) are both disconnected. At this time, the first current source S11 and the first current source S13 are working, and the other first current sources are not working, and the output first current sub-signal is 50μA×2=100μA.

[0165] In some embodiments, the second current source branch 1222 is used to adjust the number of second current sources operating in the second current source branch 1222 under the control of the second frequency control signal FCTW to output a second current sub-signal, wherein the current value of the first current sub-signal is greater than the current value of the second current sub-signal.

[0166] Similarly, under the control of the second frequency control signal FCTW, one or more of the third switches (K21, K22, . . . , K2n) are selectively closed, and the second current source connected to the closed third switch outputs a corresponding current signal to form a second current sub-signal.

[0167] It should be noted that the currents output by the multiple current sources in each current source branch (including the current source mirror branch 1212, the first current source branch 1221 and the second current source branch 1222) in the embodiment of the present invention can increase successively, or decrease successively, or can be equal, that is, they can be flexibly set according to actual business needs, and the embodiment of the present invention does not impose any restrictions on this.

[0168] In the above embodiment, the current generating module 122 adjusts the current value of the first current signal by coarse adjustment and fine adjustment. The first current source branch 1221 adjusts the output first current sub-signal under the control of the first frequency control signal CCTW, that is, the frequency adjustment is performed by the coarse adjustment method. The second current source branch 1222 adjusts the output second current sub-signal under the control of the second frequency control signal FCTW, that is, the frequency adjustment is performed by the fine adjustment method.

[0169] After introducing the current source circuit 12, a specific example of the digital controller 11 provided by the embodiment of the present invention is given below:

[0170] Figure 6 A schematic diagram of the internal structure of a digital controller 11 is shown. Figure 6 As shown, the digital controller 11 includes a frequency adjustment module 111 and a transmission mode selection module 112, wherein:

[0171] The frequency adjustment module 111 is electrically connected to the transmission mode selection module 112, the clock generation module 13, the first current source branch 1221 and the second current source branch 1222 respectively, and is used to output a target frequency control signal;

[0172] The transmission mode selection module 112 is also electrically connected to the transmission mode selection module 112 for outputting a mode selection switch signal M_SEL.

[0173] It should be noted that the specific working process of the digital controller 11 will be described in detail in the subsequent part of the introduction to the working principle of the clock data recovery circuit.

[0174] After introducing the digital controller 11, a specific example of the clock generation module 13 provided in the embodiment of the present invention is given below:

[0175] Figure 7 A schematic diagram of the internal structure of the clock generation module 13 is shown. Figure 7 As shown, the clock generation module 13 includes a phase detector 131, a charge pump 132, a low pass filter 133 (Low Pass Filter, LPF), a voltage-to-current converter 134 and a voltage-controlled oscillator 135, wherein:

[0176] The phase detector 131, the charge pump 132, the low-pass filter 133, the voltage-current converter 134 and the voltage-controlled oscillator 135 are electrically connected in sequence. The voltage-controlled oscillator 135 is also electrically connected to the phase detector 131, the digital controller 11 and the current source circuit 12 respectively. The voltage-current converter 134 is also electrically connected to the digital controller 11.

[0177] In a specific implementation, the phase detector 131 is used to receive the data signal Din and multiple clock signals (EClk, DClk, LClk) output by the voltage-controlled oscillator 135, and compare the phase of the data signal Din with the phase of each clock signal (EClk, DClk, LClk), and output a pull-up pulse signal or a pull-down pulse signal;

[0178] A charge pump 132, used to obtain a low-frequency control signal according to the pull-up pulse signal or the pull-down pulse signal;

[0179] A low-pass filter 133, used for filtering the low-frequency control signal to obtain a phase control signal;

[0180] The voltage-to-current converter 134 is used to start working under the control of the switching control signal output by the digital controller 11, and output a second current signal according to the phase control signal;

[0181] The voltage controlled oscillator 135 is used to output a plurality of clock signals (EClk, DClk, LClk) according to the first current signal output by the current source circuit 12, or to output a target clock signal DClk_1 according to the first current signal and the second current signal.

[0182] Optionally, the phase detector 131 may be a BB phase detector (Bang-Bang Phase Detector, BBPD).

[0183] Then, based on Figure 1 to Figure 7 The clock data recovery circuit shown in the figure specifically introduces the working principle of the clock data recovery circuit:

[0184] It should be noted that the display device has multiple data transmission modes, for example, RBR mode, HBR mode, HBR2 mode, HBR3 mode, Vbyone mode, etc. In different data transmission modes, the frequency of the data signal sent from the transmitter to the receiver is also different. Therefore, the frequency of the target clock signal generated by the clock data recovery circuit 10 is also required to be different.

[0185] In some embodiments, the digital controller 11 detects the frequency of the received data signal Din, and when it detects that the frequency of the data signal Din changes, it controls the transmission mode selection module 112 to generate a corresponding mode selection switch signal M_SEL according to the frequency change direction of the data signal Din.

[0186] Optionally, the mode selection switch signal M_SEL is an r-bit digital signal, and the number of bits of the mode selection switch signal M_SEL is consistent with the number of first switches (K01, K02, ..., K0r) in the current source mirror branch 1212. Therefore, the mode selection switch signal M_SEL can be set to multiple levels, and the level of the mode selection switch signal M_SEL is positively correlated with the current value of the first reference current signal.

[0187] Specifically, the first-stage mode selection switch signal M_SEL corresponds to the minimum current value of the first reference current signal, and the last-stage mode selection switch signal M_SEL corresponds to the maximum current value of the first reference current signal.

[0188] In some embodiments, if the digital controller 11 detects that the frequency of the data signal Din increases, the transmission mode selection module 112 is controlled to increase the level of the mode selection switch signal M_SEL to increase the current value of the first reference current signal.

[0189] In a specific implementation, taking the mode selection switch signal M_SEL as 4 bits as an example, there are two implementation methods for adjusting the mode selection switch signal M_SEL:

[0190] Method 1:

[0191] If the first switches (K01, K02, K03, K04) are turned on under the control of a high level (1) and are turned off under the control of a low level (0), the mode selection switch signal M_SEL can be adjusted from 0000 to 1111, where 0000 is the first-level mode selection switch signal M_SEL and 1111 is the last-level mode selection switch signal M_SEL.

[0192] Exemplarily, assuming that the four mirror current sources (S01, S02, S03, S04) in the current source mirror branch 1212 increase in sequence, and assuming that the digital controller 11 detects that the frequency of the data signal Din increases, the transmission mode selection module 112 increases the level of the mode selection switch signal M_SEL, for example, from 0001 to 0010.

[0193] At this time, in the current source mirror branch 1212, the mirror current source S01 switches to the mirror current source S02. Since the current output by the mirror current source S02 is larger than the current output by the mirror current source S01, the first reference current signal output by the current source mirror branch 1212 becomes larger. Accordingly, the first current signal generated by the current generating module 122 will also become larger, and the frequency of the clock signal generated by the voltage-controlled oscillator 135 will also increase accordingly.

[0194] Method 2:

[0195] If the first switches (K01, K02, K03, K04) are turned on under the control of a low level (0) and turned off under the control of a high level (1), the mode selection switch signal M_SEL can be adjusted from 1111 to 0000, where 1111 is the first-level mode selection switch signal M_SEL and 0000 is the last-level mode selection switch signal M_SEL.

[0196] Exemplarily, assuming that the current source mirror branch 1212 includes four mirror current sources (S01, S02, S03, S04), and assuming that the digital controller 11 detects that the frequency of the data signal Din increases, the transmission mode selection module 112 increases the level of the mode selection switch signal M_SEL, for example, from 0111 to 0110.

[0197] At this time, in the current source mirror branch 1212, the mirror current source S04 is switched to both the mirror current source S04 and the mirror current source S01 working. Therefore, the first reference current signal output by the current source mirror branch 1212 becomes larger. Correspondingly, the first current signal generated by the current generating module 122 will also become larger, and the frequency of the clock signal generated by the voltage-controlled oscillator 135 will also increase accordingly.

[0198] In some embodiments, if the digital controller 11 detects that the frequency of the data signal Din decreases, the transmission mode selection module 112 is controlled to reduce the level of the mode selection switch signal M_SEL to reduce the current value of the first reference current signal.

[0199] It should be noted that the transmission mode selection module 112 adjusts the level of the mode selection switch signal M_SEL in a manner similar to the aforementioned manner of increasing the level of the mode selection switch signal M_SEL, and its implementation may refer to the aforementioned embodiment, and thus will not be described in detail.

[0200] In some embodiments, the clock data recovery circuit 10 further includes a register (not shown in the figure), in which a correspondence between a preset frequency value of a data signal and a mode selection switch signal is stored, wherein the frequency value of the data signal in the correspondence corresponds to each data transmission mode one by one.

[0201] If the digital controller 11 obtains or detects the frequency value of the data signal Din after the jump, it controls the transmission mode selection module 112 to directly output a mode selection switch signal corresponding to the frequency value.

[0202] If the digital controller 11 does not detect the frequency value of the data signal Din after the jump, the transmission mode selection module 112 is controlled to gradually increase or decrease the level of the mode selection switch signal to achieve frequency locking of the clock signal.

[0203] In the above-mentioned embodiment, a multi-level mode selection switch signal is set, and the level of the mode selection switch signal is adjusted according to the frequency change direction of the detected data signal to increase or decrease the current value of the first reference current signal accordingly, thereby realizing the adjustment of the first current value and the target clock signal, expanding the output frequency of the clock data recovery circuit, and realizing broadband output.

[0204] After the transmission mode selection module 112 outputs the mode selection switch signal M_SEL to the current source mirror branch 1212 , the digital controller 11 enters a global reset state and performs a reset operation on each signal inside it.

[0205] After the global reset of the digital controller 11 is completed, the level state of the frequency adjustment mode signal is detected, and the target frequency control signal is generated according to the detection result, as follows:

[0206] In some embodiments, if the digital controller 11 detects that the level state of the frequency adjustment mode signal is in the first level state, the frequency adjustment module 111 is controlled to output a preset target frequency control signal.

[0207] In some embodiments, if the digital controller 11 detects that the level state of the frequency adjustment mode signal is the second level state, the frequency adjustment module 111 is controlled to generate a target frequency control signal according to the frequency of the data signal and the frequency of the first clock signal.

[0208] The first clock signal is generated by the clock generation module 13 according to the first current signal when the switching control signal Mode_Switch is not received.

[0209] The first level state is level 0, and the second level state is level 1, or the first level state is level 1, and the second level state is level 0, and the embodiment of the present invention does not impose any limitation on this.

[0210] The following embodiments are described by taking the first level state as level 0 and the second level state as level 1 as an example:

[0211] In a specific implementation, the digital controller 11 determines its own frequency adjustment working mode according to the level state of the frequency adjustment mode signal. For example, if the digital controller 11 detects that the frequency adjustment mode signal is at level 0, it controls itself to enter the first frequency adjustment mode; if the digital controller 11 detects that the frequency adjustment mode signal is at level 1, it controls itself to enter the second frequency adjustment mode.

[0212] Among them, the first frequency adjustment mode represents that the digital controller 11 adopts an externally controlled frequency adjustment method. That is, after the digital controller 11 enters the first frequency adjustment mode, the first frequency control signal CCTW and the second frequency control signal FCTW outputted by the digital controller 11 are both externally input, or pre-configured in the register. Therefore, in this mode, the first frequency control signal CCTW and the second frequency control signal FCTW outputted by the digital controller 11 are fixed, and no adjustment is required, and the BB adjustment process can be directly entered (the specific implementation process of BB adjustment can be referred to the subsequent embodiments).

[0213] The second frequency adjustment mode indicates that the digital controller 11 adopts an internal adaptive frequency adjustment method. That is, after the digital controller 11 enters the second frequency adjustment mode, the first frequency control signal CCTW and the second frequency control signal FCTW outputted by the digital controller 11 are determined by repeated adjustment according to the frequency of the data signal Din. Therefore, in this mode, the digital controller 11 can determine the first frequency control signal CCTW and the second frequency control signal FCTW outputted by the digital controller 11 through repeated frequency adjustment, and can enter the BB adjustment process after the frequency adjustment is completed.

[0214] In the above embodiment, the frequency adjustment mode signal is set to select different target frequency control signal generation modes according to different level states of the frequency adjustment mode signal, thereby realizing flexible control of frequency adjustment.

[0215] Therefore, in order to generate the target clock signal, it is necessary to perform frequency adjustment and phase adjustment on the clock signal generated by the clock generation module 13, wherein:

[0216] The frequency adjustment process can be divided into 7 states: CCTW adjustment state, CCTW confirmation state, CCTW output state, FCTW reset state, FCTW adjustment state, FCTW confirmation state, FCTW output state;

[0217] The phase adjustment process can be divided into two states: BB adjustment state and BB completion state.

[0218] The frequency adjustment process of the digital controller 11 is specifically introduced below:

[0219] In the global reset state, the first frequency control signal CCTW and the second frequency control signal FCTW are both reset, and at this time, the digital controller 11 controls the voltage-to-current converter 134 in the clock generation module 13 to not work.

[0220] After the global reset state ends, and the level state of the frequency adjustment mode signal is the second level state, the CCTW adjustment state is entered, as follows:

[0221] In some embodiments, Figure 8 As shown, in the CCTW adjustment state, the specific working process of the frequency adjustment module 111 is as follows:

[0222] Step S801 , detecting a first count value, wherein the first count value is used to represent the number of times the digital controller 11 outputs the first frequency control signal CCTW.

[0223] In a specific implementation, a first counter is further provided in the digital controller 11 , and the first counter may be provided in the frequency adjustment module 111 or outside the frequency adjustment module 111 , and the embodiment of the present invention does not impose any limitation on this.

[0224] The number of times that the frequency adjustment module 111 in the digital controller 11 outputs the first frequency control signal CCTW is counted by the first counter, and the first count value of the first counter is detected in real time.

[0225] Step S802, if it is detected that the first count value is less than the first preset value, the first frequency control signal CCTW is adjusted according to the first frequency difference to change the first current sub-signal, wherein the first frequency difference is the difference between the frequency of the data signal and the frequency of the current first clock signal.

[0226] Optionally, the current first clock signal is the first clock signal sent by the clock generation module 13 to the digital controller 11 during the current round of adjustment.

[0227] In a specific implementation, when the count value of the first counter, that is, the first count value, does not reach the first preset value, the frequency adjustment module 111 adjusts the first frequency control signal CCTW according to the first frequency difference. The specific adjustment method is as follows:

[0228] In some embodiments, the first frequency control signal CCTW includes a plurality of levels, and the level of the first frequency control signal CCTW is positively correlated with the current value of the first current sub-signal.

[0229] In some embodiments, the frequency adjustment module 111 detects the first frequency difference; if the first frequency difference is a positive value, the level of the first frequency control signal CCTW is increased to increase the current value of the first current sub-signal; if the first frequency difference is a negative value, the level of the first frequency control signal CCTW is decreased to reduce the current value of the first current sub-signal.

[0230] In a specific implementation, the first frequency control signal CCTW may be an m-bit digital signal, and the number of bits of the first frequency control signal CCTW is consistent with the number of the second switches ( K11 , K12 , . . . , K1m ) in the first current source branch 1221 .

[0231] Therefore, the first frequency control signal CCTW can be set to multiple levels, and the level of the first frequency control signal CCTW is positively correlated with the current value of the first current sub-signal. That is, the first level of the first frequency control signal CCTW corresponds to the minimum current value of the first current sub-signal, and the last level of the first frequency control signal CCTW corresponds to the maximum current value of the first current sub-signal.

[0232] Exemplarily, taking the first frequency control signal CCTW as 4 bits as an example, the first current source branch 1221 includes four second switches (K11, K12, K13, K14):

[0233] If the second switches (K11, K12, K13, K14) are set to be turned on under the control of a high level (1) and turned off under the control of a low level (0), the first frequency control signal CCTW can be adjusted from 0000 to 1111, where 0000 is the first-level first frequency control signal CCTW and 1111 is the last-level first frequency control signal CCTW.

[0234] If the second switches (K11, K12, K13, K14) are set to be turned on under the control of a low level (0) and turned off under the control of a high level (1), the first frequency control signal CCTW can be adjusted from 1111 to 0000, where 1111 is the first-level first frequency control signal CCTW and 0000 is the last-level first frequency control signal CCTW.

[0235] Therefore, there are two ways to adjust the first frequency control signal CCTW:

[0236] Method 1:

[0237] The first frequency control signal CCTW is a digital signal adjusted from 0000 to 1111:

[0238] In a specific implementation, if the frequency adjustment module 111 detects that the first frequency difference is a positive value, it means that the frequency of the data signal is greater than the frequency of the current first clock signal, and the frequency of the first clock signal needs to be increased. Therefore, the first frequency control signal CCTW is increased to increase the first current signal, thereby rapidly increasing the frequency of the first clock signal.

[0239] For example, the first frequency control signal CCTW is adjusted from 0001 to 0010 to control the first sub-current output by the first current source branch 1221 to increase, thereby increasing the first current signal and the frequency of the first clock signal correspondingly increases.

[0240] If the frequency adjustment module 111 detects that the first frequency difference is a negative value, it means that the frequency of the data signal is less than the frequency of the current first clock signal, and the frequency of the first clock signal needs to be reduced. Therefore, the first frequency control signal CCTW is reduced to reduce the first current signal, so that the frequency of the first clock signal is quickly reduced.

[0241] For example, the first frequency control signal CCTW is adjusted from 0011 to 0010 to control the first sub-current output by the first current source branch 1221 to decrease, thereby reducing the first current signal and the frequency of the first clock signal correspondingly decreases.

[0242] Method 2:

[0243] The first frequency control signal CCTW is a digital signal adjusted from 1111 to 0000:

[0244] In a specific implementation, if the frequency adjustment module 111 detects that the first frequency difference is a positive value, it means that the frequency of the data signal is greater than the frequency of the current first clock signal, and the frequency of the first clock signal needs to be increased. Therefore, the first frequency control signal CCTW is reduced to increase the first current signal, thereby rapidly increasing the frequency of the first clock signal.

[0245] For example, the first frequency control signal CCTW is adjusted from 0111 to 0110 to control the first sub-current output by the first current source branch 1221 to increase, thereby increasing the first current signal and increasing the frequency of the first clock signal accordingly.

[0246] If the frequency adjustment module 111 detects that the first frequency difference is a negative value, it means that the frequency of the data signal is less than the frequency of the current first clock signal, and the frequency of the first clock signal needs to be reduced. Therefore, the first frequency control signal CCTW is increased to reduce the first current signal, so that the frequency of the first clock signal is quickly reduced.

[0247] For example, the first frequency control signal CCTW is adjusted from 0101 to 0110 to control the first sub-current output by the first current source branch 1221 to decrease, thereby reducing the first current signal and the frequency of the first clock signal correspondingly decreases.

[0248] In some embodiments, the frequency adjustment module 111 may also detect the difference between the frequency of the current first clock signal and the frequency of the data signal, and adjust the first frequency control signal CCTW according to the frequency difference. The specific adjustment process is similar to that of the aforementioned embodiment and will not be described in detail.

[0249] In addition, the specific implementation of the first current source branch 1221 increasing or decreasing the first current sub-signal output by itself under the control of the first frequency control signal CCTW can refer to the specific implementation of the control method of the current source mirror branch 1212 by the mode selection switch signal M_SEL, and therefore will not be repeated here and should not impose any limitations on the embodiments of the present invention.

[0250] By means of the above method, the frequency of the adjusted first clock signal can be made closer to the frequency of the data signal, thereby achieving rapid frequency approximation.

[0251] Step S803, if it is detected that the first count value is greater than or equal to the first preset value, the first frequency difference is detected, and according to the detection result, the mode selection switch signal M_SEL is adjusted, or the current first frequency control signal CCTW is locked, and the locked first frequency control signal is used as the target frequency signal.

[0252] In a specific implementation, when the count value of the first counter, that is, the first count value, reaches the first preset value, the frequency adjustment module 111 detects the first frequency difference, and executes subsequent processes based on the detection result, as follows:

[0253] In some embodiments, if the frequency adjustment module 111 detects that the first frequency difference is within the first preset threshold range, the current first frequency control signal CCTW is locked, and the locked first frequency control signal CCTW is used as the target frequency signal; if the frequency adjustment module 111 detects that the first frequency difference is outside the first preset threshold range, the adjustment mode selection switch signal M_SEL is adjusted.

[0254] In some embodiments, the digital controller 11 is provided with a first locking detection signal and a first error indication signal to indicate whether the first frequency locking is successful.

[0255] In a specific implementation, when the frequency adjustment module 111 detects that the first frequency difference is within the first preset threshold range, it means that the frequency of the data signal is relatively close to the frequency of the current first clock signal. At this time, the first lock detection signal will become a high level, and the first error indication signal will remain at a low level, to indicate that the first frequency lock is successful, that is, the CCTW adjustment state ends.

[0256] When the frequency adjustment module 111 detects that the first frequency difference is outside the first preset threshold range, it means that the frequency of the data signal is significantly different from the frequency of the current first clock signal and exceeds the frequency locking range of the voltage-controlled oscillator 135. At this time, the first locking detection signal will remain at a low level and the first error indication signal will become a high level to indicate that the first frequency locking failed, that is, the CCTW adjustment failed.

[0257] The first error indication signal is fed back to the transmission mode selection module 112 to control the transmission mode selection module 112 to adjust the level of the output mode selection switch signal M_SEL and restart the CCTW adjustment with reference to the above embodiment.

[0258] In the above embodiment, if the numerical controller detects that the first frequency difference is within the first preset threshold range, it means that the frequency of the data signal is close to the frequency of the first clock signal, and the purpose of coarse adjustment is achieved, and the frequency locking operation can be performed. Otherwise, it means that the frequency of the data signal is still far from the frequency of the first clock signal, which exceeds the lockable range, and it is necessary to adjust the mode selection switch signal to change the reference for generating the first current signal, and perform coarse adjustment again. The above method can achieve rapid frequency approximation.

[0259] Based on the above embodiment, there is another preferred implementation method to achieve locking of the first frequency control signal CCTW, which is as follows:

[0260] In some embodiments, when the frequency adjustment module 111 detects that the first count value is greater than or equal to the first preset value and less than the second preset value, the first frequency control signal CCTW is adjusted according to the first frequency difference, and the first frequency difference is continuously detected;

[0261] If the frequency adjustment module 111 detects that the first frequency difference is outside the first preset threshold range within the first time period, the mode selection switch signal M_SEL is adjusted, wherein the first time period is the time period required for the first count value to change from the first preset value to the second preset value;

[0262] If the frequency adjustment module 111 does not detect that the first frequency difference is outside the first preset threshold range within the first time period, the current first frequency control signal CCTW is locked and the locked first frequency control signal CCTW is used as the target frequency signal.

[0263] In a specific implementation, when the count value of the first counter, that is, the first count value, reaches the first preset value and the first lock detection signal becomes a high level, the CCTW adjustment state is maintained, that is, the frequency adjustment module 111 continues to adjust the first frequency control signal CCTW and continuously detects the first frequency difference.

[0264] At this time, the first counter continues to count, and during the period when the count value of the first counter changes from the first preset value to the second preset value, that is, during the first time period, the frequency adjustment module 111 continues to detect the level state of the first lock detection signal. If during this period, the first lock detection signal always maintains a high level, it means that the first frequency difference always remains within the first preset threshold range, the first frequency lock is successful, and the CCTW adjustment state ends.

[0265] If during this period, the first lock detection signal cannot maintain a high level, it means that the first frequency difference is outside the first preset threshold range, the first frequency lock fails, and the CCTW adjustment fails. At this time, the first error indication signal is changed to a high level and sent to the transmission mode selection module 112 to control the transmission mode selection module 112, adjust the level of the output mode selection switch signal M_SEL, and restart the CCTW adjustment with reference to the above embodiment.

[0266] In the above embodiment, by continuously detecting the first frequency difference for a first time period, and when it is determined that the first frequency difference is within the first preset threshold range within the first time period, it can be determined that the frequency of the data signal and the frequency of the first clock signal remain stably close. At this time, the frequency is locked to avoid the occurrence of frequency mislock or loss of lock, thereby achieving precise frequency locking.

[0267] In some embodiments, after the CCTW adjustment state ends, the frequency adjustment module 111 enters the CCTW determination state. In the CCTW determination state, the frequency adjustment module 111 detects the level state of the first output control signal, and outputs the locked first frequency control signal CCTW when the level state of the first output control signal jumps to the second level state.

[0268] In a specific implementation, the frequency adjustment module 111 outputs the first frequency control signal CCTW to the first current source circuit 1221 according to the first output control signal, that is, when the first output control signal jumps from a low level to a high level, that is, at the rising edge, the corresponding first frequency control signal CCTW is used as the locked first frequency control signal CCTW.

[0269] Specifically, when the frequency adjustment module 111 detects that the first output control signal is at a low level, the CCTW determination state is maintained; when the frequency adjustment module 111 detects that a rising edge of the first output control signal has arrived, the first frequency control signal CCTW is output and the CCTW determination state is ended.

[0270] Since the locked first frequency control signal CCTW may be a digital signal of a fixed level, or may be a digital signal that jumps between two adjacent levels. For example, if the frequency of the first clock signal generated when the first frequency control signal CCTW is 0011 is similar to the frequency of the first clock signal generated when the first frequency control signal CCTW is 0100, the first frequency control signal CCTW will jump between the two values ​​of 0011 and 0100. By using the first frequency control signal CCTW corresponding to the rising edge of the first output control signal as the locked first frequency control signal CCTW, repeated jumps of the first frequency control signal CCTW are avoided.

[0271] In some embodiments, after the CCTW determination state ends, the frequency adjustment module 111 enters the CCTW output state. In the CCTW output state, the frequency adjustment module 111 updates, stores and outputs the locked first frequency control signal CCTW based on the first update signal.

[0272] In a specific implementation, the frequency adjustment module 111 detects the level state of the first update signal. When the first update signal is detected to be at a low level, it indicates that the update storage of the first frequency control signal CCTW has not been completed, and the CCTW output state is maintained. Until the first update signal is detected to jump to a high level, it indicates that the update storage of the first frequency control signal CCTW has been completed, and the CCTW output state is ended. At this point, the entire first frequency adjustment process is completed.

[0273] During the first frequency adjustment process, the voltage-to-current converter 134 in the clock generation module 13 does not work, so that the phase detector 131, the charge pump 132 and the low-pass filter 133 in the front stage cannot work, and only the voltage-controlled oscillator 135 works normally, thereby reducing system power consumption.

[0274] After the CCTW output state ends, the FCTW reset state is entered. At this time, the specific working process of the frequency adjustment module 111 is as follows:

[0275] In some embodiments, in the FCTW reset state, the frequency adjustment module 111 performs a reset operation on the second frequency control signal FCTW according to the FCTW reset signal.

[0276] In a specific implementation, the frequency adjustment module 111 detects the level state of the FCTW reset signal. When the FCTW reset signal is detected to be at a low level, it indicates that the reset operation of the second frequency control signal FCTW has not been completed, and the FCTW reset state is maintained. Until it is detected that the FCTW reset signal jumps to a high level, it indicates that the reset operation of the second frequency control signal FCTW has been completed, the FCTW reset state is ended, and the FCTW adjustment state is entered.

[0277] In some embodiments, Fig. 9 As shown, in the FCTW adjustment state, the specific working process of the frequency adjustment module 111 is as follows:

[0278] Step S901 , detecting a second count value, wherein the second count value is used to represent the number of times the digital controller 11 outputs the second frequency control signal FCTW.

[0279] In a specific implementation, a second counter is further provided in the digital controller 11 , and the second counter may be provided in the frequency adjustment module 111 or outside the frequency adjustment module 111 , and the embodiment of the present invention does not impose any limitation on this.

[0280] The number of times that the frequency adjustment module 111 in the digital controller 11 outputs the second frequency control signal FCTW is counted by the second counter, and the second count value of the second counter is detected in real time.

[0281] Step S902 , if it is detected that the second count value is less than the third preset value, the second frequency control signal FCTW is adjusted according to the first frequency difference to change the second current sub-signal.

[0282] In a specific implementation, when the count value of the second counter, that is, the second count value, does not reach the third preset value, the frequency adjustment module 111 adjusts the second frequency control signal FCTW according to the first frequency difference. The specific adjustment method is as follows:

[0283] In some embodiments, the second frequency control signal FCTW includes a plurality of levels, and the level of the second frequency control signal FCTW is positively correlated with the current value of the second current sub-signal.

[0284] In some embodiments, the frequency adjustment module 111 detects the first frequency difference; if the first frequency difference is a positive value, the level of the second frequency control signal FCTW is increased to increase the current value of the second current sub-signal; if the first frequency difference is a negative value, the level of the second frequency control signal FCTW is decreased to reduce the current value of the second current sub-signal.

[0285] In a specific implementation, the second frequency control signal FCTW may be an n-bit digital signal, and the number of bits of the second frequency control signal FCTW is consistent with the number of third switches ( K21 , K22 , . . . , K2n ) in the second current source branch 1222 .

[0286] Therefore, the second frequency control signal FCTW can be set to multiple levels, and the level of the second frequency control signal FCTW is positively correlated with the current value of the second current sub-signal. That is, the first level of the second frequency control signal FCTW corresponds to the minimum current value of the second current sub-signal, and the last level of the second frequency control signal FCTW corresponds to the maximum current value of the second current sub-signal.

[0287] It should be noted that the specific setting method of the second frequency control signal FCTW is similar to the setting method of the first frequency control signal CCTW, and its specific implementation can refer to the relevant embodiments of the first frequency control signal CCTW, so it is not repeated here.

[0288] In a specific implementation, if the frequency adjustment module 111 detects that the first frequency difference is a positive value, it means that the frequency of the data signal Din is greater than the frequency of the current first clock signal, and the frequency of the first clock signal needs to be increased. Therefore, the level of the second frequency control signal FCTW is increased to increase the second current sub-signal output by the second current source branch 1222, thereby increasing the first current signal, and then slowly increasing the frequency of the first clock signal.

[0289] If the frequency adjustment module 111 detects that the first frequency difference is a negative value, it means that the frequency of the data signal Din is less than the frequency of the current first clock signal, and the frequency of the first clock signal needs to be reduced. Therefore, the level of the second frequency control signal FCTW is reduced to reduce the second current sub-signal output by the second current source branch 1222, thereby reducing the first current signal, and then slowly reducing the frequency of the first clock signal.

[0290] It should be noted that the specific implementation method of the second current source branch 1222 increasing or decreasing the second current sub-signal output by itself under the control of the second frequency control signal FCTW can refer to the specific implementation of the control method of the current source mirror branch 1212 by the mode selection switch signal M_SEL. Therefore, it will not be repeated here and it should not impose any limitations on the embodiments of the present invention.

[0291] Since the current value of the second current sub-signal is less than the current value of the first current sub-signal, in the process of FCTW adjustment, the second current sub-signal is slowly changed to achieve slow adjustment of the first current signal, so that the frequency of the first clock signal is also slowly adjusted accordingly, gradually approaching the frequency of the data signal. In this way, the frequency of the adjusted first clock signal can be more accurately close to the frequency of the data signal, and accurate determination of the frequency can be achieved.

[0292] In step S903, if it is detected that the second count value is greater than or equal to the third preset value, the first frequency difference is detected, and according to the detection result, the mode selection switch signal M_SEL is adjusted, or the current second frequency control signal FCTW is locked, and the locked second frequency control signal FCTW is used as the target frequency signal.

[0293] In a specific implementation, when the count value of the second counter, that is, the second count value, reaches the third preset value, the frequency adjustment module 111 detects the first frequency difference, and executes subsequent processes based on the detection result, as follows:

[0294] In some embodiments, if the frequency adjustment module 111 detects that the second frequency difference is within the second preset threshold range, the current second frequency control signal FCTW is locked and the locked second frequency control signal FCTW is used as the target frequency signal; if the frequency adjustment module 111 detects that the second frequency difference is outside the second preset threshold range, the adjustment mode selection switch signal M_SEL is adjusted.

[0295] The first preset threshold range includes the second preset threshold range.

[0296] In a specific implementation, since the first preset threshold range is included in the first preset threshold range, the FCTW adjustment is to perform a more accurate frequency approximation based on the CCTW adjustment result to improve the accuracy of the generated target clock signal.

[0297] In some embodiments, the digital controller 11 is provided with a second locking detection signal and a second error indication signal to indicate whether the second frequency locking is successful.

[0298] In a specific implementation, when the frequency adjustment module 111 detects that the first frequency difference is within the second preset threshold range, it means that the frequency of the data signal is close to the frequency of the current first clock signal, that is, it is considered that the frequency of the data signal is consistent with the frequency of the first clock signal. At this time, the second lock detection signal will become a high level, and the second error indication signal will remain at a low level, to indicate that the second frequency lock is successful, that is, the FCTW adjustment state is ended.

[0299] When the frequency adjustment module 111 detects that the first frequency difference is outside the second preset threshold range, it means that the frequency difference between the data signal and the current first clock signal is still large, which exceeds the frequency locking range of the voltage-controlled oscillator 135. At this time, the second locking detection signal will remain at a low level and the second error indication signal will become a high level to indicate that the second frequency locking failed, that is, the FCTW adjustment failed.

[0300] The second error indication signal is fed back to the transmission mode selection module 112 to control the transmission mode selection module 112 to adjust the level of the output mode selection switch signal M_SEL, and restart the CCTW adjustment and FCTW adjustment with reference to the above embodiment.

[0301] In the above embodiment, if the numerical controller detects that the first frequency difference is within the second preset threshold range, it means that the frequency of the data signal is close to the frequency of the first clock signal, that is, it is considered that the frequency of the data signal is consistent with the frequency of the first clock signal, and the purpose of fine adjustment is achieved, and the frequency locking operation can be performed. Otherwise, it means that the frequency of the data signal is still significantly different from the frequency of the first clock signal, which exceeds the lockable range, and it is necessary to adjust the mode selection switch signal to change the reference for generating the first current signal, and perform fine adjustment again. Accurate determination of the frequency can be achieved in the above manner.

[0302] Based on the above embodiment, there is another preferred implementation method to achieve locking of the second frequency control signal FCTW, which is as follows:

[0303] In some embodiments, when the frequency adjustment module 111 detects that the second count value is greater than or equal to the third preset value and less than the fourth preset value, the second frequency control signal FCTW is adjusted according to the first frequency difference, and the first frequency difference is continuously detected;

[0304] If the frequency adjustment module 111 detects that the first frequency difference is outside the second preset threshold range within the second time period, the mode selection switch signal M_SEL is adjusted, wherein the second time period is the time period required for the second count value to change from the third preset value to the fourth preset value;

[0305] If the frequency adjustment module 111 does not detect that the first frequency difference is outside the second preset threshold range within the second time period, the current second frequency control signal FCTW is locked and the locked second frequency control signal FCTW is used as the target frequency signal.

[0306] In a specific implementation, when the count value of the second counter, that is, the second count value, reaches the third preset value and the second lock detection signal becomes a high level, the FCTW adjustment state is maintained, that is, the frequency adjustment module 111 continues to adjust the second frequency control signal FCTW and continuously detects the first frequency difference.

[0307] At this time, the second counter continues to count, and during the period when the count value of the second counter changes from the third preset value to the fourth preset value, that is, during the second time period, the frequency adjustment module 111 continues to detect the level state of the second lock detection signal. If during this period, the second lock detection signal always maintains a high level, it means that the first frequency difference always remains within the second preset threshold range, the second frequency locking is successful, and the FCTW adjustment state ends.

[0308] If during this period, the second lock detection signal cannot maintain a high level, it means that the first frequency difference is outside the first preset threshold range, the second frequency lock fails, and the FCTW adjustment fails. At this time, the second error indication signal is changed to a high level and sent to the transmission mode selection module 112 to control the transmission mode selection module 112, adjust the level of the output mode selection switch signal M_SEL, and restart the CCTW adjustment and FCTW adjustment with reference to the above embodiment.

[0309] In the above embodiment, by continuously detecting the first frequency difference for a second time period, and when it is determined that the first frequency difference is within the second preset threshold range within the second time period, it can be determined that the frequency of the data signal and the frequency of the first clock signal remain stably close. At this time, the frequency is locked to avoid the occurrence of frequency mislock or loss of lock, thereby achieving precise frequency locking.

[0310] In some embodiments, after the FCTW adjustment state ends, the frequency adjustment module 111 enters the FCTW determination state. In the FCTW determination state, the frequency adjustment module 111 detects the level state of the second output control signal, and outputs the locked second frequency control signal FCTW when the level state of the second output control signal jumps to the second level state.

[0311] In a specific implementation, the frequency adjustment module 111 outputs the second frequency control signal FCTW to the second current source circuit 1222 according to the second output control signal, that is, when the second output control signal jumps from a low level to a high level, that is, at the rising edge, the corresponding second frequency control signal FCTW is used as the locked second frequency control signal FCTW.

[0312] Specifically, when the frequency adjustment module 111 detects that the second output control signal is at a low level, the FCTW determination state is maintained; when the frequency adjustment module 111 detects that a rising edge of the second output control signal has arrived, the second frequency control signal FCTW is output, and the FCTW determination state is ended.

[0313] Since the locked second frequency control signal FCTW may be a digital signal of a fixed level, or may be a digital signal jumping between two adjacent levels. For example, if the frequency of the first clock signal generated when the second frequency control signal FCTW is 0101 is similar to the frequency of the first clock signal generated when the second frequency control signal FCTW is 0110, the second frequency control signal FCTW will jump between the two values ​​of 0101 and 0110. By using the second frequency control signal FCTW corresponding to the rising edge of the second output control signal as the locked second frequency control signal FCTW, repeated jumping of the second frequency control signal FCTW is avoided.

[0314] In some embodiments, after the FCTW determination state ends, the frequency adjustment module 111 enters the FCTW output state. In the FCTW output state, the frequency adjustment module 111 updates, stores and outputs the locked second frequency control signal FCTW based on the second update signal.

[0315] In a specific implementation, the frequency adjustment module 111 detects the level state of the second update signal. When the second update signal is detected to be at a low level, it indicates that the update storage of the second frequency control signal FCTW has not been completed, and the FCTW output state is maintained. Until the second update signal is detected to jump to a high level, it indicates that the update storage of the second frequency control signal FCTW has been completed, and the FCTW output state is ended. At this point, the entire second frequency adjustment process is completed.

[0316] During the second frequency adjustment process, the voltage-to-current converter 134 in the clock generation module 13 does not work, so that the phase detector 131, charge pump 132 and low-pass filter 133 in the front stage cannot work, and only the voltage-controlled oscillator 135 works normally, reducing system power consumption.

[0317] In the embodiment of the present invention, both the CCTW adjustment process and the FCTW adjustment process are implemented by the frequency adjustment module 111. By sharing the modules, circuit area overhead and cost can be saved.

[0318] In some embodiments, the CCTW adjustment process and the FCTW adjustment process may be implemented in two independent modes, respectively, and the embodiment of the present invention does not impose any limitation on this.

[0319] Through two frequency adjustments, the frequency of the clock signal generated by the voltage-controlled oscillator 135 can be locked. Then, the clock signal can be phase-adjusted by the clock generation module 13 composed of the phase detector 131, the charge pump 132, the low-pass filter 133, the voltage-current converter 134 and the voltage-controlled oscillator 135.

[0320] After introducing the frequency adjustment process of the digital controller 11, the phase adjustment process of the clock generation module 13 is specifically introduced below:

[0321] In some embodiments, after locking the second frequency control signal FCTW, the frequency adjustment module 111 outputs the switching control signal Mode_Switch.

[0322] In a specific implementation, after locking the first frequency control signal CCTW and the second frequency control signal FCTW, the frequency adjustment module 111 outputs a switching control signal Mode_Switch to the voltage-current converter 134 to control the voltage-current converter 134 to work normally.

[0323] After the voltage-to-current converter 134 works normally, the path composed of the phase detector 131, the charge pump 132, the low-pass filter 133, the voltage-to-current converter 134 and the voltage-controlled oscillator 135 is turned on, that is, the phase detector 131, the charge pump 132 and the low-pass filter 133 of the previous stage can also work normally.

[0324] In some embodiments, the clock generation module 13, under the control of the switching control signal Mode_Switch, generates a second clock signal according to the first current signal; compares the phase of the data signal Din with the phase of the second clock signal, and adjusts the second clock signal according to the comparison result; and uses the adjusted second clock signal as the target clock signal DClk_1.

[0325] In the above embodiment, after frequency locking is achieved by coarse adjustment plus fine adjustment, the clock generation module is used to adjust the phase of the second clock signal, and the second clock signal after the phase adjustment is completed is used as the target clock signal to determine the target clock signal. The frequency and phase of the target clock signal generated in the above manner are close to the frequency and phase of the data signal, so that the target clock signal can be considered to have the same frequency and phase as the data signal, so that the receiving end can read the data signal according to the target clock signal to ensure the correctness of the data signal reading result.

[0326] In the specific implementation, after the FCTW output state ends, it enters the BB adjustment state, as follows:

[0327] In some embodiments, Fig.10 As shown in the figure, the specific working process of the clock generation module 13 in the BB adjustment state is as follows:

[0328] Step S1001 , detecting a third count value, wherein the third count value is used to represent the number of times the clock generation module 13 adjusts the second clock signal.

[0329] In a specific implementation, a third counter is further provided in the clock generation module 13 , through which the number of times the voltage-controlled oscillator 135 outputs the second clock signal is counted, and the third count value of the third counter is detected in real time.

[0330] Step S1002: if it is detected that the third count value is less than the fifth preset value, the phase of the second clock signal is adjusted according to the first phase difference, wherein the first phase difference is the difference between the phase of the data signal and the phase of the current second clock signal.

[0331] In a specific implementation, when the count value of the third counter, that is, the third count value, does not reach the fifth preset value, the clock generation module 13 adjusts the phase of the second clock signal according to the first phase difference, and the specific adjustment method is as follows:

[0332] In some embodiments, the phase detector 131 compares the phase of the data signal with the phase of the current second clock signal, and adjusts the pull-up pulse signal or the pull-down pulse signal according to the comparison result to adjust the phase of the second clock signal output by the voltage-controlled oscillator 135.

[0333] Step S1003, if it is detected that the third count value is greater than or equal to the fifth preset value, the first phase difference value is detected, and according to the detection result, the mode selection switch signal M_SEL is adjusted, or the current second clock signal is locked and the locked second clock signal is used as the target clock signal DClk_1.

[0334] In a specific implementation, when the count value of the third counter, that is, the third count value, reaches the fifth preset value, the clock generation module 13 detects the first phase difference value, and executes subsequent processes based on the detection result, as follows:

[0335] In some embodiments, if the clock generation module 13 detects that the first phase difference value is within the third preset threshold range, the current second clock signal is locked and the locked second clock signal is used as the target clock signal DClk_1; if the clock generation module 13 detects that the first phase difference value is outside the third preset threshold range, the mode selection switch signal M_SEL is adjusted.

[0336] In some embodiments, a third lock detection signal and a third error indication signal are further provided to indicate whether the phase lock is successful.

[0337] In a specific implementation, when the clock generating module 13 detects that the first phase difference is within the third preset threshold range, it indicates that the phase of the data signal is relatively close to the phase of the current second clock signal. At this time, the third lock detection signal will become a high level, and the third error indication signal will remain at a low level to indicate that the phase lock is successful, that is, the BB adjustment state ends.

[0338] When the clock generation module 13 detects that the first phase difference is outside the third preset threshold range, it means that the phase of the data signal is significantly different from the phase of the current second clock signal. At this time, the third lock detection signal will remain at a low level and the third error indication signal will become a high level to indicate a phase lock failure, that is, BB adjustment failure.

[0339] The third error indication signal is fed back to the transmission mode selection module 112 to control the transmission mode selection module 112, adjust the level of the output mode selection switch signal M_SEL, and restart the CCTW adjustment, FCTW adjustment and BB adjustment with reference to the above embodiment.

[0340] In the above embodiment, the phase of the second clock signal is adjusted by the clock generation module, and after the adjustment is performed for the fifth preset value times, the first phase difference is detected. If the first phase difference is within the third preset threshold range, it means that the phase of the data signal is close to the phase of the current second clock signal, and a phase locking operation can be performed.

[0341] In some embodiments, after the BB adjustment state is completed, the BB completion state is entered. In the BB completion state, the digital controller 11 detects whether the mode selection switch signal M_SEL has changed. If no change in the mode selection switch signal M_SEL is detected, the BB completion state is maintained. If a change in the mode selection switch signal M_SEL is detected, the above-mentioned frequency locking and phase locking processes are re-executed.

[0342] Based on the same concept, an embodiment of the present invention also provides a method for adjusting a clock signal, which is applied to a clock data recovery circuit provided in any of the above embodiments. Since this method is the method executed by the clock data recovery circuit in the embodiment of the present invention, and the principle of solving the problem by this method is similar to that of the clock data recovery circuit, the implementation of this method can refer to the implementation of the clock data recovery circuit, and the repeated parts will not be repeated.

[0343] like Fig.11 As shown, the method comprises the following steps:

[0344] Step S1101, when it is detected that the frequency of the data signal changes, a mode selection switch signal is output according to the detection result, and a target frequency control signal is generated based on the level state of the frequency adjustment mode signal;

[0345] Step S1102, outputting a first current signal under the control of a mode selection switch signal and a target frequency control signal;

[0346] Step S1103, generating a target clock signal according to the first current signal under the control of the switching control signal;

[0347] The switching control signal is generated after the target frequency control signal is output, the frequency of the target clock signal matches the frequency of the data signal, and the phase of the target clock signal matches the phase of the data signal.

[0348] Based on the same concept, an embodiment of the present invention further provides a display chip, comprising the clock data recovery circuit as described in any of the above embodiments.

[0349] The principle of the display chip in the embodiment of the present application to solve the problem is similar to that of the aforementioned clock data recovery circuit. Therefore, the implementation of the display chip can refer to the implementation of the clock data recovery circuit in any of the above embodiments, and the repeated parts will not be repeated.

[0350] Based on the same concept, an embodiment of the present invention further provides a display device, comprising a display chip as described in any of the above embodiments.

[0351] The principle of solving the problem by the display device in the embodiment of the present application is similar to that of the aforementioned display chip or the aforementioned clock data recovery circuit. Therefore, the implementation of the display device can refer to the implementation of the clock data recovery circuit in any of the above embodiments, and the repeated parts will not be repeated.

[0352] In a specific implementation, the display device in the embodiment of the present invention can be a smart terminal, a smart mobile terminal, a tablet computer, a laptop computer, a smart handheld device, a personal computer (PC), a computer, a smart screen, a display device, a vehicle-mounted device, various wearable devices, a personal digital assistant (PDA), etc.; among them, wearable devices such as virtual reality (VR) devices, augmented reality (AR) devices and other products or components.

[0353] In addition, other essential components of the display device should be understood by those skilled in the art and will not be described in detail herein, nor should they be used as limitations to the present invention.

[0354] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0355] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A clock data recovery circuit, characterized in that: include: A digital controller, for outputting a mode selection switch signal according to a detection result when a change in the frequency of the data signal is detected, and generating a target frequency control signal based on a level state of the frequency adjustment mode signal; A current source circuit, the current source circuit includes a reference current source module and a current generating module, the reference current source module includes a reference current source and a current source mirror branch, the current source mirror branch is electrically connected to the reference current source, the current generating module and the digital controller respectively, the current generating module is electrically connected to the digital controller, wherein: The reference current source is used to output a second reference current signal; The current source mirror branch is used to adjust the number of mirror current sources working in the current source mirror branch under the control of the mode selection switch signal, and output a first reference current signal based on the second reference current signal; The current generating module is configured to output a first current signal based on the first reference current signal under the control of the target frequency control signal; A clock generation module, used to generate a target clock signal according to the first current signal under the control of a switching control signal; Among them, the current value of the first reference current signal is a multiple of the current value of the second reference current signal, the switching control signal is generated by the digital controller after outputting the target frequency control signal, the frequency of the target clock signal matches the frequency of the data signal, and the phase of the target clock signal matches the phase of the data signal.

2. The circuit according to claim 1, characterized in that The digital controller is specifically used for: If it is detected that the frequency of the data signal increases, the level of the mode selection switch signal is increased to increase the current value of the first reference current signal; If it is detected that the frequency of the data signal becomes smaller, then the level of the mode selection switch signal is reduced to reduce the current value of the first reference current signal; The mode selection switch signal includes a plurality of levels, and the level of the mode selection switch signal is positively correlated with the current value of the first reference current signal.

3. The circuit according to claim 1, characterized in that The current generating module comprises a first current source branch and a second current source branch, wherein: The first current source branch is electrically connected to the current source mirror branch, the digital controller and the clock generation module respectively, and the second current source branch is electrically connected to the current source mirror branch, the digital controller and the clock generation module respectively; The first current source branch is used to adjust the number of first current sources working in the first current source branch under the control of a first frequency control signal to output a first current sub-signal; The second current source branch is used to adjust the number of second current sources working in the second current source branch under the control of a second frequency control signal to output a second current sub-signal; Among them, the target frequency control signal includes the first frequency control signal and the second frequency control signal, the first current signal is determined according to the first current sub-signal and the second current sub-signal, and the current value of the first current sub-signal is greater than the current value of the second current sub-signal.

4. The circuit according to claim 3, characterized in that The digital controller is specifically used for: If the level state of the frequency adjustment mode signal is the first level state, outputting a preset target frequency control signal; If the level state of the frequency adjustment mode signal is the second level state, generating the target frequency control signal according to the frequency of the data signal and the frequency of the first clock signal; The first clock signal is generated by the clock generation module according to the first current signal when the clock generation module does not receive the switching control signal.

5. The circuit according to claim 4, characterized in that If the level state of the frequency adjustment mode signal is the second level state, the digital controller is specifically used for: Detecting a first count value, wherein the first count value is used to represent the number of times the digital controller outputs the first frequency control signal; If it is detected that the first count value is less than a first preset value, adjusting the level of the first frequency control signal according to the first frequency difference so that the first current sub-signal changes; If it is detected that the first count value is greater than or equal to the first preset value, the first frequency difference is detected, and according to the detection result, the mode selection switch signal is adjusted, or the current first frequency control signal is locked, and the locked first frequency control signal is used as the target frequency signal; The first frequency difference is the difference between the frequency of the data signal and the frequency of the current first clock signal, the first frequency control signal includes a plurality of levels, and the level of the first frequency control signal is positively correlated with the current value of the first current sub-signal.

6. The circuit according to claim 5, characterized in that If it is detected that the first count value is greater than or equal to the first preset value, the digital controller is specifically configured to: If it is detected that the first frequency difference is within a first preset threshold range, locking the current first frequency control signal, and using the locked first frequency control signal as the target frequency signal; If it is detected that the first frequency difference is outside the first preset threshold range, the mode selection switch signal is adjusted.

7. The circuit according to claim 5, characterized in that The digital controller is also used for: When it is detected that the first count value is greater than or equal to the first preset value and less than a second preset value, adjusting the first frequency control signal according to the first frequency difference, and continuously detecting the first frequency difference; If it is detected that the first frequency difference is outside a first preset threshold range within a first time period, adjusting the mode selection switch signal; If it is not detected that the first frequency difference is outside the first preset threshold range within the first time period, locking the current first frequency control signal, and using the locked first frequency control signal as the target frequency signal; The first time duration is the time duration required for the first count value to change from the first preset value to the second preset value.

8. The circuit according to claim 7, characterized in that After locking the first frequency control signal, the digital controller is specifically used for: Detecting a second count value, wherein the second count value is used to represent the number of times the digital controller outputs the second frequency control signal; If it is detected that the second count value is less than a third preset value, adjusting the level of the second frequency control signal according to the first frequency difference so that the second current sub-signal changes; If it is detected that the second count value is greater than or equal to the third preset value, the first frequency difference is detected, and according to the detection result, the mode selection switch signal is adjusted, or the current second frequency control signal is locked, and the locked second frequency control signal is used as the target frequency signal; The second frequency control signal includes a plurality of levels, and the level of the second frequency control signal is positively correlated with the current value of the second current sub-signal.

9. The circuit according to claim 8, characterized in that If it is detected that the second count value is greater than or equal to the third preset value, the digital controller is specifically configured to: If it is detected that the second frequency difference is within the second preset threshold range, the current second frequency control signal is locked, and the locked second frequency control signal is used as the target frequency signal; If it is detected that the second frequency difference is outside the second preset threshold range, adjusting the mode selection switch signal; The first preset threshold range includes the second preset threshold range.

10. The circuit according to claim 8, characterized in that The digital controller is also used for: When it is detected that the second count value is greater than or equal to the third preset value and less than a fourth preset value, adjusting the second frequency control signal according to the first frequency difference, and continuously detecting the first frequency difference; If it is detected that the first frequency difference is outside a second preset threshold range within a second time period, adjusting the mode selection switch signal; If it is not detected that the first frequency difference is outside the second preset threshold range within the second time period, locking the current second frequency control signal, and using the locked second frequency control signal as the target frequency signal; The second time duration is the time duration required for the second count value to change from the third preset value to the fourth preset value.

11. The circuit according to claim 9 or 10, characterized in that After locking the second frequency control signal, the digital controller is specifically used for: outputting the switching control signal; The clock generation module is specifically used for: Under the control of the switching control signal, a second clock signal is generated according to the first current signal; the phase of the data signal is compared with the phase of the second clock signal, and the second clock signal is adjusted according to the comparison result; the adjusted second clock signal is used as the target clock signal.

12. The circuit according to claim 11, characterized in that The clock generation module is specifically used for: detecting a third count value, wherein the third count value is used to represent the number of times the clock generation module adjusts the second clock signal; If it is detected that the third count value is less than a fifth preset value, adjusting the phase of the second clock signal according to the first phase difference value; If it is detected that the third count value is greater than or equal to the fifth preset value, the first phase difference value is detected, and according to the detection result, the mode selection switch signal is adjusted, or the current second clock signal is locked, and the locked second clock signal is used as the target clock signal; The first phase difference is the difference between the phase of the data signal and the phase of the current second clock signal.

13. A method for adjusting a clock signal, characterized in that: Applied to the clock data recovery circuit according to any one of claims 1 to 12, the method comprising: When a change in the frequency of the data signal is detected, a mode selection switch signal is output according to the detection result, and a target frequency control signal is generated based on the level state of the frequency adjustment mode signal; Under the control of the mode selection switch signal, the number of mirror current sources working in the current source mirror branch is adjusted, and a first reference current signal is output based on a second reference current signal output by the reference current source; under the control of the target frequency control signal, a first current signal is output based on the first reference current signal; Under the control of the switching control signal, generating a target clock signal according to the first current signal; Among them, the current value of the first reference current signal is a multiple of the current value of the second reference current signal, the switching control signal is generated after the target frequency control signal is output, the frequency of the target clock signal matches the frequency of the data signal, and the phase of the target clock signal matches the phase of the data signal.

14. A display chip, characterized in that: It comprises a clock data recovery circuit as described in any one of claims 1 to 12.

15. A display device, characterized in that: Comprising the display chip as claimed in claim 14.

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