Epitaxial wafer and preparation method thereof

Abstract

The present application discloses an epitaxial wafer and a preparation method thereof. The epitaxial wafer includes a substrate layer, a nucleation layer, a buffer layer, a superlattice stack layer, a back barrier layer, a channel layer, an insertion layer, a barrier layer, and a cap layer which are stacked; the superlattice layer is selected from any one of an AlN / GaN stack, an AlN / AlaGa1-aN stack, an AlbGa1-bN / GaN stack, and an AlcGa1-cN / AldGa1-dN stack, satisfying: 0≤a<1; 0≤b<1; 0<c<1, 0≤d<1, and d<c. In the present application, a superlattice stack layer is disposed on the side of the buffer layer away from the nucleation layer. Among them, the superlattice layer in the superlattice stack layer can block dislocations, slow down the rate of curvature decrease, and perform curvature compensation, which can improve the stress and warping in the epitaxial growth process, improve the occurrence of microcracks, and improve the quality and uniformity of the epitaxial wafer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial wafer and a method for preparing the same. Background Art

[0002] In the field of semiconductor materials, compared with traditional silicon materials, gallium nitride (GaN) has the advantages of large bandgap, strong breakdown electric field, low on-resistance, high electron mobility, high conversion efficiency, high thermal conductivity, and low loss. It can be widely used in communications, radar, consumer electronics, automotive electronics, electric power, industrial laser processing, instrumentation and other fields. Therefore, the research and development and mass production of gallium nitride have received much attention from many countries around the world.

[0003] Gallium nitride cannot be obtained directly from nature. Currently, metal organic compound vapor phase epitaxy is still the main technology for preparing gallium nitride, and the commonly used substrates are mainly silicon and sapphire. Due to the lattice mismatch and thermal mismatch between the substrate material and gallium nitride, the high-density defects inside the gallium nitride epitaxial wafer can easily cause poor device performance and even cause rapid device failure. How to grow high-quality gallium nitride epitaxial wafers is one of the important issues in solving gallium nitride power devices. In order to solve the lattice mismatch and thermal mismatch between the gallium nitride epitaxy and the substrate, aluminum nitride is often used as the nucleation layer to grow gallium nitride epitaxy in a two-step method, and the aluminum gallium nitride buffer layer technology is used to improve the crystal quality of the epitaxy. With the increase in the withstand voltage requirements for GaN-based high electron mobility transistors (HEMTs), the increase in the thickness of the epitaxial layer causes a sudden increase in the warping of the epitaxy during the growth process, which is more likely to produce microcracks, while exacerbating the difference between the inner and outer circles of the epitaxy, resulting in a decrease in crystal quality. Therefore, under the trend of high withstand voltage and large size, how to reduce warping to improve microcracks in the epitaxial layer and improve the crystal quality of the epitaxial layer is an important issue that needs to be urgently solved for GaN-based HEMTs. Summary of the invention

[0004] The purpose of the present application is to provide an epitaxial wafer and a method for preparing the same, which can improve stress and warping during epitaxial growth and improve microcracks.

[0005] In a first aspect, the present application provides an epitaxial wafer, comprising a stacked substrate layer, a nucleation layer, a buffer layer, a superlattice stacking layer, a back barrier layer, a channel layer, an insertion layer, a barrier layer, and a cap layer disposed on the barrier layer;

[0006] The superlattice stacking layer comprises multiple superlattice layers and multiple gallium nitride layers, wherein one layer of the multiple superlattice layers and one layer of the multiple gallium nitride layers are alternately stacked; one layer of the multiple superlattice layers is arranged on a side of the buffer layer away from the nucleation layer, and another layer is arranged on a side of the back barrier layer away from the channel layer, and the superlattice layer is selected from AlN / GaN stacking, AlN / Al a Ga1-a N stack, Al b Ga 1-b N / GaN stack, Al c Ga 1-c N / Al d Ga 1-d Any one of the N stacks satisfies: 0 ≤ a < 1; 0 ≤ b < 1; 0 < c < 1, 0 ≤ d < 1, and d < c.

[0007] In some embodiments, the multiple superlattice layers are greater than or equal to three layers; the multiple gallium nitride layers are greater than or equal to two layers.

[0008] In some embodiments, in the AlN / GaN stack, the thickness of the AlN layer is 1 - 10 nm, and the thickness of the GaN layer is 10 - 50 nm; and / or,

[0009] In the AlN / Al a Ga 1-a N stack, the thickness of the AlN layer is 1 - 10 nm, and the Al a Ga 1-a N layer is 10 - 50 nm; and / or,

[0010] In the Al b Ga 1-b N / GaN stack, the Al b Ga 1-b N layer is 1 - 10 nm, and the thickness of the GaN layer is 10 - 50 nm; and / or,

[0011] In the Al c Ga 1-c N / Al d Ga 1-d N stack, the Al c Ga 1-c N layer is 1 - 10 nm, and the Al d Ga 1-d N layer is 10 - 50 nm.

[0012] In some embodiments, the superlattice stack layer includes a first sub - superlattice layer, a first sub - gallium nitride layer, a second sub - superlattice layer, a second sub - gallium nitride layer, and a third sub - superlattice layer which are stacked; the first sub - superlattice layer is disposed on a side of the buffer layer away from the nucleation layer; the third sub - superlattice layer is disposed on a side of the back - barrier layer away from the channel layer.

[0013] In some embodiments, the first sub - superlattice layer has a first carbon doping amount Q 1, the second sub-superlattice layer has a second carbon doping amount Q 2 , the third sub-superlattice layer has a third carbon doping amount Q 3 , satisfying: Q 3 ≤Q 2 ≤Q 1 , and Q 3 ≤5E18 / cm 3 .

[0014] In some embodiments, the first GaN sub-layer has a fourth carbon doping amount Q 4 The second GaN sub-layer has a fifth carbon doping amount Q 5 , meet: 5E19 / cm 3 ≤Q 4 =Q 5 .

[0015] In some embodiments, the first sub-superlattice layer is doped with a first carbon source, the first carbon source being selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane; and / or,

[0016] The second sub-superlattice layer is doped with a second carbon source, wherein the second carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane; and / or,

[0017] The third sub-superlattice layer is doped with a third carbon source, wherein the third carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane and butane; and / or,

[0018] The first gallium nitride sub-layer is doped with a fourth carbon source, wherein the fourth carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane; and / or,

[0019] The second gallium nitride sub-layer is doped with a fifth carbon source, and the fifth carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane.

[0020] In some embodiments, the material of the buffer layer includes k layers of aluminum gallium nitride stacked together, satisfying: 1≤k≤5; and / or,

[0021] The molar content of aluminum in the buffer layer ranges from 5% to 95%, and the molar content of aluminum in the buffer layer gradually decreases in a direction away from the nucleation layer.

[0022] In some embodiments, the material of the back barrier layer is selected from at least one of AlGaN doped with the sixth carbon source or GaN doped with the seventh carbon source; and / or the carbon doping amount in the back barrier layer is in the range of 1E18 to 5E18 / cm 3 ; and / or, the molar content of aluminum in the back barrier layer is in the range of 3 to 10%.

[0023] In some embodiments, the material of the barrier layer includes aluminum gallium nitride; and / or the molar content of aluminum in the barrier layer is in a range of 10 to 30%.

[0024] In some embodiments, the material of the substrate layer is selected from any one of silicon, silicon carbide or sapphire; and / or,

[0025] The material of the nucleation layer is selected from at least one of aluminum nitride and silicon nitride; and / or,

[0026] The material of the channel layer is selected from gallium nitride; and / or,

[0027] The material of the insertion layer is selected from at least one of aluminum nitride, aluminum scandium nitride, and aluminum gallium gallium nitride; and / or,

[0028] The material of the cap layer is selected from any one of nGaN, SiN and pGaN.

[0029] In some embodiments, the thickness of the nucleation layer is 100 to 400 nm; and / or,

[0030] The thickness of the buffer layer is 300 to 2000 nm; and / or,

[0031] The thickness of the superlattice layer is 100-1000 nm; and / or,

[0032] The thickness of the gallium nitride layer is 200-600 nm; and / or,

[0033] The thickness of the back barrier layer is 200 to 1500 nm; and / or,

[0034] The thickness of the channel layer is 100-400 nm; and / or,

[0035] The thickness of the insertion layer is 1 to 5 nm; and / or,

[0036] The thickness of the barrier layer is 10 to 30 nm; and / or,

[0037] The thickness of the cap layer is 1 to 120 nm.

[0038] A second aspect of the present application provides a method for preparing an epitaxial wafer, comprising:

[0039] providing a substrate layer;

[0040] forming a nucleation layer on one side of the substrate layer;

[0041] forming a buffer layer on a side of the nucleation layer away from the substrate layer;

[0042] A superlattice stack layer is formed on a side of the buffer layer facing away from the nucleation layer;

[0043] A back barrier layer is formed on a side of the superlattice stack layer facing away from the buffer layer;

[0044] A channel layer is formed on a side of the back barrier layer facing away from the superlattice stack layer;

[0045] An insertion layer is formed on a side of the channel layer facing away from the back barrier layer;

[0046] A barrier layer is formed on a side of the insertion layer facing away from the channel layer;

[0047] A cap layer is formed on a side of the barrier layer facing away from the insertion layer;

[0048] Wherein, the superlattice stack layer includes multiple superlattice layers and multiple gallium nitride layers, and one layer of the multiple superlattice layers and one layer of the multiple gallium nitride layers are alternately stacked; one layer of the multiple superlattice layers is arranged on a side of the buffer layer far from the nucleation layer, and the other layer is arranged on a side of the back barrier layer far from the channel layer. The superlattice layer is selected from any one of AlN / GaN stacks, Al a Ga 1-a N stacks, Al b Ga 1-b N / GaN stacks, Al c Ga 1-c N / Al d Ga 1-d N stacks, satisfying: 0 ≤ a < 1; 0 ≤ b < 1; 0 < c < 1, 0 ≤ d < 1, and d < c.

[0049] In some embodiments, the superlattice layer includes a first sub-superlattice layer, a second sub-superlattice layer, and a third sub-superlattice layer; the gallium nitride layer includes a first sub-gallium nitride layer and a second sub-gallium nitride layer; the first sub-gallium nitride layer is located between the first sub-superlattice layer and the second sub-superlattice layer, and the second sub-gallium nitride layer is located between the second sub-superlattice layer and the third sub-superlattice layer;

[0050] Dope the first sub-superlattice layer with a first carbon source;

[0051] Dope the second sub-superlattice layer with a second carbon source;

[0052] Dope the third sub-superlattice layer with a third carbon source;

[0053] Dope the first sub-gallium nitride layer with a fourth carbon source;

[0054] Dope the second sub-gallium nitride layer with a fifth carbon source.

[0055] In some embodiments, the flow rate of the first carbon source is 100 to 1000 sccm; and / or,

[0056] the flow rate of the second carbon source is 100 to 1000 sccm; and / or,

[0057] the flow rate of the third carbon source is 100 to 1000 sccm; and / or,

[0058] the flow rate of the fourth carbon source is 100 to 1000 sccm; and / or,

[0059] the flow rate of the fifth carbon source is 100 to 1000 sccm.

[0060] The beneficial effects of this application are as follows:

[0061] This application provides an epitaxial wafer, which includes a substrate layer, a nucleation layer, a buffer layer, a superlattice stack layer, a back barrier layer, a channel layer, an insertion layer, a barrier layer, and a cap layer arranged in a stacked manner; wherein, the superlattice stack layer includes multiple superlattice layers and multiple gallium nitride layers, and one layer of the multiple superlattice layers and one layer of the multiple gallium nitride layers are alternately stacked; one layer of the multiple superlattice layers is arranged on the side of the buffer layer away from the nucleation layer, and the other layer is arranged on the side of the back barrier layer away from the channel layer. The superlattice layer is selected from any one of AlN / GaN stacks, AlN / AlaGa1-aN stacks, AlbGa1-bN / GaN stacks, AlcGa1-cN / AldGa1-dN stacks, satisfying: 0 ≤ a < 1; 0 ≤ b < 1; 0 < c < 1, 0 ≤ d < 1, and d < c. By arranging the superlattice stack layer on the side of the buffer layer facing away from the nucleation layer in this application, wherein the superlattice layer in the superlattice stack layer can block dislocations, slow down the rate of curvature decline, and perform curvature compensation, which can improve the stress and warpage during the epitaxial growth process, improve the occurrence of microcracks, and improve the quality and uniformity of the epitaxial wafer. Description of the Drawings

[0062] Figure 1 is a schematic structural diagram of the epitaxial wafer provided by this application;

[0063] Figure 2 is a schematic structural diagram of the superlattice stack layer provided by this application;

[0064] Figure 3 is a graph of the warpage measurement results of the epitaxial wafers prepared in Example 1 and Comparative Example 1 of this application.

[0065] In the drawings, the components represented by each reference numeral are as follows:

[0066] 1. Substrate layer; 2. Nucleation layer; 3. Buffer layer; 4. Superlattice stacking layer; 41. Superlattice layer; 411. First sub-superlattice layer; 412. Second sub-superlattice layer; 413. Third sub-superlattice layer; 42. GaN layer; 421. First sub-GaN layer; 422. Second sub-GaN layer; 5. Back barrier layer; 6. Channel layer; 7. Insertion layer; 8. Barrier layer; 9. Cap layer. DETAILED DESCRIPTION

[0067] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments and drawings of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. The various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and simplicity, and should not be understood as a rigid limitation on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values ​​within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which are applicable regardless of the range. In addition, whenever a numerical range is indicated in this article, it is meant to include any quoted numbers (fractions or integers) within the indicated range.

[0068] like Figure 1-Figure 2 As shown, an epitaxial wafer comprises a stacked substrate layer 1, a nucleation layer 2, a buffer layer 3, a superlattice stacking layer 4, a back barrier layer 5, a channel layer 6, an insertion layer 7, a barrier layer 8 and a cap layer 9 arranged on the barrier layer 8; wherein the superlattice stacking layer 4 comprises a plurality of superlattice layers 41 and a plurality of gallium nitride layers 42, wherein one layer of the plurality of superlattice layers 41 and one layer of the plurality of gallium nitride layers 42 are alternately stacked; one layer of the plurality of superlattice layers 41 is arranged on a side of the buffer layer 3 away from the nucleation layer 2, and another layer is arranged on a side of the back barrier layer 5 away from the channel layer 6, and the superlattice layer 41 is selected from an AlN / GaN stack, an AlN / Al a Ga 1-a N stack, Al b Ga 1-b N / GaN stack, Al c Ga 1-c N / A d Ga 1-dAny one of the N stacks satisfies: 0 ≤ a < 1; 0 ≤ b < 1; 0 < c < 1, 0 ≤ d < 1, and d < c. Specifically, the value of a can be any value among 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or a range composed of any two of these values; the value of b can be any value among 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or a range composed of any two of these values; the value of c can be any value among 0.01, 0.05, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or a range composed of any two of these values. The value of d can be any value among 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or a range composed of any two of these values. In this application, the stack means the alternate growth of one substance and another substance.

[0069] It can be understood that in this application, by providing a superlattice stack layer 4 on the side of the buffer layer 3 away from the nucleation layer 2, where the superlattice layer 41 in the superlattice stack layer 4 can block dislocations, slow down the rate of curvature decline and perform curvature compensation, which can improve the stress and warping during the epitaxial growth process, improve the occurrence of microcracks, and improve the quality and uniformity of the epitaxial wafer.

[0070] In some embodiments, the multi-layer superlattice layer 41 is greater than or equal to three layers; the multi-layer gallium nitride layer 42 is greater than or equal to two layers.

[0071] In some embodiments, in the AlN / GaN stack, the thickness of the AlN layer is 1 - 10 nm, and the thickness of the GaN layer is 10 - 50 nm. Specifically, in the AlN / GaN stack, the thickness of the AlN layer is any value among 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm or a range composed of any two of these values; the thickness of the GaN layer is any value among 10 nm, 20 nm, 30 nm, 40 nm, 50 nm or a range composed of any two of these values. It can be understood that in the AlN / GaN stack, the AlN layer is a wide bandgap layer and the GaN layer is a narrow bandgap layer.

[0072] In some embodiments, in the AlN / Al a Ga 1-a N stack, the thickness of the AlN layer is 1 - 10 nm, and the Al a Ga 1-a N layer has a thickness of 10 - 50 nm. Specifically, in the AlN / Al a Ga 1-aIn the N stack, the thickness of the AlN layer is any one of 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm, or a range consisting of any two values; a Ga 1-a The thickness of the N layer is any one of 10nm, 20nm, 30nm, 40nm, and 50nm, or a range consisting of any two values. a Ga 1-a In the N stack, the AlN layer is a wide bandgap layer, and the Al a Ga 1-a The N layer is a narrow bandgap layer.

[0073] In some embodiments, in Al b Ga 1-b In N / GaN stack, Al b Ga 1-b The thickness of the N layer is 1 to 10 nm, and the thickness of the GaN layer is 10 to 50 nm. b Ga 1-b In N / GaN stack, Al b Ga 1-b The thickness of the N layer is any one of 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm, or a range consisting of any two values; the thickness of the GaN layer is any one of 10nm, 20nm, 30nm, 40nm, and 50nm, or a range consisting of any two values. It is understood that in Al b Ga 1-b In N / GaN stack, Al b Ga 1-b The N layer is a wide bandgap layer, and the GaN layer is a narrow bandgap layer.

[0074] In some embodiments, in Al c Ga 1-c N / A d Ga 1-d In the N stack, Al c Ga 1-c The thickness of the N layer is 1 to 10 nm, and the Al d Ga 1-d The thickness of the N layer is 10 to 50 nm. c Ga 1-c N / A d Ga 1-d In the N stack, Al c Ga 1-cThe thickness of the N layer is any one of 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm, or a range consisting of any two values; d Ga 1-d The thickness of the N layer is any one of 10nm, 20nm, 30nm, 40nm, and 50nm, or a range consisting of any two values. c Ga 1-c N / A d Ga 1-d In the N stack, Al c Ga 1-c The N layer is a wide bandgap layer, Al d Ga 1-d The N layer is a narrow bandgap layer.

[0075] In some embodiments, the superlattice stacking layer 4 includes a first sub-superlattice layer 411, a first sub-gallium nitride layer 421, a second sub-superlattice layer 412, a second sub-gallium nitride layer 422 and a third sub-superlattice layer 413 which are stacked; the first sub-superlattice layer 411 is arranged on a side of the buffer layer 3 away from the nucleation layer 2; the third sub-superlattice layer 413 is arranged on a side of the back barrier layer 5 away from the channel layer 6.

[0076] It can be understood that the first sub-superlattice layer 411 and the second sub-superlattice layer 412 can slow down the rate of curvature decrease; the third sub-superlattice layer 413 can perform curvature compensation; it can improve the warping during epitaxial growth, improve the occurrence of microcracks, and improve the quality and uniformity of the epitaxial wafer.

[0077] In some embodiments, the first sub-superlattice layer 411 has a first carbon doping amount Q 1 , the second sub-superlattice layer 412 has a second carbon doping amount Q 2 , the third sub-superlattice layer 413 has a third carbon doping amount Q 3 , satisfying: Q 3 ≤Q 2 ≤Q 1 , and Q 3 ≤5E18 / cm 3 .

[0078] It can be understood that by controlling the first carbon doping amount Q 1 , the second carbon doping amount Q 2 and the third carbon doping amount Q 3 , satisfying: Q 3 ≤Q 2 ≤Q 1 , which can more effectively reduce defect density and control warpage.

[0079] In some embodiments, the first GaN sub-layer 421 has a fourth carbon doping amount Q 4 The second GaN sub-layer 422 has a fifth carbon doping amount Q 5 , meet: 5E19 / cm 3 ≤Q 4 =Q 5 .

[0080] It can be understood that by controlling the fourth carbon doping amount Q 4 and the fifth carbon doping amount Q 5 , meet: 5E19 / cm 3 ≤Q 4 =Q 5 , which can more effectively reduce defect density and control warpage.

[0081] In some embodiments, the first sub-superlattice layer 411 is doped with a first carbon source, and the first carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane.

[0082] In some embodiments, the second sub-superlattice layer 412 is doped with a second carbon source, and the second carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane.

[0083] In some embodiments, the third sub-superlattice layer 413 is doped with a third carbon source, and the third carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane.

[0084] In some embodiments, the first gallium nitride sub-layer 421 is doped with a fourth carbon source, and the fourth carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane.

[0085] In some embodiments, the second gallium nitride sub-layer 422 is doped with a fifth carbon source, and the fifth carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane.

[0086] In some embodiments, the material of the buffer layer 3 includes k stacked layers of aluminum gallium nitride, satisfying: 1≤k≤5. Specifically, the value of n can be any one of 1, 2, 3, 4, 5, or a range consisting of any two values.

[0087] It is understandable that the buffer layer 3 can gradually filter the penetrating dislocations formed by the growth of the nucleation layer 2. By controlling the buffer layer 3 to include k stacked layers of aluminum gallium nitride, satisfying: 1≤k≤5, layer-by-layer filtering can be achieved, greatly reducing crystal defects.

[0088] In some embodiments, the molar content of aluminum in the buffer layer 3 is in the range of 5% to 95%, and the molar content of aluminum in the buffer layer 3 gradually decreases in the direction away from the nucleation layer 2. Specifically, the molar content of aluminum in the buffer layer 3 is any one of 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, and 95%, or a range consisting of any two values.

[0089] It can be understood that by controlling the aluminum molar content in the buffer layer 3 to be in the range of 5% to 95%, the aluminum molar content in the buffer layer 3 gradually decreases in the direction away from the nucleation layer 2, which can quickly reduce the defect density while reducing the lattice mismatch of epitaxial growth.

[0090] In some embodiments, the material of the back barrier layer 5 is selected from at least one of AlGaN doped with a sixth carbon source or GaN doped with a seventh carbon source.

[0091] In some embodiments, the carbon doping amount in the back barrier layer 5 is in the range of 1E18 to 5E18 / cm 3 Specifically, the carbon doping amount in the back barrier layer 5 is 1E18 / cm 3 , 2E18 / cm 3 、3E18 / cm 3 、4E18 / cm 3 、5E18 / cm 3 Any value or any range of two values ​​in .

[0092] It can be understood that by controlling the carbon doping amount in the back barrier layer 5 to be in the range of 1E18 to 5E18 / cm 3 , which can improve the voltage resistance of the epitaxial wafer.

[0093] In some embodiments, the aluminum molar content of the back barrier layer 5 is in the range of 3-10%. Specifically, the aluminum molar content of the back barrier layer 5 is in the range of any one of 3%, 4%, 5%, 6%, 7%, 8%, 9%, and 10%, or any two of the above.

[0094] It is understandable that by controlling the aluminum molar content in the back barrier layer 5 to be in the range of 3-10%, the channel layer can have a smaller lattice mismatch when grown, while raising the energy band of the channel layer and increasing the mobility of the two-dimensional electron gas.

[0095] In some embodiments, the material of barrier layer 8 includes aluminum gallium nitride.

[0096] In some embodiments, the aluminum molar content of the barrier layer 8 is in the range of 10-30%. Specifically, the aluminum molar content of the barrier layer 8 is any one of 10%, 15%, 20%, 25%, and 30%, or a range consisting of any two values.

[0097] It can be understood that by controlling the aluminum molar content in the barrier layer 8 to be in the range of 10-30%, a high-mobility two-dimensional electron gas can be formed through the dual polarization effect.

[0098] In some embodiments, the material of the substrate layer 1 is selected from any one of silicon, silicon carbide or sapphire.

[0099] In some embodiments, the material of the nucleation layer 2 is selected from at least one of aluminum nitride and silicon nitride.

[0100] In some embodiments, the material of the channel layer 6 is selected from gallium nitride.

[0101] In some embodiments, the material of the insertion layer 7 is selected from at least one of aluminum nitride, aluminum scandium nitride, and aluminum gallium nitride.

[0102] In some embodiments, the material of the cap layer 9 is selected from any one of nGaN, SiN, and pGaN.

[0103] In some embodiments, the thickness of the nucleation layer 2 is 100-400 nm. Specifically, the thickness of the nucleation layer 2 is any one of 100 nm, 200 nm, 300 nm, and 400 nm, or a range consisting of any two of the values.

[0104] In some embodiments, the thickness of the buffer layer 3 is 300-2000 nm. Specifically, the thickness of the buffer layer 3 is any one of 300 nm, 500 nm, 1000 nm, 1500 nm, and 2000 nm, or a range consisting of any two of the values.

[0105] In some embodiments, the thickness of the superlattice layer 41 is 100-1000 nm. Specifically, the thickness of the superlattice layer 41 is any one of 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, and 1000 nm, or a range consisting of any two of the values.

[0106] In some embodiments, the thickness of the gallium nitride layer 42 is 200-600 nm. Specifically, the thickness of the gallium nitride layer 42 is any one of 200 nm, 300 nm, 400 nm, 500 nm, and 600 nm, or a range consisting of any two of the values.

[0107] In some embodiments, the thickness of the back barrier layer 5 is 200-1500 nm. Specifically, the thickness of the back barrier layer 5 is any one of 200 nm, 500 nm, 1000 nm, 1500 nm, and 2000 nm, or a range consisting of any two of the values.

[0108] In some embodiments, the thickness of the channel layer 6 is 100-400 nm. Specifically, the thickness of the channel layer 6 is any one of 100 nm, 200 nm, 300 nm, and 400 nm, or a range consisting of any two of the values.

[0109] In some embodiments, the thickness of the insertion layer 7 is 1-5 nm. Specifically, the thickness of the insertion layer 7 is any one of 1 nm, 2 nm, 3 nm, 4 nm, and 5 nm, or a range consisting of any two of the values.

[0110] In some embodiments, the thickness of the barrier layer 8 is 10-30 nm. Specifically, the thickness of the barrier layer 8 is any one of 10 nm, 15 nm, 20 nm, 25 nm, and 30 nm, or a range consisting of any two of the values.

[0111] In some embodiments, the thickness of the cap layer 9 is 1-120 nm. Specifically, the thickness of the cap layer 9 is any one of 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, and 120 nm, or a range consisting of any two of the values.

[0112] It can be understood that when the thickness of each layer of the epitaxial wafer satisfies the above value range, the comprehensive performance of the epitaxial wafer has a relatively ideal performance.

[0113] A second aspect of the present application provides a method for preparing an epitaxial wafer, comprising:

[0114] Providing a substrate layer 1;

[0115] forming a nucleation layer 2 on one side of the substrate layer 1;

[0116] A buffer layer 3 is formed on a side of the nucleation layer 2 facing away from the substrate layer 1;

[0117] A superlattice stacking layer 4 is formed on a side of the buffer layer 3 away from the nucleation layer 2;

[0118] A back barrier layer 5 is formed on a side of the superlattice stacking layer 4 away from the buffer layer 3;

[0119] A channel layer 6 is formed on a side of the back barrier layer 5 away from the superlattice stack layer 4;

[0120] An insertion layer 7 is formed on a side of the channel layer 6 away from the back barrier layer 5;

[0121] A barrier layer 8 is formed on a side of the insertion layer 7 away from the channel layer 6;

[0122] A cap layer 9 is formed on a side of the barrier layer 8 away from the insertion layer 7;

[0123] Wherein, the superlattice stack layer 4 includes multiple superlattice layers 41 and multiple gallium nitride layers 42, and one layer of the multiple superlattice layers 41 and one layer of the multiple gallium nitride layers 42 are alternately stacked; one layer of the multiple superlattice layers 41 is disposed on a side of the buffer layer 3 away from the nucleation layer 2, and the other layer is disposed on a side of the back barrier layer 5 away from the channel layer 6. The superlattice layer 41 is selected from any one of AlN / GaN stacks, Al a Ga 1-a N stacks, Al b Ga 1-b N / GaN stacks, Al c Ga 1-c N / Al d Ga 1-d N stacks, satisfying: 0 ≤ a < 1; 0 ≤ b < 1; 0 < c < 1, 0 ≤ d < 1, and d < c.

[0124] In some embodiments, the nucleation layer 2 can be prepared by any one of a metal organic chemical vapor deposition system (MOCVD), magnetron sputtering, and hydride vapor phase epitaxy (HVPE).

[0125] In some embodiments, the superlattice stack layer 4 can be obtained by in-situ pulsed growth using a metal organic chemical vapor deposition system (MOCVD).

[0126] In some embodiments, the superlattice layer 41 includes a first sub-superlattice layer 411, a second sub-superlattice layer 412, and a third sub-superlattice layer 413; the gallium nitride layer 42 includes a first sub-gallium nitride layer 421 and a second sub-gallium nitride layer 422; the first sub-gallium nitride layer 421 is located between the first sub-superlattice layer 411 and the second sub-superlattice layer 412, and the second sub-gallium nitride layer 422 is located between the second sub-superlattice layer 412 and the third sub-superlattice layer 413;

[0127] Dope the first sub-superlattice layer 411 with a first carbon source;

[0128] Dope the second sub-superlattice layer 412 with a second carbon source;

[0129] Dope the third sub-superlattice layer 413 with a third carbon source;

[0130] Dope the first sub-gallium nitride layer 421 with a fourth carbon source;

[0131] Dope the second sub-gallium nitride layer 422 with a fifth carbon source.

[0132] In some embodiments, the flow rate of the first carbon source is 100-1000 sccm. Specifically, the flow rate of the first carbon source is any one of 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, and 1000 sccm, or a range consisting of any two of the values.

[0133] In some embodiments, the flow rate of the second carbon source is 100-1000 sccm. Specifically, the flow rate of the second carbon source is any one of 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, and 1000 sccm, or a range consisting of any two of the values.

[0134] In some embodiments, the flow rate of the third carbon source is 100-1000 sccm. Specifically, the flow rate of the third carbon source is any one of 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, and 1000 sccm, or a range consisting of any two of the values.

[0135] In some embodiments, the flow rate of the fourth carbon source is 100-1000 sccm. Specifically, the flow rate of the fourth carbon source is any one of 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, and 1000 sccm, or a range consisting of any two of the values.

[0136] In some embodiments, the flow rate of the fifth carbon source is 100-1000 sccm. Specifically, the flow rate of the fifth carbon source is any one of 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, and 1000 sccm, or a range consisting of any two of the values.

[0137] The present application will be described below with reference to specific embodiments.

[0138] Example 1

[0139] A silicon substrate is provided as the substrate layer 1 , and the thickness of the substrate layer 1 is 1000 μm.

[0140] An aluminum nitride nucleation layer 2 is grown on a silicon substrate by in-situ metal organic compound vapor phase epitaxy. The thickness of the nucleation layer 2 is 300 nm.

[0141] Four aluminum gallium nitride buffer layers 3 are grown on the nucleation layer 2. Along the direction away from the nucleation layer 2, the aluminum molar contents of the four aluminum gallium nitride buffer layers 3 are 80%, 50%, 35%, and 20%, respectively. The thicknesses of the four aluminum gallium nitride buffer layers 3 are 100nm, 400nm, 500nm, and 500nm, respectively.

[0142] A superlattice stacking layer 4 is grown on the buffer layer 3, and the superlattice stacking layer 4 includes a first sub-superlattice layer 411, a first sub-gallium nitride layer 421, a second sub-superlattice layer 412, a second sub-gallium nitride layer 422 and a third sub-superlattice layer 413 which are stacked; the thicknesses are 500nm, 300nm, 500nm, 300nm and 500nm respectively; wherein the first sub-superlattice layer 411, the second sub-superlattice layer 412 and the third sub-superlattice layer 413 are all AlN / GaN stacking layers; in the AlN / GaN stacking layers, the thickness of the AlN layer is 5nm; the thickness of the GaN layer is 30nm; the carbon doping amounts in the first sub-superlattice layer 411, the second sub-superlattice layer 412 and the third sub-superlattice layer 413 are 1E20 / cm 3 、8E19 / cm 3 、6E19 / cm 3 The carbon doping amount in the first GaN sub-layer 421 and the second GaN sub-layer 422 is 5E19 / cm 3 .

[0143] An aluminum gallium nitride back barrier layer 5 is grown on the superlattice stack layer 4, wherein the molar content of aluminum in the back barrier layer 5 is 8%; the thickness of the back barrier layer 5 is 800 nm; and the carbon doping amount in the back barrier layer 5 is 6E18 / cm 3 , the doping method is self-doping.

[0144] An intrinsic gallium nitride channel layer 6 is grown on the back barrier layer 5 , and the thickness of the channel layer 6 is 250 nm.

[0145] An aluminum nitride insertion layer 7 and an aluminum gallium nitride barrier layer 8 are grown on the channel layer 6. The thickness of the insertion layer 7 is 2 nm. The thickness of the barrier layer 8 is 23 nm. The aluminum molar content of the barrier layer 8 is 23%.

[0146] A silicon nitride cap layer 9 is grown on the barrier layer 8 . The thickness of the cap layer 9 is 20 nm.

[0147] Example 2

[0148] The preparation method of Example 2 is the same as that of Example 1, except that the first sub-superlattice layer 411, the second sub-superlattice layer 412 and the third sub-superlattice layer 413 are all AlN / Al 0.5 Ga 0.5 N stack; in AlN / Al 0.5 Ga 0.5 In the N stack, the thickness of the AlN layer is 5nm; 0.5 Ga 0.5 The thickness of the N layer is 30 nm.

[0149] Example 3

[0150] The preparation method of Example 3 is the same as that of Example 1, except that the first sub-superlattice layer 411, the second sub-superlattice layer 412 and the third sub-superlattice layer 413 are all Al 0.5 Ga 0.5 N / GaN stack; in Al 0.5 Ga 0.5 In N / GaN stack, Al 0.5 Ga 0.5 The thickness of the N layer is 5 nm; the thickness of the GaN layer is 30 nm.

[0151] Comparative Example 1

[0152] The preparation method of comparative example 1 is the same as that of embodiment 1, except that the superlattice stacking layer 4 includes a first sub-superlattice layer 411, a first sub-gallium nitride layer 421, and a second sub-superlattice layer 412 which are stacked; the thicknesses are 750nm, 600nm, and 750nm, respectively; the carbon doping concentrations in the first sub-superlattice layer 411, the first sub-gallium nitride layer 421, and the second sub-superlattice layer 412 are 1E20 / cm 3 、5E19 / cm 3 、8E19 / cm 3 .

[0153] Performance Test:

[0154] (1) The temperature difference between the center and edge (radius = 70 mm) of the barrier layer 8 is monitored by Laytec in-situ temperature real-time monitoring technology.

[0155] (2) Monitor the warping of the barrier layer 8 through Laytec in-situ curvature real-time monitoring technology.

[0156] (3) Using a high-resolution X-ray diffractometer, the channel layer 6 was evaluated by measuring the crystal quality (FWHM) from the crystal plane index (002).

[0157] (4) Using a high-resolution X-ray diffractometer, the channel layer 6 was evaluated by measuring the crystal quality (FWHM) from the crystal plane index (102).

[0158] (5) The uniformity of the aluminum molar content in the barrier layer 8 using a photoluminescence spectrometer.

[0159] (6) Using wafer defect detector, crack length.

[0160] Table 1 shows the performance test results of the epitaxial wafers prepared in Example 1 and Comparative Example 1.

[0161]

[0162]

[0163] Result analysis:

[0164] Depend on Figure 3 From the test results in Table 1, we can see that:

[0165] (1) Since the third sub-superlattice layer 413 in the superlattice stacking layer 4 has a rebound effect on the warpage, the warpage of the epitaxial wafer prepared in Example 1 is improved, and the temperature difference between the inner and outer circles of the surface is improved. In addition, since the three-layer superlattice structure has a better dislocation blocking effect than the two-layer superlattice structure, the arc seconds of the epitaxial wafer prepared in Example 1 are improved.

[0166] (2) Due to the improvement in warpage, the stress of the epitaxial wafer during the growth process is improved, and the warpage rebound amplitude is small, so the microcracks on the epitaxial wafer are improved.

[0167] (3) As the warpage is improved, the growth conditions of the barrier layer 8 are improved, and the uniformity of the aluminum molar content in the barrier layer 8 is increased by 0.8%.

[0168] The above is a detailed introduction to the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An epitaxial wafer, characterized in that: It comprises a stacked substrate layer (1), a nucleation layer (2), a buffer layer (3), a superlattice stacking layer (4), a back barrier layer (5), a channel layer (6), an insertion layer (7), a barrier layer (8), and a cap layer (9) arranged on the barrier layer (8); Among them, the superlattice stack layer (4) includes multiple superlattice layers (41) and multiple gallium nitride layers (42), and one layer of the multiple superlattice layers (41) and one layer of the multiple gallium nitride layers (42) are alternately stacked; one layer of the multiple superlattice layers (41) is disposed on a side of the buffer layer (3) away from the nucleation layer (2), and another layer is disposed on a side of the back barrier layer (5) away from the channel layer (6), and the superlattice layer (41) is selected from any one of AlN / GaN stacks, AlN / Al a Ga 1-a N stacks, Al b Ga 1-b N / GaN stacks, Al c Ga 1-c N / Al d Ga 1-d N stacks, where 0 ≤ a < 1; 0 ≤ b < 1; 0 < c < 1, 0 ≤ d < 1, and d < c; The superlattice stacked layer (4) comprises a first sub-superlattice layer (411), a first sub-gallium nitride layer (421), a second sub-superlattice layer (412), a second sub-gallium nitride layer (422) and a third sub-superlattice layer (413) which are stacked; the first sub-superlattice layer (411) is arranged on a side of the buffer layer (3) away from the nucleation layer (2); and the third sub-superlattice layer (413) is arranged on a side of the back barrier layer (5) away from the channel layer (6).

2. The epitaxial wafer according to claim 1, characterized in that: In the AlN / GaN stack, the thickness of the AlN layer is 1 to 10 nm, and the thickness of the GaN layer is 10 to 50 nm; and / or, In the AlN / Al a Ga 1-a In the N stack, the thickness of the AlN layer is 1 to 10 nm. a Ga 1-a The thickness of the N layer is 10 to 50 nm; and / or, In the Al b Ga 1-b In the N / GaN stack, the Al b Ga 1-b The thickness of the N layer is 1 to 10 nm, and the thickness of the GaN layer is 10 to 50 nm; and / or, In the Al c Ga 1-c N / A d Ga 1-d In the N stack, the Al c Ga 1-c The thickness of the N layer is 1 to 10 nm. d Ga 1-d The thickness of the N layer is 10 to 50 nm.

3. The epitaxial wafer according to claim 1, characterized in that: The first sub-superlattice layer (411) has a first carbon doping amount Q1, the second sub-superlattice layer (412) has a second carbon doping amount Q2, and the third sub-superlattice layer (413) has a third carbon doping amount Q3, satisfying: Q3≤Q2≤Q1, and Q3≤5E18 / cm 3 .

4. The epitaxial wafer according to claim 1, characterized in that: The first gallium nitride sub-layer (421) has a fourth carbon doping amount Q4, and the second gallium nitride sub-layer (422) has a fifth carbon doping amount Q5, satisfying: 5E19 / cm 3 ≤Q4=Q5.

5. The epitaxial wafer according to claim 1, characterized in that: The first sub-superlattice layer (411) is doped with a first carbon source, wherein the first carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane and butane; and / or, The second sub-superlattice layer (412) is doped with a second carbon source, wherein the second carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane; and / or, The third sub-superlattice layer (413) is doped with a third carbon source, wherein the third carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane and butane; and / or, The first gallium nitride sub-layer (421) is doped with a fourth carbon source, wherein the fourth carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane; and / or, The second gallium nitride sub-layer (422) is doped with a fifth carbon source, and the fifth carbon source is selected from at least one of acetylene, carbon tetrabromide, ethylene, propane, and butane.

6. The epitaxial wafer according to claim 1, characterized in that: The material of the buffer layer (3) comprises k layers of aluminum gallium nitride stacked together, satisfying: 1≤k≤5; and / or, The molar content of aluminum in the buffer layer (3) ranges from 5% to 95%, and the molar content of aluminum in the buffer layer (3) gradually decreases in a direction away from the nucleation layer (2).

7. The epitaxial wafer according to claim 1, characterized in that: The material of the back barrier layer (5) is selected from at least one of AlGaN doped with the sixth carbon source or GaN doped with the seventh carbon source; and / or the carbon doping amount in the back barrier layer (5) is in the range of 1E18 to 5E18 / cm 3 ; and / or, the molar content of aluminum in the back barrier layer (5) is in the range of 3 to 10%.

8. The epitaxial wafer according to claim 1, characterized in that: The material of the barrier layer (8) includes aluminum gallium nitride; and / or the molar content of aluminum in the barrier layer (8) is in the range of 10 to 30%.

9. The epitaxial wafer according to claim 1, characterized in that: The material of the substrate layer (1) is selected from any one of silicon, silicon carbide or sapphire; and / or, The material of the nucleation layer (2) is selected from at least one of aluminum nitride and silicon nitride; and / or, The material of the channel layer (6) is selected from gallium nitride; and / or, The material of the insertion layer (7) is selected from at least one of aluminum nitride, aluminum scandium nitride, and gallium aluminum gallium nitride; and / or, The material of the cap layer (9) is selected from any one of nGaN, SiN and pGaN.

10. The epitaxial wafer according to claim 1, characterized in that: The thickness of the nucleation layer (2) is 100 to 400 nm; and / or, The thickness of the buffer layer (3) is 300 to 2000 nm; and / or, The thickness of the superlattice layer (41) is 100 to 1000 nm; and / or, The gallium nitride layer (42) has a thickness of 200 to 600 nm; and / or, The thickness of the back barrier layer (5) is 200 to 1500 nm; and / or, The thickness of the channel layer (6) is 100 to 400 nm; and / or, The thickness of the insertion layer (7) is 1 to 5 nm; and / or, The barrier layer (8) has a thickness of 10 to 30 nm; and / or, The thickness of the cap layer (9) is 1 to 120 nm.

11. A method for preparing an epitaxial wafer, characterized in that: include: Providing a substrate layer (1); forming a nucleation layer (2) on one side of the substrate layer (1); forming a buffer layer (3) on a side of the nucleation layer (2) facing away from the substrate layer (1); forming a superlattice stacking layer (4) on a side of the buffer layer (3) away from the nucleation layer (2); forming a back barrier layer (5) on a side of the superlattice stacked layer (4) facing away from the buffer layer (3); forming a channel layer (6) on a side of the back barrier layer (5) facing away from the superlattice stacked layer (4); forming an insertion layer (7) on a side of the channel layer (6) facing away from the back barrier layer (5); forming a barrier layer (8) on a side of the insertion layer (7) facing away from the channel layer (6); forming a cap layer (9) on a side of the barrier layer (8) facing away from the insertion layer (7); Among them, the superlattice stack layer (4) includes multiple superlattice layers (41) and multiple gallium nitride layers (42), and one layer of the multiple superlattice layers (41) and one layer of the multiple gallium nitride layers (42) are alternately stacked; one layer of the multiple superlattice layers (41) is disposed on a side of the buffer layer (3) away from the nucleation layer (2), and another layer is disposed on a side of the back barrier layer (5) away from the channel layer (6), and the superlattice layer (41) is selected from any one of an AlN / GaN stack, an Al a Ga 1-a N stack, an Al b Ga 1-b N / GaN stack, an Al c Ga 1-c N / Al d Ga 1-d N stack, where 0≤a<1; 0≤b<1; 0<c<1, 0≤d<1, and d<c; The superlattice layer (41) comprises a first sub-superlattice layer (411), a second sub-superlattice layer (412) and a third sub-superlattice layer (413); the gallium nitride layer (42) comprises a first sub-gallium nitride layer (421) and a second sub-gallium nitride layer (422); the first sub-gallium nitride layer (421) is located between the first sub-superlattice layer (411) and the second sub-superlattice layer (412), and the second sub-gallium nitride layer (422) is located between the second sub-superlattice layer (412) and the third sub-superlattice layer (413); the first sub-superlattice layer (411) is arranged on a side of the buffer layer (3) away from the nucleation layer (2); and the third sub-superlattice layer (413) is arranged on a side of the back barrier layer (5) away from the channel layer (6).

12. The method for preparing an epitaxial wafer according to claim 11, characterized in that: Using a first carbon source to dope the first sub-superlattice layer (411); doping the second sub-superlattice layer (412) with a second carbon source; Using a third carbon source to dope the third sub-superlattice layer (413); Using a fourth carbon source to dope the first gallium nitride sub-layer (421); The second gallium nitride sub-layer (422) is doped with a fifth carbon source.

13. The method for preparing an epitaxial wafer according to claim 12, characterized in that: The flow rate of the first carbon source is 100 to 1000 sccm; and / or, The flow rate of the second carbon source is 100 to 1000 sccm; and / or, The flow rate of the third carbon source is 100 to 1000 sccm; and / or, The flow rate of the fourth carbon source is 100 to 1000 sccm; and / or, The flow rate of the fifth carbon source is 100-1000 sccm.

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