Memory management device, method, chip, and electronic device

Abstract

The present disclosure relates to the field of storage technology, and proposes a memory management device, method, chip, and electronic device. In the memory management device, a size selection module obtains at least one page table size according to a request from a first request end; a sorting module prioritizes at least one page table size to obtain a sorting result; a judgment module starts from the page table size with the highest priority in the sorting result, and judges whether the request hits the current page table size in order from high to low priority. When the request hits the current page table size, the cache module is notified to obtain and output the physical address corresponding to the request in a first preset manner, and the judgment on the hit of the request is terminated. The memory management device supports multiple page table sizes, and the judgment on whether the request hits each page table size can be terminated after the request hits a certain page table size. When supporting more page table sizes, it can maintain a high request response efficiency and improve the throughput of the memory management device.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology and proposes a memory management device, method, chip, and electronic device. Background Art

[0002] A memory management unit (MMU) is a computer hardware that is responsible for processing address mapping requests from a central processing unit (CPU). The MMU can respond to an address mapping request and return a physical address corresponding to a virtual address included in the address mapping request.

[0003] In order to improve the response speed to address mapping requests, a cache unit can be used in the MMU to store a page table, which is used to record the historical address mapping requests received by the MMU and the physical address obtained in response to the historical address mapping request. With the rapid development of computer applications, a single page table size has gradually been unable to meet the application's higher requirements for MMU's address allocation flexibility and address space utilization, so the MMU needs to support page tables of mixed sizes. How to enable the MMU to support more page table sizes and maintain a high request response efficiency, and improve the throughput of the memory management device, has become a research hotspot in this field. Summary of the invention

[0004] In view of this, the present disclosure proposes a memory management device, method, chip, and electronic device. The cache module of the memory management device of the present disclosure embodiment supports multiple page table sizes, and the judgment of whether the request hits each page table size can be ended after the request hits a certain page table size, so that when supporting more page table sizes, a high request response efficiency can be maintained, and the throughput of the memory management device can be improved.

[0005] According to one aspect of the present disclosure, a memory management device is provided, including a cache module, a size selection module, a sorting module, and a judgment module. The cache module supports multiple page table sizes. The size selection module is used to select at least one page table size from the multiple page table sizes according to a request from a first request end, output the at least one page table size to the sorting module, and output the request to the judgment module; the sorting module is used to prioritize the at least one page table size according to the hit situation of the at least one page table size by historical requests from the first request end, and output the sorting result to the judgment module; the judgment module is used to, starting from the page table size with the highest priority in the sorting result, judge whether the request hits the current page table size in order from high to low priority, and when the request hits the current page table size, notify the cache module to obtain and output the physical address corresponding to the request in a first preset manner, and end the judgment on the hit situation of the request.

[0006] In one possible implementation, the sorting module is specifically used to determine the frequency of hitting the at least one page table size based on the hit status of the historical requests of the first request end for the at least one page table size; determine the priority of the at least one page table size based on the frequency of hitting the at least one page table size, wherein a page table size with a larger frequency has a higher priority, and a page table size with the same frequency, a later hit time has a higher priority.

[0007] In one possible implementation, the size selection module is specifically used to, based on the request, query the size configuration mask corresponding to the first request end, each bit of the size configuration mask corresponds to one of the multiple page table sizes, and the value of each bit indicates whether the first request end is allowed to use the corresponding page table size; based on the value of each bit in the size configuration mask, select the page table size that the first request end indicates is allowed to be used as the at least one page table size.

[0008] In one possible implementation, the cache module includes multiple cache units, the request includes a first virtual address, and the judgment module is specifically used to generate a first destination address according to the current page table size and the first virtual address, and the first destination address corresponds to a cache unit in the cache module; access the cache unit at the first destination address, and read the virtual address queue stored in the cache unit; determine whether the virtual address queue includes the first virtual address, and when the virtual address queue includes the first virtual address, determine that the request hits the current page table size; when the virtual address queue does not include the first virtual address, determine that the request does not hit the current page table size; the first preset method includes enabling the cache unit corresponding to the first destination address to find and output the physical address corresponding to the request from its own storage area.

[0009] In one possible implementation, the judgment module is also used to, when the request hits any page table size, output the request and the page table size hit by the request to the sorting module; the sorting module is also used to, when receiving the request and the page table size hit by the request, increase the page table size hit by the number of historical request hits by the first request end by one.

[0010] In one possible implementation, the judgment module is also used to, when the request does not hit the current page table size and there are other page table sizes ranked lower than the current page table size, use the next page table size as the current page table size, and re-execute the steps of judging whether the request hits the current page table size and subsequent steps; when the request does not hit the current page table size and the current page table size is already the lowest ranked page table size, notify the cache module to obtain and output the physical address corresponding to the request in a second preset manner, and end the judgment on the hit status of the request.

[0011] In a possible implementation manner, the second preset manner includes enabling a cache unit corresponding to the first destination address to obtain and output a physical address corresponding to the request from an off-chip physical address storage module.

[0012] According to another aspect of the present disclosure, a memory management method is provided, the method is applied to a memory management device, the memory management device includes a cache module, a size selection module, a sorting module, and a judgment module, the cache module supports multiple page table sizes, the method includes: the size selection module selects at least one page table size from the multiple page table sizes according to a request from a first request end, outputs the at least one page table size to the sorting module, and outputs the request to the judgment module; the sorting module prioritizes the at least one page table size according to the hit situation of the at least one page table size by historical requests of the first request end, and outputs the sorting result to the judgment module; the judgment module starts from the page table size with the highest priority in the sorting result, and judges whether the request hits the current page table size in order from high to low priority; when the request hits the current page table size, the judgment module notifies the cache module to obtain and output the physical address corresponding to the request in a first preset manner, and ends the judgment on the hit situation of the request.

[0013] In a possible implementation, the priority sorting of the at least one page table size according to the hit situation of the at least one page table size by the historical requests of the first request end includes: determining the frequency of the at least one page table size being hit according to the hit situation of the at least one page table size by the historical requests of the first request end; determining the priority of the at least one page table size according to the frequency of the at least one page table size being hit, wherein a page table size with a greater frequency has a higher priority, and a page table size with the same frequency, a later hit time has a higher priority.

[0014] In one possible implementation, selecting at least one page table size from the multiple page table sizes according to the request of the first request end includes: querying a size configuration mask corresponding to the first request end according to the request, each bit of the size configuration mask corresponding to one of the multiple page table sizes, and the value of each bit indicating whether the first request end is allowed to use the corresponding page table size; and selecting, according to the value of each bit in the size configuration mask, the page table size indicated by the first request end to be allowed to be used as the at least one page table size.

[0015] In one possible implementation, the cache module includes multiple cache units, the request includes a first virtual address, and starting from the page table size with the highest priority in the sorting result, judging whether the request hits the current page table size in order from high to low priority includes: generating a first destination address according to the current page table size and the first virtual address, the first destination address corresponding to a cache unit in the cache module; accessing the cache unit at the first destination address and reading the virtual address queue stored in the cache unit; judging whether the virtual address queue includes the first virtual address, and judging that the request hits the current page table size when the virtual address queue includes the first virtual address, and judging that the request does not hit the current page table size when the virtual address queue does not include the first virtual address; the first preset method includes enabling the cache unit corresponding to the first destination address to find and output the physical address corresponding to the request from its own storage area.

[0016] In a possible implementation, the method further includes: when the request hits any page table size, the judgment module outputs the request and the page table size hit by the request to the sorting module; when the sorting module receives the request and the page table size hit by the request, the page table size hit by the request is increased by one by the number of historical request hits of the first request end.

[0017] In a possible implementation, the method further includes: when the request does not hit the current page table size and there are other page table sizes ranked lower than the current page table size, the judgment module uses the next page table size as the current page table size, and re-executes the steps of judging whether the request hits the current page table size and subsequent steps; when the request does not hit the current page table size and the current page table size is already the lowest ranked page table size, the judgment module notifies the cache module to obtain and output the physical address corresponding to the request in a second preset manner, and ends the judgment on the hit situation of the request.

[0018] In a possible implementation manner, the second preset manner includes enabling a cache unit corresponding to the first destination address to obtain and output a physical address corresponding to the request from an off-chip physical address storage module.

[0019] According to another aspect of the present disclosure, a chip is provided, comprising the memory management device described above.

[0020] According to another aspect of the present disclosure, an electronic device is provided, comprising the chip described above and an off-chip physical address storage module.

[0021] According to the memory management device of the embodiment of the present disclosure, a size selection module can be used to select at least one page table size from a plurality of page table sizes in advance when responding to the request of the first request end, thereby reducing the upper limit of the number of judgments of the judgment module on the hit situation of the requested page table size, thereby reducing the time cost and the upper limit of the power consumption of the memory management device when responding to the request; a sorting module is used to prioritize at least one page table size according to the hit situation of the historical requests of the first request end on at least one page table size, and the sorting result is output to the judgment module. The judgment module starts from the page table size with the highest priority in the sorting result and judges whether the request hits the current page table size in order from high to low priority. When the request hits the current page table size, the cache module is notified to obtain and output the physical address corresponding to the request in a first preset manner, and the judgment on the hit situation of the request is ended, thereby reducing the time cost waste of judging whether the request also hits other page table sizes when it has been judged that the request hits a certain page table size, enabling the cache module to support more page table sizes, and ensuring a higher request response efficiency, thereby improving the throughput of the memory management device.

[0022] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0024] Figure 1 An exemplary application scenario of the memory management device according to an embodiment of the present disclosure is shown.

[0025] Figure 2 A schematic diagram showing the structure of a memory management device according to an embodiment of the present disclosure.

[0026] Figure 3 A schematic diagram showing the workflow of the judgment module and the cache module according to an embodiment of the present disclosure.

[0027] Figure 4 A schematic diagram showing the process of a memory management method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0029] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0030] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0031] A memory management unit (MMU) is a computer hardware that is responsible for processing address mapping requests from a central processing unit (CPU). The MMU can respond to an address mapping request and return a physical address corresponding to a virtual address included in the address mapping request.

[0032] In order to improve the response speed to address mapping requests, the MMU can use a cache unit to store page tables, which are used to record historical address mapping requests received by the MMU and the physical addresses obtained in response to the historical address mapping requests. With the rapid development of computer applications, a single page table size has gradually failed to meet the application's higher requirements for MMU's address allocation flexibility and address space utilization, so the MMU needs to support mixed-size page tables.

[0033] An MMU usually includes multiple cache units, each of which stores a corresponding page table. To ensure load balancing between cache units and improve cache resource utilization, the MMU of the prior art usually adopts the following two solutions to support mixed-size page tables:

[0034] The first solution is to divide the virtual address space into multiple intervals, and pre-specify the page table size used by each interval. When responding to each address mapping request, the corresponding interval is directly found according to the virtual address included in the address mapping request, and the appropriate cache unit is selected according to the page table size used by the interval to return the physical address corresponding to the virtual address included in the address mapping request. This solution selects the cache unit for returning the physical address statically, and its disadvantage is that the granularity of space segmentation is large and not precise enough, resulting in serious waste of virtual address space.

[0035] Solution 2 uses descriptors to describe the various page table sizes to be supported. When responding to each address mapping request, it is necessary to loop through the hits for each page table size, and then select the appropriate cache unit based on the hits to return the physical address corresponding to the virtual address included in the address mapping request. This solution is dynamic in selecting the cache unit that returns the physical address. The disadvantage is that the time cost and power consumption increase with the number of page table sizes. Therefore, in order to ensure the efficiency of request response, only a small number of page table sizes can be supported. When the page table size is small, the cost of looping through the hits for each page table size is lower. Therefore, in Solution 2, even if a hit has been determined during the loop, it is still necessary to complete the traversal and determination of all page table sizes.

[0036] Moreover, neither Scheme 1 nor Scheme 2 takes into account the differences in address space usage by different applications. When multiple request ends share the MMU, the flexibility of page table size allocation is greatly reduced.

[0037] In summary, how to enable the MMU to support more page table sizes and maintain a high request response efficiency to improve the throughput of the memory management device has become a research hotspot in this field.

[0038] In view of this, the present disclosure proposes a memory management device, method, chip, and electronic device. The cache module of the memory management device of the present disclosure embodiment supports multiple page table sizes, and the judgment of whether the request hits each page table size can be ended after the request hits a certain page table size, so that when supporting more page table sizes, a high request response efficiency can be maintained, and the throughput of the memory management device can be improved.

[0039] Furthermore, when the memory management device of the present invention is shared by multiple requesting ends, the page table size preferred by the requesting end is selected in a targeted manner for hit judgment in combination with the preference setting of each requesting end for the page table size, thereby making the allocation of the page table size more flexible.

[0040] Figure 1 An exemplary application scenario of the memory management device according to an embodiment of the present disclosure is shown.

[0041] like Figure 1As shown, the application scenario may include a memory management device and a central processing unit arranged on a chip, and an off-chip physical address storage module that can communicate with the memory management device. The central processing unit runs a variety of applications, and different applications can be used by different request ends (including the first request end described below). In the process of the request end using the application, the central processing unit may be triggered to access the memory (which may be an off-chip physical address storage module or other memory), and the central processing unit may generate an address mapping request (such as the request of the first request end described below) in response, and the address mapping request includes a virtual address. The address mapping request is output to the memory management device.

[0042] Among them, the request end refers to a logical object, including a virtual machine, an application, different processes of an application, etc. Different request ends are independent access sources of the virtual address space. The present disclosure does not limit the specific type of the request end.

[0043] The memory management device can respond to the address mapping request, determine the hit of the request on the page table size supported by the cache module included in it, and notify the cache module to return the physical address corresponding to the address mapping request to the central processing unit in a certain manner (such as the first preset manner or the second preset manner described below). The physical address can be an address on the memory. Optionally, when the cache module is notified to return the physical address in the second preset manner, it can access the off-chip physical address storage module to obtain the physical address corresponding to the address mapping request. After the central processing unit obtains the physical address, it can access the memory to complete data reading / writing.

[0044] Figure 2 A schematic diagram showing the structure of a memory management device according to an embodiment of the present disclosure.

[0045] like Figure 2 As shown, in a possible implementation, the present disclosure proposes a memory management device, including a cache module, a size selection module, a sorting module, and a judgment module. The cache module supports multiple page table sizes.

[0046] The size selection module is used to select at least one page table size from a plurality of page table sizes according to a request from the first request end, output the at least one page table size to the sorting module, and output the request to the determination module;

[0047] The sorting module is used to prioritize at least one page table size according to the hit status of the historical request of the first request end on at least one page table size, and output the sorting result to the judgment module;

[0048] The judgment module is used to judge whether the request hits the current page table size, starting from the page table size with the highest priority in the sorting result, in order from high to low priority. When the request hits the current page table size, the cache module is notified to obtain and output the physical address corresponding to the request in a first preset manner, and the judgment on the hit of the request is ended.

[0049] For example, the memory management device includes a cache module, a size selection module, a sorting module, and a judgment module. The cache module is used to store page tables and supports multiple page table sizes. The cache module can be a hardware module, and the size selection module, the sorting module, and the judgment module can be a hardware module or a software module, which is not limited in the present disclosure.

[0050] The size selection module can communicate with other modules (such as a central processing unit) outside the memory management device, and can receive address mapping requests generated by other modules, such as a request from a first request end. According to the request from the first request end, the size selection module can select at least one page table size from a plurality of page table sizes, and when the subsequent judgment module loops to judge the hit condition of the page table size, it is not necessary to judge the page table size that is not selected by the size selection module.

[0051] Each address mapping request corresponds to a request end. Therefore, at least one page table size selected according to each address mapping request may also correspond to the request end corresponding to the address mapping request. For example, at least one page table size selected according to the request of the first request end may correspond to the first request end, and at least one page table size selected according to the request of the second request end may correspond to the second request end. The size selection module may receive multiple address mapping requests corresponding to multiple request ends at the same time. In this case, the size selection module may respond to multiple address mapping requests in parallel and select at least one page table size corresponding to each request end.

[0052] A request end may have more than one address mapping request. At least one page table size selected by the size selection module in response to different requests from the same request end may be the same. At least one page table size corresponding to each request end may be specified by the request end. The correspondence between the request end and at least one page table size may be stored in the size selection module. Through the stored correspondence, the size selection module may select at least one page table size according to any request.

[0053] The size selection module can output at least one selected page table size to the sorting module and output a request to the judgment module. When the size selection module outputs at least one page table size, the identifier of the requesting end can be added. For example, at least one page table size selected according to the request of the first requesting end can be output to the sorting module together with the identifier of the first requesting end, and at least one page table size selected according to the request of the second requesting end can be output to the sorting module together with the identifier of the second requesting end, so that when the sorting module receives at least one page table size, it can determine the requesting end corresponding to the at least one page table size. The request itself can also carry the identifier of the corresponding requesting end. Therefore, each module that receives the request of the first requesting end can directly determine that the request corresponds to the first requesting end.

[0054] The sorting module can communicate with the size selection module and the judgment module respectively. The sorting module can record the hits of the historical requests of each request end to each page table size, wherein the historical request refers to the address mapping request that the memory management device has received and responded to. When the sorting module receives at least one page table size from the size selection module, assuming that it is determined that the at least one page table size corresponds to the first request end, it can query the hits of the historical requests of the first request end to at least one page table size, and prioritize the at least one page table size according to the hits of the historical requests of the first request end to at least one page table size. The priority of each page table size determines the order of the page table sizes judged when the subsequent judgment module judges the hits of the page table sizes in response to the request loop of the first request end. The sorting module can output the sorting result to the judgment module. An example of priority sorting is given later.

[0055] Furthermore, the sorting module may simultaneously receive multiple groups of page table sizes corresponding to multiple request ends (each group of page table sizes includes at least one page table size corresponding to the request end). In this case, the sorting module can prioritize the multiple groups of page table sizes in parallel. When outputting the sorting results, the identifier of the request end can be added. For example, the sorting result of at least one page table size selected according to the request of the first request end can be output to the judgment module together with the identifier of the first request end. The sorting result of at least one page table size selected according to the request of the second request end can be output to the judgment module together with the identifier of the second request end, so that when the judgment module receives a certain sorting result, it can determine the request end corresponding to the sorting result.

[0056] The judgment module can communicate with the sorting module and the cache module. When the judgment module receives a request from the size selection module, it can determine that a round of cyclic judgment on the hit of the request of the first request end to the page table size needs to be completed. The number of judgments required for this round of cyclic judgment does not exceed the number of types of page table sizes allowed to be used by the received first request end. Taking a round of cyclic judgment corresponding to the request of the first request end as an example, starting from the page table size with the highest priority in the sorting result, in order from high to low priority, it is judged whether the request hits the current page table size. When the request hits the current page table size, the hit return process is started, that is, the cache module is notified to obtain the physical address corresponding to the request in the first preset manner and output it to the initiator of the request, and the judgment on the hit of the request is ended at the same time, that is, the current round of cyclic judgment is jumped out. The details of the judgment module judging whether the request hits the current page table size, the details of notifying the cache module, and an example of the first preset method are given later.

[0057] Furthermore, the judgment module may complete multiple rounds of cyclic judgments on hit situations of multiple address mapping requests in parallel to improve request response efficiency.

[0058] According to the memory management device of the embodiment of the present disclosure, a size selection module can be used to select at least one page table size from a plurality of page table sizes in advance when responding to the request of the first request end, thereby reducing the upper limit of the number of judgments of the judgment module on the hit situation of the requested page table size, thereby reducing the time cost and the upper limit of the power consumption of the memory management device when responding to the request; a sorting module is used to prioritize at least one page table size according to the hit situation of the historical requests of the first request end on at least one page table size, and the sorting result is output to the judgment module. The judgment module starts from the page table size with the highest priority in the sorting result and judges whether the request hits the current page table size in order from high to low priority. When the request hits the current page table size, the cache module is notified to obtain and output the physical address corresponding to the request in a first preset manner, and the judgment on the hit situation of the request is ended, thereby reducing the time cost waste of judging whether the request also hits other page table sizes when it has been judged that the request hits a certain page table size, enabling the cache module to support more page table sizes, and ensuring a higher request response efficiency, thereby improving the throughput of the memory management device.

[0059] For the sake of clarity, the requests that appear below are all considered to be requests from the first request end.

[0060] In a possible implementation, the sorting module is specifically used to:

[0061] Determining a frequency of hitting at least one page table size according to hit conditions of historical requests of the first request end for at least one page table size;

[0062] The priority of at least one page table size is determined according to the frequency at which at least one page table size is hit, wherein a page table size with a greater frequency has a higher priority, and a page table size with a same frequency has a higher priority when it is hit later.

[0063] For example, there is locality in the access of the application to the memory, that is, multiple address mapping requests corresponding to a certain request end usually repeatedly hit the same page table size. Based on this, when the sorting module records the hits of the historical requests of each request end to each page table size, it can record, for each page table size corresponding to the request end, the number of times the page table size was hit when responding to the historical requests of the request end and the time of the most recent hit. In this case, when the sorting module determines the priority order of at least one page table size, it can determine the frequency of each page table size being hit according to the number of times each page table size in at least one page table size is hit.

[0064] The sorting module can determine the priority of at least one page table size according to the frequency of at least one page table size being hit, wherein the page table size with a greater frequency has a higher priority, and the page table size with the same frequency has a higher priority the later it is hit. In this case, the probability of a page table size being hit with a higher priority is also higher, and when the judgment module makes a cyclic judgment based on the order from high to low priority, the earlier it judges that the request hits a certain page table size, the higher the probability is. Thus, a round of cyclic judgment can be ended earlier.

[0065] If the request from the first request end occurs for the first time, that is, there is no historical request from the first request end, the priority of at least one page table size may be determined in a default order.

[0066] In this way, the probability of judging a hit at the beginning of a loop judgment can be improved, the time consumed by the judgment module in a round of loop judgment can be reduced, and the judgment power consumption can be reduced.

[0067] Those skilled in the art should understand that the priority of the page table size may also be determined in other ways, such as randomly determining or determining only based on the number of times the page table size is hit by historical requests from the first request end. The embodiments of the present disclosure do not limit the specific method for determining the priority of the page table size.

[0068] In a possible implementation, the size selection module is specifically used to:

[0069] In response to the request, querying a size configuration mask corresponding to the first request end, each bit of the size configuration mask corresponds to one of a plurality of page table sizes, and a value of each bit indicates whether the first request end is allowed to use the corresponding page table size;

[0070] According to the value of each bit in the size configuration mask, a page table size indicated by the first request end as allowed to be used is selected as at least one page table size.

[0071] For example, the parameters that may be used by the memory management device can be pre-configured in the size selection module through the register configuration method of the prior art, such as the size configuration mask corresponding to each request end. Among them, each bit of the size configuration mask corresponds to one of a plurality of page table sizes, and the value of each bit indicates whether the request end corresponding to the size configuration mask is allowed to use the corresponding page table size. For example, "0" can indicate that the corresponding page table size is not allowed to be used, and "1" indicates that the corresponding page table size is allowed to be used. That is, the size configuration mask can indicate the correspondence between the request end and the page table size.

[0072] The size selection module may query the size configuration mask corresponding to the first request end according to the request of the first request end, and select the page table size indicated by the first request end as at least one page table size according to the value of each bit in the size configuration mask. In one example, when there are 8 supported page table sizes, if the size configuration mask corresponding to the first request end is 0000 1111. It may indicate that the first request end is not allowed to use the 1st to 4th page table sizes, and is allowed to use the 5th to 8th page table sizes. At this time, the at least one page table size selected may include the 5th to 8th page table sizes.

[0073] Those skilled in the art should understand that as long as whether the first request end is allowed to use the corresponding page table size corresponds to different values, the embodiment of the present disclosure does not limit the relationship between the value of each bit of the size configuration mask and whether the first request end is allowed to use the corresponding page table size.

[0074] In this way, the flexibility of page table size allocation for applications on different request ends can be improved.

[0075] Those skilled in the art should understand that the page table size corresponding to each request end may also be determined in other ways, such as setting a corresponding sub-mask for each page table size, so that the size configuration mask corresponding to the request end includes the sub-mask of the page table size allowed to be used by the request end, and the page table size allowed to be used by the request end can be found according to the sub-mask included in the size configuration mask. The embodiments of the present disclosure do not limit the specific method for determining the page table size corresponding to each request end.

[0076] In a possible implementation, the judgment module is further used to, when the request hits any page table size, output the request and the page table size hit by the request to the sorting module;

[0077] The sorting module is also used to, when receiving the request and the page table size of the request hit, increase the page table size of the request hit by the number of historical request hits of the first request end by one.

[0078] For example, if the judgment module determines that the request of the first request end hits a certain page table size, the request and the page table size hit by the request can be output to the sorting module. When the sorting module receives the request of the first request end and the page table size hit by the request, it can determine that the hit status of the historical requests of the first request end for each page table size needs to be updated. And the update method can be: increase the number of times the page table size hit by the historical requests of the first request end by one. Accordingly, the time when the request and the page table size hit by the request are received can be used to update the time when the page table size hit by the historical requests of the first request end was last hit.

[0079] In this way, the sorting module can timely update the hit status of historical requests on the page table size, thereby improving the accuracy of subsequent judgment on the hit status of other received requests on the page table size.

[0080] The following describes the details of the determination module determining whether the request hits the current page table size, the details of notifying the cache module, and an example of the first preset method.

[0081] In a possible implementation, the cache module includes a plurality of cache units, the request includes a first virtual address, and the determination module is specifically configured to:

[0082] Generate a first destination address according to the current page table size and the first virtual address, the first destination address corresponding to a cache unit in the cache module;

[0083] Accessing a cache unit at a first destination address, and reading a virtual address queue stored in the cache unit;

[0084] Determine whether the virtual address queue includes the first virtual address, and when the virtual address queue includes the first virtual address, determine that the request hits the current page table size; when the virtual address queue does not include the first virtual address, determine that the request does not hit the current page table size;

[0085] The first preset manner includes causing the cache unit at the first destination address to find the physical address corresponding to the request from its own storage area and output it.

[0086] Figure 3 A schematic diagram showing the workflow of the judgment module and the cache module according to an embodiment of the present disclosure.

[0087] For example, the cache module may include multiple cache units, each of which stores a corresponding page table. The request from the first request end received by the memory management device may include the first virtual address. Figure 3As shown, the judgment module first determines the page table size to be judged this time (that is, the current page table size) according to the priority sorting result of the page table size corresponding to the first request end, and generates a first destination address according to the page table size and the first virtual address. The generation of the first destination address can be implemented based on the existing technology. For example, an address segment corresponding to the page table size can be selected in the first virtual address according to the page table size, and the address segment is hashed to obtain the first destination address. The first destination address can be a read address of a static random access memory, corresponding to a cache unit in the cache module. When the page table sizes are different, the address segments selected in the first virtual address according to the page table size are different. In this way, the load balancing between the cache units can be guaranteed, and the cache resource utilization rate can be improved. The embodiment of the present disclosure does not limit the specific method of generating the first destination address according to the first virtual address.

[0088] The judgment module can access the cache unit corresponding to the first destination address, read the virtual address queue stored in the cache unit, the addresses in the virtual address queue can be virtual addresses included in the historical requests responded to by the cache unit, and the cache unit also stores physical addresses corresponding to the addresses in the virtual address queue. These physical addresses are also physical addresses corresponding to the historical requests responded to by the cache unit.

[0089] The judgment module can judge whether the virtual address queue includes the first virtual address. If the virtual address queue includes the first virtual address, it means that the physical address corresponding to the request has been stored in the cache unit, and the request hits the current page table size. If the virtual address queue does not include the first virtual address, it means that the physical address corresponding to the first request is not stored in the cache unit, and the request does not hit the current page table size.

[0090] When the request hits the current page table size, the judgment module notifies the cache module to obtain and output the physical address corresponding to the request in a first preset manner. Under the first preset manner, the cache module does not need to access the off-chip physical address storage module. The cache module itself has stored the physical address corresponding to the request, and the cache module can directly output the physical address corresponding to the request. The judgment module can send a first signal to the cache module, and the first signal indicates the identifier of the first preset method and the identifier of the cache unit corresponding to the first destination address, and includes the request. After the cache module receives the first signal, according to the indication of the first signal, the cache unit corresponding to the first destination address can find the physical address corresponding to the request from its own storage area and output it to the initiator of the request in accordance with the first preset method.

[0091] For example, assume that the first requestor corresponds to N page table sizes, and the first to i-1 page table sizes are not hit by the request. N is an integer greater than 2, 1 < i < N, and i is an integer. When the determination module determines whether the request hits the i-th page table size, it can select the address segment corresponding to the i-th page table size from the first virtual address, and perform hash processing on the address segment to obtain the i-th first destination address. The determination module can access the cache unit corresponding to the i-th first destination address (such as cache unit 1), read the virtual address queue stored in the cache unit 1, and determine whether the virtual address queue includes the first virtual address. If the virtual address queue includes the first virtual address, it means that the physical address corresponding to the request has been stored in the cache unit 1, and the request hits the i-th page table size. If the virtual address queue does not include the first virtual address, it means that the physical address corresponding to the request is not stored in the cache unit 1, and the request does not hit the i-th page table size. When the request hits the i-th page table size, the determination module sends a first signal to the cache module. The first signal indicates the identifier of the first preset method and the identifier of cache unit 1, and includes the request. After receiving the first signal, the cache module can, according to the indication of the first signal, in accordance with the first preset method, make cache unit 1 find out the physical address corresponding to the request from its own storage area and output it to the initiator of the request.

[0092] In this way, when the request hits any page table size, the cache module can quickly return the physical address corresponding to the first request.

[0093] In a possible implementation, the determination module is further configured to,

[0094] When the request does not hit the current page table size and there are other page table sizes with a lower order than the current page table size, use the next page table size as the current page table size and re-execute the steps of determining whether the request hits the current page table size and subsequent steps;

[0095] When the request does not hit the current page table size and the current page table size is already the page table size with the lowest order, notify the cache module to obtain the physical address corresponding to the request in the second preset manner and output it, and end the determination of the hit situation of the request.

[0096] For example, if the request does not hit (also called miss) the current page table size, and there are other page table sizes ranked lower than the current page table size, then the cyclic judgment of the hit situation of the request needs to continue, and the next page table size can be used as the current page table size, and the steps of judging whether the request hits the current page table size and the subsequent steps are re-executed until the request hits a certain page table size; if the request does not hit the current page table size, and the current page table size is already the lowest ranked page table size, it can be considered that at least one page table size corresponding to the first request end is not hit, and there is no cache unit in the cache module to store the physical address corresponding to the request. At this time, the judgment module can start the missing return process, notify the cache module to obtain and output the physical address corresponding to the request in the second preset mode, and end the judgment of the hit situation of the request. In the second preset mode, the cache module accesses the off-chip physical address storage module to obtain the physical address corresponding to the request and then outputs it.

[0097] In a possible implementation manner, the second preset manner includes enabling a cache unit corresponding to the first destination address to obtain and output a physical address corresponding to the request from an off-chip physical address storage module.

[0098] For example, when the request does not hit the current page table size, and the current page table size is already the lowest ranked page table size, when notifying the cache module, the judgment module may send a second signal to the cache module, the second signal indicating the identifier of the second preset method and the identifier of the cache unit corresponding to the first destination address, and including the request. After receiving the second signal, the cache module may, according to the indication of the second signal, enable the cache unit corresponding to the first destination address to obtain the physical address corresponding to the request from the off-chip physical address storage module in accordance with the second preset method and output it to the initiator of the request.

[0099] For example, assuming that the first request end corresponds to N page table sizes, the 1st to N-1st page table sizes are not hit by the request, and the Nth page table size is the lowest priority among the N page table sizes, and N is an integer greater than 2. When the judgment module judges whether the request hits the Nth page table size, the address segment corresponding to the Nth page table size can be selected from the first virtual address, and the address segment is hashed to obtain the Nth first destination address. The judgment module can access the cache unit (such as cache unit 2) corresponding to the Nth first destination address, read the virtual address queue stored in the cache unit 2, and judge whether the virtual address queue includes the first virtual address. If the virtual address queue does not include the first virtual address, it means that the physical address corresponding to the request is not stored in the cache unit 2, and the request does not hit the Nth page table size. The request does not hit the Nth page table size, and the Nth page table size is already the lowest ranked page table size, so the judgment module sends a second signal to the cache module, and the second signal indicates the identifier of the second preset mode and the identifier of the cache unit 2, and includes the request. After receiving the second signal, the cache module can, according to the instruction of the second signal, enable the cache unit 2 to access the off-chip physical address storage module to obtain the physical address corresponding to the request in a second preset manner, and output it to the initiator of the request. Furthermore, the cache module can also enable the cache unit 2 to store the request and the physical address corresponding to the request in its own storage area. In this case, when other address mapping requests including the same virtual address as the request are subsequently received, the hit return process can be directly started without obtaining the physical address from the off-chip physical address storage module, thereby improving the request response efficiency.

[0100] Optionally, when the judgment module determines that the request does not hit the i-th page table size, the request can also be sent to the cache unit corresponding to the i-th first destination address calculated according to the i-th page table size. And when it is judged that the request hits the k-th page table size, the identifier of the cache unit (first group of cache units) corresponding to the first destination address calculated according to other page table sizes with a priority higher than the k-th page table size is also sent to the cache module along with the first signal. In the cache module, the cache unit corresponding to the k-th first destination address (calculated according to the k-th page table size when judging the hit of the request on the page table size) can send the read physical address corresponding to the request to the first group of cache units. After receiving the physical address corresponding to the request, the first group of cache units can store the physical address corresponding to the request and the request in their own storage area.

[0101] Optionally, when the judgment module determines that the request does not hit N page table sizes, the request can also be sent to N cache units (second group of cache units) corresponding to the N first destination addresses calculated according to the N page table sizes. And the identifier of the second group of cache units is also sent to the cache module with the second signal. In the cache module, the cache unit that reads the physical address corresponding to the request can send the read physical address corresponding to the request to the second group of cache units. After receiving the physical address corresponding to the request, the second group of cache units can store the physical address corresponding to the request and the request in their own storage area.

[0102] In this way, when other address mapping requests including the same virtual address as the request are subsequently received, the probability of determining the request hitting the page table size earlier can be improved, thereby improving the request response efficiency.

[0103] The present disclosure also provides a chip, including the memory management device described above. The schematic diagram of the chip structure can be found in Figure 1 .

[0104] The present disclosure also provides an electronic device, comprising the above-mentioned chip and an off-chip physical address storage module. The electronic device may be a terminal device or a server, and the present disclosure does not limit the specific type of the electronic device.

[0105] The present disclosure also provides a memory management method. Figure 4 A schematic diagram showing the process of a memory management method according to an embodiment of the present disclosure.

[0106] like Figure 4 As shown, in a possible implementation, the method is applied to a memory management device, the memory management device includes a cache module, a size selection module, a sorting module, and a judgment module, the cache module supports multiple page table sizes, and the method includes:

[0107] Step S41, the size selection module selects at least one page table size from a plurality of page table sizes according to the request of the first request end, outputs the at least one page table size to the sorting module, and outputs the request to the determination module;

[0108] Step S42, the sorting module prioritizes at least one page table size according to the hit status of the historical request of the first request end on at least one page table size, and outputs the sorting result to the judgment module;

[0109] Step S43, the judgment module starts from the page table size with the highest priority in the sorting result, and judges whether the request hits the current page table size in descending order of priority;

[0110] Step S44, when the request hits the current page table size, the judgment module notifies the cache module to obtain and output the physical address corresponding to the request in a first preset manner, and ends the judgment on the hit status of the request.

[0111] In a possible implementation, the prioritizing the at least one page table size according to a hit condition of the historical request of the first request end on the at least one page table size includes:

[0112] Determining a frequency of hitting the at least one page table size according to hit conditions of historical requests of the first request end for the at least one page table size;

[0113] The priority of the at least one page table size is determined according to the frequency at which the at least one page table size is hit, wherein a page table size with a greater frequency has a higher priority, and a page table size with a same frequency has a higher priority when it is hit later.

[0114] In a possible implementation, selecting at least one page table size from the multiple page table sizes according to the request of the first request end includes:

[0115] According to the request, query the size configuration mask corresponding to the first request end, each bit of the size configuration mask corresponds to one of the multiple page table sizes, and the value of each bit indicates whether the first request end is allowed to use the corresponding page table size;

[0116] According to the value of each bit in the size configuration mask, a page table size indicated by the first request end as being allowed to be used is selected as the at least one page table size.

[0117] In a possible implementation, the cache module includes a plurality of cache units, the request includes a first virtual address,

[0118] The step of starting from the page table size with the highest priority in the sorting result and judging whether the request hits the current page table size in descending order of priority includes:

[0119] Generate a first destination address according to the current page table size and the first virtual address, wherein the first destination address corresponds to a cache unit in the cache module;

[0120] Accessing the cache unit at the first destination address, and reading the virtual address queue stored in the cache unit;

[0121] Determine whether the virtual address queue includes the first virtual address, and when the virtual address queue includes the first virtual address, determine that the request hits the current page table size; and when the virtual address queue does not include the first virtual address, determine that the request does not hit the current page table size;

[0122] The first preset manner includes enabling the cache unit corresponding to the first destination address to find the physical address corresponding to the request from its own storage area and output it.

[0123] In a possible implementation, the method further includes:

[0124] When the request hits any page table size, the judging module outputs the request and the page table size hit by the request to the sorting module;

[0125] When receiving the request and the size of the page table hit by the request, the sorting module increases the size of the page table hit by the number of historical request hits by the first request end by one.

[0126] In a possible implementation, the method further includes:

[0127] When the request does not hit the current page table size and there are other page table sizes ranked lower than the current page table size, the judging module uses the next page table size as the current page table size and re-executes the steps of judging whether the request hits the current page table size and subsequent steps;

[0128] When the request does not hit the current page table size and the current page table size is already the lowest ranked page table size, the judgment module notifies the cache module to obtain and output the physical address corresponding to the request in a second preset manner, and ends the judgment on the hit status of the request.

[0129] In a possible implementation manner, the second preset manner includes enabling a cache unit corresponding to the first destination address to obtain and output a physical address corresponding to the request from an off-chip physical address storage module.

[0130] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0131] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A memory management device, characterized in that: It includes a cache module, a size selection module, a sorting module, and a judgment module. The cache module includes multiple cache units, each cache unit stores a corresponding page table, and the page table is used to record historical requests and physical addresses obtained in response to the historical requests. The cache module supports multiple page table sizes. The size selection module is used to select at least one page table size from the multiple page table sizes according to the request of the first request end, output the at least one page table size to the sorting module, and output the request to the determination module; The sorting module is used to prioritize the at least one page table size according to the hit status of the historical request of the first request end on the at least one page table size, and output the sorting result to the judgment module; The judgment module is used to judge whether the request hits the current page table size, starting from the page table size with the highest priority in the sorting result, in order from high to low priority. When the request hits the current page table size, the cache module is notified to find and output the physical address corresponding to the request from the storage area of ​​the included cache unit in a first preset manner, and the judgment on the hit of the request is ended.

2. The device according to claim 1, characterized in that The sorting module is specifically used for: Determining a frequency of hitting the at least one page table size according to hit conditions of historical requests of the first request end for the at least one page table size; The priority of the at least one page table size is determined according to the frequency at which the at least one page table size is hit, wherein a page table size with a greater frequency has a higher priority, and a page table size with a same frequency has a higher priority when it is hit later.

3. The device according to claim 1, characterized in that The size selection module is specifically used to: According to the request, query the size configuration mask corresponding to the first request end, each bit of the size configuration mask corresponds to one of the multiple page table sizes, and the value of each bit indicates whether the first request end is allowed to use the corresponding page table size; According to the value of each bit in the size configuration mask, a page table size indicated by the first request end as being allowed to be used is selected as the at least one page table size.

4. The device according to claim 1, characterized in that The request includes a first virtual address, and the determination module is specifically configured to: Generate a first destination address according to the current page table size and the first virtual address, wherein the first destination address corresponds to a cache unit in the cache module; Accessing the cache unit at the first destination address, and reading the virtual address queue stored in the cache unit; Determine whether the virtual address queue includes the first virtual address, and when the virtual address queue includes the first virtual address, determine that the request hits the current page table size; and when the virtual address queue does not include the first virtual address, determine that the request does not hit the current page table size; The first preset manner includes enabling the cache unit corresponding to the first destination address to find the physical address corresponding to the request from its own storage area and output it.

5. The device according to claim 1, characterized in that The judgment module is further configured to, when the request hits any page table size, output the request and the page table size hit by the request to the sorting module; The sorting module is further configured to, upon receiving the request and the size of the page table hit by the request, increase the size of the page table hit by the number of historical request hits by the first request end by one.

6. The device according to claim 4, characterized in that The judging module is also used for: When the request does not hit the current page table size and there are other page table sizes ranked lower than the current page table size, the next page table size is used as the current page table size, and the steps of determining whether the request hits the current page table size and subsequent steps are re-executed; When the request does not hit the current page table size and the current page table size is already the lowest ranked page table size, the cache module is notified to obtain and output the physical address corresponding to the request in a second preset manner, and the judgment on the hit status of the request is terminated.

7. The device according to claim 6, characterized in that The second preset manner includes enabling the cache unit corresponding to the first destination address to obtain and output the physical address corresponding to the request from an off-chip physical address storage module.

8. A chip, characterized in that: A memory management device comprising any one of claims 1-7.

9. An electronic device, characterized in that: It comprises the chip as claimed in claim 8, and an off-chip physical address storage module.

10. A memory management method, characterized in that: The method is applied to a memory management device, the memory management device includes a cache module, a size selection module, a sorting module, and a judgment module, the cache module includes a plurality of cache units, each cache unit stores a corresponding page table, the page table is used to record historical requests and physical addresses obtained in response to the historical requests, the cache module supports multiple page table sizes, and the method includes: The size selection module selects at least one page table size from the multiple page table sizes according to the request of the first request end, outputs the at least one page table size to the sorting module, and outputs the request to the determination module; The sorting module prioritizes the at least one page table size according to the hit status of the historical requests of the first request end on the at least one page table size, and outputs the sorting result to the judgment module; The judging module starts from the page table size with the highest priority in the sorting result, and judges whether the request hits the current page table size in descending order of priority; When the request hits the current page table size, the judgment module notifies the cache module to find and output the physical address corresponding to the request from the storage area of ​​the included cache unit in a first preset manner, and ends the judgment on the hit of the request.

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