A method for ion implantation in a well region

Abstract

The present invention provides a well region ion implantation method, comprising: providing a substrate, wherein a plurality of active regions are arranged in the substrate, and a shallow trench isolation structure is arranged between the plurality of active regions; forming a pad oxide layer on the surface of the substrate; forming a photoresist layer with a patterned well region on the surface of the pad oxide layer; forming a sidewall blocking layer on the photoresist layer with the patterned well region; etching the sidewall blocking layer to form sidewalls at the edges of the photoresist layer with the patterned well region, and the width of the sidewalls is within the boundary / boundaries of the shallow trench isolation structure; performing ion implantation using the photoresist layer with the patterned well region and the sidewalls as a mask to form a well region in the substrate. The technical solution provided by the present invention solves the problem of well proximity effect induced during ion implantation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a method for ion implantation in a well region. Background Art

[0002] Contemporary semiconductor device manufacturing processes require doping of well ions by means of high-energy ion implantation. Since the doping energy of well ions is relatively high, a relatively thick photoresist is often required as a masking layer. When high-energy ions are implanted to the edge of the photoresist, they will be laterally scattered from the sidewall of the photoresist into the device channel, thereby increasing the doping concentration of the device channel in the well edge region, ultimately leading to an increase in the absolute value of the device threshold voltage and the drift of other electrical parameters, and thus inducing the well proximity effect (full name: Well Proximity Effect, abbreviated as WPE).

[0003] The well proximity effect has attracted the attention of technicians at the 0.25μm technology node. As integrated circuits become smaller and smaller according to Moore's law, the adverse effects brought by the well proximity effect will become more and more significant and gradually cannot be ignored.

[0004] Therefore, how to reduce or eliminate the well proximity effect induced during ion implantation has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0005] The present invention provides a method for ion implantation in a well region to solve the problem of the well proximity effect induced during ion implantation.

[0006] According to a first aspect of the present invention, there is provided a method for ion implantation in a well region, including:

[0007] Providing a substrate, wherein a plurality of active regions are provided in the substrate, and a shallow trench isolation structure is provided between the plurality of active regions;

[0008] Forming a pad oxide layer on the surface of the substrate;

[0009] Forming a photoresist layer with a patterned well region on the surface of the pad oxide layer;

[0010] Forming a sidewall blocking layer on the photoresist layer with a patterned well region;

[0011] Etching the sidewall blocking layer to form sidewalls at the edges of the photoresist layer with a patterned well region, and the width of the sidewalls is within the boundary / boundaries of the shallow trench isolation structure;

[0012] Using the photoresist layer with a patterned well region and the sidewalls as a mask for ion implantation to form a well region in the substrate.

[0013] Optionally, the sidewall blocking layer is one of SiN, SiON, and SiO2, or a combination of two of the three.

[0014] Optionally, the sidewall blocking layer is fabricated by a chemical vapor deposition process at a temperature below 200 °C.

[0015] Optionally, the sidewall blocking layer is etched by isotropic dry plasma etching.

[0016] Optionally, the thickness of the photoresist layer is 1.4 μm to 4 μm; the thickness of the sidewall blocking layer is 0.12 μm to 0.71 μm.

[0017] Optionally, the angle between the sidewall and the surface of the substrate is 80° to 85°.

[0018] Optionally, it further includes removing the photoresist layer patterned in the well region after ion implantation in the well region.

[0019] Optionally, after removing the photoresist layer patterned in the well region, it further includes an annealing step for the ions in the well region.

[0020] Optionally, after forming a pad oxide layer on the surface of the substrate, it further includes:

[0021] Forming a bottom anti-reflection layer on the surface of the pad oxide layer.

[0022] Optionally, the material of the bottom anti-reflection layer is silicon oxide or silicon-containing carbon oxide.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] An ion implantation method for a well region provided by the present invention forms a sidewall blocking layer on a photoresist layer patterned in the well region and etches the sidewall blocking layer to form a sidewall at the edge of the photoresist layer patterned in the well region; the sidewall is disposed at or within the boundary of the shallow trench isolation structure, blocking the scattering of ions into the substrate at the edge of the well region, reducing the non-uniformity of the substrate doping concentration at the edge of the well region, and effectively improving the doping uniformity.

[0025] Further, when the inclination angle of the sidewall is set to 80° to 85°, the implanted ions need to undergo multiple collision scatterings in the same direction to enter the substrate smoothly, reducing the probability that the incident ions bounce off the sidewall of the photoresist layer patterned in the well region and enter the edge of the well region.

[0026] Furthermore, the present invention also forms a bottom anti-reflection layer on the surface of the pad oxide layer located on the surface of the substrate, which plays a role in blocking the laterally scattered ions, further preventing the laterally scattered ions from entering the edge substrate, and ensuring the doping uniformity of the well region. Brief Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0028] Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present invention;

[0029] Figure 2 is a schematic flow chart of a well region ion implantation method provided by an embodiment of the present invention;

[0030] Figures 3 - 9 is a schematic diagram of device structures at different process stages fabricated according to a well region ion implantation method provided by an embodiment of the present invention;

[0031] Figures 10 - 16 is a schematic diagram of device structures at different process stages fabricated according to a well region ion implantation method provided by another embodiment of the present invention;

[0032] Description of the Reference Numerals:

[0033] 100, 200, 300 - Substrate;

[0034] 101, 201, 301 - Shallow Trench Isolation Structure;

[0035] 102, 202, 302 - Pad Oxide Layer;

[0036] 104, 204, 304 - Photoresist Layer for Well Region Patterning;

[0037] 2041, 3041 - Photoresist Layer;

[0038] 205, 305 - Curing Layer;

[0039] 206, 306 - Sidewall Barrier Layer;

[0040] 2061, 3061 - Sidewall;

[0041] 303 - Bottom Anti-Reflection Layer. Detailed Description of the Embodiments

[0042] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0043] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices. The terms "above" and "upper" and any variations thereof are intended to describe the positional relationship and do not represent a direct contact relationship between the described objects.

[0044] As described in the background art, the well proximity effect will be induced when doping well ions by means of high-energy ion implantation. The following will be described in conjunction with Figure 1 for illustration. Figure 1 is a schematic diagram of a semiconductor structure, including a substrate 100, the surface of the substrate 100 has a pad oxide layer 102, the substrate 100 includes a plurality of active regions, and a shallow trench isolation structure 101 is provided in the substrate 100 between the active regions; a patterned photoresist layer 104 located on the surface of the pad oxide layer 102, and the patterned photoresist layer 104 exposes any one of the active regions.

[0045] In Figure 1 , when performing well region ion implantation on the exposed active region, the implanted ions and the fixed ions in the photoresist are likely to collide and scatter, resulting in the implanted ions being laterally scattered from the sidewall of the photoresist into the channel of the semiconductor structure, thereby increasing the channel doping concentration of the device in the well edge region, and thus inducing the well proximity effect (Well Proximity Effect, WPE), which affects the electrical parameters of the device formed at the well region edge. Figure 1The arrow in the figure represents the implantation direction of well region ions. When doping well ions by means of high-energy ion implantation, the doping energy of well ions is relatively high, and a relatively thick patterned photoresist layer 104 of the well region is often required as a masking layer. Due to the higher photoresist thickness, the region where the implanted ions are scattered is farther from the sidewall of the patterned photoresist layer 104, resulting in a larger lateral scattering range. Therefore, especially for small-sized semiconductor devices, the corresponding well proximity effect will be more significant during well region ion implantation.

[0046] In response to the above problems, those skilled in the art have provided some solutions. For example, when designing the layout, simulating the performance parameters of the devices at the well edge and appropriately increasing the distance between the well edge and the device channel, but this method cannot save the layout area and is not conducive to improving the device integration.

[0047] To solve the above problems, the present invention provides a method for well region ion implantation, as Figure 2 shown, Figure 2 is a schematic flow chart of the well region ion implantation method of the present invention, including:

[0048] Step S11: Provide a substrate, in which a plurality of active regions are provided, and shallow trench isolation structures are provided between the plurality of active regions;

[0049] Step S12: Form a pad oxide layer on the surface of the substrate;

[0050] Step S13: Form a patterned photoresist layer of the well region on the surface of the pad oxide layer;

[0051] Step S14: Form a sidewall blocking layer on the patterned photoresist layer of the well region;

[0052] Step S15: Etch the sidewall blocking layer to form sidewalls at the edges of the patterned photoresist layer of the well region, and the width of the sidewalls is within the boundary / boundaries of the shallow trench isolation structure;

[0053] Step S16: Use the patterned photoresist layer of the well region and the sidewalls as masks for ion implantation to form a well region in the substrate.

[0054] The technical solution provided by the present invention forms a sidewall barrier layer on the photoresist layer with the well region patterned, and etches the sidewall barrier layer to form sidewalls at the edges of the photoresist layer with the well region patterned; the sidewalls are disposed at or within the boundary of the shallow trench isolation structure, and sidewalls are provided on the sidewalls of the photoresist layer with the well region patterned to block well region ions from entering the well region edge; further, an appropriate sidewall tilt angle will cause the implanted ions to collide and scatter multiple times in the same direction before smoothly entering the substrate. Therefore, the technical solution provided by the present invention blocks the scattering of ions into the substrate at the well region edge by setting sidewalls, reduces the non-uniformity of the substrate doping concentration at the well region edge, and improves the well region proximity effect.

[0055] The technical solution of the present invention will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0056] Figures 3 to 9 It is a schematic cross-sectional structure diagram of the process of a well region ion implantation method according to an embodiment of the present invention.

[0057] Please refer to Figure 2 and Figure 3 , and perform step S11 to provide a substrate 200, wherein a plurality of active regions are provided in the substrate 200, and a shallow trench isolation structure 201 is provided between the plurality of active regions.

[0058] The active region described herein in the present invention refers to: in the substrate 200, the region for doping well region ions to form a well region.

[0059] Please continue to refer to Figure 2 and Figure 3 , and perform step S12 to form a pad oxide layer 202 on the surface of the substrate 200 to protect the substrate 200;

[0060] In a specific example, the pad oxide layer 202 is: silicon dioxide.

[0061] In one embodiment, when forming the pad oxide layer 202, the process used is: furnace tube thermal oxidation process.

[0062] Please refer to Figure 2 , and perform step S13 to form a well region patterned photoresist layer 204 on the surface of the pad oxide layer 202.

[0063] In one embodiment, the formation process of forming the well region patterned photoresist layer 204 on the surface of the pad oxide layer 202 is as shown in Figures 4 to 5 shown.

[0064] Please refer to Figure 4, a photoresist layer 2041 is coated on the surface of the pad oxide layer 202.

[0065] In one embodiment, the photoresist layer 2041 can be a negative photoresist or a positive photoresist, and the choice of the photoresist material is not limited.

[0066] In one embodiment, the process used for coating the photoresist layer 2041 includes but is not limited to: ultrasonic spraying, spin coating method and other coating methods.

[0067] Please refer to Figure 5 , perform photolithography and development on the photoresist layer 2041 to form a patterned photoresist layer 204 for the well region.

[0068] Specifically, use a photomask to expose and develop the photoresist layer 2041. Among them, if the photoresist selected is a positive photoresist, the exposed photoresist is removed after exposure and development; if the photoresist layer selected is a negative photoresist, the unexposed photoresist is removed after exposure and development to form a patterned photoresist layer 204 for the well region. The specific type of photoresist selected is not limited here and is subject to the specific process.

[0069] In one embodiment, when performing photolithography and development, the selected mask is: the mask used for well ion implantation.

[0070] Since a sidewall blocking layer needs to be deposited on the surface of the patterned photoresist layer for the well region later, and the patterned photoresist layer for the well region is prone to collapse or deformation, and the deposition of the sidewall blocking layer on the surface of the patterned photoresist layer for the well region will also affect the internal stress of the patterned photoresist layer for the well region.

[0071] Please refer to Figure 6 , after forming the patterned photoresist layer 204 for the well region, it further includes: performing a curing treatment on the patterned photoresist layer 204 for the well region to form a cured layer 205 in the patterned photoresist layer 204 on the surface part of the well region.

[0072] The curing treatment can include ultraviolet light irradiation or heating baking treatment in some specific embodiments.

[0073] In this preferred embodiment, since the cured layer formed on the surface of the patterned photoresist layer for the well region after the curing treatment has a relatively high hardness, the phenomenon of deformation or collapse of the patterned photoresist layer for the well region in subsequent processes can be avoided.

[0074] Please refer to Figure 2 and Figure 7 , perform step S14 to form a sidewall blocking layer 206 on the patterned photoresist layer 204 for the well region.

[0075] In one embodiment, the sidewall blocking layer 206 is formed by a chemical vapor deposition process at a temperature below 200 degrees Celsius. Among them, the commonly used photoresist at present is prone to deformation or collapse at a relatively high temperature. The deformation or collapse may be caused by the decomposition of the photoresist or the deformation of the material, or other reasons, which are not specifically limited here. In short, in order to ensure that the photoresist does not deform, a low-temperature chemical vapor deposition method is used to fabricate the sidewall blocking layer. The deformation of the photoresist will directly cause a change in the ion implantation range during subsequent well ion implantation, which easily leads to the failure of the fabricated device and reduces the yield of the fabricated chip. Therefore, according to the commonly used material of the photoresist for well ion implantation, the temperature of the chemical vapor deposition of the sidewall blocking layer is controlled below 200 degrees Celsius.

[0076] In one embodiment, the sidewall blocking layer 206 is one of SiN / SiON / SiO2 or a combination of two of the three. That is, the material of the sidewall blocking layer is any one of SiN, SiON or SiO2, or a combination of any two of the three. These three materials can be fabricated by a chemical vapor deposition method at a relatively low temperature.

[0077] Please refer to Figure 2 and Figure 8 , perform step S15 to etch the sidewall blocking layer 206 to form a sidewall 2061 at the edge of the patterned photoresist layer 204 in the well region, and the width of the sidewall 2061 is within the boundary / boundaries of the shallow trench isolation structure 201.

[0078] Among them, the width of the sidewall 2061 being within the boundary / boundaries of the shallow trench isolation structure 201 means that the side of the sidewall 2061 close to the well region is on or outside the boundary of the well region. The width of the sidewall needs not to affect the ion dose implantation in the well region. Therefore, the width of the sidewall after etching needs to be controlled on or outside the boundary of the well region, so that the final sidewall can block the scattered ions and scatter the ions in the direction outside the well region, greatly reducing the well proximity effect.

[0079] In one embodiment, the process used for etching the sidewall blocking layer 206 is: isotropic dry plasma etching.

[0080] Since isotropic dry plasma etching can naturally form a sidewall inclination angle θ on the sidewalls of the etched object after etching, isotropic dry plasma etching can be used to etch the sidewall barrier layer 206 within the aforementioned thickness range, thereby preparing the sidewall 2061 within the subsequent preferred inclination angle range. Here, the sidewall inclination angle θ refers to the angle between the inner side of the sidewall and the substrate. The width of the sidewall 2061 is consistent with the thickness of the deposited sidewall barrier layer 206 and is related to the thickness of the photoresist and the set sidewall inclination angle. The width of the sidewall, that is, the thickness of the sidewall barrier layer = photoresist thickness / tanθ. The meaning of the width of the sidewall here is that the width of the sidewall described below is within the boundary / boundary of the shallow trench isolation structure, so as to ensure that the formed sidewall can effectively reduce the well region proximity effect while ensuring the uniformity of ion implantation. The sidewall width is related to the photoresist thickness and the inclination angle formed by etching, and is related to the semiconductor device manufacturing technology node. The etching process can be adaptively adjusted according to the material and etching rate of the sidewall barrier layer. The present invention does not limit this, and those skilled in the art can select appropriate processes according to needs.

[0081] Please refer to Figure 2 and Figure 9 , perform step S16, and use the photoresist layer 204 patterned with the well region and the sidewall 2061 as a mask for ion implantation to form a well region in the substrate 200. Figure 9 The arrow in

[0082] In one embodiment, the type of ions implanted in the substrate 200 is: N-type ions or P-type ions.

[0083] In one implementation, the N-type ions can be: phosphorus (P) or arsenic (As).

[0084] In another implementation, the P-type ions can be: boron (B) or indium (In).

[0085] When forming the photoresist layer patterned with the well region, a mask plate for well region ion implantation is used to form a window for well region ion implantation; the same mask plate is used during ion implantation, achieving precise alignment between the photoresist patterned with the well region and the well region.

[0086] In a preferred embodiment, while using the photoresist layer 204 patterned with the well region and the sidewall 2061 as a mask for ion implantation, the substrate 200 is rotated so that the doped ions can be incorporated into the active region from multiple angles, further improving the uniformity of well region doping.

[0087] In a specific example, taking the ion implantation of the N-type well region as an example, when performing well region ion doping, the well region ion doping is carried out at an inclination angle of 2°.

[0088] In one embodiment, after the ion implantation, it further includes: removing the patterned photoresist layer 204, the curing layer 205, and the sidewall 2061 of the well region after the well region ion implantation.

[0089] In one embodiment, after removing the patterned photoresist layer 204, the curing layer 205, and the sidewall 2061 of the well region, it further includes: an annealing step for the well region ions.

[0090] Since in the ion implantation process, substitutional defects will be introduced into the crystal structure, annealing after the well region ion doping can improve the activation rate of doping, reduce defects, improve physical or chemical properties, achieve electrical activation, and reduce defects near the interface, thereby improving the performance and reliability of semiconductor devices.

[0091] As an example, applying this embodiment in a 55nm semiconductor process, a plurality of active regions are formed on the substrate 200, and a shallow trench isolation structure is provided between the plurality of active regions. A pad oxide layer is formed on the surface of the substrate. A patterned photoresist layer 204 of the well region is formed on the surface of the pad oxide layer, and the thickness of this photoresist layer is 1.4μm - 4.0μm. Then, the surface of the patterned photoresist layer is cured by ultraviolet light to form a curing layer 205 with a thickness of 0.07μm - 0.2μm. A sidewall blocking layer 206 with a thickness of 0.12μm - 0.71μm is formed on the photoresist layer by a chemical vapor deposition process at 200 degrees Celsius. The width of the sidewall 2061 left after etching the sidewall blocking layer 206 is: 0.12μm - 0.71μm, which does not exceed the shallow trench isolation structure 201 where it is located, ensuring the uniformity of the well region ion implantation. The included angle between the side of the etched sidewall 2061 and the surface of the substrate 200 is 80° - 85°.

[0092] When the inclination angle is too large, the probability of the primary collision scattering ejecting the incident ions out of the photoresist sidewall and into the well region edge increases. When the inclination angle is too small, the ions cannot be effectively blocked from entering the substrate 200 either. When the inclination angle of the sidewall 2061 is set to 80° - 85°, the injected ions can be more effectively made to undergo multiple collision scatterings in the same direction before smoothly entering the substrate 200, reducing the probability of the incident ions being ejected out of the photoresist sidewall and into the well region edge, which is beneficial to the improvement of the well proximity effect.

[0093] Finally, using the photoresist layer patterned with the well region and the sidewall as a mask for ion implantation to form a well region in the substrate. The formed sidewall will block the scattered ions that will be implanted into the well edge region after collision scattering, change their scattering angle and scattering path, and reduce their scattering energy, effectively preventing the implanted ions from laterally scattering into the well edge substrate through the edge of the photoresist, thereby achieving the purpose of improving the well proximity effect.

[0094] In summary, the technical solution provided in this embodiment forms a sidewall blocking layer on the photoresist layer patterned with the well region and etches the sidewall blocking layer to form a sidewall at the edge of the photoresist layer patterned with the well region; the sidewall is disposed at or within the boundary of the shallow trench isolation structure, blocking the scattering of ions into the substrate at the well edge, reducing the non-uniformity of the substrate doping concentration at the well edge, and improving the well proximity effect.

[0095] Figures 10 - 16 is a schematic structural diagram of a well region ion implantation method according to another embodiment of the present invention. The difference between this embodiment and Figures 3 - 9 the above-mentioned embodiment is that in this embodiment, a bottom anti-reflection layer 303 is further formed on the surface of the pad oxide layer 302.

[0096] On the basis of Figure 3 please refer to Figure 2 and Figure 10 , perform step S11: Provide a substrate, S12: After forming a pad oxide layer 302 on the surface of the substrate 300, it further includes: forming a bottom anti-reflection layer 303 on the surface of the pad oxide layer 302. The structure before forming the bottom anti-reflection layer 303 includes: a substrate 300, several active regions are provided in the substrate 300, and a shallow trench isolation structure 301 is provided between the several active regions; a pad oxide layer 302 is formed on the surface of the substrate 300.

[0097] The selected material of the bottom anti-reflection layer 303 should be insoluble in the developer used for developing the photoresist layer 3041 on the surface of the bottom anti-reflection layer 303.

[0098] In one embodiment, the material of the bottom anti-reflection layer 303 is silicon oxide or silicon-containing carbon oxide.

[0099] The bottom anti-reflection layer 303 is used to: block the doping of the substrate 300 outside the boundary of the photoresist layer 304 patterned with the well region by the laterally scattered ions. Better ion doping uniformity is achieved.

[0100] In a specific embodiment, taking the 55-nanometer technology node as an example, the thickness of the bottom anti-reflection layer 303 is: 0.35 μm to 1.0 μm.

[0101] In the 55-nanometer technology node, according to the implantation energy and dose of well ion implantation, and with the existing thickness of the pad oxide layer, controlling the thickness of the bottom anti-reflection layer 303 within the range of 0.35 μm to 1.0 μm can ensure that the well region ion implantation falls within the distribution range of the ion concentration that ultimately needs to be formed.

[0102] Please refer to Figure 2 , perform step S13 to form a patterned photoresist layer 304 for the well region on the surface of the pad oxide layer 302.

[0103] In one embodiment, the formation process of forming the patterned photoresist layer 304 for the well region on the surface of the pad oxide layer 302 is as Figures 11 - 12 shown.

[0104] Please refer to Figure 11 , coat a photoresist layer 3041 on the surface of the pad oxide layer 302.

[0105] Please refer to Figure 12 , perform photolithography and development on the photoresist layer 3041 to form the patterned photoresist layer 304 for the well region.

[0106] Please refer to Figure 13 , in a preferred embodiment, when forming the patterned photoresist layer 304 for the well region, it further includes: performing a curing treatment on the formed patterned photoresist layer 304 for the well region to form a cured layer 305 on the surface portion of the formed patterned photoresist layer 304 for the well region.

[0107] Please refer to Figure 2 and Figure 14 , perform step S14 to form a sidewall barrier layer 306 on the patterned photoresist layer 304 for the well region.

[0108] Please refer to Figure 2 and Figure 15 , perform step S15 to etch the sidewall barrier layer 306 to form a sidewall 3061 at the edge of the patterned photoresist layer 304 for the well region, and the width of the sidewall 3061 is within the boundary / boundaries of the shallow trench isolation structure 301.

[0109] Please refer to Figure 2 and Figure 16 , perform step S16 to perform ion implantation using the patterned photoresist layer 304 for the well region and the sidewall 3061 as a mask to form a well region in the substrate 300. Figure 16 The arrow direction in

[0110] In one embodiment, after ion implantation, it further includes: removing the patterned photoresist layer 304, curing layer 305, sidewall 3061, and bottom anti-reflection layer 303 of the well region after ion implantation in the well region.

[0111] In one embodiment, after removing the patterned photoresist layer 304, curing layer 305, sidewall 3061, and bottom anti-reflection layer 303 of the well region, it further includes: an annealing step for the well region ions.

[0112] In this embodiment, the materials and preparation processes of the liner oxide layer 302, the patterned photoresist layer 304 of the well region, and the sidewall blocking layer 306, the type of well region ion implantation, the tilt angle and extension width of the sidewall 3061, the curing method of the patterned photoresist layer 304 of the well region, etc., are all the same as those of Figures 3 - 9 the said embodiment and will not be elaborated here.

[0113] In summary, the well region ion implantation method provided in this embodiment improves the uniformity of well region ion implantation by setting a sidewall at the edge of the patterned photoresist layer in the well region to block the lateral scattering of ions into the substrate in the well region.

[0114] In summary, for a well region ion implantation method of the present invention, by setting a sidewall at the edge of the patterned photoresist layer in the well region, the uniformity of doping at the well region edge is improved, and the problem of well proximity effect induced during well region ion implantation is solved.

[0115] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A well region ion implantation method, characterized in that Comprising: Providing a substrate, in which a plurality of active regions are provided, and a shallow trench isolation structure is provided between the plurality of active regions; Forming a pad oxide layer on the surface of the substrate; Forming a photoresist layer with a patterned well region on the surface of the pad oxide layer; Performing a curing treatment on the photoresist layer to form a cured layer in the photoresist layer of the surface portion with the patterned well region; Forming a sidewall blocking layer by chemical vapor deposition at a temperature lower than 200 °C on the photoresist layer with the patterned well region; Etching the sidewall blocking layer to form a sidewall at the edge of the photoresist layer with the patterned well region, and the width of the sidewall is within the boundary / boundaries of the shallow trench isolation structure; Performing ion implantation using the photoresist layer with the patterned well region and the sidewall as a mask to form a well region in the substrate; Wherein, the included angle between the side of the sidewall and the surface of the substrate is 80° - 85°, the thickness of the photoresist layer is 1.4 μm - 4 μm; the thickness of the sidewall blocking layer is 0.12 μm - 0.71 μm.

2. The well region ion implantation method according to claim 1, wherein The sidewall blocking layer is one of SiN / SiON / SiO2 or a combination of two of the three.

3. The well region ion implantation method according to claim 1, wherein Etching the sidewall blocking layer is isotropic dry plasma etching.

4. The ion implantation method for the well region according to claim 1, wherein Further comprising removing the photoresist layer with the patterned well region after ion implantation of the well region.

5. The well region ion implantation method according to claim 4, wherein After removing the photoresist layer with the patterned well region, it further includes an annealing step for ions in the well region.

6. The well region ion implantation method according to any one of claims 1 to 5, characterized in that, After forming the pad oxide layer on the surface of the substrate, it further includes: Forming a bottom anti-reflection layer on the surface of the pad oxide layer.

7. The well region ion implantation method according to claim 6, wherein The material of the bottom anti-reflection layer is silicon oxide or silicon-containing carbon oxide.

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