A reference model integration method, device, electronic device and storage medium

Abstract

The embodiment of the present invention provides a reference model integration method, device, electronic device and storage medium, the method comprising: obtaining a reference model of a verification object and data transmission parameters of the reference model; loading the reference model into the software simulator; configuring communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters; the communication control instructions include loading instructions and storing instructions; executing the loading instructions to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model; after the reference model generates a calculation result, executing the storing instruction to store the calculation result into the virtual memory of the software simulator. The embodiment of the present invention realizes the automatic integration of the reference model in the software simulator, which is conducive to improving the verification efficiency of the verification object.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a reference model integration method, device, electronic equipment and storage medium. Background Art

[0002] Differential verification is a commonly used verification method. It verifies whether the function of the Design Under Verification (DUV) is correct by comparing the behavior of the verification object and the reference model. Therefore, it is necessary to provide a software reference model as the gold standard of the DUV. In order to perform differential verification on the custom extended instruction system, the reference model of the extended instruction needs to be integrated into the reference model ISA simulator of the CPU. In the traditional verification process, the reference model is often handwritten by software modeling engineers, and the model needs to be manually inserted for integration, which seriously affects the efficiency of verification. Summary of the invention

[0003] The embodiments of the present invention provide a reference model integration method, device, electronic device and storage medium, which can solve the problem that manual integration of reference models affects verification efficiency in related technologies.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a reference model integration method, which is applied to a software simulator. The method includes:

[0005] Acquire a reference model of a verification object and data transmission parameters of the reference model;

[0006] loading the reference model into the software simulator;

[0007] According to the instruction set architecture of the verification object and the data transmission parameters, configuring communication control instructions; the communication control instructions include load instructions and store instructions;

[0008] Executing the loading instruction to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model, so that the reference model reads the test stimulus data from the buffer;

[0009] After the reference model generates a calculation result, the storage instruction is executed to store the calculation result in the virtual memory of the software simulator.

[0010] Optionally, the data transmission parameters include a buffer address corresponding to the reference model, an array address, an array size, and a data type corresponding to the virtual memory;

[0011] The configuring of the communication control instruction according to the instruction set architecture of the verification object and the data transmission parameter includes:

[0012] encoding the array address into a first source register corresponding to a communication control instruction; the communication control instruction is an instruction defined according to an instruction set architecture of the verification object;

[0013] encoding the buffer address into a second source register corresponding to the communication control instruction;

[0014] Encode a first operation code corresponding to the communication control instruction according to the array size;

[0015] A second operation code corresponding to the communication control instruction is encoded according to the data type.

[0016] Optionally, executing the load instruction to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model includes:

[0017] Reading and parsing a first buffer parameter and a first virtual memory parameter in the load instruction;

[0018] In response to the load instruction, calling a first read function according to the first virtual memory parameter; the first read function is used to read test stimulus data from the virtual memory according to the first virtual memory parameter;

[0019] Obtaining the test stimulus data returned by the first read function;

[0020] A first write function is called according to the first buffer parameter; the first write function is used to write the test stimulus data into the buffer according to the first buffer parameter.

[0021] Optionally, after the reference model generates a calculation result, executing the storage instruction to store the calculation result in a virtual memory of the software simulator includes:

[0022] After the reference model generates a calculation result, reading and parsing a second buffer parameter and a second virtual memory parameter in the storage instruction;

[0023] In response to the storage instruction, calling a second read function according to the second buffer parameter; the second read function is used to read the operation result from the buffer according to the second buffer parameter;

[0024] Obtaining the operation result returned by the second read function;

[0025] A second write function is called according to the second virtual memory parameter; the second write function is used to write the operation result into the virtual memory according to the second virtual memory parameter.

[0026] Optionally, the communication control instruction further includes a control instruction; and the method further includes:

[0027] When the control instruction is read, analyzing the target function to be achieved by the control instruction;

[0028] The target function function of the reference model is called according to the target function so that the reference model performs the target function.

[0029] Optionally, the method further comprises:

[0030] The operation result is read from the virtual memory, and the operation result is written into a software buffer of a verification system, so that the verification system can verify the verification object according to the operation result recorded in the software buffer.

[0031] On the other hand, an embodiment of the present invention discloses an integrated device of a reference model, which is applied to a software simulator, and the device includes:

[0032] An acquisition module, used to acquire a reference model of a verification object and data transmission parameters of the reference model;

[0033] A loading module, used for loading the reference model into the software simulator;

[0034] A configuration module, configured to configure communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters; the communication control instructions include load instructions and store instructions;

[0035] A first execution module, configured to execute the loading instruction to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model, so that the reference model reads the test stimulus data from the buffer;

[0036] The second execution module is used to execute the storage instruction after the reference model generates the operation result, so as to store the operation result in the virtual memory of the software simulator.

[0037] Optionally, the data transmission parameters include a buffer address corresponding to the reference model, an array address, an array size, and a data type corresponding to the virtual memory;

[0038] The configuration module includes:

[0039] A first encoding submodule, configured to encode the array address into a first source register corresponding to a communication control instruction; the communication control instruction is an instruction defined according to an instruction set architecture of the verification object;

[0040] A second encoding submodule, used for encoding the buffer address into a second source register corresponding to the communication control instruction;

[0041] A third encoding submodule, used for encoding a first operation code corresponding to the communication control instruction according to the array size;

[0042] The fourth encoding submodule is used to encode the second operation code corresponding to the communication control instruction according to the data type.

[0043] Optionally, the first execution module includes:

[0044] A first reading submodule, used for reading and parsing a first buffer parameter and a first virtual memory parameter in the load instruction;

[0045] A first calling submodule, configured to call a first read function according to the first virtual memory parameter in response to the load instruction; the first read function is configured to read test stimulus data from the virtual memory according to the first virtual memory parameter;

[0046] A stimulus acquisition submodule, used to acquire the test stimulus data returned by the first read function;

[0047] The second calling submodule is used to call a first writing function according to the first buffer parameter; the first writing function is used to write the test stimulus data into the buffer according to the first buffer parameter.

[0048] Optionally, the second execution module includes:

[0049] A second reading submodule, configured to read and parse a second buffer parameter and a second virtual memory parameter in the storage instruction after the reference model generates a calculation result;

[0050] a third calling submodule, configured to call a second read function according to the second buffer parameter in response to the storage instruction; the second read function is configured to read the operation result from the buffer according to the second buffer parameter;

[0051] A result acquisition submodule, used for acquiring the operation result returned by the second read function;

[0052] The fourth calling submodule is used to call the second writing function according to the second virtual memory parameter; the second writing function is used to write the operation result into the virtual memory according to the second virtual memory parameter.

[0053] Optionally, the communication control instruction further includes a control instruction; and the device further includes:

[0054] An instruction parsing module, used for parsing the target function to be achieved by the control instruction when the control instruction is read;

[0055] A function calling module is used to call the target function function of the reference model according to the target function so that the reference model executes the target function.

[0056] Optionally, the device further comprises:

[0057] The result transmission module is used to read the operation result from the virtual memory and write the operation result into the software buffer of the verification system, so that the verification system can verify the verification object according to the operation result recorded in the software buffer.

[0058] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned reference model integration method.

[0059] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned reference model integration method.

[0060] The embodiments of the present invention include the following advantages:

[0061] The reference model integration method provided in the embodiment of the present invention configures the communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters of the reference model after loading the reference model onto the software simulator, which may specifically include loading instructions and storage instructions. The software simulator can load the test stimulus data from the virtual memory into the buffer of the reference model for the reference model to read by the software simulator by executing the configured loading instructions; and can store the calculation results generated by the reference model in the virtual memory by executing the configured storage instructions, so that the verification system or the verification platform can read the calculation results to verify the verification object, thereby realizing the data transmission between the reference model and the software simulator. Compared with manually inserting the reference model into the software simulator for integration, the embodiment of the present invention does not need to perform complex configuration operations on the reference model or the software simulator, realizes the automatic integration of the reference model in the software simulator, shortens the development cycle of the software reference model and the time cost of building the verification platform, and is conducive to improving the verification efficiency of the verification object. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0063] Figure 1 is a flowchart of steps of an embodiment of a reference model integration method of the present invention;

[0064] Figure 2 It is a schematic diagram of the architecture of a software simulator of the present invention;

[0065] Figure 3 is a structural block diagram of an integrated device embodiment of a reference model of the present invention;

[0066] Figure 4 It is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0069] Method Embodiment

[0070] Reference Figure 1 , shows a flowchart of a reference model integration method embodiment of the present invention, the method may specifically include the following steps:

[0071] Step 101: Obtain a reference model of a verification object and data transmission parameters of the reference model;

[0072] Step 102: Load the reference model into a software simulator;

[0073] Step 103: configuring communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters; the communication control instructions include load instructions and store instructions;

[0074] Step 104: execute the loading instruction to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model, so that the reference model reads the test stimulus data from the buffer when executing the test program;

[0075] Step 105: After the reference model generates a calculation result, execute the storage instruction to store the calculation result in the virtual memory of the software simulator.

[0076] The reference model integration method provided in the embodiment of the present invention can be applied to a software simulator. A software simulator (Emulator, EMU) is a software program written in a high-level language to simulate the operating state of a CPU. Exemplarily, the software simulator in the embodiment of the present invention can be a NEMU, an ISA simulator, etc.

[0077] The verification object or the design to be tested refers to the circuit design or implementation to be tested in the prototype verification. Exemplarily, the verification object in the embodiment of the present invention can be a register transfer level (RTL) circuit or other hardware design. It should be noted that the RTL circuit is a common hardware description level circuit. The RTL circuit describes the behavior and structure of the digital circuit and is represented by the abstract level of the register transfer level. The RTL circuit description is usually written in a hardware description language (HDL), such as VHDL (VHSIC Hardware Description Language), Verilog HDL, and System Verilog HDL. Designers can use the RTL level description to define and implement the required digital circuit functions, and then use the synthesis tool to convert the RTL level description into a physical implementation in the field programmable gate array (FPGA). In the field of FPGA, chip design and verification, the RTL level description is very important for design, verification and debugging. It provides an abstract level that enables designers to describe circuit behavior at a higher level of abstraction, and use appropriate tools for simulation, verification and synthesis, and finally generate a bitstream file that can be configured into the FPGA chip to implement specific digital circuit functions.

[0078] The reference model is used to implement the same function as the verification object or the design to be tested. During the verification process of the verification object or the design to be tested, the data generated when the reference model is called can be considered correct and used as reference data for comparison with the data generated by the verification object or the design to be tested. It is understandable that different reference models are generated for different verification objects or designs to be tested. As an example, before high-level synthesis processing is performed on the verification object or the design to be tested, a source design model of the verification object or the design to be tested can be generated based on the design code of the verification object or the design to be tested in C / C++ language. The source design model has the same algorithm function as the verification object or the design to be tested and can be used as a reference model of the verification object or the design to be tested.

[0079] In an embodiment of the present invention, the reference model may be first loaded into the software simulator, and then communication control instructions may be configured according to data transmission parameters of the reference model to achieve communication between the reference model and the software simulator, thereby automatically integrating the reference model into the software simulator.

[0080] It should be noted that the data transmission parameters of the reference model in the embodiment of the present invention are used to indicate the information required for data transmission between the reference model and the software simulator, and may specifically include the buffer address (bufferaddress) of the reference model, the array address (array address) in the virtual memory of the software simulator, the array size (arraysize), the data type (data type), the checksum (checksum), and the like. Among them, the buffer address of the reference model refers to the base address of the buffer array required by the reference model in the software simulator. The array address in the virtual memory refers to the base address of the data stored in the virtual memory of the software simulator, the array size refers to the size of the array data to be transmitted between the buffer of the reference model and the virtual memory of the software simulator, and the data type refers to the type of transmitted data. The checksum refers to the value used to return the execution status of the control instruction (execute instruction), which is generally 0. As an example, the data transmission parameters of the reference model can be determined by parsing the C / C++ design port of the reference model.

[0081] The embodiment of the present invention defines a set of communication control instructions, which realizes data transmission between the reference model and the software simulator through virtual address read and write calls, thereby integrating the reference model into the software simulator. Specifically, in the embodiment of the present invention, the communication control instructions can be configured according to the instruction set architecture and data transmission parameters of the verification object. Among them, the FPGA chip is used to integrate the verification object or the design to be tested. The instruction set architecture of the verification object refers to the instruction set architecture of the processor design to be tested, for example, it can be a RISC-V instruction set or an ARM instruction set.

[0082] The communication control instructions in the present invention may include a load instruction (load instruction) and a store instruction (store instruction). The load instruction is used to load data in the virtual memory of the software simulator into the buffer of the reference model; the store instruction is used to store data in the buffer of the reference model into the virtual memory of the software simulator.

[0083] Exemplarily, load instructions and store instructions can be encoded according to the definition of the R-type RISC-V instruction set, and the encoded instructions can be encapsulated into C language macros. During the verification of the verification object or the design to be tested, the macro is used to pass the data transmission parameters of the reference model to the reference model.

[0084] Furthermore, in an embodiment of the present invention, the data transmission parameters required by the reference model, such as array variable name, array size, array data type, etc., can be determined by parsing the C / C++ design port of the reference model, and a corresponding buffer can be generated for the reference model based on these data transmission parameters.

[0085] Reference Figure 2 , shows a schematic diagram of the architecture of a software simulator provided by an embodiment of the present invention. Figure 2 As shown, a reference model is loaded in the software simulator, and a corresponding buffer is allocated to the reference model. The software simulator and the reference model communicate through data transmission between the virtual memory and the buffer. Specifically, when verifying the verification object or the design to be tested, the software simulator can generate test stimulus data locally, or obtain test stimulus data from other devices, such as the verification system or the verification platform sending the test stimulus data to the software simulator. The software simulator can store the generated or received test stimulus data in the virtual memory, and after starting the verification, pass the test stimulus data to the reference model. Specifically, the software simulator can load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model by executing a custom load instruction, so that the reference model can read the test stimulus data from the buffer and generate a calculation result.

[0086] After the reference model generates the operation result, the software simulator can execute the custom storage instruction to store the operation result in the virtual memory of the software simulator. For example, the reference model can write the generated operation result into a buffer, and after a set of operations is completed, the operation result is transferred from the buffer to the virtual memory of the software simulator.

[0087] It is understandable that the software simulator can pass the data in the virtual memory to other devices through the address mapping between the virtual address and the physical address. For example, the verification system or verification platform can access the data in the virtual memory of the software simulator based on the page table of the electronic device equipped with the software simulator.

[0088] Optionally, the method further comprises:

[0089] The operation result is read from the virtual memory, and the operation result is written into a software buffer of a verification system, so that the verification system can verify the verification object according to the operation result recorded in the software buffer.

[0090] In a possible application scenario, the software simulator can write the operation results in the virtual memory into the software buffer of the verification system. The verification system is provided with a hardware buffer and a software buffer, wherein the hardware buffer is used to record the operation data of the verification object or the design to be tested, and the software buffer is used to record the operation data of the software simulator. Furthermore, both the hardware buffer and the software buffer are storage structures that adopt a "first in, first out" storage strategy, and the storage space size of the hardware buffer and the software buffer is the same. Usually, the operation speed of the hardware is relatively fast, so when the hardware buffer is full, the operation of the verification object or the design to be tested can be paused to wait for the data in the software buffer to be written.

[0091] The verification system can compare the data in the hardware buffer with the data in the software buffer, that is, compare the operation results of the verification object or verification design with the operation results of the reference model. When the two sets of operation results do not match, it can be determined that the verification object or the design to be tested has an operation error.

[0092] The reference model integration method provided in the embodiment of the present invention can configure communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters of the reference model, and realize the data transmission between the reference model and the software simulator through these communication control instructions. Compared with manually inserting the reference model into the software simulator for integration, the embodiment of the present invention does not need to perform complex configuration operations on the reference model or the software simulator, realizes the automatic integration of the reference model in the software simulator, shortens the development cycle of the software reference model and the time cost of building the verification platform, and is conducive to improving the verification efficiency of the verification object.

[0093] Optionally, the communication control instruction further includes a control instruction; and the method further includes:

[0094] Step S11, when the control instruction is read, parsing the target function indicated by the control instruction;

[0095] Step S12: calling the target function function of the reference model according to the target function, so that the reference model performs the target function.

[0096] The communication control instructions configured in the embodiment of the present invention may also include control instructions (execute instructions) for starting the control function of the reference model and calling the reference model to implement the function.

[0097] When the software simulator reads the control instruction, it parses the control instruction to determine the target function indicated by the control instruction, and then calls the target function function corresponding to the reference model so that the reference model executes the target function.

[0098] For example, take the test case sort / merge in the test program that contains the merge sort algorithm. sort / merge is used to convert 2 11 The software simulator controls the reference model to implement this test case through the following three instructions:

[0099] ROCC_INTERFACE_LOAD_EXTEND(a_base,a,11,WD);

[0100] ROCC_INTERFACE_EXEC(checksum_inst);

[0101] ROCC_INTERFACE_STORE_EXTEND(a_base,a,11,WD)

[0102] Among them, LOAD_EXTEND is a loading instruction, which is used to transfer the data to be sorted from the virtual memory of the software simulator to the buffer of the reference model. Then, the software simulator calls the function of the reference model by executing the EXEC instruction to merge and sort the data. Finally, the software simulator transfers the sorted data output by the reference model from the buffer of the reference model back to the virtual memory of the software simulator by executing the STORE_EXTEND instruction. Among the parameters passed by the above instructions, a_base is the base address of the buffer of the reference model, a is the base address of the array to be calculated in the virtual memory of the ISA simulator, and 11 represents that the array size is 2 11 , WD represents the data type in the array is 32 bits.

[0103] In an optional embodiment of the present invention, the data transmission parameters include a buffer address corresponding to the reference model, an array address, an array size, and a data type corresponding to the virtual memory; and the step 103 configuring the communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters includes:

[0104] Step S21, encoding the array address into a first source register corresponding to a communication control instruction; the communication control instruction is an instruction defined according to an instruction set architecture of the verification object;

[0105] Step S22, encoding the buffer address into a second source register corresponding to the communication control instruction;

[0106] Step S23, encoding a first operation code corresponding to the communication control instruction according to the array size;

[0107] Step S24: Encode a second operation code corresponding to the communication control instruction according to the data type.

[0108] In an embodiment of the present invention, the communication control instruction can be defined according to the instruction set architecture of the verification object and the data transmission parameters required by the reference model. Specifically, according to the R-type RISC-V instruction set definition, the array base address in the virtual memory of the software simulator can be encoded into the first source register corresponding to the communication control instruction, the buffer address of the reference model (that is, the base address of the buffer) can be encoded into the second source register, and the first opcode can be encoded according to the array size in the virtual memory, and the second opcode can be encoded according to the data type. Exemplarily, referring to Table 1, the encoding format of a set of communication control instructions provided in an embodiment of the present invention is shown:

[0109] Table 1

[0110]

[0111] Among them, the custom_load instruction is a loading instruction, which is used to load the data in the virtual memory of the software simulator into the buffer of the reference model; the custom_store instruction is a storage instruction, which is used to store the data in the buffer of the reference model into the virtual memory of the software simulator; the custom_load_extend instruction is a large-capacity loading instruction, which has the same function as the custom_load instruction and can load a larger capacity of data; the custom_store_extend instruction is a large-capacity storage instruction, which has the same function as the custom_store instruction and can store a larger capacity of data; the custom_execute instruction is a control instruction, which is used to start the control function of the reference model.

[0112] It should be noted that in the R-type RISC-V instruction set, all operations read the rs1 and rs2 registers as source operands and write the results to register rd. {funct[4:2],rd} is used to encode the array size information of the load instruction and the store instruction. rd Used to encode the array size information of the load_extend instruction and the store_extend instruction; the funct[1:0] field is used to select the data type. gpr[rd] is used to instruct the execute instruction to write the checksum value back to the destination register.

[0113] Taking the custom_load instruction in Table 1 as an example, the buffer address of the reference model can be encoded into rs2 according to the R-type RISC-V instruction set definition, the array address in the virtual memory of the software simulator can be encoded into rs1, the array size can be encoded into funct[4:2],rd, and the data type of the array can be encoded into funct[1:0]. This communication control instruction is used in the actual running test program to realize data transmission between the software simulator and the reference model during verification.

[0114] Furthermore, these communication control instructions can be encapsulated into C language macros, for example, ROCC_INTERFACE_LOAD(k_base, k, 32, BT). Using this macro in the test program can pass the above data transmission parameters to the reference model.

[0115] In an optional embodiment of the present invention, executing the load instruction in step 104 to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model includes:

[0116] Step S31, reading and parsing the first buffer parameter and the first virtual memory parameter in the load instruction;

[0117] Step S32: in response to the load instruction, calling a first read function according to the first virtual memory parameter; the first read function is used to read the test stimulus data from the virtual memory according to the first virtual memory parameter;

[0118] Step S33, obtaining the test stimulus data returned by the first read function;

[0119] Step S34, calling a first write function according to the first buffer parameters; the first write function is used to write the test stimulus data into the buffer according to the first buffer parameters.

[0120] In the embodiment of the present invention, the data required for the reference model operation is stored in the virtual memory of the software simulator, so virtual address reading and writing are required to realize the data transmission between the virtual memory of the software simulator and the buffer of the reference model. The virtual address reading and writing can be realized by the read function and write function provided by the software simulator, for example, the vaddr_read() function and the vaddr_write() function provided by the ISA simulator.

[0121] Specifically, if the software simulator executes the customized load instruction in the embodiment of the present invention, the first buffer parameter and the first virtual memory parameter transmitted in the load instruction are parsed. The first buffer parameter may include the buffer address, that is, the base address of the buffer. The first virtual memory parameter may include the array address, data size, and data type in the virtual memory.

[0122] Next, a first read function, such as a vaddr_read() function, is called according to the first virtual memory parameter, thereby reading test stimulus data from the software-simulated virtual memory according to the array address, array size and data type indicated by the first virtual memory parameter.

[0123] After obtaining the test stimulus, the software simulator calls the first write function, such as the vaddr_write() function, according to the first buffer parameter, thereby writing the test stimulus data into the buffer of the reference model according to the buffer address indicated by the first buffer parameter for the reference model to read.

[0124] Optionally, after the reference model generates the operation result, the step 105 executes the storage instruction to store the operation result in the virtual memory of the software simulator, including:

[0125] Step S41, after the reference model generates a calculation result, reading and parsing the second buffer parameter and the second virtual memory parameter in the storage instruction;

[0126] Step S42, in response to the storage instruction, calling a second read function according to the second buffer parameter; the second read function is used to read the operation result from the buffer according to the second buffer parameter;

[0127] Step S43, obtaining the operation result returned by the second read function;

[0128] Step S44, calling a second write function according to the second virtual memory parameter; the second write function is used to write the operation result into the virtual memory according to the second virtual memory parameter.

[0129] If the software simulator executes the customized storage instruction in the embodiment of the present invention, the second buffer parameter and the second virtual memory parameter transmitted in the storage instruction are parsed. The second buffer parameter may include a buffer address, that is, a base address of the buffer. The second virtual memory parameter may include an array address in the virtual memory.

[0130] Next, the second buffer parameter calls the second read function, thereby reading the operation result generated by the reference model according to the buffer address indicated by the second buffer parameter.

[0131] After obtaining the calculation result of the reference model, the second write function is called according to the second virtual memory parameter, so that the calculation result is written into the virtual memory simulated by the software according to the array address indicated by the second virtual memory parameter, so as to be obtained by the verification system or verification platform, and then compared with the calculation result of the verification object or the design to be tested, so as to verify the design to be tested.

[0132] In summary, the embodiment of the present invention provides a reference model integration method, which can configure communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters of the reference model, and realize the data transmission between the reference model and the software simulator through these communication control instructions. Compared with manually inserting the reference model into the software simulator for integration, the embodiment of the present invention does not need to perform complex configuration operations on the reference model or the software simulator, realizes the automatic integration of the reference model in the software simulator, shortens the development cycle of the software reference model and the time cost of building the verification platform, and is conducive to improving the verification efficiency of the verification object.

[0133] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0134] Device Embodiment

[0135] Reference Figure 3 , shows a structural block diagram of an integrated device of a reference model of the present invention, the device is applied to a software simulator, and specifically may include:

[0136] An acquisition module 301 is used to acquire a reference model of a verification object and data transmission parameters of the reference model;

[0137] A loading module 302, used for loading the reference model into the software simulator;

[0138] A configuration module 303, configured to configure communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters; the communication control instructions include load instructions and store instructions;

[0139] A first execution module 304 is used to execute the loading instruction to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model, so that the reference model reads the test stimulus data from the buffer;

[0140] The second execution module 305 is used to execute the storage instruction after the reference model generates the operation result, so as to store the operation result in the virtual memory of the software simulator.

[0141] Optionally, the data transmission parameters include a buffer address corresponding to the reference model, an array address, an array size, and a data type corresponding to the virtual memory;

[0142] The configuration module includes:

[0143] A first encoding submodule, configured to encode the array address into a first source register corresponding to a communication control instruction; the communication control instruction is an instruction defined according to an instruction set architecture of the verification object;

[0144] A second encoding submodule, used for encoding the buffer address into a second source register corresponding to the communication control instruction;

[0145] A third encoding submodule, used for encoding a first operation code corresponding to the communication control instruction according to the array size;

[0146] The fourth encoding submodule is used to encode the second operation code corresponding to the communication control instruction according to the data type.

[0147] Optionally, the first execution module includes:

[0148] A first reading submodule, used for reading and parsing a first buffer parameter and a first virtual memory parameter in the load instruction;

[0149] A first calling submodule, configured to call a first read function according to the first virtual memory parameter in response to the load instruction; the first read function is configured to read test stimulus data from the virtual memory according to the first virtual memory parameter;

[0150] A stimulus acquisition submodule, used to acquire the test stimulus data returned by the first read function;

[0151] The second calling submodule is used to call a first writing function according to the first buffer parameter; the first writing function is used to write the test stimulus data into the buffer according to the first buffer parameter.

[0152] Optionally, the second execution module includes:

[0153] A second reading submodule, configured to read and parse a second buffer parameter and a second virtual memory parameter in the storage instruction after the reference model generates a calculation result;

[0154] a third calling submodule, configured to call a second read function according to the second buffer parameter in response to the storage instruction; the second read function is configured to read the operation result from the buffer according to the second buffer parameter;

[0155] A result acquisition submodule, used for acquiring the operation result returned by the second read function;

[0156] The fourth calling submodule is used to call the second writing function according to the second virtual memory parameter; the second writing function is used to write the operation result into the virtual memory according to the second virtual memory parameter.

[0157] Optionally, the communication control instruction further includes a control instruction; and the device further includes:

[0158] An instruction parsing module, used for parsing the target function to be achieved by the control instruction when the control instruction is read;

[0159] A function calling module is used to call the target function function of the reference model according to the target function so that the reference model executes the target function.

[0160] Optionally, the device further comprises:

[0161] The result transmission module is used to read the operation result from the virtual memory and write the operation result into the software buffer of the verification system, so that the verification system can verify the verification object according to the operation result recorded in the software buffer.

[0162] In summary, the embodiment of the present invention provides an integrated device for a reference model, which can configure communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters of the reference model, and realize the data transmission between the reference model and the software simulator through these communication control instructions. Compared with manually inserting the reference model into the software simulator for integration, the embodiment of the present invention does not need to perform complex configuration operations on the reference model or the software simulator, realizes the automatic integration of the reference model in the software simulator, shortens the development cycle of the software reference model and the time cost of building the verification platform, and is conducive to improving the verification efficiency of the verification object.

[0163] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0164] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0165] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0166] Reference Figure 4 , is a structural block diagram of an electronic device for integrating a reference model provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the reference model integration method of the aforementioned embodiment.

[0167] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0168] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0169] The memory can be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk and optical data storage device, etc.

[0170] The embodiment of the present invention also provides a non-temporary computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is able to execute Figure 1 The integrated approach of the reference model is shown.

[0171] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0172] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0173] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0174] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0175] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0176] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0177] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0178] The above is a detailed introduction to the reference model integration method, device, electronic device and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A reference model integration method, characterized in that: Applied to a software simulator, the method comprises: Acquire a reference model of a verification object and data transmission parameters of the reference model; loading the reference model into the software simulator; According to the instruction set architecture of the verification object and the data transmission parameters, configuring communication control instructions; the communication control instructions include load instructions and store instructions; Executing the loading instruction to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model, so that the reference model reads the test stimulus data from the buffer; After the reference model generates a calculation result, executing the storage instruction to store the calculation result in the virtual memory of the software simulator; The data transmission parameters are used to indicate information required for data transmission between the reference model and the software simulator; and the communication control instructions are configured according to the instruction set architecture of the verification object and the data transmission parameters, including: Encoding the communication control instructions according to the instruction set architecture, and using the encoded communication control instructions to implement data transmission between the software simulator and the reference model; A corresponding buffer is generated for the reference model according to the data transmission parameters.

2. The method according to claim 1, characterized in that The data transmission parameters include a buffer address corresponding to the reference model, an array address, an array size, and a data type corresponding to the virtual memory; The configuring of the communication control instruction according to the instruction set architecture of the verification object and the data transmission parameter includes: encoding the array address into a first source register corresponding to a communication control instruction; the communication control instruction is an instruction defined according to an instruction set architecture of the verification object; encoding the buffer address into a second source register corresponding to the communication control instruction; Encode a first operation code corresponding to the communication control instruction according to the array size; A second operation code corresponding to the communication control instruction is encoded according to the data type.

3. The method according to claim 1, characterized in that The executing the loading instruction to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model includes: Reading and parsing a first buffer parameter and a first virtual memory parameter in the load instruction; In response to the load instruction, calling a first read function according to the first virtual memory parameter; the first read function is used to read test stimulus data from the virtual memory according to the first virtual memory parameter; Obtaining the test stimulus data returned by the first read function; A first write function is called according to the first buffer parameter; the first write function is used to write the test stimulus data into the buffer according to the first buffer parameter.

4. The method according to claim 1, characterized in that After the reference model generates the operation result, executing the storage instruction to store the operation result in the virtual memory of the software simulator includes: After the reference model generates a calculation result, reading and parsing a second buffer parameter and a second virtual memory parameter in the storage instruction; In response to the storage instruction, calling a second read function according to the second buffer parameter; the second read function is used to read the operation result from the buffer according to the second buffer parameter; Obtaining the operation result returned by the second read function; A second write function is called according to the second virtual memory parameter; the second write function is used to write the operation result into the virtual memory according to the second virtual memory parameter.

5. The method according to claim 1, characterized in that The communication control instruction also includes a control instruction; the method also includes: When the control instruction is read, analyzing the target function to be achieved by the control instruction; The target function function of the reference model is called according to the target function so that the reference model performs the target function.

6. The method according to claim 1, characterized in that The method further comprises: The operation result is read from the virtual memory, and the operation result is written into a software buffer of a verification system, so that the verification system can verify the verification object according to the operation result recorded in the software buffer.

7. An integrated device for a reference model, characterized in that: Applied to a software simulator, the device comprises: An acquisition module, used to acquire a reference model of a verification object and data transmission parameters of the reference model; A loading module, used for loading the reference model into the software simulator; A configuration module, configured to configure communication control instructions according to the instruction set architecture of the verification object and the data transmission parameters; the communication control instructions include load instructions and store instructions; A first execution module, configured to execute the loading instruction to load the test stimulus data in the virtual memory of the software simulator into the buffer of the reference model, so that the reference model reads the test stimulus data from the buffer; A second execution module, configured to execute the storage instruction after the reference model generates a calculation result, so as to store the calculation result in the virtual memory of the software simulator; The data transmission parameters are used to indicate the information required for data transmission between the reference model and the software simulator; the configuration module is specifically used to: Encoding the communication control instructions according to the instruction set architecture, and using the encoded communication control instructions to implement data transmission between the software simulator and the reference model; A corresponding buffer is generated for the reference model according to the data transmission parameters.

8. The device according to claim 7, characterized in that The data transmission parameters include a buffer address corresponding to the reference model, an array address, an array size, and a data type corresponding to the virtual memory; The configuration module includes: A first encoding submodule, configured to encode the array address into a first source register corresponding to a communication control instruction; the communication control instruction is an instruction defined according to an instruction set architecture of the verification object; A second encoding submodule, used for encoding the buffer address into a second source register corresponding to the communication control instruction; A third encoding submodule, used for encoding a first operation code corresponding to the communication control instruction according to the array size; The fourth encoding submodule is used to encode the second operation code corresponding to the communication control instruction according to the data type.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the reference model integration method according to any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to perform the reference model integration method as claimed in any one of claims 1 to 6.

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