Fully transparent waveform encoding, decoding and recovery and reconstruction method for multiple FPGA platforms

Abstract

The present invention discloses a fully transparent waveform encoding and decoding and recovery and reconstruction method for a multi-FPGA platform, including recording and encapsulating the interface signal sent by the reconfigurable logic module RLM into a network message format by a message encapsulation module in a source FPGA chip in a way of transmitting only valid signals, sending it to an interconnection network through a high-speed serial port of the source FPGA and then routing it to a destination FPGA chip; through a message recovery module at the lower layer of the reconfigurable logic module RLM in the destination FPGA chip, recovering the valid signal in the network message format into the original interface signal including data Data, signal Signal and status Status, and sending it to the reconfigurable logic module RLM. The present invention aims to save inter-chip transmission bandwidth while improving data transmission efficiency, solve the fixed coupling relationship between link bandwidth and FPGA system frequency, and improve simulation performance.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a fully transparent waveform encoding, decoding and recovery and reconstruction method for a multi-FPGA platform. Background Art

[0002] As the integration of chips becomes higher and higher, some high-end chips such as processor chips, accelerator chips and other ultra-large-scale chips integrate tens of billions of gates. The current FPGA chip with the largest capacity is Xilinx's UltraScale VU19P, which has a capacity of approximately 50 million gates. Therefore, a single FPGA chip is difficult to meet the simulation and verification needs of today's high-end chips. This requires a simulation platform composed of multiple FPGA arrays for joint simulation. Most of the current multi-FPGA hardware simulation systems use a signal transmission method based on time division multiplexing, and use a parallel interface for inter-chip communication. This method divides the signals to be transmitted into multiple groups, and the width of each group of signals is equal to the actual physical channel width. Each group of signals to be transmitted is mapped to the parallel interface of the physical channel in a time-division sequence, and time division multiplexing is used to complete the transmission of all signals. Such as Figure 1 As shown in the figure, (a) shows the signal interface between module A and module B before logic division; (b) shows the signal transmission process in time division multiplexing mode after modules A and B are divided into two adjacent FPGA chips. However, in time division multiplexing mode, it is assumed that all signals will change in every clock cycle. If the number of signals to be transmitted r is greater than the number of transmissions c that can be provided by the chip-to-chip interface per cycle, the signals of each cycle of the user logic need to be divided into ⌈r⁄c⌉ time slots to complete the transmission, that is, the clock frequency of the user logic is ⌊c⁄r⌋ times the transmission interface frequency. For example, the transmission interface frequency between FPGA chips is 100MHz, which can provide a total of c = 500bit signal transmission; the signals that need to be transmitted between the design logic of the two chips are r = 5000bit, then the core frequency inside the FPGA will be 1⁄10 of the interface frequency, that is, the core frequency is 10MHz. This TDM (Time Division Multiplexing) transmission method realizes signal transmission between adjacent FPGAs from the physical signal level, and completely restores the original signal at the FPGA end. The underlying channel is a non-blocking physical transmission channel, and does not require flow control at the protocol layer, which is simple to implement. However, the user logic frequency is directly related to the number of signals to be transmitted and the physical channel bandwidth. When the design is complex or the TDM multi-channel division is unbalanced, it will seriously restrict the overall performance of the system. Summary of the invention

[0003] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a fully transparent waveform encoding and decoding and recovery and reconstruction method for a multi-FPGA platform is provided. The present invention aims to save inter-chip transmission bandwidth while improving data transmission efficiency, solve the fixed coupling relationship between link bandwidth and FPGA system frequency, and improve simulation performance.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A fully transparent waveform encoding, decoding and recovery and reconstruction method for multiple FPGA platforms, comprising:

[0006] Step S101, through the message encapsulation module of the lower layer of the reconfigurable logic module RLM in the source FPGA chip, the interface signal including data Data, signal Signal and status Status sent by the reconfigurable logic module RLM is recorded in a way of transmitting only valid signals, the recorded valid signal is encapsulated into a network message format, and sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA, and then routed to the destination FPGA chip through the interconnection network;

[0007] Step S102, through the message recovery module of the lower layer of the reconfigurable logic module RLM in the target FPGA chip, the valid signal in the network message format is restored to the original interface signal including data Data, signal Signal and status Status, and sent to the reconfigurable logic module RLM in the target FPGA chip.

[0008] Optionally, the recording in step S101 in a manner of transmitting only valid signals includes: for the data Data and the signal Signal, checking the valid signal Valid of the data Data, if the valid signal Valid of the data Data is 1, recording the data Data and the signal Signal, otherwise not recording the data Data and the signal Signal; for the status Status, determining whether the status Status has changed, recording the status Status only if the status Status has changed, otherwise not recording the status Status.

[0009] Optionally, in step S102, restoring the valid signal in the network message format into the original interface signal including data Data, signal Signal and status Status includes: for the data Data and signal Signal, checking the valid signal Valid of the data Data, if the valid signal Valid of the data Data is 1, restoring the data Data and signal Signal, otherwise not generating the data Data and signal Signal; for the status Status, determining whether the status Status has changed, if the status Status has changed, updating the status Status, otherwise keeping the status Status unchanged.

[0010] Optionally, when the recorded valid signal is encapsulated into a network message format in step S101, the payload width of the encapsulated network message format is W_D_max+m* W_S+N_S, where W_D_max is the maximum width of the data Data, m is the number of signals Signal, W_S is the bit width of the signal Signal, and N_S is the bit width of the status Status.

[0011] Optionally, sending to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA in step S101 includes: sending a valid signal in the network message format to the network module of the current FPGA, determining the corresponding high-speed serial port in the current FPGA according to the routing table of the reconfigurable logic module RLM through the cross-network module of the source FPGA, and then sending to the interconnection network of multiple FPGA platforms through the corresponding high-speed serial port in the current FPGA.

[0012] Optionally, when the data is sent to the interconnection network of multiple FPGA platforms through the corresponding high-speed serial port in the current FPGA, the corresponding high-speed serial ports in each FPGA are transmitted based on a network hierarchical structure, and the network hierarchical structure includes a physical layer, a link layer and a network layer. The physical layer is used to realize point-to-point transmission of bit streams between FPGA chips at both ends, including electrical signal connection, signal quality assurance, data encoding and multi-channel binding; the link layer is used for message format definition, transmission flow control and data reliable transmission protocol; the network layer is used to realize global communication between multiple FPGA chips in the system to ensure that the data is sent to the correct destination FPGA chip.

[0013] Optionally, before step S101, the message encapsulation module also includes initializing the sending credit Credit to the cache size in the message recovery module. When sending to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA in step S101, it includes detecting the sending credit Credit. Only when the sending credit Credit is greater than 0, it is sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA, and the sending credit Credit is reduced by 1; in step S102, when the message recovery module restores the valid signal in the network message format to the original interface signal including data Data, signal Signal and status Status, and sends it to the reconfigurable logic module RLM in the destination FPGA chip, a credit release signal is sent to the message encapsulation module in the source FPGA chip after processing each valid signal in the network message format, and the message encapsulation module increases the sending credit Credit by 1 after receiving the credit release signal.

[0014] Optionally, the message encapsulation module initializes the sending credit Credit to the cache size in the message recovery module, specifically including the message encapsulation module respectively initializing the sending credit Credit of the physical layer, link layer and network layer to the cache size of the physical layer, link layer and network layer in the message recovery module; the detecting the sending credit Credit, only when the sending credit Credit is greater than 0, is it sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA, and the sending credit Credit is reduced by 1, including: detecting the sending credit Credit of the network layer, only when the sending credit Credit of the network layer is greater than 0, is the valid signal of the network message format sent to the link layer and the sending credit Credit of the network layer is reduced by 1, detecting the sending credit Credit of the link layer, only when the sending credit Credit of the link layer is greater than 0, is the valid signal of the network message format sent to the physical layer and the sending credit Credit of the link layer is reduced by 1, detecting the sending credit Credit of the physical layer, and only when the sending credit Credit of the link layer is greater than 0, is the network message The valid signal of the format is sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA and the sending credit Credit of the physical layer is reduced by 1; the sending of a credit release signal to the message encapsulation module in the source FPGA chip after each processing of a valid signal of the network message format includes: the physical layer sends a credit release signal for the physical layer to the message encapsulation module in the source FPGA chip after each processing of a valid signal of the network message format, so that the message encapsulation module increases the sending credit Credit of the physical layer by 1 after receiving the credit release signal; the link layer sends a credit release signal for the link layer to the message encapsulation module in the source FPGA chip after each processing of a valid signal of the network message format, so that the message encapsulation module increases the sending credit Credit of the link layer by 1 after receiving the credit release signal; the network layer sends a credit release signal for the network layer to the message encapsulation module in the source FPGA chip after each processing of a valid signal of the network message format, so that the message encapsulation module increases the sending credit Credit of the network layer by 1 after receiving the credit release signal.

[0015] Optionally, the front end of the message encapsulation module is connected to a signal multiplexer, a data majority selector and a status detection module tx_status, wherein the signal multiplexer is used to check the valid signal Valid of the data Data for the signal Signal, and if the valid signal Valid of the data Data is 1, then n signal Signals are selected from the total m paths, otherwise the signal Signal is not selected; the data majority selector is used to check the valid signal Valid of the data Data for the data Data, and if the valid signal Valid of the data Data is 1, then one path of the data Data is selected and output, otherwise the data Data is not selected; the status detection module tx_status is used to determine whether the status Status has changed, and the status Status is output only if the status Status has changed, otherwise the status Status is not output.

[0016] In addition, the present invention also provides a multi-FPGA platform, including multiple FPGA chips interconnected by an interconnection network, and the multiple FPGA chips are programmed or configured to execute the fully transparent waveform encoding and decoding and recovery and reconstruction method for the multi-FPGA platform.

[0017] Compared with the prior art, the present invention mainly has the following advantages: for large-scale FPGA platforms used for chip verification, the fully transparent waveform encoding and decoding and recovery and reconstruction method for multiple FPGA platforms of the present invention provides a data transmission technology between multiple FPGA partitions. By dividing the signal into data and status signals, only valid data between FPGA partition blocks is transmitted. The data is transmitted through multiple high-speed serial ports integrated in the FPGA chip to achieve interconnection with dedicated high-order switches, and the system scale is expanded and the performance is optimized. It can improve data transmission efficiency while saving inter-chip transmission bandwidth, solve the fixed coupling relationship between link bandwidth and FPGA system frequency, and improve simulation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the time division multiplexing signal transmission method of the prior art.

[0019] Figure 2 Schematic diagram of the process of the embodiment of the present invention.

[0020] Figure 3 This is a signal transmission method between FPGAs based on network message exchange on multiple FPGA platforms in an embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of the principle of recording a valid signal for data Data in an embodiment of the present invention.

[0022] Figure 5The figure is a schematic diagram of the principle of recording a valid signal for the status Status in an embodiment of the present invention.

[0023] Figure 6 This is a hierarchical transmission model of signals between modules in an embodiment of the present invention.

[0024] Figure 7 This is a communication effect diagram based on credit flow control in an embodiment of the present invention.

[0025] Figure 8 Schematic diagram of the design of inter-module hierarchical flow control in an embodiment of the present invention.

[0026] Fig. 9 Schematic diagram of the data record structure of the message encapsulation module in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] like Figure 2 As shown, the fully transparent waveform encoding, decoding and recovery and reconstruction method for multiple FPGA platforms in this embodiment includes:

[0028] Step S101, through the message encapsulation module of the lower layer of the reconfigurable logic module RLM in the source FPGA chip, the interface signal including data Data, signal Signal and status Status sent by the reconfigurable logic module RLM is recorded in a way of transmitting only valid signals, the recorded valid signal is encapsulated into a network message format, and sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA, and then routed to the destination FPGA chip through the interconnection network;

[0029] Step S102, through the message recovery module of the lower layer of the reconfigurable logic module RLM in the target FPGA chip, the valid signal in the network message format is restored to the original interface signal including data Data, signal Signal and status Status, and sent to the reconfigurable logic module RLM in the target FPGA chip.

[0030] In step S101 of this embodiment, sending the signal to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA includes: sending the valid signal in the network message format to the network module of the current FPGA, determining the corresponding high-speed serial port in the current FPGA according to the routing table of the reconfigurable logic module RLM through the cross-network module of the source FPGA, and then sending the signal to the interconnection network of multiple FPGA platforms through the corresponding high-speed serial port in the current FPGA. Figure 3As shown, in this embodiment, the data transmission between the source FPGA chip and the destination FPGA chip in the multi-FPGA platform is taken as an example. The source FPGA chip includes modules A1~An, a total of n reconfigurable logic modules RLM. The lower layer of each reconfigurable logic module RLM corresponds to a message packaging and recovery module Packer A1~An composed of a message encapsulation module and a message recovery module. The message packaging and recovery module Packer A1~An is connected to m ports A1~Am through an internal cross network module to realize sending data through different ports. The destination FPGA chip is connected to the source FPGA chip through the interconnection network of the multi-FPGA platform, and the structure of the destination FPGA chip is exactly the same as that of the source FPGA chip. The source FPGA is sent to the interconnection network of the multi-FPGA platform through the high-speed serial port of the source FPGA, and then reaches the destination FPGA chip through the interconnection network routing, and finally reaches the reconfigurable logic module RLM in the destination FPGA chip.

[0031] According to statistics and analysis, in most RTL designs, the interface signals between two reconfigurable logic modules RLM can generally be divided into interface signals of data Data, signal Signal and status Status. Data Data is a pulse signal, which keeps synchronization with the clock signal, and is usually transmitted together with the corresponding valid signal Valid. When the valid signal Valid is high in a certain clock cycle, it indicates that the corresponding data Data is valid, otherwise the data Data is invalid data. The status signal Status is generally used to indicate a certain state value. Data Data is strictly synchronized with the clock, and all data during the valid period of the valid signal Valid must be transmitted from the source end to the destination end completely and without error; whether the data signal during the invalid period of the valid signal Valid requires complete transmission is generally not required. The status signal Status is generally not required to keep synchronization with the clock, and it is only necessary to be able to perceive the state change of the signal at the source end at the destination end. In order to achieve efficient data transmission between FPGAs, in step S101 of this embodiment, the interface signals including data Data, signal Signal and status Status sent by the reconfigurable logic module RLM are recorded in a way that only valid signals are transmitted. Specifically, the recording in the manner of transmitting only valid signals in step S101 includes: for data Data and signal Signal, checking the valid signal Valid of data Data, if the valid signal Valid of data Data is 1, then recording data Data and signal Signal, otherwise not recording data Data and signal Signal; for status Status, judging whether status Status has changed, only recording status Status if status Status has changed, otherwise not recording status Status. Figure 4 As shown, clk Indicates the clock, valid Indicates valid signal Valid, data Represents data Data, packet Indicates the recorded data packet, Figure 4 In black data Indicates that the data Data whose valid signal Valid is 1 has a corresponding recorded data packet; and the white data The data Data indicating that the valid signal Valid is 0 has no corresponding recorded data packet. Figure 5 As shown, clk Indicates the clock, state Indicates the status Status, packet Indicates the recorded data packet, Figure 5 In the data packet recording, only when the status Status rises or falls will it trigger the recording of the data packet. Since the effective data transmission between adjacent reconfigurable logic modules RLM is not always effective, there is an idle state; the status signal changes very slowly, and generally the status signal needs to be transmitted only when new notifications or alarm information appears in the system. Therefore, by adopting the above-mentioned method of transmitting only valid data, a large amount of useless information can be discarded, which improves the data transmission efficiency while saving the transmission bandwidth, releases the fixed coupling relationship between the link bandwidth and the system frequency, eliminates the bandwidth bottleneck of signal transmission, and improves the system simulation performance.

[0032] Based on the recording method of transmitting only valid signals, in order to realize decoding of the original waveform and data recovery, in step S102 of this embodiment, the valid signal in the network message format is restored to the original interface signal including data Data, signal Signal and status Status, including: for data Data and signal Signal, checking the valid signal Valid of data Data, if the valid signal Valid of data Data is 1, then recovering data Data and signal Signal, otherwise not generating data Data and signal Signal; for status Status, judging whether status Status has changed, if status Status has changed, updating status Status, otherwise keeping status Status unchanged.

[0033] It should be noted that the high-speed serial ports connecting the source FPGA, the destination FPGA chip and the interconnection network of the multi-FPGA platform can use the required high-speed serial ports as needed. For example, this embodiment uses the GTY high-speed serial port.

[0034] The waveform transmission function needs to achieve a transparent pipeline transmission effect and provide it to the upper-level EDA software to complete the signal packaging. According to the network layered transmission protocol, the communication between modules at two equal levels is achieved through the low-level protocol layer, such as Figure 6 As shown. For communication between modules A and B in two FPGA chips A and B, the signal must first be sent to the message encapsulation module (Packer), then the data must be sent to the other chip through the link layer and the physical layer, and then the data must be processed by the physical layer and the link layer in turn. Then the message must be decapsulated and the data must be restored to form the original signal between module A and module B and sent to the destination module. At the sending end, after the interface logic receives the data from the user logic, it is temporarily stored in a temporary buffer. After queuing arbitration, the data is organized into a dedicated message format and sent to the network port, and the corresponding flow control information is returned to the user logic; at the receiving end, the interface logic parses the data from the network into user data, sends it to the user logic, and then processes the flow control information returned by the user logic. In this process, the original direct data transmission between the two user logics is divided into multiple segments, and the flow control information is changed from a global flow control protocol between the source and the destination to a multi-level distributed flow control protocol. For the user logic, this process is carried out at the link layer, which is fully transparent and does not affect the normal transmission of data at the application layer.

[0035] Time division multiplexing is also a way to improve data transmission efficiency. It is generally based on a parallel transmission interface, which has the advantages of low latency and simple implementation, but its transmission bandwidth is low, and the simulation frequency is limited by the transmission bandwidth, which restricts the performance of the system. Compared with time division multiplexing, network message transmission is generally based on a serial transmission interface, which has the advantages of high bandwidth and easy expansion. Since only valid signals are transmitted, useless signals are prevented from occupying the network bandwidth for a long time, and there is no direct correlation between the simulation frequency and the transmission bandwidth, which makes the system have higher performance.

[0036] In most cases, after appropriate logical division, a large amount of data transmission between adjacent FPGA chips is loosely coupled signals, and only a few signals are tightly coupled. When a small amount of tightly coupled signals are transmitted between two adjacent FPGA chips, a parallel transmission interface is generally used, and a time division multiplexing method is used for signal transmission, which can reduce the transmission delay of the signal between the two modules; when a large amount of loosely coupled signals are transmitted between two adjacent FPGA chips, a serial transmission interface is generally used, and a method based on network message exchange is used for signal transmission, which can improve the data transmission bandwidth. Therefore, in the multi-FPGA platform of this embodiment, in addition to using a high-speed serial port to connect the two adjacent FPGA chips to realize the data transmission of step S101 and step S102, it also includes using a parallel transmission interface to connect between some adjacent two FPGA chips to use a time division multiplexing method for signal transmission to reduce the transmission delay of the signal between the two modules. Undoubtedly, at least one connection interface and data transmission method of the high-speed serial port and the parallel transmission interface can be used between the two adjacent FPGA chips, which can be configured or selected according to actual needs.

[0037] In this embodiment, user data is divided into three types: data, signal and status. Data is accompanied by a valid signal Valid. When the valid signal Valid is 1, the data is considered valid, otherwise it is invalid; the signal Signal is a scattered signal, which can be considered as a Data signal with a width of 1, and the valid signal Valid is the same as the data Data, that is, when the valid signal Valid is 1, it is valid, otherwise it is invalid; the state State is a signal that changes very slowly and does not have a strong time requirement. The signal Signal can be specified to select m from n at compile time, where n and m are determined; in addition, the count width (W_S) required for each Signal is also determined at compile time. If the number of the current n signals that can be transmitted is less than m, they are also transmitted as m to keep the design simple. The state State can be selected in full due to its small number and infrequent changes, and its total number is N_S. The width of the data Data signal is specified by the user. For each message encapsulation module, if multiple groups of Data signals are input at the same time, only one Data is selected for transmission each time. Therefore, the width of the output data should be the maximum width of these multiple groups of Data (W_D_max). Therefore, after the compilation is completed, the message format should be determined. The total payload width is W_D_max+m* W_S+N_S. That is, when the recorded valid signal is encapsulated into a network message format in step S101 of this embodiment, the payload width of the encapsulated network message format is W_D_max+m* W_S+N_S, where W_D_max is the maximum width of the data Data, m is the number of signal Signals, W_S is the bit width of the signal Signal, and N_S is the bit width of the status Status.

[0038] For the above data Data and state signal State, this embodiment records them and encapsulates them into a network message format, sends them to the switched interconnection network through the network port, and routes them to the destination FPGA chip, such as Figure 2As shown. In order to enable the high-speed serial port to support sending valid signals in the format of network messages, when the corresponding high-speed serial port in the current FPGA is sent to the interconnection network of multiple FPGA platforms in this embodiment, the corresponding high-speed serial ports in each FPGA are transmitted based on the network layered structure. The network layered structure includes a physical layer, a link layer and a network layer. The physical layer is used to realize point-to-point transmission of bit streams between FPGA chips at both ends, including electrical signal connection, signal quality assurance, data encoding and multi-channel binding; the link layer is used for message format definition, transmission flow control and data reliable transmission protocol; the network layer is used to realize global communication between multiple FPGA chips in the system to ensure that the data is sent to the correct destination FPGA chip. The signals between user logics in this embodiment are transmitted according to the network layered structure. In this embodiment, the message encapsulation module and the message recovery module implement the three-layer protocol of the physical layer, link layer and network layer with reference to the network transmission protocol, wherein the physical layer realizes the point-to-point transmission of the bit stream between the two end FPGA chips, including electrical signal connection, signal quality assurance, data encoding and multi-channel binding; the link layer is responsible for message format definition, transmission flow control and data reliable transmission protocol; the network layer realizes the global communication between multiple FPGA chips in the system, ensuring that the data is sent to the correct destination FPGA chip. Figure 6 As shown, A and B represent two different FPGA chips in the multi-FPGA platform, where module A represents the reconfigurable logic module RLM of FPGA chip A, and module B represents the reconfigurable logic module RLM of FPGA chip B. The physical medium from module A to the serial interface includes three layers: network layer A, link layer A, and physical layer A, and the physical medium from module B to the serial interface includes three layers: network layer B, link layer B, and physical layer B. This inter-FPGA connection method based on network exchange only transmits valid signals, reduces the requirements for communication bandwidth between FPGA chips, decouples the relationship between signal transmission bandwidth and core frequency, and improves system operation performance.

[0039] like Figure 7The communication principle diagram of two RLM modules across chips based on credit flow control is described. Module A has data to send to module B. In order to avoid data loss caused by module B not being able to process the received data in time, a receiving buffer is generally set inside the receiving end (B) to cache the data arriving from the network link; at the same time, a credit-based flow control mechanism is adopted to ensure that the buffer will not overflow. At the sending end, A maintains the sending credit Credit, and its initial value is the capacity of the receiving buffer at B; every time A sends a data message, the credit Credit is reduced by one, indicating that the buffer capacity at B will consume one space; if Credit is greater than 0, A can continue to send data; if Credit is 0, it means that the buffer space at B has been occupied, and A stops sending data at this time; when a data is read out of the buffer at B, a credit release signal is returned to A, indicating that the available buffer space has increased, and A increases Credit by one after receiving the credit release signal. Based on the above principles, this embodiment provides a specific implementation mechanism: before step S101, the message encapsulation module also includes initializing the sending credit Credit to the cache size in the message recovery module. When sending to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA in step S101, it includes detecting the sending credit Credit. Only when the sending credit Credit is greater than 0, it is sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA, and the sending credit Credit is reduced by 1; in step S102, the message recovery module recovers the valid signal in the network message format into the original interface signal including data Data, signal Signal and status Status, and sends it to the reconfigurable logic module RLM in the destination FPGA chip. After processing each valid signal in the network message format, a credit release signal is sent to the message encapsulation module in the source FPGA chip, and the message encapsulation module increases the sending credit Credit by 1 after receiving the credit release signal.

[0040] like Figure 8As shown, in this embodiment, the message encapsulation module initializes the sending credit Credit as the cache size in the message recovery module, specifically including the message encapsulation module respectively initializing the sending credit Credit of the physical layer, the link layer and the network layer as the cache size of the physical layer, the link layer and the network layer in the message recovery module; the detection of the sending credit Credit, only when the sending credit Credit is greater than 0, is it sent to the interconnection network of the multi-FPGA platform through the high-speed serial port of the source FPGA, and the sending credit Credit is reduced by 1, including: detecting the sending credit Credit of the network layer, only when the sending credit Credit of the network layer is greater than 0, is the valid signal of the network message format sent to the link layer and the sending credit Credit of the network layer is reduced by 1, detecting the sending credit Credit of the link layer, only when the sending credit Credit of the link layer is greater than 0, is the valid signal of the network message format sent to the physical layer and the sending credit Credit of the link layer is reduced by 1, detecting the sending credit Credit of the physical layer, and only when the sending credit Credit of the link layer is greater than 0, is the network The valid signal of the message format is sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA and the sending credit Credit of the physical layer is reduced by 1; the sending of a credit release signal to the message encapsulation module in the source FPGA chip after processing each valid signal of the network message format includes: the physical layer sends a credit release signal for the physical layer to the message encapsulation module in the source FPGA chip after processing each valid signal of the network message format, so that the message encapsulation module increases the sending credit Credit of the physical layer by 1 after receiving the credit release signal; the link layer sends a credit release signal for the link layer to the message encapsulation module in the source FPGA chip after processing each valid signal of the network message format, so that the message encapsulation module increases the sending credit Credit of the link layer by 1 after receiving the credit release signal; the network layer sends a credit release signal for the network layer to the message encapsulation module in the source FPGA chip after processing each valid signal of the network message format, so that the message encapsulation module increases the sending credit Credit of the network layer by 1 after receiving the credit release signal. In this embodiment, in the actual transmission process, according to the aforementioned network layering protocol, the communication between FPGA chips A and B is achieved through the underlying transport layer, link layer and physical layer. The transport layer encapsulates data messages, the link layer ensures reliable point-to-point transmission of data, and the physical layer implements channel binding, data encoding and the underlying sending and receiving circuits, as shown in Figure 8. Since the simulation system cannot modify the user logic at will, in order to enable FPGA chip A to communicate normally with B, it is necessary to set an input buffer of the same size at A and the transmission layer of the sending end, and generate a corresponding credit release signal to A according to the flow control requirements.In order to avoid input buffer overflow at the receiving end B, it is also necessary to set up an appropriate intermediate buffer between B and the transmission layer according to the waveform delay, and transmit data to B according to the current credit status of the receiving end B. Under this mechanism, the original direct transmission between FPGA chips A and B is interrupted, and the network transmission layer, link layer and physical layer are inserted in the middle. The signal to be transmitted between FPGA chips A and B is encapsulated and transmitted to the other end through the network. At the same time, the flow control path between FPGA chips A and B is replaced with the segmented flow control between the corresponding protocol processing layers at both ends of the network. At this time, FPGA chips A and B still communicate normally according to the previous transmission protocol and flow control mechanism. Except for a slight increase in transmission delay, there are no other abnormalities, so that fully transparent data transmission can be achieved between FPGA chips A and B.

[0041] Fig. 9 This is a schematic diagram of the data record structure of the message encapsulation module in this embodiment, see Fig. 9 In this embodiment, the front end of the message encapsulation module is connected to a signal multiplexer (tx_multi_select), a data majority selector (tx_multi_select_data) and a status detection module tx_status. The signal multiplexer is used to check the valid signal Valid of the data Data for the signal Signal. If the valid signal Valid of the data Data is 1, then n signal Signals are selected from the total m signals, otherwise the signal Signal is not selected; the data majority selector is used to check the valid signal Valid of the data Data. If the valid signal Valid of the data Data is 1, then one data Data is selected and output, otherwise the data Data is not selected; the status detection module tx_status is used to determine whether the status Status has changed. The status Status is output only if the status Status has changed, otherwise the status Status is not output. Fig. 9 As shown, N groups of Signal signals are selected by the multi_select module to select M groups. If any of the selected data groups is valid, all M groups of data are transmitted to the packer module. The tx_status module transmits the changed state signal to the packer module. Since the Data signal has a large bit width, only one group of data is transmitted to the message encapsulation module when Valid is valid. After receiving all the valid information that the message needs to carry, the message encapsulation module completes the signal packaging and encapsulation, and the resulting data can be transmitted through the network.

[0042] In addition, this embodiment also provides a multi-FPGA platform, including multiple FPGA chips interconnected through an interconnection network, and the multiple FPGA chips are programmed or configured to execute the fully transparent waveform encoding and decoding and recovery and reconstruction method for the multi-FPGA platform. It should be noted that the number of FPGA chips in the multi-FPGA platform can be two or more, and the interface between the FPGA chip and the interconnection network includes a serial interface, and a parallel interface can also be used simultaneously or partially.

[0043] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0044] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A fully transparent waveform encoding, decoding and recovery and reconstruction method for multiple FPGA platforms, characterized in that: include: Step S101, through the message encapsulation module of the lower layer of the reconfigurable logic module RLM in the source FPGA chip, the interface signal including data Data, signal Signal and status Status sent by the reconfigurable logic module RLM is recorded in a way of transmitting only valid signals, the recorded valid signal is encapsulated into a network message format, and sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA, and then routed to the destination FPGA chip through the interconnection network; Step S102, through the message recovery module of the lower layer of the reconfigurable logic module RLM in the target FPGA chip, the valid signal in the network message format is restored to the original interface signal including data Data, signal Signal and status Status, and sent to the reconfigurable logic module RLM in the target FPGA chip; Before step S101, the message encapsulation module also includes initializing the sending credit Credit to the cache size in the message recovery module. When sending to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA in step S101, it includes detecting the sending credit Credit. Only when the sending credit Credit is greater than 0, it is sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA, and the sending credit Credit is reduced by 1; in step S102, the message recovery module recovers the valid signal in the network message format into the original interface signal including data Data, signal Signal and status Status, and sends it to the reconfigurable logic module RLM in the destination FPGA chip. After processing a valid signal in the network message format, a credit release signal is sent to the message encapsulation module in the source FPGA chip, and the message encapsulation module increases the sending credit Credit by 1 after receiving the credit release signal; The message encapsulation module initializes the sending credit Credit as the cache size in the message recovery module, specifically including the message encapsulation module respectively initializing the sending credit Credit of the physical layer, the link layer and the network layer as the cache size of the physical layer, the link layer and the network layer in the message recovery module; the detecting the sending credit Credit, only when the sending credit Credit is greater than 0, is it sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA, and the sending credit Credit is reduced by 1, including: detecting the sending credit Credit of the network layer, only when the sending credit Credit of the network layer is greater than 0, is the valid signal of the network message format sent to the link layer and the sending credit Credit of the network layer is reduced by 1, detecting the sending credit Credit of the link layer, only when the sending credit Credit of the link layer is greater than 0, is the valid signal of the network message format sent to the physical layer and the sending credit Credit of the link layer is reduced by 1, detecting the sending credit Credit of the physical layer, and only when the sending credit Credit of the link layer is greater than 0, is the network message format The valid signal is sent to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA and the sending credit Credit of the physical layer is reduced by 1; the sending of a credit release signal to the message encapsulation module in the source FPGA chip after each valid signal in the network message format is processed includes: the physical layer sends a credit release signal for the physical layer to the message encapsulation module in the source FPGA chip after each valid signal in the network message format is processed, so that the message encapsulation module increases the sending credit Credit of the physical layer by 1 after receiving the credit release signal; the link layer sends a credit release signal for the link layer to the message encapsulation module in the source FPGA chip after each valid signal in the network message format is processed, so that the message encapsulation module increases the sending credit Credit of the link layer by 1 after receiving the credit release signal; the network layer sends a credit release signal for the network layer to the message encapsulation module in the source FPGA chip after each valid signal in the network message format is processed, so that the message encapsulation module increases the sending credit Credit of the network layer by 1 after receiving the credit release signal.

2. The fully transparent waveform encoding, decoding and recovery and reconstruction method for a multi-FPGA platform according to claim 1, characterized in that: The recording method of transmitting only valid signals in step S101 includes: for data Data and signal Signal, checking the valid signal Valid of data Data, if the valid signal Valid of data Data is 1, recording data Data and signal Signal, otherwise not recording data Data and signal Signal; for status Status, judging whether status Status has changed, recording status Status only if status Status has changed, otherwise not recording status Status.

3. The fully transparent waveform encoding, decoding and recovery and reconstruction method for a multi-FPGA platform according to claim 2, characterized in that: In step S102, the valid signal in the network message format is restored to the original interface signal including data Data, signal Signal and status Status, including: for data Data and signal Signal, checking the valid signal Valid of data Data, if the valid signal Valid of data Data is 1, then restoring data Data and signal Signal, otherwise not generating data Data and signal Signal; for status Status, judging whether status Status has changed, if status Status has changed, updating status Status, otherwise keeping status Status unchanged.

4. The fully transparent waveform encoding, decoding and recovery and reconstruction method for multiple FPGA platforms according to claim 1, characterized in that: When the recorded valid signal is encapsulated into a network message format in step S101, the payload width of the encapsulated network message format is W_D_max+m* W_S+N_S, where W_D_max is the maximum width of the data Data, m is the number of signals Signal, W_S is the bit width of the signal Signal, and N_S is the bit width of the status Status.

5. The fully transparent waveform encoding, decoding and recovery and reconstruction method for multiple FPGA platforms according to claim 1, characterized in that: Sending to the interconnection network of multiple FPGA platforms through the high-speed serial port of the source FPGA in step S101 includes: sending a valid signal in the network message format to the network module of the current FPGA, determining the corresponding high-speed serial port in the current FPGA according to the routing table of the reconfigurable logic module RLM through the cross-network module of the source FPGA, and then sending to the interconnection network of multiple FPGA platforms through the corresponding high-speed serial port in the current FPGA.

6. The fully transparent waveform encoding, decoding and recovery and reconstruction method for multiple FPGA platforms according to claim 5, characterized in that: When the data is sent to the multi-FPGA platform interconnection network through the corresponding high-speed serial port in the current FPGA, the corresponding high-speed serial ports in each FPGA are transmitted based on the network layered structure, and the network layered structure includes a physical layer, a link layer and a network layer. The physical layer is used to realize point-to-point transmission of the bit stream between the FPGA chips at both ends, including electrical signal connection, signal quality assurance, data encoding and multi-channel binding; The link layer is used for message format definition, transmission flow control and data reliable transmission protocol; the network layer is used to realize global communication between multiple FPGA chips in the system to ensure that the data is sent to the correct destination FPGA chip.

7. The fully transparent waveform encoding, decoding and recovery and reconstruction method for a multi-FPGA platform according to claim 1, characterized in that: The front end of the message encapsulation module is connected to a signal multiplexer, a data majority selector and a status detection module tx_status. The signal multiplexer is used to check the valid signal Valid of the data Data for the signal Signal. If the valid signal Valid of the data Data is 1, then n signal Signals are selected from the total m paths, otherwise the signal Signal is not selected; the data majority selector is used to check the valid signal Valid of the data Data for the data Data. If the valid signal Valid of the data Data is 1, then one path of the data Data is selected and output, otherwise the data Data is not selected; the status detection module tx_status is used to determine whether the status Status has changed. The status Status is output only if the status Status has changed, otherwise the status Status is not output.

8. A multi-FPGA platform, comprising a plurality of FPGA chips interconnected by an interconnection network, characterized in that: The multiple FPGA chips are programmed or configured to execute the fully transparent waveform encoding, decoding and recovery and reconstruction method for a multi-FPGA platform as described in any one of claims 1 to 7.

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