Drive control circuit, drive control method, and display panel

Abstract

The application provides a driving control circuit, a driving control method and a display panel. The driving control circuit comprises a timing controller, a gate driving circuit and a first clock signal processing unit. The timing controller is configured to output a first control signal. The gate driving circuit is electrically connected to the timing controller. The gate driving circuit is configured to receive the first control signal and generate a gate scanning signal according to the first control signal. The first control signal is configured to control a pulse falling edge of the gate scanning signal. The first clock signal processing unit is electrically connected to the timing controller. The first clock signal processing unit is configured to receive the first control signal and generate a second control signal according to the first control signal. The second control signal is configured to control a charge sharing switch unit between two columns of data lines to be shared to be turned on at the pulse falling edge of the gate scanning signal, so as to increase a charge sharing time.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driving control circuit, a driving control method, and a display panel. Background Technology

[0002] In display technology, charge sharing technology can effectively reduce power consumption. For example, before the next charge, the positive and negative pixel voltages, such as a first voltage higher than the common voltage and a second voltage lower than the common voltage, are shared to neutralize the positive and negative pixel voltages. This is equivalent to discharging without consuming power, effectively reducing the power consumption of the display panel. For high refresh rate display panels or dual-gate driven display panels, the reserved discharge time is short, which leads to a shorter charge sharing time, less power consumption reduction, and higher temperature of the source drive circuit. This can easily reduce the operating efficiency of the source drive circuit or even damage it. Summary of the Invention

[0003] The purpose of this application is to provide a driving control circuit, a driving control method, and a display panel to solve the technical problem in the related art where the charge sharing time in the display panel is compressed to a shorter duration.

[0004] In a first aspect, this application provides a drive control circuit, including:

[0005] A timing controller configured to output a first control signal;

[0006] A gate driving circuit, electrically connected to the timing controller, is configured to receive a first control signal and generate a gate scan signal based on the first control signal, wherein the first control signal is configured to control the falling edge of the pulse of the gate scan signal; and

[0007] A first clock signal processing unit is electrically connected to the timing controller. The first clock signal processing unit is configured to receive the first control signal and generate a second control signal based on the first control signal. The second control signal is configured to control the charge sharing switch unit between the two columns of data lines to be shared to be turned on at the falling edge of the pulse of the gate scan signal.

[0008] The drive control circuit provided in this application includes a timing controller, a gate drive circuit, and a first clock signal processing unit. The timing controller is configured to output a first control signal. The gate drive circuit is electrically connected to the timing controller and is configured to receive the first control signal and generate a gate scan signal based on the first control signal. The first control signal is configured to control the falling edge of the pulse of the gate scan signal. The first clock signal processing unit is electrically connected to the timing controller and is configured to receive the first control signal and generate a second control signal based on the first control signal. The second control signal is configured to control the charge sharing switch unit between two columns of data lines to be shared to be turned on at the falling edge of the pulse of the gate scan signal. Thus, the charge sharing time is between the falling edge of the previous row of gate scan signal and the time point when charging begins during the scanning process of the next row. Within one cycle of a gate scan signal, all time except for the charging time is the charge sharing time. The longer the charge sharing time, the more complete the charge sharing, the longer the passive discharge time, the more power consumption is saved, and the risk of overheating is reduced.

[0009] In one optional implementation, the first clock signal processing unit includes a first register electrically connected to the timing controller. The first register is configured to receive the first control signal and output a target register signal when the pulse edge of the first control signal is a preset edge.

[0010] In one optional implementation, the first clock signal processing unit includes a second register electrically connected to the first register. The second register is configured to receive the target register signal and output the second control signal according to the target register signal, such that the first rising edge of the second control signal corresponds to the falling edge of the pulse of the first row gate scan signal of each frame.

[0011] In one optional embodiment, the timing controller is further configured to output a third control signal, and the gate drive circuit is further configured to receive the third control signal and generate a gate scan signal based on the first control signal and the third control signal, wherein the third control signal is configured to control the rising edge of the pulse of the gate scan signal.

[0012] In one optional embodiment, the drive control circuit further includes a source drive circuit electrically connected to the timing controller. The source drive circuit includes a first clock signal processing unit and a charge sharing switch unit, wherein the charge sharing switch unit is electrically connected between two columns of data lines to be shared.

[0013] The drive control circuit further includes a first wiring and a second wiring. The first wiring is electrically connected to the timing controller and the source drive circuit, and the first wiring is used to transmit the first control signal. The second wiring is electrically connected between the first clock signal processing unit and the charge sharing switch unit, and the second wiring is used to transmit the second control signal.

[0014] In one optional embodiment, the timing controller is further configured to output a frame start signal and a line start signal; the gate driving circuit is further configured to receive the frame start signal, the source driving circuit is further configured to receive the line start signal, the gate driving circuit is further configured to sequentially generate a plurality of the gate scan signals under the indication of the frame start signal, and the source driving circuit is further configured to output a source data signal to the pixel unit when the gate scan signal is high and under the indication of the line start signal, so that the pixel unit performs one charging and discharging cycle in each pulse period of the line start signal.

[0015] In one optional embodiment, the drive control circuit further includes a third wiring, which is electrically connected to the timing controller and the source drive circuit, and the third wiring is used to transmit the row start signal;

[0016] The source drive circuit further includes a second clock signal processing unit, which is configured to receive the row start signal and generate a fourth control signal based on the row start signal. The fourth control signal is used to control the charge sharing switch unit between the two columns of data lines to be shared to be turned on after charging and on the rising edge of the pulse of the row start signal.

[0017] The first clock signal processing unit is configured to operate in a first working mode and not operate in a second working mode; the second clock signal processing unit is configured to operate in the second working mode and not operate in the first working mode, wherein the refresh rate in the first working mode is greater than or equal to a preset refresh rate, and the refresh rate in the second working mode is less than the preset refresh rate.

[0018] Secondly, this application provides a drive control method, the method comprising:

[0019] The first control signal is generated;

[0020] A gate scan signal is generated based on the first control signal, wherein the first control signal is configured to control the falling edge of the pulse of the gate scan signal;

[0021] A second control signal is generated based on the first control signal, and the second control signal is configured to control the charge-sharing switch unit between the two columns of data lines to be shared to be turned on at the falling edge of the pulse of the gate scan signal.

[0022] This application provides a driving control method that generates a first control signal; generates a gate scan signal based on the first control signal, the first control signal being configured to control the falling edge of the pulse of the gate scan signal; and generates a second control signal based on the first control signal, the second control signal being configured to control the charge sharing switch unit between two columns of data lines to be shared to be turned on at the falling edge of the pulse of the gate scan signal. Thus, the charge sharing time is between the falling edge of the previous row of the gate scan signal and the time point when charging begins during the scanning process of the next row. Within one cycle of the gate scan signal, all time except for the charging time is the charge sharing time. The longer the charge sharing time, the more complete the charge sharing, the longer the passive discharge time, the more power consumption is saved, and the risk of excessive temperature is reduced.

[0023] In one optional implementation, generating the second control signal based on the first control signal includes:

[0024] When the pulse edge of the first control signal is a preset edge, the target register signal is output;

[0025] The second control signal is output according to the target register signal, such that the first rising edge of the second control signal corresponds to the falling edge of the pulse of the first row gate scan signal of each frame.

[0026] Thirdly, an embodiment of this application provides a display panel including multiple rows of gate lines, multiple columns of data lines, an array of pixel units, and the aforementioned driving control circuit. Each pixel unit is electrically connected to at least one row of gate lines and one column of data lines. The gate driving circuit is electrically connected to multiple rows of gate lines. The first clock signal processing unit is electrically connected to a charge sharing switch unit between two columns of data lines to be shared.

[0027] The display panel provided in this application, through the design of multiple rows of gate lines, multiple columns of data lines, pixel units arranged in an array, and the aforementioned driving control circuit, wherein each pixel unit is electrically connected to at least one row of gate lines and one column of data lines, the gate driving circuit is electrically connected to multiple rows of gate lines, and the driving control circuit includes a timing controller, a gate driving circuit, and a first clock signal processing unit. The timing controller is configured to output a first control signal; the gate driving circuit is electrically connected to the timing controller, and is configured to receive the first control signal and generate a gate scan signal according to the first control signal. The first control signal is configured to control the falling edge of the pulse of the gate scan signal; the first clock signal processing unit is electrically connected to... The timing controller, wherein the first clock signal processing unit is configured to receive the first control signal and generate a second control signal based on the first control signal, the second control signal being configured to control the charge sharing switch unit between the two columns of data lines to be shared to be turned on at the falling edge of the gate scan signal pulse, thus the charge sharing time is between the falling edge of the previous row gate scan signal and the time point when charging begins during the next row scan. Within one cycle of the gate scan signal, all time except for the charging time is the charge sharing time. The longer the charge sharing time, the more sufficient the charge sharing. The longer the passive discharge time, the less power the source drive circuit consumes to realize the pixel voltage of the pixel unit, the more power is saved, and the risk of the source drive circuit overheating is reduced. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0030] Figure 2 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0031] Figure 3 This application provides a pixel driving circuit formed by electrically connecting a pixel unit to multiple columns of data lines and multiple rows of gate lines when the pixel unit is in the dot inversion mode.

[0032] Figure 4 This is a schematic diagram of the polarity distribution of a pixel unit in a dot-reversed manner, provided in an embodiment of this application;

[0033] Figure 5This is a circuit framework diagram of a source drive circuit provided in an embodiment of this application;

[0034] Figure 6 This is a circuit framework diagram of a drive control circuit provided in an embodiment of this application;

[0035] Figure 7 This is a timing diagram of charge sharing in the first type of drive control circuit provided in the embodiments of this application;

[0036] Figure 8 This is a first circuit framework diagram formed by the timing controller and source drive circuit provided in the embodiments of this application;

[0037] Figure 9 This is a circuit framework diagram of a timing controller, a first clock signal processing unit, and a charge sharing switch unit provided in an embodiment of this application;

[0038] Figure 10 This is a timing diagram of charge sharing in the second type of drive control circuit provided in the embodiments of this application;

[0039] Figure 11 This is a timing diagram of charge sharing in the third type of drive control circuit provided in the embodiments of this application;

[0040] Figure 12 This is a second circuit framework diagram formed by the timing controller and source drive circuit provided in the embodiments of this application;

[0041] Figure 13 yes Figure 12 The timing diagram of charge sharing in the provided drive control circuit;

[0042] Figure 14 This is a third circuit framework diagram formed by the timing controller and source drive circuit provided in the embodiments of this application;

[0043] Figure 15 This is a flowchart of the drive control method provided in the embodiments of this application;

[0044] Figure 16 yes Figure 15 The flowchart of step S100 in the provided drive control method.

[0045] Label Explanation:

[0046] Display panel 1000; display area 1000a; gate line g; data line s; drive control circuit 100; pixel unit 200; timing controller 10; gate drive circuit 20; source drive circuit 30; frame start signal STV; start signal TP; PCBA circuit board 91; gate scan signal G; first row gate scan signal G1; second row gate scan signal G2; third row gate scan signal G3; source data signal S; first column source data signal S1; second column source data signal S2; flip-chip film 92; charge sharing switch unit sw1; first control signal CK1; level conversion unit 80; first clock signal processing unit 40; second control signal SW1; first register R1; second register R2; third control signal CK2; first wiring 51; second wiring 52; third wiring 53; fourth wiring 54; second clock signal processing unit 60; fourth control signal SW2. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0048] In this document, references to "embodiment" or "implementation" mean that a particular feature, structure, or characteristic described in connection with an embodiment or implementation may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0050] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0051] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0052] During the driving process of an LCD panel, the difference between the positive and negative grayscale voltages is significant. At high frequencies of several hundred MHz, the dynamic power consumption of the source driver circuit is substantial, while charge sharing technology can reduce power consumption. For some high refresh rate display panels, such as gaming monitors and dual-gate display panels, the high refresh rate leads to a shorter horizontal scan time. While sufficient charging is required for normal display, this results in a very short charge sharing time during pixel unit discharge. The charge sharing process during pixel unit discharge occurs with little or no power consumption, effectively reducing power consumption. However, the shortened charge sharing time reduces the power savings, increasing the power consumption required for the source driver circuit to handle the pixel unit discharge process, leading to increased temperature in the source driver circuit, potentially exceeding specifications.

[0053] Please see Figure 1 The display panel 1000 provided in this application increases the power consumption saved by the source drive circuit by increasing the charge sharing time, reduces the power consumption required for the pixel unit discharge process processed by the source drive circuit, and reduces the risk of excessive temperature of the source drive circuit.

[0054] Please see Figure 1 and Figure 2The display panel 1000 includes multiple rows of gate lines g (including g1, g2, g3... in the figure), multiple columns of data lines s (including s1, s2, s3... in the figure), an array of pixel units 200, and a driving control circuit 100 located in the wiring area, all situated in the display area 1000a. Each pixel unit 200 is located within the area enclosed by two adjacent rows of gate lines g and adjacent columns of data lines s. It should be noted that the gate lines g and data lines s are located on different layers; that is, the gate lines g and data lines s do not intersect. Each pixel unit 200 is electrically connected to at least one row of gate lines g and one column of data lines s. Optionally, the gate of the driving switch transistor of each pixel unit 200 is electrically connected to one gate line g. For example, the driving switch transistor can also be called a driving thin-film transistor (TFT). Alternatively, the display panel 1000 is a dual-gate display panel 1000. Specifically, each pixel unit 200 has a dual-gate driving TFT, and each dual-gate driving TFT is electrically connected to two gate lines g. Compared to a single-gate display panel 1000, the horizontal scanning time of the dual-gate display panel 1000 is reduced by half, and the refresh rate is higher.

[0055] Please see Figure 1 The drive control circuit 100 includes a timing controller 10, a gate drive circuit 20, and a source drive circuit 30.

[0056] The timing controller 10 (TCON) is the core circuit for controlling the timing of the display panel 1000. For example, the timing controller 10 sends a frame start signal STV to the gate drive circuit 20 to control the start point of each frame. The timing controller 10 also provides a transmit line start signal TP to the source drive circuit 30 to control the start point of each line display, etc. The timing controller 10 also provides the source drive circuit 30 with the information required for charge sharing, so that after the pixel unit 200 is displayed, charge sharing is achieved between the two columns of data lines s to neutralize part of the voltage and reduce the power consumption required for the pixel unit 200 discharge process processed by the source drive circuit 30.

[0057] Please see Figure 2 The gate drive circuit 20 is electrically connected to multiple rows of gate lines g and is used to provide a gate scan signal G for each row of gate lines g. The gate scan signal G includes a first row gate scan signal G1, a second row gate scan signal G2, and a third row gate scan signal G3.

[0058] Please see Figure 2The source drive circuit 30 is electrically connected to multiple rows of data lines s, and is used to provide a source data signal S for each row of data lines s. The source data signal S includes a first row source data signal S1, a second row source data signal S2, and so on.

[0059] Optional, please refer to Figure 1 The timing controller 10 is mounted on the PCBA circuit board 91, and the source drive circuit 30 is mounted on multiple chip-on-flex (COF) films 92. The multiple COF films 92 are connected between the PCBA circuit board 91 and the display substrate. The gate drive circuits 20 are respectively located on both sides of the display area 1000a of the display substrate.

[0060] The display voltage of the display panel 1000 cannot be fixed at a certain value. Otherwise, over time, the liquid crystal molecules will become polarized and lose their optical rotation properties. To avoid damaging the properties of the liquid crystal molecules, the polarity of the driving voltage needs to be reversed. Therefore, the display voltage within the liquid crystal display needs to be divided into two polarities: positive and negative. When the voltage of the pixel electrode is higher than the voltage of the common electrode, it is called positive polarity. When the voltage of the pixel electrode is lower than the voltage of the common electrode, it is called negative polarity. Regardless of whether it is positive or negative polarity, there is a set of grayscale values ​​with the same brightness. Therefore, when the absolute value of the voltage difference between the upper and lower glass panes is constant, the displayed grayscale values ​​are the same. However, in both cases, the orientation of the liquid crystal molecules is completely opposite, thus avoiding the property damage caused by keeping the orientation of the liquid crystal molecules fixed in one direction. Common polarity reversal methods include frame-by-frame reversal, row-by-row reversal, column-by-column reversal, and dot-by-dot reversal.

[0061] Please see Figure 3 , Figure 3 This is a pixel driving circuit formed by electrically connecting the pixel unit 200 with multiple columns of data lines s and multiple rows of gate lines g, taking the dot-by-dot inversion method as an example. In the dot-by-dot inversion method, the polarity of each pixel unit 200 is different from that of its four adjacent pixel units 200 (upper, lower, left, and right). Figure 3 The "-" in the figure indicates negative polarity, and the data voltage in pixel unit 200 is less than the common voltage. Figure 3 The "+" sign indicates positive polarity, meaning the data voltage in pixel unit 200 is greater than the common voltage.

[0062] Please see Figure 4 , Figure 4 This is a schematic diagram of the polarity distribution of pixel unit 200 in dot-inversion mode. In dot-inversion mode, the polarities of two adjacent columns of data lines s are opposite, that is, the source data signals S output by two adjacent columns of data lines s are voltages higher than the common voltage and voltages lower than the common voltage, respectively. Therefore, charge sharing between two adjacent columns of data lines s can be controlled.

[0063] Optional, please refer to Figure 5 The source drive circuit 30 includes a charge sharing switch unit sw1, which is used to electrically connect to two columns of data lines s to be shared (e.g., ...). Figure 5 Between s1 and s2 in the diagram. In this embodiment, taking the dot inversion method as an example, the two columns of data lines s to be shared are two adjacent columns of data lines s. In other inversion methods, charge sharing can also be achieved between other different data lines s. In summary, the source data signals S on the data lines s to be shared have a certain voltage difference. Furthermore, the source data signals S on the data lines s to be shared are voltages higher than the common voltage and voltages lower than the common voltage, respectively.

[0064] When the charge-sharing switch unit sw1 is configured to be turned on, the two columns of data lines s to be shared are connected, and the source data signals S (data voltage or grayscale voltage) on the two columns of data lines s to be shared are neutralized. Taking a common voltage of 6-7V as an example, the source data signals S on the two columns of data lines s to be shared are a first voltage higher than the common voltage and a second voltage lower than the common voltage, for example, the first voltage is 3V and the second voltage is 9V. After the charge-sharing switch unit sw1 is turned on, the first voltage and the second voltage share charge, resulting in both the first voltage and the second voltage being 6V. Without the additional processing of the source driving circuit 30, the first voltage and the second voltage can be discharged to the common voltage. When the grayscale voltage of the next frame image is reversed, the positive and negative polarity grayscale voltages only need to be charged and discharged from near the common voltage to the target voltage. That is, the voltage only needs to drive half the amplitude, not the full swing, which can reduce power consumption, save the power consumption of the source driving circuit 30, and reduce the risk of overheating of the source driving circuit 30.

[0065] In this embodiment, please refer to Figure 6 The timing controller 10 is configured to output a first control signal CK1. Optionally, the first control signal CK1 is a first clock signal.

[0066] Please see Figure 6 The gate drive circuit 20 is electrically connected to the timing controller 10. Further, the drive control circuit 100 also includes a level conversion unit 80. The level conversion unit 80 is electrically connected between the timing controller 10 and the gate drive circuit 20.

[0067] Typical TFTs require a turn-on voltage of 20V or higher and a turn-off voltage of -5V or lower, while the voltage from the timing controller 10 is typically a logic voltage of 0V or 3.3V. Therefore, the level conversion unit 80 is used to convert the voltage output by the timing controller 10 into the high and low levels required by the gate drive circuit 20. Optionally, the level conversion unit 80 can be located on the PCBA circuit board 91. The gate drive circuit 20 is generally located inside the glass substrate, hence it is called a GOA (Gate On Array) circuit.

[0068] Please see Figure 6 The gate driving circuit 20 is configured to receive the first control signal CK1 and generate gate scan signals G (including G1, G2, and G3) according to the first control signal CK1. G1, G2, and G3 represent the gate scan signals of the first row, the second row, and the third row, respectively.

[0069] Please see Figure 6 and Figure 7 The first control signal CK1 is configured to control the falling edge of the gate scan signal G. Optionally, the rising edge of the first control signal CK1 corresponds to the falling edge of the gate scan signal G. In other words, the gate driving circuit 20 pulls down the level of the output gate scan signal G according to the rising edge of the input first control signal CK1. Alternatively, the falling edge of the first control signal CK1 corresponds to the falling edge of the gate scan signal G. In other words, the gate driving circuit 20 pulls down the level of the output gate scan signal G according to the falling edge of the input first control signal CK1. When the level of the gate scan signal G switches from high to low, the driving TFT of the pixel unit 200 in the row corresponding to the gate scan signal G is turned off.

[0070] Optionally, the gate driving circuit 20 outputs multiple rows of gate scan signals G sequentially according to the first control signal CK1. For example, the second rising edge, the third rising edge, and the fourth rising edge in the first control signal CK1 correspond to the falling edge of the first row of gate scan signals G1, the falling edge of the second row of gate scan signals G2, and the falling edge of the third row of gate scan signals G3, respectively.

[0071] Please see Figure 5 and Figure 8 The drive control circuit 100 also includes a first clock signal processing unit 40, which is electrically connected to the timing controller 10.

[0072] Please see Figures 5-8The first clock signal processing unit 40 is configured to receive the first control signal CK1 and generate a second control signal SW1 based on the first control signal CK1. Optionally, the second control signal SW1 is a switch control signal. In other words, the first clock signal processing unit 40 is used to process the first clock signal into a switch control signal.

[0073] The second control signal SW1 is configured to control the charge-sharing switch unit sw1 between the two columns of data lines s to be shared to turn on at the falling edge of the pulse of the gate scan signal G. As mentioned above, the rising edge of the pulse of the first control signal CK1 corresponds to the falling edge of the pulse of the gate scan signal G, and the rising edge of the pulse of the second control signal SW1 is directly opposite to the rising edge of the pulse of the first control signal CK1 corresponding to the falling edge of the pulse of the gate scan signal G. In other words, when multiple rising edges of the pulse of the first control signal CK1 are corresponding within one cycle of the gate scan signal G, the rising edge of the pulse of each second control signal SW1 is set to be directly opposite to the rising edge of the pulse of the first control signal CK1 corresponding to the falling edge of the pulse of the gate scan signal G. Thus, the charge-sharing time is between the falling edge of the previous row of the gate scan signal G and the start of charging during the scanning process of the next row. Within one cycle of the gate scan signal G, all time except for the charging time is the charge-sharing time. A longer charge-sharing time results in more complete charge sharing, a longer passive discharge time, greater power savings, and a reduced risk of overheating.

[0074] The drive control circuit 100 provided in this application includes a timing controller 10, a gate drive circuit 20, and a first clock signal processing unit 40. The timing controller 10 is configured to output a first control signal CK1. The gate drive circuit 20 is electrically connected to the timing controller 10 and is configured to receive the first control signal CK1 and generate a gate scan signal G based on the first control signal CK1. The first control signal CK1 is configured to control the falling edge of the pulse of the gate scan signal G. The first clock signal processing unit 40 is electrically connected to the timing controller 10. 0 is configured to receive the first control signal CK1 and generate a second control signal SW1 based on the first control signal CK1. The second control signal SW1 is configured to control the charge sharing switch unit sw1 between the two columns of data lines s to be shared to be turned on at the falling edge of the pulse of the gate scan signal G. Thus, the charge sharing time is between the falling edge of the previous row gate scan signal G and the time point when charging begins during the next row scan. Within one cycle of the gate scan signal G, all time except for the charging time is the charge sharing time. The longer the charge sharing time, the more fully the charge sharing is achieved. The longer the passive discharge time, the more power is saved and the risk of overheating is reduced.

[0075] Taking a refresh rate of 500Hz and a resolution of 2560*1440 as an example, the scanning time per line is 1H (time for one line) = 1 / 500 / 1440 ≈ 1.39us. Assuming the actual charging time of the display panel 1000 is 0.5us, the charge sharing time is 1.39us - 0.5us = 0.89us. Compared to the 0.5us charge sharing time indicated by the line start signal, the increased charge sharing time further saves the power consumption required for the discharge process of the pixel unit 200 processed by the source drive circuit 30. For some high refresh rate display panels 1000, such as gaming monitors and dual-gate display panels 1000, the temperature of the source drive circuit 30 can be reduced more significantly. For example, when the charge sharing time is increased from 0.5us to 0.89us, the temperature of the source drive circuit 30 decreases by about 5-10%.

[0076] Lowering the actual temperature of the source drive circuit 30 can prevent abnormalities caused by excessive temperature of the source drive circuit 30 when the ambient temperature is high, or it can reduce the additional costs of cooling measures that need to be taken, such as thermal pads and thermal silicone.

[0077] Please see Figure 6 The timing controller 10 is also configured to output a frame start signal STV and a line start signal TP.

[0078] Please see Figure 6 and Figure 7 The gate driving circuit 20 is further configured to receive the frame start signal STV. The frame start signal STV is used to indicate the start time point of a frame. The gate driving circuit 20 is also configured to sequentially generate a plurality of gate scan signals G under the indication of the frame start signal STV, such as a first row gate scan signal G1, a second row gate scan signal G2, a third row gate scan signal G3, etc.

[0079] Please see Figure 6 and Figure 7 The source drive circuit 30 is further configured to receive the row start signal TP. The row start signal TP is used to indicate the start time point of a row of pixel units 200. The source drive circuit 30 is also configured to output a source data signal S to the pixel unit 200 when the gate scan signal G is high and indicated by the row start signal TP, so that the pixel unit 200 performs one charge and discharge cycle in each pulse period of the row start signal TP. The second rising edge of the row start signal TP is located after the falling edge of the first row gate scan signal G1.

[0080] For details, please refer to Figure 6 and Figure 7The rising edge of the line start signal TP follows the rising edge of the frame start signal STV, meaning that line scanning begins after the start time of a frame. The rising edge of the first line gate scan signal G1 occurs at the rising edge of the line start signal TP. In other words, the rising edge of the gate scan signal G for each line is also the rising edge of the line start signal TP. The line start signal TP is a pulse signal. Within the period of one line start signal TP, which is also the period of one line gate scan signal G, the line gate scan signal G outputs a high level, turning on the driving TFT of the pixel unit 200 in that line. The source driving circuit 30 sends a source data signal S to each pixel unit 200 in that line, charging the pixel unit 200. The starting time for charging the pixel unit 200 is the falling edge of the line start signal TP. After charging is complete, as described above, in the dot-reversal polarity implementation, at the falling edge of the gate scan signal G for that row, the charge-sharing switch unit sw1 in the source drive circuit 30 is turned on, and the adjacent two data lines s are connected, allowing the pixel unit 200 to begin charge sharing and the discharge process to begin. After charge sharing ends, the charge-sharing switch unit sw1 is turned off. At the next falling edge of the row start signal TP, the next row of pixel units 200 begins charging, and so on.

[0081] The following explains t1ˋ, t2ˋ, t3ˋ, and t4ˋ in the timing diagram.

[0082] t1ˋ: The time when the first column source data signal S1 is output from the first data line s.

[0083] t2ˋ: Charge sharing time. In this embodiment, the source drive circuit 30 starts charge sharing when the gate scan signal G falls, thus increasing the charge sharing time. For high refresh rate display panels 1000 and dual-gate architecture display panels 1000, the single-line scan time is relatively short. In this embodiment, the increased charge sharing time can reduce the temperature of the source drive circuit 30.

[0084] t3ˋ: The falling edge of the next row start signal TP, the time when the second row data line s outputs the second column source data signal S2.

[0085] t4ˋ: According to the panel display principle, t4ˋ is the charging time of each row of pixel units 200; the charging time of each row of pixel units 200 is the same.

[0086] The specific architecture of the first clock signal processing unit 40 is illustrated below with reference to the accompanying drawings.

[0087] Optional, please refer to Figure 9The first clock signal processing unit 40 includes a first register R1. The first register R1 is electrically connected to the timing controller 10. It should be noted that the electrical connection described in this application refers to the ability for electrical signals to be conducted between the two, including both direct and indirect electrical connections.

[0088] Please refer to the following: Figures 5-8 The first register R1 is configured to receive the first control signal CK1 and output a target register signal when the pulse edge of the first control signal CK1 is a preset edge. Optionally, the first control signal CK1 is a pulse clock signal.

[0089] Please refer to the following: Figures 5-8 In the embodiment where the rising edge of the first control signal CK1 corresponds to the falling edge of the gate scan signal G, the preset edge is a rising edge. Specifically, the clock control terminal (which is also the register instruction control terminal) of the first register R1 is preset to a rising edge signal instruction. The clock control terminal of the first register R1 receives the first control signal CK1. When the clock control terminal of the first register R1 receives the rising edge signal in the first control signal CK1, it triggers the first register R1 to enable the register function and outputs the target register signal.

[0090] In the embodiment where the falling edge of the first control signal CK1 corresponds to the falling edge of the gate scan signal G, the preset edge is a falling edge. Specifically, the clock control terminal (which is also the register instruction control terminal) of the first register R1 is preset to a falling edge signal instruction. The clock control terminal of the first register R1 receives the first control signal CK1. When the clock control terminal of the first register R1 receives the falling edge signal in the first control signal CK1, it triggers the first register R1 to enable the register function and outputs the target register signal.

[0091] In other words, the first register R1 determines the pulse edge of the input first control signal CK1 after setting a preset edge of the trigger signal. For example, if the preset edge is a rising edge, the first register R1 determines the rising edge of the input first control signal CK1. If the preset edge is a falling edge, the first register R1 determines the falling edge of the input first control signal CK1.

[0092] Optionally, the first register R1 includes two flip-flops, one of which has its clock control terminal set to the rising edge and the other to the falling edge, thereby the first register R1 determines the rising and falling edges of the first control signal CK1.

[0093] Please see Figure 9The first clock signal processing unit 40 includes a second register R2. The second register R2 is electrically connected to the first register R1. The second register R2 is configured to receive the target register signal and output the second control signal SW1 according to the target register signal, such that the first rising edge of the second control signal SW1 corresponds to the falling edge of the pulse of the first row gate scan signal G1 of each frame.

[0094] Optionally, the second register R2 can be a shift register, such as a right shift register.

[0095] Please refer to the following: Figures 5-8 The number of clock signals that do not need to be triggered in the second register R2 is determined based on which rising edge of the first control signal CK1 corresponds to the falling edge of the pulse of the first row gate scan signal G1 in each frame. For example, if the falling edge of the pulse of the first row gate scan signal G1 corresponds to the second rising edge of the first control signal CK1, then the number of clock signals that do not need to be triggered in the second register R2 is determined to be 1. If the falling edge of the pulse of the first row gate scan signal G1 corresponds to the third rising edge of the first control signal CK1, then the number of clock signals that do not need to be triggered in the second register R2 is determined to be 2. This application does not limit the number of clock signals that do not need to be triggered in the second register R2.

[0096] Please refer to the following: Figures 5-8 The second register R2 determines the starting point of the second control signal SW1 by setting the number of clock signals that do not need to be triggered. For example, setting the number of clock signals that do not need to be triggered to 1 makes the second rising edge of the first control signal CK1 the first rising edge of the second control signal SW1. From the final timing waveform diagram, after processing by the second register R2, it is equivalent to shifting the timing waveform to the right by one cycle.

[0097] Please refer to the following: Figures 5-8 The first rising edge of the second control signal SW1 controls the charge sharing switch unit SW1 to turn on, that is, charge sharing begins at the falling edge of the first row gate scan signal G1, i.e., at the end of the first row scan. Thus, the charge sharing time is between the falling edge of the first row gate scan signal G1 and the time point when charging begins during the second row scan. Within one cycle of the gate scan signal G, all time except for the charging time is the charge sharing time. The longer the charge sharing time, the more complete the charge sharing, the longer the passive discharge time, the more power consumption is saved, and the risk of excessive temperature is reduced.

[0098] In one alternative implementation, please refer to Figure 7The first control signal CK1 controls the rising and falling edges of the multi-row gate scan signal G. For example, the first rising edge of the first control signal CK1 controls the rising edge of the first row gate scan signal G1. The second rising edge of the first control signal CK1 controls the falling edge of the first row gate scan signal G1 and the rising edge of the second row gate scan signal G2. The third rising edge of the first control signal CK1 controls the falling edge of the second row gate scan signal G2 and the rising edge of the third row gate scan signal G3. The fourth rising edge of the first control signal CK1 controls the falling edge of the third row gate scan signal G3 and the rising edge of the fourth row gate scan signal G.

[0099] Please see Figure 7 The timing controller 10 outputs a first control signal CK1 to the source drive circuit 30. The first control signal CK1 is the control signal of the falling edge of the gate scan signal G. The rising edge of the first first control signal CK1 in each frame controls the rising edge of the first row gate scan signal G1. The rising edge of the second first control signal CK1 controls the falling edge of the first row gate scan signal G1 and also controls the rising edge of the second row gate scan signal G2, and so on.

[0100] Please see Figure 7 The first control signal CK1 is sent to the source drive circuit 30. The clock control terminal of the first register R1 in the first clock signal processing unit 40 of the source drive circuit 30 is set to the rising edge, and the number of clock signals that do not need to be triggered in the second register R2 is set to 1 (because the falling edge of the first row gate scan signal G1 is the second rising edge of the first control signal CK1).

[0101] Therefore, the first clock signal processing unit 40 generates a second control signal SW1 to control the corresponding charge sharing switch unit SW1.

[0102] In another alternative implementation, please refer to Figure 11 The rising and falling edges of the gate scan signal G for each row are controlled by different control signals.

[0103] Optional, please refer to Figure 10 The timing controller 10 is also configured to output a third control signal CK2. The third control signal CK2 is a second clock signal.

[0104] Please see Figure 10 The gate driving circuit 20 is further configured to receive the third control signal CK2 and generate a gate scan signal G based on the first control signal CK1 and the third control signal CK2. One of the first control signal CK1 and the third control signal CK2 controls the rising edge of the gate scan signal G, and the other controls the falling edge of the gate scan signal G.

[0105] Optional, please refer to Figure 10 The first control signal CK1 is configured to control the falling edge of the gate scan signal G. The third control signal CK2 is configured to control the rising edge of the gate scan signal G. Alternatively, in other embodiments, the third control signal CK2 is configured to control the falling edge of the gate scan signal G. The first control signal CK1 is configured to control the rising edge of the gate scan signal G.

[0106] In this embodiment, please refer to Figure 10 By setting one of the first control signal CK1 and the third control signal CK2 to control the rising edge of the gate scan signal G, and the other to control the falling edge of the gate scan signal G, the time difference between the starting point of the first control signal CK1 and the starting point of the third control signal CK2 is not limited. In this way, the pulse width of the gate scan signal G can be flexibly set. Compared with the implementation method that controls the rising edge and falling edge of the gate scan signal G through the same control signal, this implementation method can flexibly control the pulse width of a gate scan signal G.

[0107] For example, please see Figure 10 The first rising edge of the third control signal CK2 controls the rising edge of the first row gate scan signal G1, and the second rising edge of the first control signal CK1 controls the falling edge of the first row gate scan signal G1. The third rising edge of the third control signal CK2 controls the rising edge of the second row gate scan signal G2, and the fourth rising edge of the first control signal CK1 controls the falling edge of the second row gate scan signal G2. The fifth rising edge of the third control signal CK2 controls the rising edge of the third row gate scan signal G3, and the sixth rising edge of the first control signal CK1 controls the falling edge of the third row gate scan signal G3. In this embodiment, the periods of the first control signal CK1 and the third control signal CK2 are merely examples, and other periods are also possible.

[0108] For example, please see Figure 11 The first rising edge of the third control signal CK2 controls the rising edge of the first row gate scan signal G1, and the first falling edge of the first control signal CK1 controls the falling edge of the first row gate scan signal G1. The third rising edge of the third control signal CK2 controls the rising edge of the second row gate scan signal G2, and the third falling edge of the first control signal CK1 controls the falling edge of the second row gate scan signal G2. The fifth rising edge of the third control signal CK2 controls the rising edge of the third row gate scan signal G3, and the fifth falling edge of the first control signal CK1 controls the falling edge of the third row gate scan signal G3. In this embodiment, the periods of the first control signal CK1 and the third control signal CK2 are merely examples, and other periods are also possible.

[0109] Please see Figure 11 The rising edge of the third control signal CK2 controls the rising edge of all gate scan signals G, and the falling edge of the first control signal CK1 controls the falling edge of all gate scan signals G. The first control signal CK1 output by the timing controller 10 is then sent to the first clock signal processing unit 40 of the source drive circuit 30. The clock control terminal set in the first register R1 of the first clock signal processing unit 40 is the falling edge, and the number of clock signals that do not need to be triggered in the second register R2 is set to 0 (because the falling edge of the first row gate scan signal G1 is the first falling edge of the first control signal CK1).

[0110] Therefore, the first clock signal processing unit 40 generates a second control signal SW1 to control the corresponding charge sharing switch unit SW1.

[0111] Optionally, the first clock signal processing unit 40 can be a separate chip or integrated into the source drive circuit 30.

[0112] Specifically, the source drive circuit 30 includes the first clock signal processing unit 40 and a charge sharing switch unit sw1. The charge sharing switch unit sw1 is electrically connected between the two rows of data lines s to be shared.

[0113] Please see Figure 6 and Figure 8 The drive control circuit 100 further includes a first wiring 51, a second wiring 52, a third wiring 53 and a fourth wiring 54.

[0114] The first wiring 51 is electrically connected to the timing controller 10 and the source drive circuit 30. The first wiring 51 is used to transmit the first control signal CK1 and the frame start signal STV.

[0115] The fourth wiring 54 is electrically connected in sequence to the timing controller 10, the level conversion unit 80, and the gate drive circuit 20. The first wiring 51 and the fourth wiring 54 can be electrically connected to the same output interface of the timing controller 10 to receive the first control signal CK1 and the frame start signal STV.

[0116] In other words, the first control signal CK1 and the frame start signal STV generated by the timing controller 10 are transmitted to the source drive circuit 30 via the first wiring 51 and to the gate drive circuit 20 via the fourth wiring 54.

[0117] The second wiring 52 is electrically connected between the first clock signal processing unit 40 and the charge-sharing switch unit sw1. Optionally, the second wiring 52 is located inside the source drive circuit 30, and the second wiring 52 is used to transmit the second control signal SW1 to the control terminal of the charge-sharing switch unit sw1. The charge-sharing switch unit sw1 includes, but is not limited to, a TFT switch transistor.

[0118] The third wiring 53 electrically connects the timing controller 10 and the source drive circuit 30. The third wiring 53 is used to transmit the row start signal TP generated by the timing controller 10 to the source drive circuit 30. Further, the third wiring 53 is used to transmit image display data generated by the timing controller 10 to the source drive circuit 30. The image display data includes the row start signal TP and the source data signal S.

[0119] Optional, please refer to Figure 12 and Figure 13 The source drive circuit 30 further includes a second clock signal processing unit 60. The second clock signal processing unit 60 is configured to receive the row start signal TP and generate a fourth control signal SW2 based on the row start signal TP. The fourth control signal SW2 is used to control the charge sharing switch unit sw1 between the two columns of data lines s to be shared to turn on after charging and on the rising edge of the pulse of the row start signal TP. The timing of the fourth control signal SW2 can be the same as the timing of the second control signal SW1.

[0120] The fourth control signal SW2 is a switch signal.

[0121] The second clock signal processing unit 60 includes, but is not limited to, a third register (not shown) and a fourth register (not shown). The third register is connected to the timing controller 10 and the fourth register. The third register receives the row start signal TP and determines the rising edge of the row start signal TP. The fourth register is electrically connected to the control terminal of the third register and the charge sharing switch unit sw1. The fourth register determines the starting point of the fourth control signal SW2 by setting the number of clock signals that do not need to be triggered.

[0122] For example, setting the number of clock signals that do not need to be triggered to 1, the second rising edge of the row start signal TP becomes the first rising edge of the fourth control signal SW2, controlling the charge sharing switch unit sw1 between the two columns of data lines s to be shared to be turned on. From the final timing waveform diagram, after processing by the third and fourth registers, the timing waveform of the fourth control signal SW2 is equivalent to the waveform of the row start signal TP shifted to the right by one cycle. In this embodiment, the high-level pulse width of the row start signal TP is the charge sharing time, for example, approximately 0.5µs. In this embodiment, the second rising edge of the row start signal TP triggers charge sharing, and the charge sharing time is shorter than the charge sharing time triggered by the falling edge of the gate scan signal G. This embodiment can be used in low refresh rate display scenarios, such as black screen display scenarios.

[0123] Please see Figure 13 The explanations of t1, t2, t3, and t4 in the timing diagram are as follows:

[0124] t1: The time of the first low level of the row start signal TP is also the time of the source data signal S output; when the row start signal...

[0125] At the falling edge of TP, the first data line s begins to output the time.

[0126] t2: The time of the second high level of the row start signal TP. When the row start signal TP rises for the second time, charge sharing begins in the source drive circuit 30. t2 is also the time of charge sharing in the source drive circuit 30.

[0127] t3: The duration of the next row start signal TP being low; the time when the second row data line s is output when the row start signal TP falls. Where t1 = t3.

[0128] t4: According to the panel display principle, t4 is the charging time of the first, second, and third row pixel units 200; the charging time of each row pixel unit 200 is the same.

[0129] Please see Figure 14 The first clock signal processing unit 40 is configured to operate in a first operating mode and not operate in a second operating mode. The refresh rate in the first operating mode is greater than or equal to a preset refresh rate. Furthermore, the first operating mode is a high refresh rate operating mode, such as in high refresh rate scenarios like games or dual-gate displays.

[0130] Please see Figure 14The second clock signal processing unit 60 is configured to operate in the second operating mode and not operate in the first operating mode. The refresh rate in the second operating mode is lower than a preset refresh rate. Furthermore, the second operating mode is a low refresh rate operating mode, such as in a black screen display scenario.

[0131] Furthermore, the source drive circuit 30 also includes a switching unit (not shown), which is electrically connected to the first clock signal processing unit 40 and the second clock signal processing unit 60, and is used to switch the operation of the first clock signal processing unit 40 or the second clock signal processing unit 60.

[0132] This application does not provide a specific description of the preset refresh rate. For example, the preset refresh rate may include, but is not limited to, 400Hz, 500Hz, etc.

[0133] In other embodiments, the source drive circuit 30 can also be used to drive the control circuit 100 to operate in either the first or second operating mode. For example, if the temperature sensor in the display panel 1000 detects that the temperature of the source drive circuit 30 is greater than a preset temperature, for example, a preset temperature of about 50°C (this data is only an example and is not limited to this data), the switching unit can switch the drive control circuit 100 to operate in the first operating mode.

[0134] Please see Figure 15 This application also provides a drive control method 300. The drive control method 300 can be applied to the drive control circuit 100 described in any of the above embodiments. Therefore, the steps of the drive control method 300 provided in this application can be referred to the relevant description of the drive control circuit 100 above. The method includes, but is not limited to, the following steps.

[0135] S100: Generates the first control signal CK1.

[0136] Please refer to the following for details. Figures 1-14 The timing controller 10 of the drive control circuit 100 is configured to output a first control signal CK1. Optionally, the first control signal CK1 is a first clock signal.

[0137] S200: Please refer to it as well. Figures 1-14 A gate scan signal G is generated based on the first control signal CK1. The first control signal CK1 is configured to control the falling edge of the pulse of the gate scan signal G.

[0138] Specifically, the gate drive circuit 20 of the drive control circuit 100 is configured to receive the first control signal CK1 and generate a gate scan signal G based on the first control signal CK1. The gate drive circuit 20 is electrically connected to the timing controller 10. The first control signal CK1 is configured to control the falling edge of the pulse of the gate scan signal G.

[0139] Optionally, the rising edge of the pulse of the first control signal CK1 corresponds to the falling edge of the pulse of the gate scan signal G. In other words, the gate driving circuit 20 pulls down the level of the output gate scan signal G according to the rising edge of the pulse of the input first control signal CK1. Alternatively, the falling edge of the pulse of the first control signal CK1 corresponds to the falling edge of the pulse of the gate scan signal G. In other words, the gate driving circuit 20 pulls down the level of the output gate scan signal G according to the falling edge of the pulse of the input first control signal CK1. When the level of the gate scan signal G switches from high to low, the driving TFT of the pixel unit 200 in the row corresponding to the gate scan signal G is turned off.

[0140] S300: Please refer to the following as well. Figures 1-14 A second control signal SW1 is generated based on the first control signal CK1. The second control signal SW1 is configured to control the charge-sharing switch unit sw1 between the two columns of data lines s to be shared to turn on on the falling edge of the pulse of the gate scan signal G.

[0141] Specifically, the first clock signal processing unit 40 of the drive control circuit 100 is configured to receive the first control signal CK1 and generate a second control signal SW1 based on the first control signal CK1. Optionally, the second control signal SW1 is a switch control signal. In other words, the first clock signal processing unit 40 is used to process the first clock signal into a switch control signal. The first clock signal processing unit 40 is electrically connected to the timing controller 10.

[0142] This application provides a drive control method 300, which generates a first control signal CK1; generates a gate scan signal G based on the first control signal CK1, the first control signal CK1 being configured to control the falling edge of the pulse of the gate scan signal G; and generates a second control signal SW1 based on the first control signal CK1, the second control signal SW1 being configured to control the charge sharing switch unit sw1 between two columns of data lines s to be shared to be turned on at the falling edge of the pulse of the gate scan signal G. Thus, the charge sharing time is between the falling edge of the previous row of gate scan signal G and the time point when charging begins during the scanning process of the next row. Within one cycle of the gate scan signal G, all time except for the charging time is the charge sharing time. The longer the charge sharing time, the more complete the charge sharing, the longer the passive discharge time, the more power consumption is saved, and the risk of excessive temperature is reduced.

[0143] Please see Figure 16 S300: The step of generating the second control signal SW1 based on the first control signal CK1 specifically includes, but is not limited to, the following steps:

[0144] S310: Please refer to it as well. Figures 1-14 When the pulse edge of the first control signal CK1 is a preset edge, the target register signal is output.

[0145] Specifically, the first register R1 of the first clock signal processing unit 40 is configured to receive the first control signal CK1 and output a target register signal when the pulse edge of the first control signal CK1 is a preset edge. Optionally, the first control signal CK1 is a pulse clock signal. The first register R1 is electrically connected to the timing controller 10.

[0146] In other words, the first register R1 determines the pulse edge of the input first control signal CK1 after setting a preset edge of the trigger signal. For example, if the preset edge is a rising edge, the first register R1 determines the rising edge of the input first control signal CK1. If the preset edge is a falling edge, the first register R1 determines the falling edge of the input first control signal CK1.

[0147] Optionally, the first register R1 includes two flip-flops, one of which has its clock control terminal set to the rising edge and the other to the falling edge, thereby the first register R1 determines the rising and falling edges of the first control signal CK1.

[0148] S320: Please refer to it as well. Figures 1-14 The second control signal SW1 is output according to the target register signal, such that the first rising edge of the second control signal SW1 corresponds to the falling edge of the pulse of the first row gate scan signal G1 of each frame.

[0149] Specifically, the second register R2 of the first clock signal processing unit 40 is configured to receive the target register signal and output the second control signal SW1 according to the target register signal, such that the first rising edge of the second control signal SW1 corresponds to the falling edge of the pulse of the first row gate scan signal G1 of each frame. The second register R2 is an offset register, such as a right shift register.

[0150] The number of clock signals that do not need to be triggered in the second register R2 is determined based on the rising edge of the first control signal CK1 corresponding to the falling edge of the pulse of the first row gate scan signal G1 in each frame. For example, if the falling edge of the pulse of the first row gate scan signal G1 corresponds to the second rising edge of the first control signal CK1, then the number of clock signals that do not need to be triggered in the second register R2 is determined to be 1. If the falling edge of the pulse of the first row gate scan signal G1 corresponds to the third rising edge of the first control signal CK1, then the number of clock signals that do not need to be triggered in the second register R2 is determined to be 2. This application does not limit the number of clock signals that do not need to be triggered in the second register R2.

[0151] The second register R2 determines the starting point of the second control signal SW1 by setting the number of clock signals that do not need to be triggered. For example, setting the number of clock signals that do not need to be triggered to 1 makes the second rising edge of the first control signal CK1 the first rising edge of the second control signal SW1. From the final timing waveform diagram, after processing by the second register R2, it is equivalent to shifting the timing waveform to the right by one cycle.

[0152] The first rising edge of the second control signal SW1 controls the charge sharing switch unit SW1 to turn on, that is, charge sharing begins at the falling edge of the first row gate scan signal G1, i.e., at the end of the first row scan. Thus, the charge sharing time is between the falling edge of the first row gate scan signal G1 and the time point when charging begins during the second row scan. Within one cycle of the gate scan signal G, all time except for the charging time is the charge sharing time. The longer the charge sharing time, the more complete the charge sharing, the longer the passive discharge time, the more power consumption is saved, and the risk of overheating is reduced.

[0153] The above description represents some embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A drive control circuit, characterized in that, include: A timing controller configured to output a first control signal; A gate driving circuit electrically connected to the timing controller, the gate driving circuit being configured to receive the first control signal and generate a gate scan signal according to the first control signal, the first control signal being configured to control the falling edge of the pulse of the gate scan signal; and A first clock signal processing unit is electrically connected to the timing controller. The first clock signal processing unit is configured to receive the first control signal and generate a second control signal according to the first control signal. The second control signal is configured to control the charge sharing switch unit between the two columns of data lines to be shared to be turned on at the falling edge of the pulse of the gate scan signal. The first clock signal processing unit includes a first register, which is electrically connected to the timing controller. The first register is configured to receive the first control signal and output a target register signal when the pulse edge of the first control signal is a preset edge. The first clock signal processing unit includes a second register electrically connected to the first register. The second register is configured to receive the target register signal and output the second control signal according to the target register signal, such that the first rising edge of the second control signal corresponds to the falling edge of the pulse of the first row gate scan signal of each frame.

2. The drive control circuit according to claim 1, characterized in that, The timing controller is further configured to output a third control signal, and the gate drive circuit is further configured to receive the third control signal and generate a gate scan signal based on the first control signal and the third control signal. The third control signal is configured to control the rising edge of the pulse of the gate scan signal.

3. The drive control circuit according to claim 1, characterized in that, The drive control circuit further includes a source drive circuit, which is electrically connected to the timing controller. The source drive circuit includes a first clock signal processing unit and a charge sharing switch unit. The charge sharing switch unit is used to be electrically connected between two columns of data lines to be shared. The drive control circuit further includes a first wiring and a second wiring. The first wiring is electrically connected to the timing controller and the source drive circuit. The first wiring is used to transmit the first control signal. The second wiring is electrically connected between the first clock signal processing unit and the charge sharing switch unit, and the second wiring is used to transmit the second control signal.

4. The drive control circuit according to claim 3, characterized in that, The timing controller is further configured to output a frame start signal and a line start signal; the gate driving circuit is further configured to receive the frame start signal, the source driving circuit is further configured to receive the line start signal, the gate driving circuit is further configured to sequentially generate a plurality of the gate scan signals under the indication of the frame start signal, and the source driving circuit is further configured to output a source data signal to the pixel unit when the gate scan signal is high and under the indication of the line start signal, so that the pixel unit performs one charge and discharge cycle in each pulse period of the line start signal.

5. The drive control circuit according to claim 4, characterized in that, The drive control circuit further includes a third wiring, which is electrically connected to the timing controller and the source drive circuit, and is used to transmit the row start signal; The source drive circuit further includes a second clock signal processing unit, which is configured to receive the row start signal and generate a fourth control signal based on the row start signal. The fourth control signal is used to control the charge sharing switch unit between the two columns of data lines to be shared to be turned on after charging and on the rising edge of the pulse of the row start signal. The first clock signal processing unit is configured to operate in a first working mode and not operate in a second working mode; the second clock signal processing unit is configured to operate in the second working mode and not operate in the first working mode, wherein the refresh rate in the first working mode is greater than or equal to a preset refresh rate, and the refresh rate in the second working mode is less than the preset refresh rate.

6. A drive control method, characterized in that, The method includes: The first control signal is generated; A gate scan signal is generated based on the first control signal, wherein the first control signal is configured to control the falling edge of the pulse of the gate scan signal; and Generate a second control signal based on the first control signal, including: When the pulse edge of the first control signal is a preset edge, the target register signal is output; The second control signal is output according to the target register signal, such that the first rising edge of the second control signal corresponds to the falling edge of the pulse of the first row gate scan signal of each frame; the second control signal is configured to control the charge sharing switch unit between the two columns of data lines to be shared to be turned on at the falling edge of the pulse of the gate scan signal.

7. A display panel, characterized in that, The device includes row gate lines, multiple columns of data lines, an array of pixel units, and a driving control circuit as described in any one of claims 1-5. Each pixel unit is electrically connected to at least one row of gate lines and one column of data lines. The gate driving circuit is electrically connected to multiple rows of gate lines. The first clock signal processing unit is electrically connected to a charge-sharing switch unit between two columns of data lines to be shared.

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