Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes a driving transistor and a storage capacitor, the storage capacitor includes a first plate and a second plate, the second plate is arranged in the same layer as a channel of the driving transistor, the second plate is closer to a substrate than the first plate, a projection of the second plate on the substrate overlaps a projection of a pixel opening on the substrate, and the display substrate satisfies the following relationship: a value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and a value range of S2 / (W*L) is [2.82, 28.85], wherein W is a width of the channel of the driving transistor, L is a length of the channel of the driving transistor, S2 is a facing area of the second plate and the first plate, M1 is a number of the pixel openings of the display substrate, and M2 is an area of the display substrate. The facing area of the plate of the storage capacitor is increased, the capacitance is increased, the holding capacity of the capacitance is improved, the area ratio of the storage capacitor to the pixel opening is improved, the area proportion of the storage capacitor is improved, and the display quality is improved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0002] With the rapid development of technology, display media have become an important part of people's lives. Organic light-emitting diode (OLED) displays, due to their self-emissive nature, possess superior color and image quality. Summary of the Invention

[0003] Embodiments of this disclosure provide a display substrate and a display device to improve display quality and / or reduce power consumption.

[0004] Embodiments of this disclosure provide a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, wherein each sub-pixel includes a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, and the orthographic projection of the storage capacitor on the substrate and the pixel opening on the substrate are intersected. The orthographic projections on the substrate overlap, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, S2 is the area of ​​the second electrode plate and the first electrode plate facing each other, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

[0005] For example, the second plate of the storage capacitor is connected to the first plate of the driving transistor. The storage capacitor also includes a third plate, which is connected to the second plate and is located on opposite sides of the first plate.

[0006] For example, the second electrode plate includes a first plate-shaped portion, which is integral with the channel of the driving transistor.

[0007] For example, the second electrode plate may further include a second plate-shaped portion, the first plate-shaped portion and the second plate-shaped portion being spaced apart from each other, the area of ​​the first plate-shaped portion being larger than the area of ​​the second plate-shaped portion, or both the first plate-shaped portion and the second plate-shaped portion being connected to the channel of the driving transistor.

[0008] For example, the channel of the driving transistor is made of a semiconductor material, and the material of the second electrode is a conductor obtained by doping the same semiconductor material as the channel of the driving transistor.

[0009] For example, the channel of the driving transistor extends along a first direction, the pixel opening has a central axis extending along the first direction, the maximum size of the pixel opening along a second direction is W0, the first direction intersects the second direction, the distance from the channel of the driving transistor to the central axis is D1, and the value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8].

[0010] For example, the display substrate also includes multiple signal lines located on one side of the storage capacitor. The signal lines extend along the second direction. The orthographic projection of the multiple signal lines on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The size of the pixel opening along the first direction is H0, the distance of the farthest edge of the multiple signal lines in the first direction is Hs, and the value range of L / (H0-Hs) is [0.16, 0.61].

[0011] For example, the display substrate further includes a data line, a first gate line, a second gate line, and a first initialization line. The pixel circuit further includes a data writing transistor and a first reset transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second terminal of the data writing transistor, the gate of the data writing transistor is connected to the first gate line, the first terminal of the first reset transistor is connected to the first initialization line, the second terminal of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The plurality of signal lines include the first gate line, the second gate line, and the first initialization line.

[0012] For example, the area of ​​the pixel opening is S0, and the sum of the area of ​​the second electrode and the area of ​​the first electrode facing each other and the area of ​​the channel of the driving transistor is Ss. The relationship between Ss and S0 is: Ss = A*S0 + B, where the value of A is in the range of [0.42, 0.82] and the value of B is in the range of [-2700, -3100].

[0013] For example, the orthographic projection of the pixel opening on the substrate overlaps with the orthographic projection of the third electrode plate on the substrate. The third electrode plate includes a first edge extending along a first direction and a second edge extending along the first direction. The pixel opening includes a first edge extending along the first direction and a second edge extending along the first direction. The first edge of the third electrode plate is closer to the first edge of the pixel opening than the second edge of the third electrode plate, and the second edge of the third electrode plate is closer to the second edge of the pixel opening than the first edge of the third electrode plate. The sub-pixel is full. The following formula applies: △U=|U02-U01|, where U01 is the coordinate distance between the chromaticity coordinate point in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U02 is the coordinate distance between the chromaticity coordinate point in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, and △U is the absolute value of the difference between U02 and U01. The chromaticity coordinate point in the 0-degree viewing angle is the chromaticity coordinate point located at the normal to the center of the display substrate. The first viewing angle and the second viewing angle are located on opposite sides of the normal and have equal angles with the normal, and △U≤0.0020.

[0014] For example, the display substrate further includes a first power line configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending in a first direction and a first power signal line extending in a second direction. The orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The area of ​​the third electrode plate and the first electrode plate facing each other is Sc1, and the area of ​​the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the pixel opening on the substrate is Sc2, where Sc2 / Sc1≥0.9. The width of the first power connection line is W1, and the overlap width between the first power connection line and the pixel opening is W2, where W2 / W1≥0.9.

[0015] For example, the maximum size of the pixel opening along the second direction is W0, the value range of 2×W2 / W0 is [0.71, 0.99], and the value range of voltage Uc / size Lg is [0.32, 0.74]. The voltage Uc is the voltage of the light-emitting element, and the unit of voltage Uc is volts. The size Lg is the length of the diagonal of the display substrate, and the unit of size Lg is inches.

[0016] For example, the pixel opening has a central axis extending along the first direction, the minimum distance from the first power connection line to the central axis is Xd1, the minimum distance from the third electrode plate to the central axis is Xd2, and the value range of Xd1 / Xd2 is [0.9, 1.1].

[0017] For example, the display substrate also includes multiple signal lines located on one side of the storage capacitor. The orthographic projection of the multiple signal lines on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The multiple signal lines are arranged along a first direction and extend along a second direction. The first direction intersects the second direction. The distance between the third electrode plate and the closest signal line is Xd3. The linewidth of the signal line is Xd4. The value range of Xd3 / Xd4 is [0.9, 1.1].

[0018] For example, the display substrate further includes a first power line configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending in a first direction and a first power signal line extending in a second direction. The pixel opening has a central axis extending in the first direction. The minimum distance from the first power connection line to the central axis is Xd1. The minimum distance between the first power connection line and the third electrode plate is Xd0. DP = |Xd1 - Xd0| / 2. The maximum size of the pixel opening in the second direction is W0. The value range of DP / W0 is [0.01, 0.19].

[0019] For example, the display substrate further includes a first signal line extending along a first direction, the sub-pixel including a first sub-pixel and a second sub-pixel adjacent in a second direction, the first signal line being configured to provide a data signal to the pixel circuit of the first sub-pixel, the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel being spaced apart, and the first signal line being located between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel.

[0020] For example, the minimum distances between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel and the first signal line are Xa1 and Xa2, respectively, and the value range of Xa1 / Xa2 is [0.8, 1.2].

[0021] For example, the display substrate further includes a second signal line extending along the first direction, the first signal line and the second signal line being located on opposite sides of the same third electrode plate, and the orthographic projection of the second signal line on the substrate overlapping the orthographic projection of the pixel opening of the second sub-pixel on the substrate.

[0022] For example, the spacing between the third electrode plate and the second signal line is Xa3, and the spacing between the third electrode plate and the first signal line is Xa4. The value range of Xa3 / Xa4 is [0.8, 1.2].

[0023] For example, the display substrate further includes a third signal line that extends along the first direction. The orthographic projection of the third signal line on the substrate overlaps with the orthographic projection of the pixel opening of the first sub-pixel on the substrate. The minimum distance between the third electrode of the first sub-pixel and the third signal line is Xa5, and the minimum distance between the third signal line and the first signal line is Xa6. The value range of Xa5 / Xa6 is [0.8, 1.2].

[0024] For example, the first signal line includes a data line, and at least one of the second and third signal lines includes a first power connection line.

[0025] For example, the display substrate further includes a data line and a first power line. The data line is configured to provide a data voltage to the pixel circuit and extends along a first direction. The first power line is configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending along the first direction and a first power signal line extending along a second direction. The sub-pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the second direction. The orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the pixel opening of the first sub-pixel on the substrate and overlaps with the orthographic projection of the pixel opening of the second sub-pixel on the substrate.

[0026] For example, two data lines are respectively located on both sides of the first power connection line, and the orthographic projections of the two data lines on the substrate overlap with the orthographic projections of the pixel openings of the first sub-pixel and the second sub-pixel on the substrate.

[0027] For example, two data lines are respectively located on both sides of the first power connection line. The orthographic projection of the two data lines on the substrate does not overlap with the orthographic projection of the pixel opening of the first sub-pixel on the substrate, and does not overlap with the orthographic projection of the pixel opening of the second sub-pixel on the substrate.

[0028] For example, the display substrate further includes a first power line configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending along a first direction and a first power signal line extending along a second direction. The orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The maximum dimension of the pixel opening along the second direction is W0. The sub-pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the second direction. The dimension of one of the two first power connection lines in the second direction is Xb1, and the dimension of the other of the two first power connection lines in the second direction is Xb2. The value range of (Xb1+Xb2) / W0 is [0.08, 0.48].

[0029] For example, the display substrate also includes a driving circuit located on one side of the display substrate. Subpixels away from the driving circuit have a first brightness L1; subpixels close to the driving circuit have a second brightness L2, and the value range of |L1-L2| is [1, 9].

[0030] For example, the display substrate also includes two driving circuits, which are located on opposite sides of the display area of ​​the display substrate. The sub-pixel at the central axis of the display substrate has a third brightness L3, and the sub-pixel near one of the two driving circuits has a fourth brightness L4. The extension direction of the central axis of the display substrate is the same as the extension direction of the driving circuit, and the value range of |L3-L4| is [1, 9].

[0031] For example, a first limiting portion is provided between two adjacent pixel openings in a first direction, and a second limiting portion is provided between two adjacent pixel openings in a second direction, wherein the first direction intersects the second direction; the thickness of the first limiting portion is H1, the thickness of the second limiting portion is H2, and H1≠H2.

[0032] For example, H1 is less than H2.

[0033] For example, the display substrate further includes an insulating layer, a barrier dam, and an encapsulation layer. The light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode. The first electrode of the light-emitting element is connected to the pixel circuit through a via penetrating the insulating layer. The encapsulation layer is configured to encapsulate the light-emitting element. The encapsulation layer includes a stack of inorganic encapsulation films and organic encapsulation films. An encapsulating adhesive is provided on the outer side of the encapsulation layer. The insulating layer includes a planarization layer. The planarization layer includes a first planarization portion and a second planarization portion. A groove is provided between the first planarization portion and the second planarization portion. The barrier dam is located outside the display area of ​​the display substrate. The orthographic projection of the barrier dam on the substrate covers the orthographic projection of the groove on the substrate.

[0034] For example, the display substrate further includes a data line, a first gate line, a second gate line, and a first initialization line. The pixel circuit further includes a data writing transistor and a first reset transistor. The first terminal of the data writing transistor is connected to the data line. The gate of the driving transistor is connected to the second terminal of the data writing transistor. The gate of the data writing transistor is connected to the first gate line. The first terminal of the first reset transistor is connected to the first initialization line. The second terminal of the first reset transistor is connected to the gate of the driving transistor. The gate of the first reset transistor is connected to the second gate line. The display substrate has a dummy sub-pixel near its edge. The dummy sub-pixel has a dummy driving transistor and a first dummy reset transistor. The gate of the first dummy reset transistor is connected to the gate of the dummy driving transistor. The first dummy reset transistor is disconnected from the first initialization line.

[0035] For example, the display substrate also includes dummy data lines extending along a first direction, the dummy data lines being insulated from each other by the data lines, and the dummy sub-pixels including at least two adjacent dummy sub-pixels in a second direction, the dummy data lines of the at least two dummy sub-pixels being connected to each other.

[0036] For example, the dummy data line is connected to a constant voltage terminal to be configured to provide a constant voltage.

[0037] For example, the at least two dummy sub-pixels include a first dummy sub-pixel, a second dummy sub-pixel, and a third dummy sub-pixel, and the three dummy data lines of the first dummy sub-pixel, the second dummy sub-pixel, and the third dummy sub-pixel are connected to each other.

[0038] For example, the display substrate further includes a first power line, the pixel circuit further includes a light-emitting control transistor, the first terminal of the light-emitting control transistor is connected to the first power line, the second terminal of the light-emitting control transistor is connected to the second terminal of the driving transistor, the dummy sub-pixel further includes a dummy light-emitting control transistor, the first terminal of the dummy light-emitting control transistor is disconnected from the first power line, and the second terminal of the dummy light-emitting control transistor is connected to the second terminal of the dummy driving transistor.

[0039] For example, the display substrate further includes a pixel defining layer, the pixel defining layer includes a defining portion, the pixel opening is defined by the defining portion, the light-emitting element includes a first electrode and a light-emitting functional layer, the pixel defining layer is configured to expose at least a portion of the first electrode, and the light-emitting functional layer covers the sidewall of the defining portion.

[0040] For example, the light-emitting element further includes a second electrode, the light-emitting functional layer is located between the first electrode and the second electrode, and the second electrode is in contact with the top wall of the defining portion.

[0041] For example, the display substrate further includes an insulating layer, and the first electrode of the light-emitting element is connected to the pixel circuit through a via penetrating the insulating layer. The defining portion includes a first defining portion and a second defining portion, the thickness of the first defining portion is less than the thickness of the second defining portion, and the orthographic projection of the via on the substrate overlaps with the orthographic projection of the first defining portion on the substrate.

[0042] For example, the display substrate also includes a dummy pixel defining layer, which includes a plurality of dummy defining portions. The extending direction of the dummy defining portions is the same as the extending direction of the second defining portions, and the spacing between two adjacent dummy defining portions is greater than the spacing between two adjacent second defining portions.

[0043] For example, the spacing between two adjacent dummy limiting parts is 2 to 20 times the spacing between two adjacent second limiting parts.

[0044] For example, the display substrate further includes a second reset transistor, a second initialization line, and an initialization bus. The initialization bus is located outside the display area of ​​the display substrate. The first terminal of the second reset transistor is connected to the initialization bus through the second initialization line. The second terminal of the second reset transistor is connected to the light-emitting element through the driving transistor. The second reset transistor is connected to a row of sub-pixels. For the same row of sub-pixels, the number of second reset transistors is less than the number of sub-pixels.

[0045] For example, the display substrate also includes a light-emitting control transistor, a first power line, and a first power bus. The first power line is configured to provide a first voltage signal to the pixel circuit. The first power line is connected to the first power bus. The first terminal of the light-emitting control transistor is connected to the first power line. The second terminal of the light-emitting control transistor is connected to the second terminal of the driving transistor. The number of light-emitting control transistors in a row of sub-pixels is less than the number of sub-pixels in that row.

[0046] For example, the number of light-emitting control transistors in a row of sub-pixels is greater than the number of second reset transistors.

[0047] For example, the second electrode plate is disposed on the same layer as the channel of the driving transistor, the second electrode plate is closer to the substrate than the first electrode plate, and the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the pixel opening on the substrate.

[0048] Embodiments of this disclosure also provide a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor, and the second plate of the storage capacitor being connected to the first plate of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element; each sub-pixel includes a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the substrate overlapping the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlapping the orthographic projection of the storage capacitor on the substrate. The pixel openings overlap on the substrate. The second electrode plate is disposed on the same layer as the channel of the driving transistor. The second electrode plate is closer to the substrate than the first electrode plate. The display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, S2 is the area of ​​the second electrode plate and the first electrode plate facing each other, M1 is the number of pixel openings of the display substrate, M2 is the area of ​​the display substrate, Uc is the voltage across the light-emitting element, and P is the power consumption of the sub-pixel.

[0049] Embodiments of this disclosure also provide a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a driving transistor and a storage capacitor, the storage capacitor including a first electrode and a second electrode, the first electrode of the storage capacitor being connected to the gate of the driving transistor, and the second electrode of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, each sub-pixel including a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the substrate overlapping the orthographic projection of the pixel opening on the substrate, and the channel of the driving transistor on the substrate. The orthographic projection of the pixel opening overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor. The second electrode plate is closer to the substrate than the first electrode plate. A first limiting portion is disposed between two adjacent pixel openings in a first direction, and a second limiting portion is disposed between two adjacent pixel openings in a second direction. The first direction intersects the second direction. The thickness of the first limiting portion is H1, and the thickness of the second limiting portion is H2, where H1 ≠ H2. The display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode plate and the first electrode plate facing each other.

[0050] Embodiments of this disclosure also provide a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a driving transistor and a storage capacitor, the storage capacitor including a first electrode and a second electrode, the first electrode of the storage capacitor being connected to the gate of the driving transistor, and the second electrode of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, wherein each sub-pixel includes a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, the second electrode is disposed in the same layer as the channel of the driving transistor, the second electrode is closer to the substrate than the first electrode, and the display substrate further includes an insulating layer. The display substrate comprises a barrier dam and an encapsulation layer. The light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer located between the first and second electrodes. The first electrode of the light-emitting element is connected to the pixel circuit through a via penetrating the insulating layer. The encapsulation layer is configured to encapsulate the light-emitting element and includes a stack of inorganic and organic encapsulation films. An encapsulating adhesive is provided on the outer side of the encapsulation layer. The insulating layer includes a planarization layer, which includes a first planar portion and a second planar portion. A groove is provided between the first and second planar portions. The barrier dam is located outside the display area of ​​the display substrate. The orthographic projection of the barrier dam on the substrate covers the orthographic projection of the groove on the substrate. The display substrate satisfies the following relationship: S2 / (W*L) ranges from [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode and the first electrode facing each other.

[0051] Embodiments of this disclosure also provide a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor, and the second plate of the storage capacitor being connected to the first plate of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, each sub-pixel including a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, and the storage capacitor being disposed on the substrate. The orthographic projection on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, the second electrode plate is disposed in the same layer as the channel of the driving transistor, the second electrode plate is closer to the substrate than the first electrode plate, and the display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode plate and the first electrode plate facing each other.

[0052] Embodiments of this disclosure also provide a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a driving transistor and a storage capacitor, the storage capacitor including a first electrode plate and a second electrode plate, the first electrode plate of the storage capacitor being connected to the gate of the driving transistor, and the second electrode plate of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, each sub-pixel including a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the substrate overlapping the orthographic projection of the pixel opening on the substrate, the orthographic projection of the channel of the driving transistor on the substrate overlapping the orthographic projection of the pixel opening on the substrate, the second electrode plate being disposed in the same layer as the channel of the driving transistor, the second electrode plate being closer to the substrate than the first electrode plate, the display substrate further including data lines, a first gate line, a second gate line, and a first initialization line. The pixel circuit further includes a data writing transistor and a first reset transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second terminal of the data writing transistor, and the gate of the data writing transistor is connected to the first gate line. The first terminal of the first reset transistor is connected to the first initialization line, the second terminal of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The display substrate has a dummy sub-pixel near its edge. The dummy sub-pixel has a dummy driving transistor and a first dummy reset transistor. The gate of the first dummy reset transistor is connected to the gate of the dummy driving transistor, and the first dummy reset transistor is disconnected from the first initialization line. The display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second plate and the first plate facing each other.

[0053] Embodiments of this disclosure also provide a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate; each sub-pixel includes: a pixel circuit including a driving transistor and a storage capacitor, the storage capacitor including a first electrode and a second electrode, the first electrode of the storage capacitor being connected to the gate of the driving transistor, and the second electrode of the storage capacitor being connected to the first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, each sub-pixel including a pixel opening, the pixel opening being configured to define a light-emitting area of ​​the sub-pixel, the orthographic projection of the storage capacitor on the substrate overlapping the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlapping the orthographic projection of the storage capacitor on the substrate. The pixel openings overlap in orthographic projection on the substrate. The second electrode plate is disposed in the same layer as the channel of the driving transistor. The second electrode plate is closer to the substrate than the first electrode plate. The display substrate further includes a pixel defining layer, wherein the pixel defining layer includes a defining portion, and the pixel opening is defined by the defining portion. The light-emitting element includes a first electrode and a light-emitting functional layer. The pixel defining layer is configured to expose at least a portion of the first electrode. The light-emitting functional layer covers the sidewall of the defining portion. The display substrate satisfies the following relationship: the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode plate and the first electrode plate facing each other.

[0054] For example, any of the above-mentioned display substrates that satisfies the value range of S2 / (W*L) as [2.82, 28.85] can also satisfy the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], where M1 is the number of pixel openings of the display substrate and M2 is the area of ​​the display substrate.

[0055] For example, for any of the above-mentioned display substrates where the value range of S2 / (W*L) is [2.82, 28.85] and / or the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], the following relationship can also be satisfied: P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], Uc is the voltage across the light-emitting element, and P is the power consumption of the sub-pixel.

[0056] Embodiments of this disclosure also provide a display device including any of the above-described display substrates. Attached Figure Description

[0057] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0058] Figure 1 This is a schematic diagram of the pixel arrangement of a display substrate.

[0059] Figure 2 This is a schematic diagram of a pixel circuit in a display substrate driving a light-emitting element to emit light, provided as an embodiment of the present disclosure.

[0060] Figure 3 A circuit diagram of a display substrate is provided for another embodiment of this disclosure.

[0061] Figure 4 A circuit diagram of a display substrate is provided for another embodiment of this disclosure.

[0062] Figure 5 This is a layout diagram of a display substrate provided in one embodiment of the present disclosure.

[0063] Figure 6 for Figure 5 A sectional view along line A1-A2.

[0064] Figures 7A to 7G for Figure 5 A plan view of a single layer of the display substrate.

[0065] Figures 8A to 8E for Figure 5 A plan view of a portion of the stacked layers of the display substrate.

[0066] Figure 8F for Figure 5 A schematic diagram showing the width and length of the channel of the driving transistor in the display substrate.

[0067] Figure 9 This is a layout diagram of a display substrate provided in one embodiment of the present disclosure.

[0068] Figure 10 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure.

[0069] Figure 11 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure.

[0070] Figure 12 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure.

[0071] Figure 13 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure.

[0072] Figure 14 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure.

[0073] Figure 15 for Figure 14 A partial stacking diagram of the film layers.

[0074] Figure 16 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure.

[0075] Figure 17 for Figure 16 A partial stacking diagram of the film layers.

[0076] Figure 18 This is a stacked diagram of a portion of the film layers of a display substrate provided in an embodiment of this disclosure.

[0077] Figure 19 This is a stacked diagram of a portion of the film layers of a display substrate provided in an embodiment of this disclosure.

[0078] Figure 20 This is a stacked diagram of a portion of the film layers of a display substrate provided in an embodiment of this disclosure.

[0079] Figure 21 This is a schematic diagram of the center pixel of a display substrate provided for an embodiment of the present disclosure.

[0080] Figure 22 for Figure 21 A cross-sectional view along line B1-B2.

[0081] Figure 23 This is a schematic diagram showing the coordinate distance between chromaticity coordinate points on a display substrate from two different viewing angles.

[0082] Figure 24 This is a layout diagram of a display substrate provided in one embodiment of the present disclosure.

[0083] Figure 25 This is a plan view of a display substrate provided in one embodiment of the present disclosure.

[0084] Figure 26 This is a plan view of a display substrate provided in one embodiment of the present disclosure.

[0085] Figure 27 This is a plan view of a display substrate provided in one embodiment of the present disclosure.

[0086] Figure 28 This is a plan view of a display substrate provided in one embodiment of the present disclosure.

[0087] Figure 29This is a layout diagram of a display substrate provided in one embodiment of the present disclosure.

[0088] Figure 30 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0089] Figure 31 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0090] Figure 32 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0091] Figure 33A A plan view of a pixel-defining layer in a display substrate provided for an embodiment of this disclosure.

[0092] Figure 33B A plan view of a pixel-defining layer in a display substrate provided for an embodiment of this disclosure.

[0093] Figure 34 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0094] Figure 35 This is an electron microscope image of a display substrate provided in an embodiment of this disclosure.

[0095] Figure 36 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0096] Figure 37 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0097] Figure 38 This is a circuit diagram of a dummy sub-pixel in a display substrate provided in one embodiment of the present disclosure.

[0098] Figure 39 This is a layout diagram of a dummy pixel circuit in a display substrate provided in one embodiment of the present disclosure.

[0099] Figure 40 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0100] Figure 41A This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0101] Figure 41B This is a schematic diagram of a display substrate provided for another embodiment of the present disclosure.

[0102] Figure 42 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0103] Figure 43 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0104] Figure 44 This is a circuit diagram of a display substrate provided in one embodiment of the present disclosure.

[0105] Figure 45 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure.

[0106] Figure 46 This is a schematic diagram of a brightness test of a display substrate provided in an embodiment of the present disclosure. Detailed Implementation

[0107] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0108] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0109] In typical organic light-emitting diode (OLED) displays, the organic light-emitting layer requires a vapor deposition process, which has stringent process requirements and is difficult to scale up to a large area.

[0110] Using inkjet printing to fabricate the OLED light-emitting material layer is the best way to achieve low-cost OLED production and enable OLED displays to compete in the mid-to-high-end market. Inkjet printing is a highly efficient process; compared to vapor deposition, it wastes less material and is extremely fast.

[0111] In inkjet printing to form the light-emitting functional layer of an organic light-emitting diode (OLED), a solvent is primarily used to dissolve the organic material to form a solution (ink). This solution (ink) is then directly sprayed onto the surface of a substrate to form the light-emitting functional layer for sub-pixels, such as red (R), green (G), and blue (B). Inkjet printing OLED technology offers significant advantages over vapor deposition technology in terms of manufacturing process, yield, and cost. For example, the light-emitting functional layer comprises multiple film layers, including a light-emitting layer (light-emitting material layer). The light-emitting functional layer may also include at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The organic light-emitting functional layer can be selected as needed. At least one film layer in the light-emitting functional layer can be fabricated using an inkjet printing process.

[0112] Due to the large molecular weight of polymers, solution processing is mainly used to form films, such as spin coating or printing. Inkjet printing technology is the best method for preparing luminescent polymer solutions. In recent years, much effort has been made to improve the pixel resolution, film uniformity, and lifespan of displays, and research on inkjet printing to form optoelectronic materials has become increasingly active. For example, the hole transport layer, hole injection layer, and luminescent layer of a display can all be prepared using inkjet printing technology, laying the foundation for the use of a fully printed method to manufacture displays.

[0113] When fabricating the emissive layer using inkjet printing, the flatness of the emissive layer is critical. The flatter the emissive layer in each sub-pixel, the more color shift can be reduced or avoided, resulting in better display performance. A flat emissive layer can be achieved by adjusting the structure of the display substrate. The display substrate provided in the embodiments of this disclosure can solve the color shift problem at 45-degree and 60-degree viewing angles of the entire display substrate.

[0114] Figure 1 This is a schematic diagram of the pixel arrangement of a display substrate. (For example...) Figure 1 As shown, the display substrate includes a plurality of sub-pixels 100 located on a substrate, and the plurality of sub-pixels 100 are arranged in an array. Figure 1 As shown, multiple sub-pixels 100 are arranged in an array along the first direction Y and the second direction X. Embodiments of this disclosure use... Figure 1 The example shown is of multiple sub-pixels 100 arranged in an array, but the arrangement of the multiple sub-pixels 100 is not limited to this. Figure 1 As shown.

[0115] like Figure 1 As shown, the display substrate includes multiple pixels PX, and each pixel PX includes multiple sub-pixels 100. Figure 1 As shown, the plurality of sub-pixels 100 includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. Figure 1As shown, each pixel PX includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. The first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 emit different colors. Sub-pixels in the same column emit the same color light, and multiple pixels PX are arranged sequentially in the same row. This embodiment uses the first direction Y as the column direction and the second direction X as the row direction for illustration. In other embodiments, the first direction Y can be the row direction, and the second direction X can be the column direction.

[0116] The embodiments disclosed herein are illustrated using the example of a first sub-pixel 101 being a red sub-pixel, a second sub-pixel 102 being a green sub-pixel, and a third sub-pixel 103 being a blue sub-pixel.

[0117] like Figure 1 As shown, the substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. Figure 1 The following explanation uses the example of the surrounding area R02 surrounding the display area R01.

[0118] Figure 2 This is a schematic diagram of a pixel circuit in a display substrate driving a light-emitting element to emit light, provided as an embodiment of the present disclosure. Figure 3 A circuit diagram of a display substrate is provided for another embodiment of this disclosure. Figure 4 A circuit diagram of a display substrate is provided for another embodiment of this disclosure.

[0119] like Figures 2 to 4 As shown, each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is electrically connected to the light-emitting element 100b, and the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. The light-emitting element 100b includes a light-emitting area. Figure 1 The pixel arrangement shown refers to the setting position of the light-emitting area of ​​the light-emitting element 100b in the sub-pixel 100.

[0120] Figure 2 and Figure 3 It includes the pixel circuitry and light-emitting elements within a sub-pixel. Figure 4 Three sub-pixels are shown. Figure 4 The three sub-pixels are located in a row.

[0121] For example, such as Figures 2 to 4As shown, in sub-pixel 100, pixel circuit 100a includes a data writing transistor T1, a reset transistor T2, a driving transistor T3, and a storage capacitor Cst. Light-emitting element 100b is connected to driving transistor T3. Reset transistor T2 is configured to reset the gate T3g of driving transistor T3. Figures 2 to 4 As shown, the storage capacitor Cst includes a first terminal C1 and a second terminal C2.

[0122] For example, such as Figures 2 to 4 As shown, the display substrate includes gate line G1, gate line G2, data line DT, first power line PL1, second power line PL2, initialization line INT1, etc. Gate line G2 can also be called a reset control signal line. For example, the first power line PL1 is configured to provide a constant first voltage signal VDD to the sub-pixel 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the sub-pixel 100, wherein the first voltage signal VDD is greater than the second voltage signal VSS. Gate line G1 is configured to provide a scan signal SCAN to the sub-pixel 100, gate line G2 is configured to provide a reset control signal RESET1 to the sub-pixel 100, and data line DT is configured to provide a data signal (data voltage) DATA to the sub-pixel 100. Initialization line INT1 is configured to provide an initialization signal Vinit1 to the sub-pixel 100.

[0123] like Figures 2 to 4 As shown, the driving transistor T3 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.

[0124] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED), which emits red light, green light, blue light, or white light under the drive of its corresponding pixel circuit 100a.

[0125] For example, such as Figures 2 to 4 As shown, the first electrode E1 of the light-emitting element 100b is connected to the first electrode T3a of the driving transistor T3, the second electrode E2 of the light-emitting element 100b is connected to the second power supply line PL2, the second electrode T3b of the driving transistor T3 is connected to the first power supply line PL1, the gate T3g of the driving transistor T3 is connected to the second electrode T1b of the data writing transistor T1, the first electrode T1a of the data writing transistor T1 is connected to the data line DT, and the gate T1g of the data writing transistor T1 is connected to the gate line G1.

[0126] For example, such as Figures 2 to 4As shown, the gate T3g of the driving transistor T3 is connected to the first terminal C1 of the storage capacitor Cst, and the second terminal C2 of the storage capacitor Cst is connected to the first terminal T3a of the driving transistor T3. The first terminal C1 of the storage capacitor Cst is also connected to the second terminal T1b of the data writing transistor T1.

[0127] For example, such as Figures 2 to 4 As shown, the first terminal T2a of the reset transistor T2 is connected to the initialization line INT1, the second terminal T2b of the reset transistor T2 is connected to the gate T3g of the driving transistor T3, and the gate T2g of the reset transistor T2 is connected to the gate line G2. The first terminal C1 of the storage capacitor Cst is also connected to the second terminal T2b of the reset transistor T2.

[0128] For example, such as Figures 2 to 4 As shown, the gate T3g of the driving transistor T3, the first terminal C1 of the storage capacitor Cst, the second terminal T1b of the data writing transistor T1, and the second terminal T2b of the reset transistor T2 are connected to each other and are all connected to node N1 at the same potential.

[0129] For example, such as Figures 2 to 4 As shown, the second terminal C2 of the storage capacitor Cst, the first electrode E1 of the light-emitting element 100b, and the first terminal T3a of the driving transistor T3 are connected to each other and are all connected to node N2 at the same potential.

[0130] For example, such as Figure 3 and Figure 4 As shown, the display substrate also includes a reset transistor T4, which is configured to reset the first electrode E1 of the light-emitting element 100b.

[0131] For example, such as Figure 3 and Figure 4 As shown, the display substrate also includes gate line G4, which can also be referred to as a reset control signal line. Gate line G4 is configured to provide a reset control signal RESET2 to the reset transistor T4.

[0132] For example, such as Figure 3 and Figure 4 As shown, the display substrate also includes an initialization line INT2, which is configured to provide an initialization signal Vinit2 to the reset transistor T4.

[0133] For example, such as Figure 3 and Figure 4 As shown, the first electrode T4a of the reset transistor T4 is connected to the initialization line INT2, the second electrode T4b of the reset transistor T4 is connected to the first electrode E1 of the light-emitting element 100b, and the gate T4g of the reset transistor T4 is connected to the gate line G4.

[0134] For example, such as Figure 3 and Figure 4 As shown, the second terminal T4b of the reset transistor T4 is connected to the first electrode E1 of the light-emitting element 100b through the driving transistor T3, the first terminal T3a of the driving transistor T3 is connected to the first electrode E1 of the light-emitting element 100b, and the second terminal T3b of the driving transistor T3 is connected to the second terminal T4b of the reset transistor T4.

[0135] For example, initialization signals Vinit1 and Vinit2 are constant voltage signals, whose magnitudes may be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, initialization signals Vinit1 and Vinit2 may both be less than or equal to the second voltage signal VSS.

[0136] For example, in some embodiments of this disclosure, initialization line INT1 and initialization line INT2 are connected and both are configured to provide the same initialization signal, i.e., initialization signal Vinit1 and initialization signal Vinit2 are equal, but this is not a limitation. In other embodiments, initialization line INT1 and initialization line INT2 are insulated from each other to provide different initialization signals.

[0137] For example, such as Figure 2 As shown, the second terminal T3b of the driving transistor T3 is directly connected to the first power supply line PL1. Figure 3 and Figure 4 As shown, the display substrate also includes a gate line G5 and a light-emitting control transistor T5. The gate line G5 is configured to provide a light-emitting control signal EM to the light-emitting control transistor T5. The second terminal T3b of the driving transistor T3 is connected to the first power supply line PL1 through the light-emitting control transistor T5.

[0138] For example, such as Figure 3 and Figure 4 As shown, the first terminal T5a of the light-emitting control transistor T5 is connected to the first power supply line PL1, the second terminal T5b of the light-emitting control transistor T5 is connected to the second terminal T3b of the driving transistor T3, and the gate T5g of the light-emitting control transistor T5 is connected to the gate line G5.

[0139] For example, such as Figure 3 and Figure 4 As shown, the second terminal T5b of the light-emitting control transistor T5, the second terminal T4b of the reset transistor T4, and the second terminal T3b of the driving transistor T3 are connected to each other and are all connected to node N3 at the same potential.

[0140] For example, such as Figure 4As shown, the multiple sub-pixels 100 include a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are arranged sequentially along the second direction X. Of course, the sub-pixels within a pixel can also adopt other arrangements.

[0141] For example, such as Figure 4 As shown, the driving transistor T3 is a dual-gate transistor, including sub-transistors T31 and T32. Figure 4 As shown, sub-transistor T31 and sub-transistor T32 are connected in series. Figure 4 Taking the driving transistor T3 as an example of a dual-gate transistor, in other embodiments, other transistors besides the driving transistor T3 can also be configured as dual-gate transistors. That is, each transistor in the pixel circuit can be configured as a single-gate transistor or a dual-gate transistor as needed.

[0142] For example, such as Figure 3 and Figure 4 As shown, the display substrate includes a reset signal transmission line INI, and the second terminal T4b of the reset transistor T4 is connected to the second terminal T3b (node ​​N3) of the driving transistor through the reset signal transmission line INI.

[0143] Figure 5 This is a layout diagram of a display substrate provided in one embodiment of the present disclosure. Figure 6 for Figure 5 A sectional view along line A1-A2. Figures 7A to 7G for Figure 5 A plan view of a single layer of the display substrate. Figures 8A to 8E for Figure 5 A plan view of a portion of the stacked layers of the display substrate. Figure 8F for Figure 5 A schematic diagram showing the width and length of the channel of the driving transistor in the display substrate.

[0144] For example, such as Figure 6 As shown, the display substrate includes a substrate BS, a barrier layer BR located on the substrate BS, and a buffer layer BF. Figure 6 As shown, an active layer LY0 and a gate insulating layer GI are disposed on the buffer layer BF. A first conductive pattern layer LY1 is disposed on the gate insulating layer GI. An interlayer insulating layer ILD is disposed on the first conductive pattern layer LY1. A second conductive pattern layer LY2 is disposed on the interlayer insulating layer ILD. An insulating layer ISL is disposed on the second conductive pattern layer LY2. A first electrode layer LY3 is disposed on the insulating layer ISL. Figure 5 and Figure 6 The first terminal C1 and the second terminal C2 of the storage capacitor Cst are shown. The first terminal C1 includes a first plate Ca (e.g., ... Figure 7B As shown), the second end C2 includes a second electrode plate Cb (as shown). Figure 7A (as shown) and the third plate Cc (as shown) Figure 7D (As shown).

[0145] For example, such as Figure 6 As shown, the first conductive pattern layer LY1 is closer to the substrate BS than the second conductive pattern layer LY2.

[0146] For example, such as Figure 5 and Figure 6 As shown, a display substrate provided according to an embodiment of the present disclosure includes: a substrate BS and sub-pixels 100 disposed on the substrate BS. Multiple sub-pixels 100 may be provided.

[0147] For example, such as Figure 5 and Figure 6 As shown, the display substrate also includes a pixel defining layer (PDL), and the sub-pixel 100 includes a pixel opening (P0) configured to expose at least a portion of the first electrode (E1), and the pixel opening (P0) is configured to define a light-emitting area of ​​the sub-pixel 100. For example, as Figure 6 As shown, the slope angle of the portion of the pixel opening P0 in the pixel limiting layer PDL is 40-65 degrees.

[0148] For example, such as Figure 5 and Figure 6 As shown, the sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a storage capacitor Cst, a second electrode Cb that is closer to the substrate BS than the first electrode Ca, and a first electrode Ca that is closer to the substrate BS than the third electrode Cc. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The pixel circuit 100a is configured to drive the light-emitting element 100b.

[0149] Figure 6 Taking the example where all layers of the light-emitting functional layer FL are formed by inkjet printing, that is, each layer of the light-emitting functional layer FL is disposed in the pixel opening P0. However, in other embodiments, some layers of the light-emitting functional layer FL may be formed by inkjet printing, and some layers may be formed by vapor deposition. The layers formed by vapor deposition can be common layers. An example of this can be found in [reference needed]. Figure 45 .

[0150] In some of the accompanying drawings of embodiments of this disclosure, a plan view shows a first direction Y and a second direction X, and a cross-sectional view shows a third direction Z. Both the first direction Y and the second direction X are parallel to the main surface of the substrate BS. The third direction Z is perpendicular to the main surface of the substrate BS. For example, the first direction Y and the second direction X intersect. Embodiments of this disclosure are described with the first direction Y and the second direction X being perpendicular as an example. Figure 6 As shown, the main surface of the substrate BS is the surface used to fabricate various components. For example... Figure 6 As shown, the upper surface of the substrate BS is the main surface of the substrate BS.

[0151] For example, such as Figure 5 , Figure 7B ,as well as Figure 7D As shown, the first power line PL1 includes a first power signal line PL11 extending along the second direction X and a first power connection line PL12 extending along the first direction Y. The first power signal line PL11 and the first power connection line PL12 are connected.

[0152] For example, such as Figure 5 , Figure 7B ,as well as Figure 7D As shown, the data line DT extends along the first direction Y. The data line DT is formed in segments. The data line DT includes a first part DTa, a second part DTb and a third part DTc. The first part DTa and the third part DTc are connected through the second part DTb. The first part DTa and the third part DTc are located in the first conductive pattern layer LY1, and the second part DTb is located in the second conductive pattern layer LY2.

[0153] In embodiments of this disclosure, elements located in the second conductive pattern layer LY2 can be connected to elements located in the first conductive pattern layer LY1 and elements located in the active layer LY0 through vias, and elements located in the first conductive pattern layer LY1 and elements located in the active layer LY0 can be connected through elements located in the second conductive pattern layer LY2.

[0154] For example, the insulating layer through which the via penetrates can be determined based on the condition of the insulating layer between the two conductive pattern layers connected by the via.

[0155] like Figure 5 , Figure 7B ,as well as Figure 7DAs shown, the display substrate provided according to some embodiments of this disclosure uses an active layer LY0, a first conductive pattern layer LY1, and a second conductive pattern layer LY2 to form the pixel circuit 100a, thereby simplifying the manufacturing process and reducing the thickness of the display substrate. The initialization line INT1 and / or the first power line PL1 can be referred to as the conductive structure 40. The conductive structure 40 includes a signal transmission line 411 and a signal connection line 412. The conductive structure 40 is configured to provide a voltage signal to the sub-pixel 100. The signal transmission line 411 extends along a second direction X, and the signal connection line 412 extends along a first direction Y. The signal connection line 412 is electrically connected to the signal transmission line 411.

[0156] like Figure 5 As shown, the conductive structure 40 includes a conductive structure 400 and a conductive structure 401. For example... Figure 5 As shown, the first power line PL1 can be called conductive structure 400, and the initialization line INT1 can be called conductive structure 401.

[0157] For example, such as Figure 5 As shown, the conductive structure 40 adopts a mesh structure, which includes a portion extending along the first direction Y (i.e., signal connection line 412) and a portion extending along the second direction X (i.e., signal transmission line 411).

[0158] For example, such as Figure 5 , Figure 7B ,as well as Figure 7D As shown, the first power line PL1 of the pixel circuit 100a is formed using two conductive pattern layers. (As...) Figure 5 , Figure 7B ,as well as Figure 7D As shown, the portion of the first power line PL1 extending along the first direction Y is evenly segmented. For example... Figure 5 and Figure 7D As shown, the portion of the first power line PL1 extending along the second direction X is all located in the second conductive pattern layer LY2.

[0159] For example, such as Figure 5 , Figure 7B ,as well as Figure 7D As shown, the signal connection line 412 includes a first portion 412a, a second portion 412b, and a third portion 412c. The first portion 412a and the third portion 412c are connected through the second portion 412b. The first portion 412a and the third portion 412c are located in the first conductive pattern layer LY1, and the second portion 412b is located in the second conductive pattern layer LY2. The signal connection line 412 also includes a first power connection line PL12.

[0160] For example, such as Figure 5As shown, the first part PLA and the second part PLb of the first power connection line PL12 are connected through via Va, and the second part PLb and the third part PLc of the first power connection line PL12 are connected through via Vb.

[0161] For example, such as Figure 5 As shown, the first power signal line PL11 and the first power connection line PL12 are connected through via V0.

[0162] For example, such as Figure 5 As shown, the first part DTa and the second part DTb of the data line DT are connected through via Vc, and the second part DTb and the third part DTc of the data line DT are connected through via Vd.

[0163] Figure 7A The active layer LY0 is shown. The active layer LY0 includes, but is not limited to, polysilicon.

[0164] Figure 7B The first conductive pattern layer LY1 is shown. (See diagram.) Figure 7B As shown, the first conductive pattern layer LY1 includes a first end C1 (first electrode Ca), connecting electrodes CEa, CEb, CEc, CEd, CEe, a first part DTa of the data line DT, a third part DTc of the data line DT, a first part PLA of the first power connection line PL12, and a third part PLC of the first power connection line PL12.

[0165] Figure 7C The interlayer insulating layer (ILD) is shown, illustrated by vias within the ILD. Figure 7C Vias V1 to V13, vias Va to Vd, and via V0 are shown.

[0166] Figure 7D The second conductive patterned layer LY2 is shown. (See figure) Figure 7D As shown, the second conductive pattern layer LY2 includes a third electrode Cc at the second end C2, a connecting electrode CEf, gate lines G1, G2, and G5, a reset signal transmission line INI, an initialization signal line INT11, and a first power signal line PL11.

[0167] Figure 7E The insulating layer ISL is shown, with vias in the insulating layer ISL as an example. Figure 7E The via VH is shown.

[0168] Figure 7F The first electrode layer LY3 of the light-emitting element is shown. Figure 7F The first electrode E1 is shown.

[0169] Figure 7GThe pixel defining layer (PDL) is shown, with a pixel opening P0 in the PDL. The pixel opening P0 corresponds to the effective light-emitting area of ​​the sub-pixel. When at least one film layer in the light-emitting functional layer (FL) of the display substrate is fabricated using an inkjet printing process, the inkjet-printed film layer is located in the pixel opening P0 of the pixel defining layer (PDL).

[0170] refer to Figures 5 to 8E The first power signal line PL11 and the first power connection line PL12 are connected through via V0.

[0171] refer to Figures 5 to 8E The connecting electrode CEa is connected to the gate line G5 through the via V9, and the connecting electrode CEa serves as the gate of the light-emitting control transistor T5.

[0172] refer to Figures 5 to 8E One end of the connecting electrode CEb is connected to the first power line PL1 (first power signal line PL11) through the via V11, and the other end of the connecting electrode CEb is connected to the first electrode T5a of the light-emitting control transistor T5 through the via V10.

[0173] refer to Figures 5 to 8E The connecting electrode CEc is connected to the gate line G1 through the via V12, and the connecting electrode CEc serves as the gate of the data writing transistor T1.

[0174] refer to Figures 5 to 8E The data line DT is connected to the first terminal T1a of the data writing transistor T1 through the via V4.

[0175] refer to Figures 5 to 8E The connecting electrode CEd is connected to the gate line G2 through the via V6, and the connecting electrode CEd serves as the gate of the reset transistor T2.

[0176] refer to Figures 5 to 8E One end of the connecting electrode CEe is connected to the initialization line INT1 (initialization signal line INT11) through the via V7, and the other end of the connecting electrode CEe is connected to the first electrode T2a of the reset transistor T2 through the via V8.

[0177] refer to Figures 5 to 8E One end of the connecting electrode CEf is connected to the first terminal C1 (the first plate Ca, the gate of the driving transistor T3) through the via V3, and the other end of the connecting electrode CEf is connected to the first terminal T1b of the data writing transistor T1 (that is, the second terminal T2b of the reset transistor T2) through the via V5.

[0178] refer to Figures 5 to 8E The third electrode Cc of the second terminal C2 is connected to the second electrode Cb of the second terminal C2 (that is, the first electrode T3a of the driving transistor T3) through the via V2.

[0179] refer to Figures 5 to 8E The reset signal transmission line INI is connected to the first terminal T3a of the driving transistor T3 through via V1, and the reset signal transmission line INI is connected to the second terminal T5b of the light-emitting control transistor T5 through via V13.

[0180] refer to Figures 5 to 8E The second terminal T5b of the light-emitting control transistor T5 is connected to the second terminal T3b of the driving transistor T3 through the reset signal transmission line INI.

[0181] like Figure 7A As shown, the first plate-shaped portion Cba and the second plate-shaped portion Cbb can both be connected to the channel T3c of the driving transistor T3, and the first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel T3c of the driving transistor T3 are located on the same layer. For example, the first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel T3c of the driving transistor T3 are an integral structure.

[0182] The display substrate provided in the embodiments of this disclosure optimizes the light emission uniformity and power consumption balance by matching the pattern design of the active layer LY0 with the pattern design of the channel of the driving transistor and the capacitor plate located in the active layer, thereby improving the light emission uniformity of the display substrate and reducing power consumption.

[0183] like Figure 7A As shown, the first plate-shaped portion Cba includes a first part PR1 and a second part PR2. The first part PR1 extends along the first direction Y, and the second part PR2 extends along the second direction X. The first part PR1 and the second plate-shaped portion Cbb are disposed opposite to each other and are respectively disposed on both sides of the channel T3c of the driving transistor T3 in the second direction X. Figure 7A The first part PR1, the second part PR2, and the second plate-like part Cbb are divided by dashed lines.

[0184] For example, refer to Figure 5 , Figure 7A , Figure 8B and Figure 8E The second electrode Cb and the channel of the driving transistor T3 are an integral structure, which can be formed from the same thin film using the same patterning process. The channel of the driving transistor T3 is made of semiconductor material, and the second electrode Cb is a conductor obtained by doping the semiconductor material.

[0185] Figure 8B The channel T1c of the data writing transistor T1, the channel T2c of the reset transistor T2, the channel T3c of the driving transistor T3, and the channel T5c of the light-emitting control transistor T5 are shown.

[0186] Figure 9 This is a layout diagram of a display substrate provided in one embodiment of the present disclosure. Figure 10 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure. Figure 11 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure.

[0187] Figure 9 This shows two sub-pixels 100: first sub-pixel 101 and second sub-pixel 102. (Example) Figure 9 As shown, the first sub-pixel 101 and the second sub-pixel 102 are adjacent and arranged sequentially along the second direction X. Figure 9 As shown, the layout of the pixel circuit of the first sub-pixel 101 is a mirror image design of the layout of the pixel circuit of the second sub-pixel 102. Figure 9 As shown, the pixel circuit of the first sub-pixel 101 and the pixel circuit of the second sub-pixel 102 are axially symmetrical with respect to a straight line extending along the first direction Y.

[0188] like Figure 9 As shown, the pixel opening P0 (pixel opening P01) of the first sub-pixel 101 and the pixel opening P0 (pixel opening P02) of the second sub-pixel 102 both overlap with the first power line PL1 (first power connection line PL12). That is, the orthographic projection of pixel opening P01 on the substrate overlaps with the orthographic projection of the first power line PL1 (first power connection line PL12) on the substrate, and the orthographic projection of pixel opening P02 on the substrate overlaps with the orthographic projection of the first power line PL1 (first power connection line PL12) on the substrate. The portion of the first power line PL1 (first power connection line PL12) located directly below opening P0 can act as a leveling pad, further improving the flatness of the light-emitting layer to reduce color shift, such as reducing color shift at left and right viewing angles, thereby further improving display quality. In other words, the central axis of the third plate Cc of the storage capacitor in the first direction Y is brought closer to the central axis C0 of the pixel opening P0 extending along the first direction Y, and the positions of the pixel opening P0 on both sides of the third plate Cc are leveled by signal lines. certainly, Figure 9 The adjacent sub-pixels are not limited to the first sub-pixel 101 and the second sub-pixel 102, but can also be in other forms, such as the second sub-pixel 102 and the third sub-pixel 103, or the first sub-pixel 101 and the third sub-pixel 103. Figure 9 In some embodiments, two adjacent sub-pixels may overlap with the first power connection line PL12, while the other of the two adjacent sub-pixels may not overlap with the first power connection line PL12.

[0189] like Figure 10 As shown, the third electrode plate Cc and the first power supply connection line PL12 are respectively located on both sides of the central axis C0. Figure 10 The first power line PL1 (first power connection line PL12) in the display substrate shown has a larger proportion in the width direction (second direction X) of the pixel opening. That is, the first power connection line PL12 has a larger padding size in the width direction of the pixel opening, so that the third electrode plate Cc located on both sides of the central axis C0 and the first power connection line PL12 together play a padding role, thereby improving the flatness of the light-emitting layer and reducing color shift, such as reducing color shift at the left and right viewing angles, so as to further improve the display quality. Figure 10 The diagram shows that the third sub-pixel 103 and the first sub-pixel 101 are adjacent and arranged sequentially along the second direction X.

[0190] like Figure 10 As shown, the maximum dimension W0 of the pixel opening P03 of the third sub-pixel 103 along the second direction X is different from the maximum dimension W0 of the pixel opening P01 of the first sub-pixel 101 along the second direction X. Correspondingly, the overlap area between the first power connection line PL12 and the pixel opening P03 of the third sub-pixel 103 is different from the overlap area between the first power connection line PL12 and the pixel opening P01 of the first sub-pixel 101. For example, the ratio of the overlap area of ​​the first power connection line PL12 and the pixel opening P03 of the third sub-pixel 103 to the area of ​​the pixel opening P03 of the third sub-pixel 103 is equal to or approximately equal to the ratio of the overlap area of ​​the first power connection line PL12 and the pixel opening P01 of the first sub-pixel 101 to the area of ​​the pixel opening P01 of the first sub-pixel 101.

[0191] like Figure 10 As shown, the maximum size W0 of the pixel opening P03 of the third sub-pixel 103 along the second direction X is greater than the maximum size W0 of the pixel opening P01 of the first sub-pixel 101 along the second direction X. Correspondingly, the overlap area between the first power connection line PL12 and the pixel opening P03 of the third sub-pixel 103 is greater than the overlap area between the first power connection line PL12 and the pixel opening P01 of the first sub-pixel 101.

[0192] like Figure 10 As shown, the overlap size of the first power connection line PL12 and the pixel opening P03 of the third sub-pixel 103 in the second direction X is greater than the overlap size of the first power connection line PL12 and the pixel opening P01 of the first sub-pixel 101 in the second direction X.

[0193] Figure 10 The maximum size W03 of the pixel opening P03 of the third sub-pixel 103 along the second direction X and the maximum size W01 of the pixel opening P01 of the first sub-pixel 101 along the second direction X are shown.

[0194] Figure 11The diagram shows that one of the pixel openings P0 of two adjacent sub-pixels 100 overlaps with the first power connection line PL12, while the other pixel opening P0 of the two adjacent sub-pixels 100 does not overlap with the first power connection line PL12. That is, the first power connection line PL12 acts as a padding element for one of the adjacent sub-pixels. For example, the first power connection line PL12 acts as a padding element for at least one of the adjacent sub-pixels.

[0195] refer to Figures 3 to 11 This disclosure provides a display substrate, including a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS. Each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst. The storage capacitor Cst includes a first plate Ca and a second plate Cb. The first plate Ca of the storage capacitor Cst is connected to the gate T3g of the driving transistor T3, and the second plate Cb of the storage capacitor Cst is connected to the first plate T3a of the driving transistor T3. The light-emitting element 100b is electrically connected to the pixel circuit 100a, and the pixel circuit 100a is configured to drive the light-emitting element 100b. Each sub-pixel 100 includes a pixel opening P0, which is configured to define a light-emitting area of ​​the sub-pixel 100.

[0196] like Figure 5 As shown, the orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS.

[0197] refer to Figure 5 , Figure 8E , Figure 8F , Figures 9 to 11 The orthographic projection of the channel T3c of the driving transistor T3 onto the substrate BS overlaps with the orthographic projection of the pixel opening P0 onto the substrate BS. Figure 8E and Figure 8F In this embodiment, the portion of the active layer LY0 at the dashed cross is a semiconductor, such as polysilicon, while the remaining portion is a conductor, such as doped polysilicon. In embodiments of this disclosure, the semiconductor can be formed into a conductor through a doping process. For example, the doping process can be performed before forming the first conductive pattern layer LY1, but is not limited thereto.

[0198] like Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B and Figure 8E , Figures 9 to 11 As shown, the second plate Cb and the channel T3c of the driving transistor T3 (as shown) Figure 7A and Figure 8EAs shown, the second electrode plate Cb is set in the same layer as the first electrode plate Ca, and the orthographic projection of the second electrode plate Cb on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS.

[0199] For example, the display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and the value range of S2 / (W*L) is [2.82, 28.85].

[0200] like Figure 7A , Figure 8E , Figure 8F As shown, W is the width of the channel T3c of the driving transistor T3, and L is the length of the channel T3c of the driving transistor T3. Figure 5 , Figure 6 , Figures 9 to 11 As shown, S2 is the area of ​​the second electrode Cb and the first electrode Ca facing each other, M1 is the number of pixel openings P0 of the display substrate, and M2 is the area of ​​the display substrate. For example, M2 is the total area of ​​the display substrate in the plan view. For example, M2 is the sum of the area of ​​the display area R01 and the area of ​​the peripheral area R02.

[0201] The display substrate provided in the embodiments of this disclosure maximizes the utilization of the area where the storage capacitor is located. The larger the area of ​​the pixel aperture, the larger the proportion of the area where the storage capacitor is located. Correspondingly, the smaller the area of ​​the pixel aperture, the smaller the proportion of the area where the storage capacitor is located. High-resolution display substrates need to maximize the utilization of the area where the storage capacitor is located. Display substrates that satisfy the above-mentioned value range, that is, display substrates that satisfy the value range of (W*L+S2)*M1 / M2 as [0.014, 0.133] and the value range of S2 / (W*L) as [2.82, 28.85], can increase the facing area of ​​the plates of the storage capacitor, increase the capacitance, improve the capacitance retention capability, and facilitate increasing the ratio of the storage capacitor area to the pixel aperture area, increasing the area proportion of the storage capacitor, and improving the display quality.

[0202] Of course, in other embodiments, the range of S2 / (W*L) can be left unrestricted, as long as the range of (W*L+S2)*M1 / M2 is [0.014, 0.133]. In this case, the area of ​​the plates facing each other of the storage capacitor can be increased, thereby increasing the capacitance and the retention capacity of the capacitor. It is also beneficial to increase the ratio of the area of ​​the storage capacitor to the area of ​​the pixel opening, increase the area ratio of the storage capacitor, and improve the display quality.

[0203] For example, the range of values ​​for (W*L+S2)*M1 / M2 can be [0.02, 0.1].

[0204] For example, the range of values ​​for (W*L+S2)*M1 / M2 can be [0.02, 0.05].

[0205] For example, the range of values ​​for (W*L+S2)*M1 / M2 can be [0.03, 0.05].

[0206] For example, the range of values ​​for S2 / (W*L) can be [5, 28].

[0207] For example, the range of values ​​for S2 / (W*L) can be [6, 27.5].

[0208] For example, the range of values ​​for S2 / (W*L) can be [7, 27.5].

[0209] For example, in some embodiments, the display substrate can be a 27-inch product, W = 1.5-4 micrometers, for example, W can be 2.5 micrometers, 2.6 micrometers, or 2.7 micrometers; L = 10-20 micrometers, for example, L can be 13 micrometers, 14 micrometers, or 15 micrometers; M1 is the number of pixel apertures (multiplied by resolution, 4K): 3840 * 2160 = 8,294,400; for example, M2 ranges from 1900 square centimeters to 2100 square centimeters, for example, M2 = 59.8 * 33.6 = 2009.28 square centimeters; for example, S2 = 900-1200 square micrometers; for example, S2 can be 1020 square micrometers, 1030 square micrometers, or 1040 square micrometers.

[0210] For example, for a 27-inch product, W = 2.5 micrometers, L = 15 micrometers, M1 = 8,294,400 units, M2 = 2,009.28 square centimeters, S2 = 1,030 square micrometers, the value of (W*L+S2)*M1 / M2 is 0.04, and the value of S2 / (W*L) is 27.4. When calculating, use consistent units; for example, convert square centimeters to square micrometers.

[0211] For example, in some embodiments, the display substrate can be a 65-inch product, W = 1.5-4 micrometers, for example, W can be 2.5 micrometers, 2.6 micrometers, or 2.7 micrometers; L = 20-30 micrometers, for example, L can be 23 micrometers, 24 micrometers, or 25 micrometers; M1 is the number of pixel apertures (multiplied by resolution, 8K): 7680*4320 = 33,177,600; M2 ranges from 11,600 to 11,700 square centimeters, for example, M2 = 143.9*80.94 = 11,647.27 square centimeters; for example, S2 = 900-1200 square micrometers, for example, it can be 1020 square micrometers, 1030 square micrometers, or 1040 square micrometers.

[0212] For example, for a 65-inch product, W = 2.7 micrometers; L = 25 micrometers; M1 = 7680 * 4320 = 33,177,600 units; M2 = 143.9 * 80.94 = 11,647.27 square centimeters; S2 = 1200 square micrometers; the value of (W * L + S2) * M1 / ​​M2 is 0.036; and the value of S2 / (W * L) is 17.7.

[0213] For example, in some embodiments, the display substrate may be a 75-inch product, for example, W = 1.5-4 micrometers, for example, W may be 2.5 micrometers, 2.6 micrometers, or 2.7 micrometers; for example, L = 35-45 micrometers, for example, L may be 39 micrometers, 40 micrometers, or 41 micrometers; M1 is the number of pixel apertures (multiplied by resolution, 8K) = 7680 * 4320 = 33,177,600; for example, M2 ranges from 14,400 to 14,500 square centimeters, for example, M2 = 154.96 * 93.38 = 14,470.16 square centimeters; S2 = 900-1200 square micrometers, for example, S2 may be 1020 square micrometers, 1030 square micrometers, or 1040 square micrometers.

[0214] For example, for a 75-inch product, W = 4 micrometers, L = 39 micrometers, M1 = 33,177,600 units; M2 = 154.96 * 93.38 = 14,470.16 square centimeters; S2 = 1,200 square micrometers, the value of (W * L + S2) * M1 / ​​M2 is 0.031, and the value of S2 / (W * L) is 7.69.

[0215] For example, refer to Figure 5 , Figure 6 , Figure 7D , Figure 8A and Figure 8D , Figures 9 to 11 The storage capacitor Cst also includes a third plate Cc, which is connected to a second plate Cb. The third plate Cc and the second plate Cb are located on opposite sides of the first plate Ca. The placement of the second plate Cb below the first plate Ca and the third plate Cc above the first plate Ca increases the capacitance of the storage capacitor, thus improving display quality. Of course, the placement of the third plate Cc can be determined by considering factors such as the leveling design, capacitance, the position of the first plate Ca, and the position of the second plate Cb.

[0216] Figure 12 This is a layout diagram of a display substrate provided for another embodiment of this disclosure. Figure 5 Compared to the display substrate shown, in Figure 12 In the display substrate shown, the connecting electrode CEb is located in the active layer LY0 and is an integral structure with the first electrode T5a of the light-emitting control transistor T5.

[0217] Figure 13 This is a layout diagram of a display substrate provided for another embodiment of this disclosure. Figure 5 Compared to the display substrate shown, in Figure 13 In the display substrate shown, the second terminal T5b of the light-emitting control transistor T5 is directly connected to the second terminal T3b of the driving transistor T3.

[0218] Figure 14 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure. Figure 15 for Figure 14 A partial stacking diagram of the film layers. (See attached image.) Figure 14 and Figure 15 As shown, the second electrode Cb includes a first plate-shaped portion Cba, which is integral with the channel of the driving transistor T3.

[0219] For example, Figure 14 and Figure 15 As shown, the second electrode Cb further includes a second plate-shaped portion Cbb. The first plate-shaped portion Cba and the second plate-shaped portion Cbb are spaced apart from each other, and the area of ​​the first plate-shaped portion Cba is larger than the area of ​​the second plate-shaped portion Cbb. Figure 14 and Figure 15 As shown, the second plate-shaped portion Cbb and the first plate-shaped portion Cba are located on the same layer and are spaced apart. The first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel of the driving transistor T3 are all located on the same layer, specifically in the active layer LY0.

[0220] like Figure 14 and Figure 15 As shown, the second plate-shaped part Cbb is connected to the third electrode plate Cc through the through hole V22.

[0221] like Figure 15 As shown, the first plate-shaped portion Cba includes a first part PR1 and a second part PR2. The first part PR1 extends along a first direction Y, and the second part PR2 extends along a second direction X. The first part PR1 and the second plate-shaped portion Cba are disposed opposite to each other and are located on opposite sides of the channel T3c of the driving transistor T3 in the second direction X. For example, as Figure 15 As shown, the first part PR1 and the second part PR2 form a 7 shape. Figure 15 The first part PR1 and the second part PR2 are divided by dashed lines.

[0222] Figure 16 This is a layout diagram of a display substrate provided for another embodiment of the present disclosure. Figure 17 for Figure 16 A partial stacking diagram of the film layers. (See attached image.) Figure 16 and Figure 17 As shown, the driving transistor T3 adopts a dual-gate structure. Figure 17The channels T3c1 and T3c2 of the driving transistor T3 are shown.

[0223] For example, the channel of the driving transistor T3 is made of semiconductor material, and the material of the second plate Cb is a conductor obtained by doping the same semiconductor material as the channel of the driving transistor T3.

[0224] like Figure 5 , Figures 9 to 14 , Figure 16 As shown, the pixel opening P0 has a central axis C0 extending along a first direction Y. The pixel opening P0 is symmetrical about the central axis C0.

[0225] refer to Figures 9 to 11 The pixel opening P0 of sub-pixel 100 includes the pixel opening P01 of the first sub-pixel 101, the pixel opening P02 of the second sub-pixel 102, and the pixel opening P03 of the third sub-pixel 103.

[0226] refer to Figures 9 to 11 The central axis C0 includes the central axis C01 of the pixel opening P0 (pixel opening P01) of the first sub-pixel 101, the central axis C02 of the pixel opening P0 (pixel opening P02) of the second sub-pixel 102, and the central axis C03 of the pixel opening P0 (pixel opening P03) of the third sub-pixel 103.

[0227] Figure 18 This is a stack-up diagram of a portion of the film layers of a display substrate provided in an embodiment of this disclosure. For example, such as... Figure 18 As shown, the channel of the driving transistor T3 extends along the first direction Y, the pixel opening P0 has a central axis C0 extending along the first direction Y, and the maximum size of the pixel opening P0 along the second direction X (the width of the pixel opening P0) is W0. The first direction Y intersects the second direction X, and the distance from the channel T3c of the driving transistor T3 to the central axis C0 is D1. The value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8]. The larger the value of D1, the smaller the proportion of the driving transistor T3 and the larger the area of ​​the storage capacitor. The ratio of 2*D1 / W0 within the above range defines the position of the channel or gate of the driving transistor, which is beneficial to improving the retention capability of the storage capacitor and increasing the ratio of the storage capacitor to the area of ​​the pixel opening, thereby increasing the area proportion of the storage capacitor and improving the display quality.

[0228] For example, for the blue sub-pixel, W0 = 50 micrometers, D1 = 15.3 micrometers, and the value of 2*D1 / W0 is 0.6.

[0229] For example, for the green sub-pixel, W0 = 28 micrometers, D1 = 3.25 micrometers, and the value of 2*D1 / W0 is 0.2.

[0230] For example, for the red sub-pixel, W0 = 28 micrometers, D1 = 2.55 micrometers, and the value of 2*D1 / W0 is 0.2.

[0231] The above provides several examples. The values ​​of W0 and D0 can be determined as needed, as long as the range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8]. For blue sub-pixels, the range of 2*D1 / W0 is [0.6, 0.8], and for green and / or red sub-pixels, the range of 2*D1 / W0 is [0.2, 0.4].

[0232] Figure 19 This is a stacked diagram of partial film layers of a display substrate provided in one embodiment of the present disclosure. For example, such as... Figure 19 As shown, the display substrate also includes multiple signal lines SGL located on one side of the storage capacitor Cst. The signal lines SGL extend along the second direction X. The orthographic projection of the multiple signal lines SGL on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The dimension of the pixel opening P0 along the first direction Y (the height of the pixel opening P0) is H0. The distance between the furthest edges of the multiple signal lines SGL in the first direction Y is Hs. The value range of L / (H0-Hs) is [0.59, 1.19]. The smaller the value of the channel length L of T3c, the larger the area of ​​the storage capacitor. The value of L / (H0-Hs) is within the above range to define the position of the channel or gate of the driving transistor, which is beneficial to obtaining a storage capacitor with a larger capacitance.

[0233] In some embodiments, the value of L is approximately 10-30 μm, the value of H0 is approximately 50-75 μm, and the value of Hs is approximately 10-25 μm, but is not limited thereto.

[0234] For example, L = 30 μm, H0 = 75 μm, Hs = 25 μm, and the value of L / (H0-Hs) is 0.6.

[0235] For example, such as Figure 19As shown, the display substrate also includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1. The pixel circuit 100a also includes a data writing transistor T1 and a reset transistor T2. The first terminal of the data writing transistor T1 is connected to the data line DT. The gate of the driving transistor T3 is connected to the second terminal of the data writing transistor T1. The gate of the data writing transistor T1 is connected to the gate line G1. The first terminal of the reset transistor T2 is connected to the initialization line INT1. The second terminal of the reset transistor T2 is connected to the gate of the driving transistor T3. The gate of the reset transistor T2 is connected to the gate line G2. The multiple signal lines SGL include gate lines G1, G2, and the initialization line INT1. Of course, in other embodiments, the multiple signal lines SGL may also include at least one of the gate lines G1, G2, and the initialization line INT1, or include other signal lines overlapping with the pixel opening P0.

[0236] For example, the area of ​​pixel aperture P0 is S0, and the sum of the area of ​​the opposing second plate Cb and the first plate Ca and the area of ​​the channel T3c of the driving transistor T3 is Ss. The relationship between Ss and S0 satisfies: Ss = A*S0 + B, where the value of A ranges from [0.42, 0.82] and the value of B ranges from [-2700, -3100]. Through the above formula, the design areas of the pixel aperture, storage capacitor, and driving transistor are fitted, which helps to improve the ratio of the storage capacitor area to the pixel aperture area, increase the area ratio of the storage capacitor, and improve display quality.

[0237] For example, in some embodiments, Ss = 179, S0 = 4524, and the units of area S0 and area Ss are both square micrometers. In this case, A = 0.686, B = -2924.

[0238] For example, in some embodiments, Ss = 2440, S0 = 7820, and the units of area S0 and area Ss are both square micrometers. In this case, A = 0.686, B = -2924.

[0239] For example, in some embodiments, Ss = 370, S0 = 4802, and the units of area S0 and area Ss are both square micrometers. In this case, A = 0.686, B = -2924.

[0240] For example, in some embodiments, Ss = 3219, S0 = 8955, and the units of area S0 and area Ss are both square micrometers. In this case, A = 0.686, B = -2924.

[0241] Figure 20 This is a stacked diagram of partial film layers of a display substrate provided in one embodiment of the present disclosure. For example, such as... Figure 5 , Figures 9 to 11 ,as well as Figure 20As shown, the orthographic projection of pixel opening P0 on substrate BS overlaps with the orthographic projection of third electrode Cc on substrate BS.

[0242] For example, such as Figure 20 As shown, the third electrode plate Cc includes a first edge CL1 extending along the first direction Y and a second edge CL2 extending along the first direction Y, and the pixel opening P0 includes a first edge KL1 extending along the first direction Y and a second edge KL2 extending along the first direction Y.

[0243] For example, such as Figure 20 As shown, the first edge CL1 of the third electrode plate Cc is closer to the first edge KL1 of the pixel opening P0 than the second edge CL2 of the third electrode plate Cc, and the second edge CL2 of the third electrode plate Cc is closer to the second edge KL2 of the pixel opening P0 than the first edge CL2 of the third electrode plate Cc. Sub-pixel 100 satisfies the following formula:

[0244] △U=|U02-U01|,

[0245] U01 is the coordinate distance between the chromaticity coordinate point in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle. U02 is the coordinate distance between the chromaticity coordinate point in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle. △U is the absolute value of the difference between U02 and U01. The chromaticity coordinate point in the 0-degree viewing angle is the chromaticity coordinate point at the normal line where the center of the display substrate is located. The first viewing angle and the second viewing angle are located on opposite sides of the normal line and the angle between them is equal, and △U≤0.0020.

[0246] For example, such as Figure 20 As shown, sub-pixel 100 satisfies the following formula:

[0247] △U=|U02-U01|≤k×|Xb-Xa| / KW,

[0248] Where k is the color shift influence coefficient, 0.009≤k≤0.03, △U<0.0020, Xa is the minimum distance between the first edge CL1 of the third electrode plate Cc and the first edge KL1 of the pixel opening P0 in the second direction X, Xb is the minimum distance between the second edge CL2 of the third electrode plate Cc and the second edge KL2 of the pixel opening P0 in the second direction X, the first direction Y and the second direction X intersect; KW is the maximum size of the pixel opening P0 in the second direction X, U01 is the coordinate distance between the chromaticity coordinate point in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U02 is the coordinate distance between the chromaticity coordinate point in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point in the 0-degree viewing angle is the chromaticity coordinate point at the normal line where the center of the display substrate is located, the first viewing angle and the second viewing angle are located on opposite sides of the normal line and the angle between them is equal.

[0249] The size of KW is the maximum size of the pixel opening P0 along the second direction X (the width of the pixel opening P0) W0.

[0250] For example, such as Figure 20 As shown, the third electrode plate Cc also includes a third edge CL3 extending along the second direction X and a fourth edge CL4 extending along the second direction X, and the pixel opening P0 includes a third edge KL3 extending along the second direction X and a fourth edge KL4 extending along the second direction X.

[0251] like Figure 20 As shown, the orthographic projection of the third edge CL3 on the substrate is located outside the orthographic projection of the pixel opening P0 on the substrate.

[0252] like Figure 20 As shown, the orthographic projection of the fourth edge CL4 on the substrate is located within the orthographic projection of the pixel opening P0 on the substrate.

[0253] like Figure 20 As shown, the first edge CL1 and the second edge CL2 are positioned opposite each other, and the third edge CL3 is connected to the first edge CL1 and the second edge CL2 by rounded corners. The third edge CL3 and the fourth edge CL4 are positioned opposite each other, and the fourth edge CL4 is connected to the first edge CL1 and the second edge CL2 by rounded corners. Of course, in other embodiments, adjacent edges of the opening may not be connected by rounded corners.

[0254] Figure 21 This is a schematic diagram of the center pixel of a display substrate provided for an embodiment of the present disclosure. Figure 22 for Figure 21 A cross-sectional view along line B1-B2. Figure 23 This is a schematic diagram showing the coordinate distance between chromaticity coordinate points on a display substrate from two different viewing angles.

[0255] Figure 21 The center pixel PXc is shown. For example, the center pixel PXc is the pixel PX located at the center of the display area R01.

[0256] For example, a non-contact spectrometer (such as PR630, 730; CS2000, 2000A) can be used to randomly sample (select more than 10 pieces, and choose the worst data) the display substrates (display panels) under test in a dark room environment (illuminance below 1lx). The test point is the center pixel of the display substrate. The u' and v' coordinates of this point in the 1976UV chromaticity coordinate system of the four color RBGW are read. Measurements are performed at nine viewing angles: 0 degrees, ±15 degrees, ±30 degrees, ±45 degrees, and ±60 degrees. The u' and v' values ​​at each angle are obtained. Color shift at a -60 degree viewing angle is used as an example.

[0257]

[0258] u2' and v2' are the chromaticity coordinates at a -60 degree viewing angle. u1' and v1' are the chromaticity coordinates at a 0 degree viewing angle.

[0259] Substituting into the formula yields Δu'v' for -60 degrees; similarly, Δu'v' for 60 degrees is calculated. By optimizing the structure of the display substrate, the difference between two values ​​for the four colors (RGBW) can be less than 0.0015, and the Δu'v' value at each angle can be less than 0.025. The first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel. When measuring the color shift of white light, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 in the center pixel PXc are all lit.

[0260] The uniform color space CIE1976 is derived from CIE1931 XYZ.

[0261] The CIE1976 Luv calculation formula includes:

[0262]

[0263] In the formula, u' and v' are the chromaticity coordinates of the color sample, and X, Y, and Z are the tristimulus values ​​of the sample.

[0264] It should be noted that color shift measurement methods are not limited to those described above, and the measuring instruments used are not limited to the few listed. The same measuring instrument can be used to measure the chromaticity coordinates at different viewing angles, and the coordinate distance between the chromaticity coordinate points at each viewing angle and the chromaticity coordinate point at the 0-degree viewing angle can be obtained.

[0265] The embodiments disclosed herein are illustrated by taking the measurement of the color shift of the center pixel PXc as an example. Of course, the color shift of each sub-pixel in other suitable pixels can also be measured.

[0266] Figure 23 The coordinate distance between chromaticity coordinate points P2 and P1 is shown. For example... Figure 23 As shown, x0 is the x-coordinate distance between chromaticity coordinate points P2 and P1, y0 is the y-coordinate distance between chromaticity coordinate points P2 and P1, and z0 is the coordinate distance between chromaticity coordinate points P2 and P1.

[0267] For example, the coordinate distance between two chromaticity coordinate points from two different viewpoints is the square root of the sum of the squares of the differences in the x-coordinates and the squares of the differences in the y-coordinates of the two chromaticity coordinate points.

[0268] Figure 22 The normal L0 of the center of the display substrate is shown. The normal L0 is parallel to the third direction Z. Figure 22 The first viewpoint VW1 and the second viewpoint VW2 are shown. The angle between the first viewpoint VW1 and the normal L0 is +θ, and the angle between the second viewpoint VW2 and the normal L0 is -θ. Under the positive viewpoint θ, the rotation from the normal L0 to this viewpoint is clockwise by an angle θ, and under the negative viewpoint -θ, the rotation from the normal L0 to this viewpoint is counterclockwise by an angle θ.

[0269] Figure 21 and Figure 22 The situation shown is used to measure the color shift of the left and right viewpoints. When measuring the color shift of the up and down viewpoints, the first viewpoints VW1 and VW2 are set on both sides of the normal L0 in the first direction Y.

[0270] Figure 24 This is a layout diagram of a display substrate provided in one embodiment of the present disclosure. Figure 24 The first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are shown. For example... Figure 24 As shown, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are arranged sequentially along the second direction X.

[0271] like Figure 24 As shown, the initialization line INT1 includes the initialization signal line INT11 and the initialization connection line INT12, which are connected together. Figure 24 As shown, the initialization signal line INT11 and the initialization connection line INT12 are connected through via Vj. Figure 24 As shown, the initialization signal line INT11 extends along the second direction X, and the initialization connection line INT12 extends along the first direction Y.

[0272] like Figure 24 As shown, at the corresponding positions, the initialization connection line INT12 and the first power connection line PL12 are alternately set in the second direction X.

[0273] like Figure 24 As shown, the first part INTa and the second part INTb of the initialization connection line INT12 are connected through the via Vg, and the second part INTb and the third part INTc of the initialization connection line INT12 are connected through the via Vh.

[0274] like Figure 24 As shown, the initialization connection line INT12 passes through the first sub-pixel 101, and two adjacent first power connection lines PL1 pass through the second sub-pixel 102 and the third sub-pixel 103, respectively. That is, the initialization connection line INT12, one first power connection line PL12, and the other first power connection line PL12 are sequentially arranged along the second direction X. The initialization connection line INT12 extends along the first direction Y, and the first power connection line PL12 extends along the first direction Y.

[0275] Figure 25 This is a plan view of a display substrate provided in one embodiment of this disclosure. For example, Figure 25 The sub-pixel 100 shown is the third sub-pixel 103, and the third sub-pixel 103 is the blue sub-pixel.

[0276] For example, such as Figure 5 and Figure 25 As shown, the display substrate also includes a first power line PL1, which is configured to provide a first voltage signal to the pixel circuit 100a. The first power line PL1 includes a first power connection line PL12 extending along a first direction Y and a first power signal line PL11 extending along a second direction X. The orthographic projection of the first power connection line PL12 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS.

[0277] like Figure 5 and Figure 25 As shown, the first power connection line PL12 is formed by connecting multiple conductive parts located in two conductive pattern layers. Embodiments of this disclosure include, but are not limited to, examples. In other embodiments, the first power connection line PL12 may also be composed of wires located in the same layer, or formed by connecting multiple conductive parts located in three or more conductive pattern layers.

[0278] For example, refer to Figure 5 and Figure 25The area of ​​the third electrode plate Cc is Sc1, and the overlapping area of ​​the orthographic projection of the third electrode plate Cc onto the substrate BS and the orthographic projection of the pixel opening P0 onto the substrate BS is Sc2, where Sc2 / Sc1 ≥ 0.9. The third electrode plate Cc can act as a leveling agent, leveling the bottom surface of the pixel opening P0 of sub-pixel 100, improving the flatness of the light-emitting layer, and thus enhancing display quality. For example, a sub-pixel satisfying Sc2 / Sc1 ≥ 0.9 can be a blue sub-pixel, leveling the blue sub-pixel, improving the flatness of the light-emitting layer of the blue sub-pixel, and enhancing display quality. Further, for even better leveling effect, Sc2 / Sc1 ≥ 0.95.

[0279] For example, refer to Figure 5 and Figure 25 The width of the first power connection line PL12 is W1, and the overlap width between the first power connection line PL12 and the pixel opening P0 is W2, with W2 / W1 ≥ 0.9. This ensures that the first power connection line PL12 provides better leveling for the pixel opening P0 of the sub-pixel 100, thereby improving the flatness of the light-emitting layer. Further, for example, to further enhance the leveling effect, W2 / W1 ≥ 0.95.

[0280] In embodiments of this disclosure, linewidth refers to the dimension of the line perpendicular to its direction of extension.

[0281] For example, such as Figure 25 As shown, the maximum dimension of the pixel opening P0 along the second direction X is W0, and the value range of 2×W2 / W0 is [0.71, 0.99], to enhance the flattening effect of the first power connection line PL12 and improve the flatness of the light-emitting layer. The value range of the voltage across the line Uc (V) / size Lg (inches) is [0.32, 0.74], to improve current uniformity. Size Lg is the length of the diagonal of the display substrate. For example, the voltage across the line Uc is the voltage difference between the first and second electrodes of the light-emitting element. For example, the voltage across the line Uc is the difference between the first voltage signal VDD and the second voltage signal VSS. (Reference) Figure 1 The largest rectangle represents the display substrate, and the diagonal of this rectangle is the diagonal of the display substrate. The length of the diagonal is measured in inches.

[0282] For example, in some embodiments, the first voltage signal VDD is 17V, the second voltage signal VSS is 2V, Uc = 15V, Lg = 27 inches, and the cross voltage Uc (V) / size Lg (inches) is 0.55.

[0283] For example, the value range of 2×W2 / W0 is [0.80, 0.99], and the value range of transverse pressure Uc(V) / size Lg(inches) is [0.52, 0.74].

[0284] For example, such as Figure 25 As shown, the pixel opening P0 has a central axis C0 extending along the first direction Y. The minimum distance from the first power connection line PL12 to the central axis C0 is Xd1, and the minimum distance from the third electrode plate Cc to the central axis C0 is Xd2. Furthermore, the value range of Xd1 / Xd2 is [0.9, 1.1], which helps the first power connection line PL12 and the third electrode plate Cc to flatten the bottom surface of the pixel opening of the sub-pixel, improve the flatness of the light-emitting layer, and thus improve the display quality.

[0285] For example, in some embodiments, Xd1 = 1.57 micrometers, Xd2 = 1.73 micrometers, and Xd1 / Xd2 = 0.9. In other embodiments, Xd1 = 1.73 micrometers, Xd2 = 1.57 micrometers, and Xd1 / Xd2 = 1.1. Xd1 and Xd2 are not limited to the above values ​​and can be determined as needed.

[0286] For example, such as Figure 25 As shown, the display substrate also includes a storage capacitor Cst ( Figure 25 The third electrode plate Cc shows multiple signal lines 80 on one side of the storage capacitor Cst. The orthographic projection of the multiple signal lines 80 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The signal lines 80 extend along the second direction X. The distance between the third electrode plate Cc and the closest signal line is Xd3. The linewidth of the signal line is Xd4. The value range of Xd3 / Xd4 is [0.9, 1.1], which helps to improve the flattening effect of the signal lines 80 and the third electrode plate Cc on the bottom surface of the pixel opening of the sub-pixel, reduce the color shift in the vertical direction, and improve the color shift consistency in the vertical direction.

[0287] For example, in some embodiments, Xd3 = 3 micrometers, Xd4 = 3 micrometers, and Xd3 / Xd4 = 1. Xd3 and Xd4 are not limited to the above values ​​and can be determined as needed.

[0288] Figure 26 This is a plan view of a display substrate provided in one embodiment of the present disclosure. Figure 26 Two sub-pixels 100 are shown. The first sub-pixel 101 is a red sub-pixel, and the second sub-pixel 102 is a green sub-pixel.

[0289] For example, such as Figure 26As shown, the display substrate also includes a first power line PL1, which is configured to provide a first voltage signal to the pixel circuit 100a. The first power line PL1 includes a first power connection line PL12 extending along the first direction Y and a first power signal line PL11 extending along the second direction X. The minimum distance from the first power connection line PL12 to the central axis C0 is Xd1, and the minimum distance between the first power connection line PL12 and the third electrode plate Cc is Xd0. DP = |Xd1 - Xd0| / 2, and the maximum size of the pixel opening P0 along the second direction X (the width of the pixel opening P0) is W0. The value range of DP / W0 is [0.01, 0.19], which facilitates the flattening effect of the first power connection line PL12 and the third electrode plate Cc on the bottom surface of the pixel opening of the sub-pixel, thereby improving the flatness of the light-emitting layer. For example, the red sub-pixel or green sub-pixel in the display substrate satisfies the value range of DP / W0 as [0.01, 0.19].

[0290] For example, in some embodiments, Xd1 = 22 micrometers, Xd0 = 8 micrometers, DP = 7 micrometers, W0 = 52 micrometers, and DP / W0 = 0.13.

[0291] For example, in some embodiments, the display substrate also satisfies at least one of the following: W2 / W1 ≥ 0.9, 2×W2 / W0 ranging from [0.71, 0.99], voltage Uc (V) / size Lg (inches) ranging from [0.32, 0.74], Xd1 / Xd2 ranging from [0.9, 1.1], Xd3 / Xd4 ranging from [0.9, 1.1], and DP / W0 ranging from [0.01, 0.19], so that the display substrate satisfies ΔU ≤ 0.0020. That is, through at least one of the above-mentioned dimensional designs, the color shift of the display substrate is relatively small.

[0292] For example, such as Figure 26 As shown, the display substrate also includes a first signal line 801, which extends along a first direction Y. The sub-pixel 100 includes a first sub-pixel 101 and a second sub-pixel 102 adjacent to each other in a second direction X. The first signal line 801 is configured to provide a data signal to the pixel circuit 100a of the first sub-pixel 101. The pixel opening P0 of the first sub-pixel 101 and the pixel opening P0 of the second sub-pixel 102 are spaced apart. The first signal line 801 is located between the pixel opening P0 of the first sub-pixel 101 and the pixel opening P0 of the second sub-pixel 102.

[0293] For example, such as Figure 26As shown, the minimum distances between the pixel opening P0 of the first sub-pixel 101 and the pixel opening P0 of the second sub-pixel 102 and the first signal line 801 are Xa1 and Xa2, respectively, with Xa1 / Xa2 ranging from [0.8, 1.2]. The first signal line 801 extends along the first direction Y and is located between the pixel openings P0 of adjacent sub-pixels. A pixel limiting layer material is provided directly above the first signal line 801. By limiting the ratio of the minimum distance between adjacent pixel openings and the first signal line 801, the voltage drop is reduced and the color shift is mitigated.

[0294] For example, in some embodiments, Xa1 = 12 micrometers, Xa2 = 12 micrometers, and Xa1 / Xa2 = 1. Of course, Xa1 and Xa2 can fluctuate around the above values, as long as the range of Xa1 / Xa2 is [0.8, 1.2].

[0295] For example, such as Figure 26 As shown, the display substrate also includes a second signal line 802, which extends along the first direction Y. The first signal line 801 and the second signal line 802 are located on opposite sides of the same third electrode plate Cc. The orthographic projection of the second signal line 802 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 of the second sub-pixel 102 on the substrate BS.

[0296] For example, such as Figure 26 As shown, the spacing between the third electrode plate Cc and the second signal line 802 is Xa3, and the spacing between the third electrode plate Cc and the first signal line 801 is Xa4. The value range of Xa3 / Xa4 is [0.8, 1.2], so as to enhance the flattening effect of the third electrode plate Cc and the second signal line 802 on the bottom surface of the pixel opening of the second sub-pixel 102, improve the flatness of the light-emitting layer, and reduce color shift.

[0297] For example, in some embodiments, Xa3 = 8.6 micrometers, Xa4 = 10 micrometers, and Xa3 / Xa4 = 0.86. Of course, Xa3 and Xa4 can fluctuate around the above values, as long as the value range of Xa3 / Xa4 is [0.8, 1.2].

[0298] For example, such as Figure 26As shown, the display substrate also includes a third signal line 803, which extends along the first direction Y. The orthographic projection of the third signal line 803 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 of the first sub-pixel 101 on the substrate BS. The minimum distance between the third electrode plate Cc of the first sub-pixel 101 and the third signal line 803 is Xa5, and the minimum distance between the third signal line 803 and the first signal line 801 is Xa6. The value range of Xa5 / Xa6 is [0.8, 1.2], so as to enhance the flattening effect of the third electrode plate Cc and the third signal line 803 on the bottom surface of the pixel opening of the first sub-pixel 101, improve the flatness of the light-emitting layer, and reduce color shift.

[0299] For example, in some embodiments, Xa5 = 8.7 micrometers, Xa6 = 7.3 micrometers, and Xa5 / Xa6 = 1.2. Of course, Xa5 and Xa6 can fluctuate around the above values, as long as the value range of Xa5 / Xa6 is [0.8, 1.2].

[0300] For example, such as Figure 26 As shown, the first signal line 801 includes a data line DT, and at least one of the second signal line 802 and the third signal line 803 includes a first power connection line PL12 or an initialization connection line INT12. Figure 26 The following description uses an example where both the second signal line 802 and the third signal line 803 are the first power connection line PL12. In another embodiment, the second signal line 802 is the first power connection line PL12, and the third signal line 803 is the initialization connection line INT12. Figure 26 As shown, the third signal line 803, the first signal line 801, and the second signal line 802 are arranged sequentially along the second direction X.

[0301] Figure 27 This is a plan view of a display substrate provided in one embodiment of the present disclosure. Figure 28 This is a plan view of a display substrate provided in one embodiment of this disclosure. For example, such as... Figure 27 and Figure 28As shown, the display substrate also includes a data line DT and a first power line PL1. The data line DT is configured to provide a data voltage to the pixel circuit 100a. The data line DT extends along a first direction Y. The first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a. The first power line PL1 includes a first power connection line PL12 extending along the first direction Y and a first power signal line PL11 extending along a second direction X. The sub-pixel 100 includes sub-pixels 121 and 122 adjacent to each other in the second direction X. The orthographic projection of the first power connection line PL12 on the substrate overlaps with the orthographic projection of the pixel opening P0 of the sub-pixel 121 on the substrate, and also overlaps with the orthographic projection of the pixel opening P0 of the sub-pixel 122 on the substrate.

[0302] For example, such as Figure 27 As shown, two data lines DT are respectively located on both sides of the first power connection line PL12. The orthographic projections of the two data lines DT on the substrate overlap with the orthographic projections of the pixel opening P0 of sub-pixel 121 and the pixel opening P0 of sub-pixel 122 on the substrate. Figure 27 Data lines DT1 and DT2 are shown. DT1 and DT2 provide data voltages to sub-pixels 121 and 122, respectively. The orthographic projections of DT1 and DT2 onto the substrate overlap with the orthographic projections of pixel openings P01 and P02 of sub-pixels 121 and 122, respectively. Therefore, by widening the first power connection line PL12 and cooperating with the two data lines DT1 and DT2 to flatten sub-pixels 121 and 122, the flatness of the light-emitting layer is improved, color shift is reduced, and the voltage drop problem in medium-to-large-sized display substrates can be solved, thus improving brightness uniformity.

[0303] Figure 27 The following description uses the example of the orthographic projections of two data lines DT on the substrate overlapping with the orthographic projections of the pixel opening P0 of sub-pixel 121 and the pixel opening P0 of sub-pixel 122 on the substrate, respectively. However, the embodiments disclosed herein are not limited to this. For example, by adjusting the layout design, the orthographic projections of the two data lines DT on the substrate BS can be made to not overlap with the orthographic projections of the pixel opening P0 of sub-pixel 121 and sub-pixel 122 on the substrate BS. Thus, by widening the first power connection line PL12, the first power connection line PL12, the third electrode plate Cc of sub-pixel 121, and the third electrode plate Cc of sub-pixel 122 cooperate to flatten sub-pixels 121 and 122, thereby improving the flatness of the light-emitting layer and reducing color shift.

[0304] For example, such as Figure 28As shown, the display substrate also includes a first power line PL1, which is configured to provide a first voltage signal VDD to the pixel circuit 100a. The first power line PL1 includes a first power connection line PL12 extending along a first direction Y and a first power signal line PL11 extending along a second direction X. The orthographic projection of the first power connection line PL12 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The maximum dimension of the pixel opening P0 of the sub-pixel 100 along the second direction X is W0. The sub-pixel 100 includes... For adjacent sub-pixels 131 and 132 in the second direction X, one of the two first power connection lines PL12 has a dimension of Xb1 in the second direction X, and the other of the two first power connection lines PL12 has a dimension of Xb2 in the second direction X. The value range of (Xb1+Xb2) / W0 is [0.08, 0.48], so as to enhance the flattening effect of the first power connection line PL12 on the bottom surface of the pixel opening of sub-pixels 131 and 132, improve the flatness of the light-emitting layer, and reduce color shift, such as reducing color shift in the left and right viewing angles. Figure 28 The dimensions W01 of the pixel opening P0 of sub-pixel 131 along the second direction X and W02 of the pixel opening P0 of sub-pixel 132 along the second direction X are shown. The dimension W0 of sub-pixel 100 along the second direction X can be one of dimensions W01 and W02, or the average of the two. For example, one of sub-pixels 131 and 132 can be a red sub-pixel, and the other of sub-pixels 131 and 132 can be a green sub-pixel. The embodiments of this disclosure are illustrated using the example of sub-pixel 131 being a green sub-pixel and sub-pixel 132 being a red sub-pixel.

[0305] For example, in some embodiments, Xb1 = 6 micrometers, Xb2 = 54 micrometers, W0 = 163 micrometers, and the value of (Xb1 + Xb2) / W0 is 0.37. The values ​​of Xb1, Xb2, and W0 are not limited to the above examples, as long as the value range of (Xb1 + Xb2) / W0 is [0.08, 0.48].

[0306] For example, in some embodiments, the sub-pixel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the blue sub-pixel may be as follows: Figure 25 As shown, the red sub-pixel and the green sub-pixel can be as follows: Figure 26 As shown.

[0307] Figure 29 This is a layout diagram of a display substrate provided according to an embodiment of the present disclosure. Figure 24 Compared to the display substrate shown, Figure 29The initialization connection line INT12 in the display substrate shown is located in the second sub-pixel 102, and the two first power connection lines PL1 are located in the first sub-pixel 101 and the third sub-pixel 103, respectively. That is, one first power connection line PL12, the initialization connection line INT12, and the other first power connection line PL12 are arranged sequentially along the second direction X. It should be noted that the arrangement of the initialization connection line INT12 is not limited to that shown in the figure. It can be connected to multiple initialization signal lines INT11 arranged in the first direction Y. Similarly, the arrangement of the first power connection line PL12 is not limited to that shown in the figure. It can be connected to multiple first power signal lines PL11 arranged in the first direction Y. The arrangement of the initialization connection line INT12 and the first power connection line PL12 can be determined as needed.

[0308] refer to Figure 24 and Figure 29 The first power connection line PL12 and the initialization connection line INT12 act as a leveling element for the sub-pixel. The size of the first power connection line PL12 in the second direction X is approximately half the size of the pixel opening P0 that it overlaps with in the second direction X. The size of the initialization connection line INT12 in the second direction X is less than half the size of the pixel opening P0 that it overlaps with in the second direction X, in order to accommodate the design of the storage capacitor in the second sub-pixel 102 and provide space for setting the storage capacitor.

[0309] Figure 30 This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example, such as... Figure 30 As shown, the display substrate also includes a driving circuit CCT, which is located on one side of the display substrate. Sub-pixels 100 (sub-pixels 151) away from the driving circuit CCT have a first brightness L1; sub-pixels 100 (sub-pixels 152) close to the driving circuit CCT have a second brightness L2, and the value range of |L1-L2| is [1, 9]. The unit of brightness is nits. The brightness difference of sub-pixels with different distances from the driving circuit CCT is reduced, for example, less than or equal to 9 nits. The current uniformity of the display substrate is improved, so that the voltage drop meets the design requirements. Figure 30 Two driving circuits CCTs located on the same side of the display substrate are shown. Sub-pixels 151 and 152 are at different distances from the driving circuits CCTs in the first direction Y, but the distance between sub-pixels 151 and 152 in the second direction X is not limited. The driving circuits CCTs may be driving integrated circuits (ICs).

[0310] For example, refer to Figure 28 and Figure 30Because the display substrate satisfies the value range of (Xb1+Xb2) / W0 as [0.08, 0.48], the voltage drop and color shift problems are solved, and the brightness difference is also reduced. For example, the value range of |L1-L2| is [1, 9]. That is, some display substrates satisfy the value range of (Xb1+Xb2) / W0 as [0.08, 0.48], and the value range of |L1-L2| is [1, 9].

[0311] Figure 31 This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example, such as... Figure 31 As shown, the display substrate also includes two driving circuits CCT. The two driving circuits CCT1 and CCT2 are located on opposite sides of the display area R01 of the display substrate. The sub-pixel 100 at the central axis of the display substrate has a third brightness L3, and the sub-pixel 100 close to one of the two driving circuits CCT has a fourth brightness L4. The value range of |L3-L4| is [1, 9]. The unit of brightness is nits. The brightness difference of sub-pixels with different distances from the driving circuits CCT is reduced, the current uniformity of the display substrate is improved, and the voltage drop meets the design requirements. Figure 31 The central axis CR extending along the second direction X is shown. (As shown) Figure 31 As shown, the extension direction of the central axis CR is the same as the extension direction of the drive circuit CCT. Figure 31 As shown, the central axis CR is located between the two driving circuits CCT. The distances of sub-pixels 161 and 162 from one of the two driving circuits CCT in the first direction Y are different, while the distances of sub-pixels 161 and 162 from the driving circuit CCT in the second direction X are not limited.

[0312] For example, refer to Figure 28 and Figure 31 Because the display substrate satisfies the value range of (Xb1+Xb2) / W0 as [0.08, 0.48], the voltage drop and color shift problems are solved, and the brightness difference is also reduced. For example, the value range of |L1-L2| is [1, 9]. That is, some display substrates satisfy the value range of (Xb1+Xb2) / W0 as [0.08, 0.48], and the value range of |L1-L2| is [1, 9].

[0313] In some embodiments, the display substrate satisfies that the value range of |L1-L2| is [1, 9], and that the value range of |L3-L4| is [1, 9].

[0314] Figure 32 This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example, such as... Figure 32As shown, the display substrate includes a power bus 501, a power bus 502, an initialization bus 503, and an initialization bus 504. For example, the power bus 501 is connected to the first power line PL1, the power bus 502 is connected to the second power line PL2, the initialization bus 503 is connected to the initialization line INT1, and the initialization bus 504 is connected to the initialization line INT2. Figure 32 The display substrate shown has a driving circuit on its lower side. It should be noted that the positions of the power bus 501, power bus 502, initialization bus 503, and initialization bus 504 are not limited to those shown in the figure. Figures 30 to 32 The display area R01 is shown.

[0315] Figure 33A A plan view of a pixel-defining layer in a display substrate provided for an embodiment of this disclosure. Figure 33B A plan view of a pixel-defining layer in a display substrate provided for embodiments of this disclosure. For example, such as Figure 33A and Figure 33B As shown, the pixel limiting layer (PDL) includes a plurality of first limiting portions 301 and a plurality of second limiting portions 302. The plurality of second limiting portions 302 are arranged along a second direction X and extend along a first direction Y. The plurality of first limiting portions 301 are configured as a plurality of groups 0301. Each group of first limiting portions 0301 is located between two adjacent second limiting portions 302. The first limiting portions 301 extend along the second direction X, and the first limiting portions 301 in each group are arranged along the first direction Y.

[0316] like Figure 33A and Figure 33B As shown, a groove is formed between two adjacent second defining portions 302, each groove extending along the first direction Y. During inkjet printing, ink flows in the groove. Taking the first direction Y as the column direction and the second direction X as the row direction as an example, the display substrate includes multiple columns of grooves. One column of grooves defines multiple pixel openings P0.

[0317] like Figure 6 , Figure 33A and Figure 33B As shown, the maximum height H1 from the first limiting portion 301 to the planarization layer PLN is less than the maximum height H2 from the second limiting portion 302 to the planarization layer PLN. That is, the thickness of the first limiting portion 301 is less than the thickness of the second limiting portion 302.

[0318] Figure 34 This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. Figure 34 As shown, the substrate BS includes a display area R01 and a peripheral area R02 located on at least one side of the display area R01. Figure 34As shown, the orthographic projection of the portion of data line DT located in display area R01, DT01, on the substrate BS lies within the orthographic projection of the second limiting portion 302 on the substrate BS. The orthographic projection of data line DT on the substrate BS overlaps with the orthographic projection of the second limiting portion 302 of pixel limiting layer PDL on the substrate BS, allowing the second limiting portion 302 to have a protrusion, facilitating ink flow into the pixel openings in the pixel limiting layer during inkjet printing. Figure 34 As shown, the orthographic projection of the display area R01 onto the substrate BS overlaps with the orthographic projection of the pixel defining layer PDL onto the substrate BS. The orthographic projection of the pixel opening P0 of the pixel defining layer PDL onto the substrate BS falls within the orthographic projection of the display area R01 onto the substrate BS.

[0319] Figure 34 Only two data lines DT are shown. For example, a second limiting part 302 may correspond to one data line, but it is not limited to this.

[0320] In the embodiments of this disclosure, the pixel circuit is not limited to the circuit diagram shown, and other suitable pixel circuits may be used. The layout diagram of the display substrate is also not limited to the layout diagram shown, and may be adjusted based on the given layout diagram, or other layout methods may be used.

[0321] For example, such as Figure 34 As shown, a first limiting portion 301 is provided between two adjacent pixel openings P0 in the first direction Y, and a second limiting portion 302 is provided between two adjacent pixel openings P0 in the second direction X, wherein the first direction Y and the second direction X intersect. Figure 6 As shown, the thickness of the first limiting part 301 is H1, and the thickness of the second limiting part 302 is H2, where H1 ≠ H2. For example, H1 is less than H2.

[0322] Figure 35 This is an electron microscope image of a display substrate provided in an embodiment of this disclosure. For example... Figure 35 As shown, at the via VH, the slope angle θ1 is 65-75 degrees; the slope angle θ2 is between 45-55 degrees. Slope angle θ2 is the slope angle of the planarization layer PLN at the via VH, with the reference plane (half the thickness of the planarization layer PLN) as the bottom surface. Bottom angle θ1 is the angle between the planarization layer PLN at the bottom surface of the via VH and the structure below it.

[0323] For example, such as Figure 6 and Figure 35As shown, the display substrate also includes an insulating layer ISL, and the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a through a via VH that penetrates the insulating layer ISL.

[0324] For example, such as Figure 6 As shown, the display substrate also includes an encapsulation layer EPS, which is configured to encapsulate the light-emitting element 100b. The encapsulation layer EPS comprises a stack of inorganic and organic encapsulation films. Figure 6 As shown, the encapsulation layer EPS includes an inorganic encapsulation film EPS1, an organic encapsulation film EPS2, and an inorganic encapsulation film EPS3. It should be noted that the stacking order of the organic and inorganic encapsulation films is not limited to that shown in the figure, nor is the structure of the encapsulation layer EPS limited to that shown in the figure.

[0325] Figure 36 This is a schematic diagram of a display substrate provided in one embodiment of this disclosure. For example, such as Figure 36 As shown, the display substrate also includes a barrier dam 701, and an encapsulating adhesive 702 is provided on the outer side of the encapsulation layer EPS, which serves as an adhesive. Figure 36 The EPS encapsulation layer is shown by its boundary. For example... Figure 6 and Figure 36 As shown, the insulating layer ISL includes a planarization layer PLN, which includes a first planarization portion PLN1 and a second planarization portion PLN2. A groove GR is provided between the first planarization portion PLN1 and the second planarization portion PLN2. A barrier dam 701 is located around the display area R01 of the display substrate. The orthographic projection of the barrier dam 701 on the substrate BS covers the orthographic projection of the groove GR on the substrate BS, thereby reducing or preventing water and oxygen from entering the display area R01 along the planarization layer PLN and avoiding affecting the light-emitting elements in the display area R01. Of course, in some other embodiments, the orthographic projection of the barrier dam 701 on the substrate BS may not cover the orthographic projection of the groove GR on the substrate BS.

[0326] For example, the minimum distance from the edge of the display area R01 to the edge of the peripheral area R02 ranges from 1 to 5 millimeters. That is, the size of the bezel ranges from 1 to 5 millimeters.

[0327] For example, to achieve better water and oxygen barrier effects, the groove GR is a through-hole penetrating the planarization layer PLN. For example... Figure 36 As shown, the portion of the planarization layer PLN located inside the groove GR is the first planarization portion PLN1, and the portion of the planarization layer PLN located outside the groove GR is the second planarization portion PLN2. Figure 36The first flat portion PLN1 is shown with its boundary as the first flat portion PLN1, and the second flat portion PLN2 is shown with its boundary as the second flat portion PLN2. Figure 36 This explanation uses a single recessed groove (GR) as an example, but the number of GR recesses is not limited to one and can be set as needed. The number of GR recesses depends on the narrowness of the bezel. The narrower the bezel, the fewer GR recesses are required. Of course, in some other embodiments, GR recesses may not be provided.

[0328] For example, such as Figures 3 to 5 As shown, the display substrate also includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1. The pixel circuit 100a also includes a data writing transistor T1 and a reset transistor T2. The first terminal of the data writing transistor T1 is connected to the data line DT. The gate of the driving transistor T3 is connected to the second terminal of the data writing transistor T1. The gate of the data writing transistor T1 is connected to the gate line G1. The first terminal of the reset transistor T2 is connected to the initialization line INT1. The second terminal of the reset transistor T2 is connected to the gate of the driving transistor T3. The gate of the reset transistor T2 is connected to the gate line G2.

[0329] Figure 37 This is a schematic diagram of a display substrate provided in one embodiment of the present disclosure. Figure 38 This is a circuit diagram of a dummy sub-pixel in a display substrate provided in one embodiment of the present disclosure. Figure 39 This is a layout diagram of a dummy pixel circuit in a display substrate provided in an embodiment of the present disclosure.

[0330] like Figure 37 As shown, the display substrate has a dummy sub-pixel 100d near its edge. For clarity, Figure 37 Not all dummy subpixels are shown, nor are all subpixels 100 shown. For example... Figure 37 As shown, dummy subpixel 100d is located in the peripheral area R02, and subpixel 100 is located in the display area R01. Dummy subpixel 100d does not emit light. Setting dummy subpixel 100d can improve etching uniformity and enhance display quality.

[0331] like Figure 38 As shown, the dummy sub-pixel 100d has a dummy driving transistor dT3 and a dummy reset transistor dT2. The gates of the dummy reset transistor dT2 and the dummy driving transistor dT3 are connected. The dummy reset transistor dT2 is disconnected from the initialization line INT1 to reduce power consumption. The dummy sub-pixel 100d is set up to improve etching uniformity, rather than to achieve light emission. Figure 38 As shown, the dummy sub-pixel 100d includes a dummy pixel circuit 100da and a dummy light-emitting element 100db. For example... Figure 38As shown, the composition of the virtual pixel circuit 100da can be referenced to that of the pixel circuit 100a, and the composition of the virtual light-emitting element 100db can be referenced to that of the light-emitting element 100b. However, there may be broken wires in the virtual pixel circuit 100da. Figure 38 The dummy pixel circuit 100da shown is illustrated by taking the example that the first electrode E1 of the dummy light-emitting element 100db is not connected to node N2 (the first electrode T3a of the dummy driving transistor dT3), and the dummy reset transistor dT2 is not connected to the initialization line INT1. In other embodiments, other disconnection methods can be used to prevent the dummy sub-pixel 100d from emitting light. Figure 38 The bold cross in the diagram indicates a disconnection. For example, to disconnect the dummy reset transistor dT2 of dummy subpixel 100d from the initialization line INT1, a via can be omitted.

[0332] like Figure 38 As shown, the dummy subpixel 100d also includes a dummy data writing transistor dT1. Figure 38 and Figure 39 The dummy data line dDT is also shown.

[0333] like Figure 38 As shown, the dummy sub-pixel 100d also includes a dummy storage capacitor dCst.

[0334] In the embodiments of this disclosure, apart from the main components such as transistors and storage capacitors, which are given new reference numerals, the reference numerals for the other components in the dummy sub-pixel 100d can be referred to the reference numerals in the sub-pixel 100.

[0335] Figure 40 This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example, such as... Figure 40 As shown, the display substrate also includes a dummy data line dDT, which extends along a first direction Y. The dummy data line dDT is insulated from the data line DT. A dummy sub-pixel 100d includes at least two adjacent dummy sub-pixels 100d in a second direction X, and the dummy data lines dDT of the at least two dummy sub-pixels 100d are connected to each other. Figure 40 As shown, the dummy data line dDT is located in the peripheral area R02. (As...) Figure 40 As shown, the peripheral area R02 surrounds the display area R01.

[0336] For example, a dummy data line dDT is connected to a constant voltage terminal to be configured to provide a constant voltage. The constant voltage terminal may include a port providing a first voltage signal VDD, a port providing a second voltage signal VSS, or a port providing an initialization signal Vinit1. For example, the dummy data line dDT may be connected to a first power line PL1, a second power line PL2, or an initialization line INT1. Connecting the dummy data line dDT to the constant voltage terminal helps reduce the resistance of the power lines connected to that constant voltage terminal, thus improving display quality.

[0337] For example, such as Figure 40 As shown, at least two dummy subpixels 100d include a first dummy subpixel 100d1, a second dummy subpixel 100d2, and a third dummy subpixel 100d3, and the three dummy data lines dDT of the first dummy subpixel 100d1, the second dummy subpixel 100d2, and the third dummy subpixel 100d3 are connected to each other. Figure 40 The diagram shows three dummy data lines dDT that are connected to each other.

[0338] For example, such as Figures 3 to 5 As shown, the display substrate also includes a first power line PL1, and the pixel circuit 100a also includes a light-emitting control transistor T5. The first terminal of the light-emitting control transistor T5 is connected to the first power line PL1, and the second terminal of the light-emitting control transistor T5 is connected to the second terminal of the driving transistor T3.

[0339] For example, such as Figure 38 and Figure 39 As shown, the virtual sub-pixel 100d also includes a virtual light-emitting control transistor dT5. The first terminal of the virtual light-emitting control transistor dT5 is disconnected from the first power supply line PL1, and the second terminal of the virtual light-emitting control transistor dT5 is connected to or disconnected from the second terminal of the virtual driving transistor T3.

[0340] like Figure 39 As shown, in the dashed box F1 (corresponding to Figure 5 No via is provided at via V7 in the configuration, thus disconnecting the dummy reset transistor dT2 from the initialization line INT1. For example... Figure 39 As shown, in the dashed box F2 (corresponding to Figure 5 No via is provided within the via VH location, thus causing the dummy pixel circuit 100da to disconnect from the dummy light-emitting element 100db. For example... Figure 39 As shown, in the dashed box F3 (corresponding to Figure 5 No via is provided at via V11 in the circuit, thus the first terminal of the dT5 light-emitting control transistor is disconnected from the first power supply line PL1. Figure 39 As shown, in the dashed box F4 (corresponding to Figure 5No via is provided in the via V13, so the second terminal of the dummy light-emitting control transistor dT5 is disconnected from the second terminal of the dummy driving transistor T3. Of course, in order to make the second terminal of the dummy light-emitting control transistor dT5 and the second terminal of the dummy driving transistor T3 disconnected, a via needs to be provided at the corresponding position, and the same applies to other positions.

[0341] For example, such as Figure 5 , Figure 6 , Figure 33A and Figure 33B As shown, the display substrate also includes a pixel defining layer PDL, which includes a defining portion 300. A pixel opening P0 is defined by the defining portion 300. The light-emitting element 100b includes a first electrode E1 and a light-emitting functional layer FL. The pixel defining layer PDL is configured to expose at least a portion of the first electrode E1. At least a portion of the light-emitting functional layer FL covers the sidewall SW of the defining portion 300 (e.g., ...). Figure 6 (As shown). Figure 6 The example described uses the scenario where all light-emitting functional layers FL are located within pixel openings P0. In other embodiments, the light-emitting functional layers FL may include a common layer, such as... Figure 45 As shown.

[0342] For example, such as Figure 6 As shown, the light-emitting element 100b also includes a second electrode E2, and the light-emitting functional layer FL is located between the first electrode E1 and the second electrode E2. The second electrode E2 is in contact with the top wall of the limiting portion 300. Of course, as... Figure 45 As shown, when the light-emitting functional layer FL includes a common layer, the second electrode E2 is in contact with the common layer in the light-emitting functional layer FL. For example, the second electrode E2 is in contact with the common layer in the light-emitting functional layer FL that is close to the second electrode E2. Figure 45 The common layer in the array is the electron-injected layer (EIL). For example... Figure 6 and Figure 45 As shown, the orthographic projection of the second electrode E2 on the substrate BS overlaps with the orthographic projection of the top wall of the limiting portion 300 on the substrate BS.

[0343] For example, such as Figure 6 As shown, the display substrate also includes an insulating layer ISL. The first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a through a via VH penetrating the insulating layer ISL. The orthographic projection of the via VH on the substrate BS overlaps with the orthographic projection of the first limiting portion 301 on the substrate BS. Figure 6 , Figure 33A and Figure 33B As shown, the limiting part 300 includes a first limiting part 301 and a second limiting part 302, and the thickness H1 of the first limiting part 301 is smaller than the thickness H2 of the second limiting part 302.

[0344] Figure 41A This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example, such as... Figure 41A As shown, the display substrate also includes a dummy pixel limiting layer dPDL. The dummy pixel limiting layer dPDL includes a plurality of dummy limiting portions d300 (second dummy limiting portions d302) arranged along the second direction X. The extension direction of the second dummy limiting portions d302 is the same as the extension direction of the second limiting portions 302. The distance W4 between two adjacent dummy limiting portions d300 (second dummy limiting portions d302) is greater than the distance W3 between two adjacent second limiting portions 302. Figure 41A A plurality of first dummy limiting portions d301 extending along the second direction X are also shown. As shown in FIG41, a plurality of first dummy limiting portions d301 are provided between adjacent second dummy limiting portions d302. Figure 41A The display area R01 and the peripheral area R02 are shown. The spacing W4 is greater than the spacing W3, which facilitates wiring in the peripheral area R02. For example, the spacing W4 can be the maximum spacing, meaning the maximum spacing W4 between two adjacent dummy limiting portions d300 is greater than the maximum spacing W3 between two adjacent second limiting portions 302. Alternatively, the spacing W4 can be the minimum spacing, meaning the minimum spacing W4 between two adjacent dummy limiting portions d300 is greater than the minimum spacing W3 between two adjacent second limiting portions 302. Figure 41A The example given is three columns of dummy sub-pixels 100d between two adjacent second dummy limiting portions d302. However, this is not the only example; one, two, or more than three columns of dummy sub-pixels 100d may also be provided between two adjacent second dummy limiting portions d302. That is, at least one column of dummy sub-pixels 100d may be provided between two adjacent second dummy limiting portions d302.

[0345] It should be noted that, Figure 41A Taking the peripheral region R02 as an example, which has a first dummy limiting part d301 extending along the second direction X, but not limited thereto, in some embodiments, the peripheral region R02 may not have the first dummy limiting part d301. In this case, the dummy pixel limiting layer dPDL only includes the second dummy limiting part d302.

[0346] For example, such as Figure 41A As shown, the spacing W4 between two adjacent dummy limiting portions d300 is 2 to 20 times the spacing W3 between two adjacent second limiting portions 302. When multiple columns of dummy sub-pixels 100d are provided between two adjacent second limiting portions 302, the spacing W4 can be a multiple of the spacing W3.

[0347] like Figure 41AAs shown, the width W6 of the second dummy limiting part d302 in the second direction X is greater than the width W5 of the second limiting part 302 in the second direction X. For example, widths W6 and W5 can refer to the maximum width. Of course, widths W6 and W5 can also refer to the minimum width.

[0348] Figure 41B This is a schematic diagram of a display substrate provided for another embodiment of this disclosure. (See diagram below.) Figure 41B As shown, the width W6 is greater than the width W5. This can be referenced. Figure 41A The description. Figure 41B The following explanation will be based on the example of a column of dummy sub-pixels 100d located between two adjacent second dummy limiting parts d302. Figure 41B The dummy pixel limiting layer dPDL in the middle may also contain only the second dummy limiting part d302, without setting the first dummy limiting part d301.

[0349] Of course, in some other embodiments, the width W6 can be equal to the width W5.

[0350] Figure 42 This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example, such as... Figures 3 to 5 ,as well as Figure 42 As shown, the display substrate also includes a reset transistor T4, an initialization line INT2, and an initialization bus 504. The initialization bus 504 is located outside the display area R01 of the display substrate. The first terminal of the reset transistor T4 is connected to the initialization bus 504. The first terminal T4a of the reset transistor T4 is connected to the initialization bus 504 through the initialization line INT2. The second terminal T4b of the reset transistor T4 is connected to the light-emitting element 100b through the driving transistor T3. The reset transistor T4 is connected to a row of sub-pixels 100. For the same row of sub-pixels 100, in order to reduce power consumption, the number of reset transistors T4 is less than the number of sub-pixels 100. Figure 42 The following explanation uses the example of one reset transistor T4 corresponding to one row of sub-pixels.

[0351] like Figure 42 As shown, the second terminal of the reset transistor T4 is connected to the reset signal transmission line INI. Figure 42 As shown, the reset signal transmission line INI is connected to sub-pixel 100. Figure 5 As shown, the reset signal transmission line INI is connected to the first electrode E1 of the light-emitting element 100b via the driving transistor T3. (Reference) Figures 5 to 8E The second terminal T5b of the light-emitting control transistor T5 is connected to the second terminal T3b of the driving transistor T3 through the reset signal transmission line INI.

[0352] like Figure 42 As shown, the reset transistor T4 is located in the peripheral region R02. Figure 42 As shown, the initialization bus 504 is located in the peripheral area R02.

[0353] Figure 43 This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example, such as... Figure 5 and Figure 43 As shown, the display substrate also includes a light-emitting control transistor T5, a first power line PL1, and a first power bus 501. The first power line PL1 is configured to provide a first voltage signal to the pixel circuit 100a. The first power line PL1 is connected to the first power bus 501. The first power line PL1 includes a first power connection line PL12 extending along the first direction Y and a first power signal line PL11 extending along the second direction X. The first terminal of the light-emitting control transistor T5 is connected to the first power line PL1, and the second terminal of the light-emitting control transistor T5 is connected to the second terminal of the driving transistor T3. The number of light-emitting control transistors T5 in a row of sub-pixels 100 can be equal to the number of sub-pixels 100 in that row.

[0354] Figure 44 This is a circuit diagram of a display substrate provided according to an embodiment of the present disclosure. Figure 44 As shown, the number of light-emitting control transistors T5 in a row of sub-pixels 100 is less than the number of sub-pixels 100 in that row. For example, all three sub-pixels 100 in a pixel PX are connected to the same light-emitting control transistor T5.

[0355] For example, if all three sub-pixels 100 in each pixel PX are connected to the same light-emitting control transistor T5, and different pixels PX are connected to different light-emitting control transistors T5, the number of light-emitting control transistors T5 in a row of sub-pixels 100 is greater than the number of reset transistors T4.

[0356] refer to Figures 3 to 6 , Figures 9 to 14The present disclosure also provides a display substrate, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS; each sub-pixel 100 includes: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first plate of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a, the pixel circuit 100a being configured to drive the light-emitting element 100b, each sub-pixel 100 including a pixel opening P0, the pixel opening P0 being configured to define the light-emitting area of ​​the sub-pixel 100, and the orthographic projection of the storage capacitor Cst onto the substrate BS and the pixel opening P0 onto the substrate BS. The orthographic projections on S overlap, the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, the second electrode Cb is disposed on the same layer as the channel of the driving transistor T3, the second electrode Cb is closer to the substrate BS than the first electrode Ca, and the display substrate satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and P=k0*(W / L)*Uc, the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, S2 is the area of ​​the second electrode Cb and the first electrode Ca facing each other, M1 is the number of pixel openings P0 of the display substrate, M2 is the area of ​​the display substrate, Uc is the voltage across the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0357] The display substrate provided in the embodiments of this disclosure satisfies the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], and P=k0*(W / L)*Uc, so as to obtain a display substrate with lower power consumption.

[0358] refer to Figures 3 to 6 , Figures 9 to 14 , Figure 33A , Figure 33B ,as well as Figure 34As shown, embodiments of this disclosure also provide a display substrate, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS; each sub-pixel 100 includes: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first terminal of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a, the pixel circuit 100a being configured to drive the light-emitting element 100b, each sub-pixel 100 including a pixel opening P0, the pixel opening P0 being configured to define the light-emitting area of ​​the sub-pixel 100, the orthographic projection of the storage capacitor Cst on the substrate BS overlapping the orthographic projection of the pixel opening P0 on the substrate BS, and the driving transistor... The orthographic projection of the channel of the body transistor T3 onto the substrate BS overlaps with the orthographic projection of the pixel opening P0 onto the substrate BS. The second electrode Cb is disposed on the same layer as the channel of the driving transistor T3. The second electrode Cb is closer to the substrate BS than the first electrode Ca. A first limiting part 301 is disposed between two adjacent pixel openings P0 in the first direction Y, and a second limiting part 302 is disposed between two adjacent pixel openings P0 in the second direction X. The first direction Y and the second direction X intersect. The thickness of the first limiting part 301 is H1, and the thickness of the second limiting part 302 is H2, H1≠H2. The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the voltage across the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0359] refer to Figures 3 to 6 , Figures 9 to 14 , Figure 33A , Figure 33B ,as well as Figure 36As shown, embodiments of this disclosure also provide a display substrate, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS; each sub-pixel 100 includes: a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst. The storage capacitor Cst includes a first plate Ca and a second plate Cb. The first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst is connected to the first terminal of the driving transistor T3. The light-emitting element 100b is electrically connected to the pixel circuit 100a. Circuit 100a is configured to drive light-emitting element 100b. Sub-pixel 100 includes pixel opening P0, which is configured to define the light-emitting area of ​​sub-pixel 100. The orthographic projection of storage capacitor Cst on substrate BS overlaps with the orthographic projection of pixel opening P0 on substrate BS. The orthographic projection of channel of driving transistor T3 on substrate BS overlaps with the orthographic projection of pixel opening P0 on substrate BS. Second electrode Cb is disposed in the same layer as channel of driving transistor T3. Second electrode Cb is closer to substrate BS than first electrode Cb. The display substrate also includes insulating layer ISL and barrier dam. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2. The first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a through a via VH penetrating the insulating layer ISL. The encapsulation layer EPS is configured to encapsulate the light-emitting element 100b. The encapsulation layer EPS includes a stack of inorganic encapsulation films and organic encapsulation films. An encapsulating adhesive 702 is provided on the outer side of the encapsulation layer EPS. The insulating layer ISL includes a planarization layer PLN. The planarization layer PLN includes a first planarization portion PLN1 and a second planarization portion PLN2. A groove GR is provided between the first flat portion PLN1 and the second flat portion PLN2. A blocking dam 701 is located around the display area R01 of the display substrate. The orthographic projection of the blocking dam 701 on the substrate BS covers the orthographic projection of the groove GR on the substrate BS. The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the voltage across the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0360] The display substrate provided in the embodiments of this disclosure satisfies the following relationship: P = k0*(W / L)*Uc, which is beneficial to obtain a display substrate with lower power consumption. The orthogonal projection of the blocking dam 701 on the substrate BS covers the orthogonal projection of the groove GR on the substrate BS, so as to reduce and prevent water and oxygen from entering the display area R01 along the planarization layer PLN and avoid affecting the light-emitting elements in the display area R01.

[0361] refer to Figures 3 to 5 , Figures 9 to 13 The present disclosure also provides a display substrate, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS; each sub-pixel 100 includes: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first plate of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a, the pixel circuit 100a being configured to drive the light-emitting element 100b, and each sub-pixel 100 including a pixel opening P0, the pixel opening P0 being configured to define The light-emitting area of ​​sub-pixel 100 has an orthographic projection of the storage capacitor Cst on the substrate BS overlapping with the orthographic projection of the pixel opening P0 on the substrate BS. The orthographic projection of the channel of the driving transistor T3 on the substrate BS also overlaps with the orthographic projection of the pixel opening P0 on the substrate BS. The second electrode Cb is disposed on the same layer as the channel of the driving transistor T3. The second electrode Cb is closer to the substrate BS than the first electrode Ca. The display substrate satisfies the following relationship: P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the voltage across the light-emitting element 100b, and P is the power consumption of sub-pixel 100.

[0362] The display substrate provided in the embodiments of this disclosure satisfies the following relationship: P = k0*(W / L)*Uc, which is beneficial to obtaining a display substrate with lower power consumption. The second electrode plate Cb is disposed on the same layer as the channel of the driving transistor T3, which is beneficial to improve the retention capability of the capacitor, and also beneficial to improve the ratio of the area of ​​the storage capacitor to the area of ​​the pixel opening, improve the area ratio of the storage capacitor, and improve the display quality.

[0363] Embodiments of this disclosure also provide a display substrate, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS; each sub-pixel 100 includes: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first terminal of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a. Pixel circuit 100a is configured to drive light-emitting element 100b. Sub-pixel 100 includes pixel opening P0, which is configured to define the light-emitting area of ​​sub-pixel 100. The orthographic projection of storage capacitor Cst on substrate BS overlaps with the orthographic projection of pixel opening P0 on substrate BS. The orthographic projection of channel of driving transistor T3 on substrate BS overlaps with the orthographic projection of pixel opening P0 on substrate BS. Second electrode Cb is disposed on the same layer as channel of driving transistor T3, and second electrode Cb is closer to substrate BS than first electrode Cb. The display substrate also includes data lines. The pixel circuit 100a includes a data writing transistor T1 and a reset transistor T2. The first terminal of the data writing transistor T1 is connected to the data line DT. The gate of the driving transistor T3 is connected to the second terminal of the data writing transistor T1, and the gate of the data writing transistor T1 is connected to the gate line G1. The first terminal of the reset transistor T2 is connected to the initialization line INT1. The second terminal of the reset transistor T2 is connected to the gate of the driving transistor T3, and the gate of the reset transistor T2 is connected to the gate line G2. The display substrate has a [missing information - likely a feature or design feature] near its edge. A dummy sub-pixel 100d has a dummy driving transistor T3 and a dummy reset transistor dT2. The gates of the dummy reset transistor dT2 and the dummy driving transistor T3 are connected, and the dummy reset transistor dT2 is disconnected from the initialization line INT1. The display substrate satisfies the following relationship: P = k0 * (W / L) * Uc, where the value of k0 ranges from [2.8 * E-07, 5.8 * E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the voltage across the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0364] The display substrate provided in the embodiments of this disclosure satisfies the following relationship: P = k0*(W / L)*Uc, which is beneficial to obtaining a display substrate with lower power consumption. Furthermore, the dummy reset transistor dT2 is disconnected from the initialization line INT1, which is beneficial to reduce power consumption.

[0365] Embodiments of this disclosure also provide a display substrate, including: a substrate BS and a plurality of sub-pixels 100 disposed on the substrate BS; each sub-pixel 100 includes: a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first terminal of the driving transistor T3; the light-emitting element 100b is electrically connected to the pixel circuit 100a, the pixel circuit 100a being configured to drive the light-emitting element 100b, and each sub-pixel 100 including a pixel opening P0, the pixel opening P0 being configured to define the sub-pixel 100. The light-emitting area, the orthographic projection of the storage capacitor Cst on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, the orthographic projection of the channel of the driving transistor T3 on the substrate BS overlaps with the orthographic projection of the pixel opening P0 on the substrate BS, the second electrode Cb is disposed in the same layer as the channel of the driving transistor T3, the second electrode Cb is closer to the substrate BS than the first electrode Cb, the display substrate also includes a pixel defining layer PDL, the pixel defining layer PDL includes a defining portion 300, the pixel opening P0 is defined by the defining portion 300, the light-emitting element 100b includes a first electrode E1 and a light-emitting functional layer FL, the pixel defining layer PDL is configured to expose at least a portion of the first electrode E1, the light-emitting functional layer FL covers the sidewall SW of the defining portion 300 (e.g., Figure 6 As shown), the display substrate satisfies the following relationship: P=k0*(W / L)*Uc, where the value range of k0 is [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the voltage across the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0366] The display substrate provided in the embodiments of this disclosure has a light-emitting functional layer FL covering the sidewall SW of the limiting portion 300 and satisfying the following relationship: P=k0*(W / L)*Uc, so as to obtain a display substrate with lower power consumption.

[0367] For example, in some embodiments, the first voltage signal VDD is 17V, the second voltage signal VSS is 2V, k0 = 2.8 * E-07, W = 2 micrometers, L = 30 micrometers, and Uc = 15V. Then, according to P = k0 * (W / L) * Uc, P = 2.8 * E-07 watts.

[0368] The power consumption P mentioned above refers to the power consumption of a single sub-pixel. For sub-pixels emitting different colors of light, differentiated designs can be implemented to solve the power consumption matching problem of different colored sub-pixels and reduce the overall panel power consumption. For example, for red, green, and blue sub-pixels, the power consumption of the red sub-pixel is less than that of the green sub-pixel, and the power consumption of the green sub-pixel is less than that of the blue sub-pixel, to solve the three-color power consumption matching problem and reduce the overall panel power consumption.

[0369] For example, in any of the above display substrates that satisfy P=k0*(W / L)*Uc, the display substrate can also satisfy the following relationship: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], S2 is the area of ​​the second electrode Cb and the first electrode Ca facing each other, M1 is the number of pixel openings P0 of the display substrate, and M2 is the area of ​​the display substrate, so as to facilitate the formation of a display substrate with better performance using inkjet printing technology.

[0370] For example, in the embodiments of this disclosure, the display substrate may satisfy at least one of the following: the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], the value range of S2 / (W*L) is [2.82, 28.85], and P=k0*(W / L)*Uc. The meaning of each formula can be referred to the previous description, and will not be repeated here.

[0371] In the embodiments of this disclosure, "*" in the formula represents a multiplication sign, " / " represents a division sign, the range [Mx, My] represents greater than or equal to Mx and less than or equal to My, Mx and My are numbers, and the numbers with E in [] are values ​​expressed in scientific notation.

[0372] Figure 45 This is a schematic diagram of a display substrate provided for an embodiment of this disclosure. (See diagram below.) Figure 45 As shown, the light-emitting functional layer FL includes a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, and an electron injection layer EIL. The materials of the hole injection layer HIL, the hole transport layer HTL, and the light-emitting layer EML are located in the pixel opening defined by the pixel limiting layer PDL, and the electron injection layer EIL is a common layer. Figure 45 The display substrate also includes a light extraction layer (CPL) to improve light extraction efficiency. For example, the hole injection layer (HIL) and hole transport layer (HTL) can employ gradient doping or be arranged in a single-layer stack. Of course, the structure of the display substrate provided in the embodiments of this disclosure is not limited to this. Figure 45 As shown.

[0373] Figure 46 This is a schematic diagram illustrating a brightness test of a display substrate according to an embodiment of this disclosure. Figure 46As shown, the display substrate includes a display area R01 and a peripheral area R02, with sub-pixels located within the display area R01. Multiple test points are selected from the display area. Figure 46 Nine test points were selected, and the brightness of each test point could be measured. Figure 46 This shows that a subpixel can be divided into multiple subpixel groups PG. Figure 46 Subpixel groups PG1, PG2, and PG3 are shown. For example, in some embodiments, each subpixel group PG may correspond to one or more rows of subpixels. For example, in some embodiments, each subpixel group PG may correspond to one or more columns of subpixels.

[0374] like Figure 46 As shown, the first to third test points are three test points at different positions of sub-pixel group PG1, the fourth to sixth test points are three test points at different positions of sub-pixel group PG2, and the seventh to ninth test points are three test points at different positions of sub-pixel group PG3.

[0375] For example, the brightness of a subpixel in each subpixel group PG can be the average brightness of the test points corresponding to that subpixel group PG. Figure 46 As shown, the brightness of the sub-pixels in sub-pixel group PG1 is the average of the brightness values ​​of the first test point, the second test point, and the third test point; the brightness of the sub-pixels in sub-pixel group PG2 is the average of the brightness values ​​of the fourth test point, the fifth test point, and the sixth test point; and the brightness of the sub-pixels in sub-pixel group PG3 is the average of the brightness values ​​of the seventh test point, the eighth test point, and the ninth test point.

[0376] like Figure 46 As shown, for the same sub-pixel group, the test point located in the middle position can be the middle position of the test point near the boundary of the display area. For example, the distance from the second test point to the first test point is equal to the distance from the second test point to the third test point. Correspondingly, the distance from the fifth test point to the fourth test point is equal to the distance from the fifth test point to the sixth test point, and the distance from the eighth test point to the seventh test point is equal to the distance from the eighth test point to the ninth test point.

[0377] For example, such as Figure 46 As shown, when testing the brightness of the entire display substrate, the distance between the fourth test point and the first test point is equal to the distance between the fourth test point and the seventh test point, the distance between the fifth test point and the second test point is equal to the distance between the fifth test point and the eighth test point, the distance between the sixth test point and the third test point is equal to the distance between the sixth test point and the ninth test point, but not limited to these.

[0378] like Figure 46As shown, the following principles can be adopted when selecting test points. Figure 46 The length Ly and width Lx of the display area R01 are shown. The distance Lx0 between the test point and the boundary of the display area R01 in the second direction X is greater than or equal to Lx / 10, and the distance Ly0 between the test point and the boundary of the display area R01 in the first direction Y is greater than or equal to Ly / 10.

[0379] like Figure 24 and Figure 29 As shown, the data line DT includes data line DT1, data line DT2, and data line DT3. Data line DT1 provides a data signal to the first sub-pixel 101, data line DT2 provides a data signal to the second sub-pixel 102, and data line DT3 provides a data signal to the third sub-pixel 103.

[0380] like Figure 5 , Figure 24 and Figure 29 As shown, the pixel circuit 100a uses two conductive pattern layers to form the first power line PL1 and the initialization line INT1. The portions of the first power line PL1 and the initialization line INT1 extending along the first direction Y are both formed in segments. The portions of the first power line PL1 and the initialization line INT1 extending along the second direction X are both located in the second conductive pattern layer LY2.

[0381] like Figure 5 , Figure 24 and Figure 29 As shown, the signal connection line 412 includes at least one of the first power connection line PL12 and the initialization connection line INT12.

[0382] For example, such as Figure 24 and Figure 29 As shown, the display substrate also includes a data line DT, which is configured to provide a data voltage to the sub-pixel 100. The orthographic projection of at least one of the signal connection line 412 and the data line DT on the substrate BS overlaps with the orthographic projection of the pixel opening P0 of at least one of the plurality of sub-pixels 100 on the substrate BS.

[0383] When inkjet printing is performed, the flatter the bottom surface of the pixel opening P0 of sub-pixel 100 (i.e., the first electrode E1 of the light-emitting element), the more color deviation can be reduced or avoided, and the better the display effect of the display substrate.

[0384] The portion of the data line DT or signal connection line 412 located directly below the pixel opening P0 in the second conductive pattern layer LY2 can act as a leveling layer to improve display quality.

[0385] For example, signal connection line 412 includes at least one of the portion of the first power line PL1 extending along the first direction Y and the portion of the initialization line extending along the first direction Y.

[0386] For example, such as Figure 5 , Figure 24 and Figure 29 As shown, signal connection line 412 and signal transmission line 411 are connected through vias.

[0387] For example, such as Figure 5 , Figure 24 and Figure 29 As shown, to level the bottom surface of the pixel opening P0 of the sub-pixel 100, the display substrate further includes a signal transmission line 512. The signal transmission line 512 is configured to provide a voltage signal to the sub-pixel 100. The signal transmission line 512 extends along a second direction X, and its orthographic projection on the substrate BS overlaps with the orthographic projection of the pixel opening P0 of at least one of the sub-pixels 100 on the substrate BS. This facilitates the vertical leveling of ink during inkjet printing and reduces color shift at different viewing angles.

[0388] For example, refer to Figure 5 , Figure 24 and Figure 29 The signal transmission line 512 includes at least one of the gate line G1, the gate line G2, and the portion of the initialization line INT11 extending along the second direction X.

[0389] In the embodiments of this disclosure, the pixel circuit 100a may not include at least one of the reset transistor T4 and the light-emitting control transistor T5, and the structure of the pixel circuit 100a is not limited to that shown in the figure, and can be configured as needed.

[0390] In the accompanying drawings of the embodiments of this disclosure, the example given is that the orthographic projection of the pixel opening P0 of the sub-pixel on the substrate and the orthographic projection of the via VH on the substrate do not overlap. However, in other embodiments, the orthographic projection of the pixel opening P0 of the sub-pixel on the substrate and the orthographic projection of the via VH on the substrate may overlap.

[0391] For example, in embodiments of this disclosure, the design of the backplane film layer, such as the design of the elements in the second conductive pattern layer, can be used to adapt the pixel openings of different sizes of sub-pixels to improve the flatness of the light-emitting functional layer and thereby reduce the color shift of the display substrate from the left and right viewing angles.

[0392] Since subpixels that emit different colors of light have different luminous efficiencies, color shift and display quality can be reduced and improved by adjusting the size of the pixel aperture of the subpixel, adjusting the size of the third plate of the storage capacitor, and making the aperture and signal line overlap.

[0393] For example, in embodiments of this disclosure, the thickness of an element refers to the dimension of the element in a direction perpendicular to the substrate.

[0394] For example, in some embodiments, the pixel opening P0 of the first sub-pixel 101 has a size of 28-36 micrometers in the second direction X, the pixel opening P0 of the second sub-pixel 102 has a size of 30-38 micrometers in the second direction X, and the pixel opening P0 of the third sub-pixel 103 has a size of 68-74 micrometers in the second direction X. Of course, the size of the pixel opening P0 of the sub-pixel 100 is not limited to this and can be determined as needed.

[0395] For example, refer to Figure 6 The insulating layer ISL comprises a passivation layer PVX and a planarization layer PLN. The passivation layer PVX is made of inorganic insulating materials, while the planarization layer PLN is made of organic insulating materials. For example, the thickness of the planarization layer PLN is 3-7 micrometers.

[0396] The display substrate provided in the embodiments of this disclosure can reduce color shift to less than 0.015 at left and right viewing angles. Furthermore, in the display substrate provided in the embodiments of this disclosure, by making the pixel opening of the sub-pixel overlap with the signal connection line (designing the position of the vertical wiring), the color shift problem of the second sub-pixel (green sub-pixel) is significantly improved, and the deviation at 60-degree left and right viewing angles is small.

[0397] In typical inkjet-printed products, the planarization layer (PLN) is thicker than in vapor-deposited products. However, the display substrate provided in the embodiments of this disclosure, through a backplane design, allows for a limited reduction in the thickness of the planarization layer. This, in turn, reduces the width of the vias (VH) to significantly improve color shift. For example, in the embodiments of this disclosure, the thickness of the planarization layer is 3-7 micrometers.

[0398] For example, Figure 6 The insulating layer (ISL) shown can be composed of inorganic or organic material layers, or a combination of organic and organic material layers. The fabrication of vias in the ISL is not limited to a single fabrication; to reduce the via diameter, multiple fabrications are used to create a nested structure, which facilitates the flatness of the light-emitting functional layer and thus reduces color shift. For example, the ratio of the diameter of the uppermost via to the width of the sub-pixel's pixel opening is less than 0.3. The width of the sub-pixel's pixel opening can refer to the maximum dimension of the sub-pixel's pixel opening in the second direction X.

[0399] For example, gate line G1 can be called the first gate line, gate line G2 can be called the second gate line, gate line G4 can be called the third gate line, reset transistor T2 can be called the first reset transistor, and reset transistor T4 can be called the second reset transistor. In this configuration, the display substrate further includes: a data line, a first gate line, a second gate line, a third gate line, a first power line, a first initialization line, and a second initialization line. The data line is configured to provide a data voltage to the pixel circuit; the first gate line is configured to provide a scan signal to the pixel circuit; the second gate line is configured to provide a first reset control signal to the pixel circuit; the third gate line is configured to provide a second reset control signal to the pixel circuit; the first power line is configured to provide a first voltage signal to the pixel circuit; the first initialization line is configured to provide a first initialization signal to the pixel circuit; and the second initialization line is configured to provide a second initialization signal to the pixel circuit. The pixel circuit further includes a data writing transistor, a first reset transistor, and a second reset transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the data writing transistor is connected to the first gate line, and the second terminal of the data writing transistor is connected to the gate of the driving transistor. The first terminal of the first reset transistor is connected to the first initialization line, and the second terminal of the first reset transistor is connected to the second initialization line. The first power line is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line; the first electrode of the second reset transistor is connected to the second initialization line, the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element, and the gate of the second reset transistor is connected to the third gate line; the first power line includes a first power signal line extending along the second direction and a first power connection line extending along the first direction, and the first power signal line and the first power connection line are connected; the first initialization line includes a first initialization signal line extending along the second direction and a first initialization connection line extending along the first direction, and the first initialization signal line and the first initialization connection line are connected; the second initialization line includes a second initialization signal line extending along the second direction and a second initialization connection line extending along the first direction, and the second initialization signal line and the second initialization connection line are connected; the orthographic projection of at least one of the first power connection line, the first initialization connection line, and the second initialization connection line on the substrate overlaps with the orthographic projection of the pixel opening of the sub-pixel on the substrate.

[0400] For example, gate line G5 can be referred to as the fourth gate line. The display substrate also includes the fourth gate line and a light-emitting control transistor. The fourth gate line is configured to provide a light-emitting control signal to the light-emitting control transistor. The second electrode of the driving transistor is connected to the first power line through the light-emitting control transistor.

[0401] For example, the active layer of each transistor may include a source region, a drain region, and a channel located between the source region and the drain region. For example, the channel has semiconductor characteristics; the source region and the drain region are on both sides of the channel and may be doped with impurities, and thus have conductivity, and may serve as the first and second electrodes of the transistor, respectively, with one of the first and second electrodes of the transistor being the source and the other being the drain.

[0402] For example, the materials used to fabricate the semiconductor layer (semiconductor pattern) of the active layer may include oxide semiconductors, organic semiconductors, amorphous silicon, polycrystalline silicon, etc. For example, oxide semiconductors include metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO)), and polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc. The embodiments of this disclosure are not limited in this regard. It should be noted that the source region and drain region mentioned above may be regions doped with n-type impurities or p-type impurities, and the embodiments of this disclosure are not limited in this regard.

[0403] For example, the substrate BS, buffer layer BL, barrier layer BR, gate insulating layer GI, interlayer insulating layer ILD, planarization layer PLN, and pixel defining layer PDL are all made of insulating materials. For example, the substrate BS includes flexible materials such as polyimide, but is not limited to these. At least one of the buffer layer BF, barrier layer BR, gate insulating layer GI, and interlayer insulating layer ILD is made of inorganic or organic insulating materials. For example, inorganic insulating materials include silicon oxide, silicon nitride, and silicon oxynitride, while organic insulating materials include resins, but are not limited to these. For example, the pixel defining layer PDL and planarization layer PLN can be made of organic materials, such as resins, but are not limited to these.

[0404] For example, both the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are made of metallic materials, and the specific materials can be determined according to needs. For example, the material of the first conductive pattern layer LY1 includes molybdenum (Mo). The material of the second conductive pattern layer LY2 includes titanium (Ti) and aluminum (Al), and a Ti / Al / Ti three-layer stacked structure can be used, but it is not limited to this.

[0405] For example, the material of the first electrode E1 of the light-emitting element includes a conductive material, such as, but not limited to, at least one of silver (Ag) or indium tin oxide (ITO). For example, the first electrode E1 of the light-emitting element is a three-layer stacked structure of ITO / Ag / ITO, but not limited to. In other embodiments, the material of the first electrode E1 of the light-emitting element includes aluminum (Al) and tungsten oxide (WOx). For example, the first electrode E1 includes a stack of aluminum layer and tungsten oxide layer, and the aluminum layer is closer to the substrate than the tungsten oxide layer.

[0406] For example, the material of the second electrode E2 of the light-emitting element includes conductive materials, such as silver (Ag), but is not limited thereto.

[0407] In the embodiments of this disclosure, the patterns and vias of each single layer can be fabricated using patterning processes. For example, forming a specific pattern includes forming a thin film, forming a photoresist pattern on the thin film, and using the photoresist pattern as a mask to pattern the thin film to form the specific pattern. The first conductive pattern layer LY1, the second conductive pattern layer LY2, the first electrode layer LY3, the third conductive pattern layer LY4, and vias in the insulating layer can all be formed using this method. For the active layer LY0, a semiconductor pattern can be formed first, and then doped using a doping process to form an active layer including a channel, a source region, and a drain region. An insulating layer is then formed on the active layer, and the first conductive pattern layer LY1 is formed on the insulating layer, followed by the sequential formation of subsequent film layers.

[0408] It should be noted that the sub-pixel layout of the display substrate provided in the embodiments of this disclosure is not limited to... Figure 5 As shown, it is possible to Figure 5 Based on this, other layout diagrams can be formed by transformation. The above description uses a pixel circuit with 4T1C sub-pixels as an example, but the embodiments of this disclosure are not limited to this. For example, each sub-pixel 101 may also include other numbers of transistors or other numbers of capacitors. The pixel circuit operates under the control of data signals transmitted through data lines and gate scan signals transmitted through gate lines and light emission control signals provided by light emission control signal lines, so as to drive the light emission element to emit light and thus realize operations such as display.

[0409] It should be noted that the embodiments of this disclosure do not limit the number of thin-film transistors and capacitors included in the pixel circuit.

[0410] The display substrate provided in the embodiments of this disclosure may adopt other suitable layouts, and the wiring method is not limited to that shown in the figures.

[0411] This disclosure provides at least one embodiment of a display device, including any of the display substrates described above. The display device may be a large-size display device, and at least one film layer in the light-emitting functional layer is fabricated using an inkjet printing process.

[0412] For example, the display device can be an organic light-emitting diode (OLED) display device. The display device can be any product or component with a display function, including televisions, digital cameras, mobile phones, watches, tablets, laptops, navigators, etc., which include OLED display devices.

[0413] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate; The sub-pixels include: A pixel circuit includes a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to the gate of the driving transistor; and A light-emitting element is electrically connected to the pixel circuit, and the pixel circuit is configured to drive the light-emitting element. The sub-pixel includes a pixel opening, which is configured to define the light-emitting area of ​​the sub-pixel. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The display substrate satisfies the following relationship: (W L+S2) The value range of M1 / M2 is [0.014, 0.133], and S2 / (W The value range of L is [2.82, 28.85]. Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, S2 is the area of ​​the second electrode and the first electrode facing each other, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

2. The display substrate according to claim 1, wherein, The second plate of the storage capacitor is connected to the first plate of the driving transistor. The storage capacitor also includes a third plate, which is connected to the second plate and is located on opposite sides of the first plate.

3. The display substrate according to claim 1 or 2, wherein, The second electrode plate includes a first plate-shaped portion, which is integrally formed with the channel of the driving transistor.

4. The display substrate according to claim 3, wherein, The second electrode also includes a second plate-shaped portion, the first plate-shaped portion and the second plate-shaped portion are spaced apart from each other, the area of ​​the first plate-shaped portion is larger than the area of ​​the second plate-shaped portion, or both the first plate-shaped portion and the second plate-shaped portion are connected to the channel of the driving transistor.

5. The display substrate according to any one of claims 1-4, wherein, The channel of the driving transistor is made of semiconductor material, and the material of the second electrode plate is a conductor obtained by doping the same semiconductor material as the channel of the driving transistor.

6. The display substrate according to any one of claims 1-5, wherein, The channel of the driving transistor extends along a first direction, the pixel opening has a central axis extending along the first direction, the maximum dimension of the pixel opening along a second direction is W0, the first direction intersects the second direction, and the distance from the channel of the driving transistor to the central axis is D1, 2. The value range of D1 / W0 is [0.2, 0.4] or [0.6, 0.8].

7. The display substrate according to claim 6 further includes a plurality of signal lines located on one side of the storage capacitor, wherein, The signal lines extend along the second direction, and the orthographic projections of the multiple signal lines on the substrate overlap with the orthographic projections of the pixel opening on the substrate. The size of the pixel opening along the first direction is H0, the distance of the farthest edge of the multiple signal lines in the first direction is Hs, and the value range of L / (H0-Hs) is [0.16, 0.61].

8. The display substrate according to claim 7, further comprising a data line, a first gate line, a second gate line, and a first initialization line, wherein, The pixel circuit further includes a data writing transistor and a first reset transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second terminal of the data writing transistor, and the gate of the data writing transistor is connected to the first gate line. The first terminal of the first reset transistor is connected to the first initialization line, the second terminal of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The plurality of signal lines include the first gate line, the second gate line, and the first initialization line.

9. The display substrate according to any one of claims 1-4, wherein, The area of ​​the pixel opening is S0, and the sum of the areas of the second and first electrodes facing each other and the area of ​​the channel of the driving transistor is Ss. The relationship between Ss and S0 satisfies: Ss = A S0+B, where the range of values ​​for A is [0.42, 0.82] and the range of values ​​for B is [-2700, -3100].

10. The display substrate according to claim 2, wherein, The orthographic projection of the pixel opening on the substrate overlaps with the orthographic projection of the third electrode plate on the substrate. The third electrode plate includes a first edge extending along a first direction and a second edge extending along the first direction, and the pixel aperture includes a first edge extending along the first direction and a second edge extending along the first direction. The first edge of the third electrode plate is closer to the first edge of the pixel opening than the second edge of the third electrode plate, and the second edge of the third electrode plate is closer to the second edge of the pixel opening than the first edge of the third electrode plate. The sub-pixel satisfies the following formula: △U = |U02 - U01|, where U01 is the coordinate distance between the chromaticity coordinate point in the first viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, U02 is the coordinate distance between the chromaticity coordinate point in the second viewing angle and the chromaticity coordinate point in the 0-degree viewing angle, and △U is the absolute value of the difference between U02 and U01. The chromaticity coordinate point in the 0-degree viewing angle is the chromaticity coordinate point located at the normal to the center of the display substrate. The first viewing angle and the second viewing angle are located on opposite sides of the normal and their included angles with the normal are equal. And △U≤0.0020.

11. The display substrate according to claim 10, further comprising a first power line, wherein, The first power line is configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending in a first direction and a first power signal line extending in a second direction. The orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The area of ​​the third electrode plate and the first electrode plate facing each other is Sc1, and the area of ​​the intersection of the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the pixel opening on the substrate is Sc2, where Sc2 / Sc1≥0.

9. The width of the first power connection line is W1, the overlap width between the first power connection line and the pixel opening is W2, and W2 / W1≥0.

9.

12. The display substrate according to claim 10, wherein, The maximum size of the pixel opening along the second direction is W0. The first direction intersects the second direction, and the value range of 2×W2 / W0 is [0.71, 0.99]. Furthermore, the range of the voltage Uc / size Lg is [0.32, 0.74]. The voltage Uc is the voltage across the light-emitting element, and the unit of the voltage Uc is volts. The size Lg is the length of the diagonal of the display substrate, and the unit of the size Lg is inches.

13. The display substrate according to claim 11, wherein, The pixel opening has a central axis extending along the first direction, the minimum distance from the first power connection line to the central axis is Xd1, the minimum distance from the third electrode plate to the central axis is Xd2, and the value range of Xd1 / Xd2 is [0.9, 1.1].

14. The display substrate according to claim 10, further comprising a plurality of signal lines located on one side of the storage capacitor, wherein, The orthographic projections of the plurality of signal lines on the substrate overlap with the orthographic projections of the pixel opening on the substrate. The plurality of signal lines are arranged along a first direction and extend along a second direction. The first direction intersects the second direction. The distance between the third electrode plate and the closest signal line is Xd3. The linewidth of the signal line is Xd4. The value range of Xd3 / Xd4 is [0.9, 1.1].

15. The display substrate according to claim 10, further comprising a first power line, wherein, The first power line is configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending in a first direction and a first power signal line extending in a second direction. The pixel opening has a central axis extending in the first direction. The minimum distance from the first power connection line to the central axis is Xd1. The minimum distance between the first power connection line and the third electrode plate is Xd0. DP = |Xd1 - Xd0| / 2. The maximum size of the pixel opening in the second direction is W0. The value range of DP / W0 is [0.01, 0.19].

16. The display substrate according to claim 10, further comprising a first signal line, wherein, The first signal line extends along a first direction, the sub-pixel includes a first sub-pixel and a second sub-pixel adjacent in a second direction, the first direction intersects the second direction, the first signal line is configured to provide a data signal to the pixel circuit of the first sub-pixel, the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel are spaced apart, and the first signal line is located between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel.

17. The display substrate according to claim 16, wherein, The minimum distances between the pixel opening of the first sub-pixel and the pixel opening of the second sub-pixel and the first signal line are Xa1 and Xa2, respectively, and the value range of Xa1 / Xa2 is [0.8, 1.2].

18. The display substrate according to claim 16, further comprising a second signal line, wherein, The second signal line extends along the first direction, and the first signal line and the second signal line are located on opposite sides of the same third electrode plate. The orthographic projection of the second signal line on the substrate overlaps with the orthographic projection of the pixel opening of the second sub-pixel on the substrate.

19. The display substrate according to claim 18, wherein, The distance between the third electrode plate and the second signal line is Xa3, and the distance between the third electrode plate and the first signal line is Xa4. The value range of Xa3 / Xa4 is [0.8, 1.2].

20. The display substrate according to claim 18, further comprising a third signal line, wherein, The third signal line extends along the first direction. The orthographic projection of the third signal line on the substrate overlaps with the orthographic projection of the pixel opening of the first sub-pixel on the substrate. The minimum distance between the third plate of the first sub-pixel and the third signal line is Xa5, and the minimum distance between the third signal line and the first signal line is Xa6. The value range of Xa5 / Xa6 is [0.8, 1.2].

21. The display substrate according to claim 20, wherein, The first signal line includes a data line, and at least one of the second signal line and the third signal line includes a first power connection line.

22. The display substrate according to any one of claims 1-4, further comprising a data line and a first power line, wherein, The data line is configured to provide a data voltage to the pixel circuit, and the data line extends along a first direction. The first power line is configured to provide a first voltage signal to the pixel circuit, and the first power line includes a first power connection line extending along the first direction and a first power signal line extending along the second direction. The sub-pixel includes a first sub-pixel and a second sub-pixel that are adjacent in the second direction. The orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the pixel opening of the first sub-pixel on the substrate, and also overlaps with the orthographic projection of the pixel opening of the second sub-pixel on the substrate.

23. The display substrate according to claim 22, wherein, Two data lines are respectively located on both sides of the first power connection line. The orthographic projections of the two data lines on the substrate overlap with the orthographic projections of the pixel openings of the first sub-pixel and the second sub-pixel on the substrate.

24. The display substrate according to claim 22, wherein, Two data lines are respectively located on both sides of the first power connection line. The orthographic projection of the two data lines on the substrate does not overlap with the orthographic projection of the pixel opening of the first sub-pixel on the substrate, and does not overlap with the orthographic projection of the pixel opening of the second sub-pixel on the substrate.

25. The display substrate according to any one of claims 1-4, further comprising a first power line, wherein, The first power line is configured to provide a first voltage signal to the pixel circuit. The first power line includes a first power connection line extending in a first direction and a first power signal line extending in a second direction. The orthographic projection of the first power connection line on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The maximum size of the pixel opening along the second direction is W0. The sub-pixel includes a first sub-pixel and a second sub-pixel that are adjacent in the second direction. One of the two first power connection lines has a dimension of Xb1 in the second direction, and the other of the two first power connection lines has a dimension of Xb2 in the second direction. The value range of (Xb1+Xb2) / W0 is [0.08, 0.48].

26. The display substrate according to any one of claims 1-4, further comprising a driving circuit, wherein, The driving circuit is located on one side of the display substrate. The sub-pixels away from the driving circuit have a first brightness L1; the sub-pixels close to the driving circuit have a second brightness L2, and the value range of |L1-L2| is [1, 9].

27. The display substrate according to any one of claims 1-4, further comprising two driving circuits, wherein, The two driving circuits are located on opposite sides of the display area of ​​the display substrate. The sub-pixel at the central axis of the display substrate has a third brightness L3, and the sub-pixel near one of the two driving circuits has a fourth brightness L4. The extension direction of the central axis of the display substrate is the same as the extension direction of the driving circuit, and the value range of |L3-L4| is [1, 9].

28. The display substrate according to any one of claims 1-4, wherein, A first limiting portion is provided between two adjacent pixel openings in a first direction, and a second limiting portion is provided between two adjacent pixel openings in a second direction, wherein the first direction intersects the second direction; The thickness of the first limiting part is H1, and the thickness of the second limiting part is H2, where H1 ≠ H2.

29. The display substrate according to claim 28, wherein, H1 is less than H2.

30. The display substrate according to any one of claims 1-4, further comprising an insulating layer, a barrier dam, and an encapsulation layer, wherein, The light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode. The first electrode of the light-emitting element is connected to the pixel circuit through a via penetrating the insulating layer. The encapsulation layer is configured to encapsulate the light-emitting element. The encapsulation layer comprises a stack of inorganic and organic encapsulation films. The outer side of the encapsulation layer is provided with encapsulating adhesive. The insulating layer includes a planarization layer, which comprises a first planarization portion and a second planarization portion, with a groove provided between the first planarization portion and the second planarization portion. The barrier dam is located outside the display area of ​​the display substrate, and the orthographic projection of the barrier dam on the substrate covers the orthographic projection of the groove on the substrate.

31. The display substrate according to any one of claims 1-4, further comprising a data line, a first gate line, a second gate line, and a first initialization line, wherein, The pixel circuit further includes a data writing transistor and a first reset transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second terminal of the data writing transistor, and the gate of the data writing transistor is connected to the first gate line. The first terminal of the first reset transistor is connected to the first initialization line, the second terminal of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The display substrate has dummy sub-pixels near its edge. Each dummy sub-pixel has a dummy driving transistor and a first dummy reset transistor, the gates of which are connected. The first dummy reset transistor is disconnected from the first initialization line.

32. The display substrate according to claim 31, further comprising a dummy data line, wherein, The dummy data line extends along a first direction, and the dummy data line is insulated from the data line. The dummy sub-pixel includes at least two adjacent dummy sub-pixels in the second direction. The dummy data lines of the at least two dummy sub-pixels are connected to each other.

33. The display substrate according to claim 32, wherein, The dummy data line is connected to a constant voltage terminal and configured to provide a constant voltage.

34. The display substrate according to claim 32, wherein, The at least two dummy sub-pixels include a first dummy sub-pixel, a second dummy sub-pixel, and a third dummy sub-pixel. The three dummy data lines of the first dummy sub-pixel, the second dummy sub-pixel, and the third dummy sub-pixel are connected to each other.

35. The display substrate according to any one of claims 31-34, further comprising a first power line, wherein, The pixel circuit further includes a light-emitting control transistor, the first terminal of which is connected to the first power supply line, and the second terminal of which is connected to the second terminal of the driving transistor. The dummy sub-pixel also includes a dummy light-emitting control transistor, wherein the first terminal of the dummy light-emitting control transistor is disconnected from the first power line, and the second terminal of the dummy light-emitting control transistor is connected to the second terminal of the dummy driving transistor.

36. The display substrate according to any one of claims 1-4, further comprising a pixel defining layer, wherein, The pixel defining layer includes a defining portion, the pixel opening is defined by the defining portion, the light-emitting element includes a first electrode and a light-emitting functional layer, and the pixel defining layer is configured to expose at least a portion of the first electrode. The light-emitting functional layer covers the sidewall of the defined portion.

37. The display substrate according to claim 36, wherein, The light-emitting element further includes a second electrode, and the light-emitting functional layer is located between the first electrode and the second electrode, with the second electrode in contact with the top wall of the defining portion.

38. The display substrate according to claim 36, further comprising an insulating layer, wherein, The first electrode of the light-emitting element is connected to the pixel circuit through a via penetrating the insulating layer. The limiting portion includes a first limiting portion and a second limiting portion. The thickness of the first limiting portion is less than the thickness of the second limiting portion. The orthographic projection of the via on the substrate overlaps with the orthographic projection of the first limiting portion on the substrate.

39. The display substrate according to claim 38, further comprising a dummy pixel defining layer, wherein, The dummy pixel limiting layer includes multiple dummy limiting portions, the extension direction of the dummy limiting portions is the same as the extension direction of the second limiting portions, and the spacing between two adjacent dummy limiting portions is greater than the spacing between two adjacent second limiting portions.

40. The display substrate according to claim 39, wherein, The spacing between two adjacent dummy limiting parts is 2 to 20 times the spacing between two adjacent second limiting parts.

41. The display substrate according to any one of claims 1-4, further comprising a second reset transistor, a second initialization line, and an initialization bus, wherein, The initialization bus is located outside the display area of ​​the display substrate. The first terminal of the second reset transistor is connected to the initialization bus via the second initialization line, and the second terminal of the second reset transistor is connected to the light-emitting element via the driving transistor. The second reset transistor is connected to a row of sub-pixels, and for the same row of sub-pixels, the number of the second reset transistors is less than the number of the sub-pixels.

42. The display substrate according to claim 41, further comprising a light-emitting control transistor, a first power line, and a first power bus, wherein, The first power line is configured to provide a first voltage signal to the pixel circuit, and the first power line is connected to the first power bus. The first terminal of the light-emitting control transistor is connected to the first power supply line, and the second terminal of the light-emitting control transistor is connected to the second terminal of the driving transistor. The number of light-emitting control transistors in a row of sub-pixels is less than the number of sub-pixels in that row.

43. The display substrate according to claim 42, wherein, The number of light-emitting control transistors in a row of sub-pixels is greater than the number of second reset transistors.

44. The display substrate according to any one of claims 3-4 and 12, wherein, The second electrode plate is disposed on the same layer as the channel of the driving transistor. The second electrode plate is closer to the substrate than the first electrode plate. The orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the pixel opening on the substrate.

45. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate; The sub-pixels include: A pixel circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first plate and a second plate. The first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first plate of the driving transistor. A light-emitting element is electrically connected to the pixel circuit, and the pixel circuit is configured to drive the light-emitting element. The sub-pixel includes a pixel opening, which is configured to define the light-emitting area of ​​the sub-pixel. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed on the same layer as the channel of the driving transistor, and the second electrode plate is closer to the substrate than the first electrode plate. A first limiting portion is provided between two adjacent pixel openings in a first direction, and a second limiting portion is provided between two adjacent pixel openings in a second direction, wherein the first direction intersects the second direction; The thickness of the first limiting part is H1, and the thickness of the second limiting part is H2, where H1 ≠ H2; The display substrate satisfies the following relationship: S2 / (W The value range of L is [2.82, 28.85]. Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode and the first electrode facing each other.

46. ​​The display substrate according to claim 45, wherein, The display substrate satisfies the following relationship: P=k0 (W / L) Uc, where k0 takes values ​​in the range [2.8]. E-07, 5.8 [E-06], Uc is the voltage across the light-emitting element, and P is the power consumption of the sub-pixel.

47. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate; The sub-pixels include: A pixel circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first plate and a second plate. The first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first plate of the driving transistor. A light-emitting element is electrically connected to the pixel circuit, and the pixel circuit is configured to drive the light-emitting element. The sub-pixel includes a pixel opening, which is configured to define the light-emitting area of ​​the sub-pixel. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed on the same layer as the channel of the driving transistor, and the second electrode plate is closer to the substrate than the first electrode plate. The display substrate further includes an insulating layer, a barrier dam, and an encapsulation layer. The light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode. The first electrode of the light-emitting element is connected to the pixel circuit through a via penetrating the insulating layer. The encapsulation layer is configured to encapsulate the light-emitting element. The encapsulation layer comprises a stack of inorganic and organic encapsulation films. The outer side of the encapsulation layer is provided with encapsulating adhesive. The insulating layer includes a planarization layer, which comprises a first planarization portion and a second planarization portion, with a groove provided between the first planarization portion and the second planarization portion. The barrier dam is located outside the display area of ​​the display substrate, and the orthographic projection of the barrier dam on the substrate covers the orthographic projection of the groove on the substrate. The display substrate satisfies the following relationship: S2 / (W The value range of L is [2.82, 28.85]. Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode and the first electrode facing each other.

48. The display substrate according to claim 47, wherein, The display substrate satisfies the following relationship: P=k0 (W / L) Uc, where k0 takes values ​​in the range [2.8]. E-07, 5.8 [E-06], Uc is the voltage across the light-emitting element, and P is the power consumption of the sub-pixel.

49. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate; The sub-pixels include: A pixel circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first plate and a second plate. The first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first plate of the driving transistor. A light-emitting element is electrically connected to the pixel circuit, and the pixel circuit is configured to drive the light-emitting element. The sub-pixel includes a pixel opening, which is configured to define the light-emitting area of ​​the sub-pixel. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed on the same layer as the channel of the driving transistor, and the second electrode plate is closer to the substrate than the first electrode plate. The display substrate satisfies the following relationship: S2 / (W The value range of L is [2.82, 28.85]. Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode and the first electrode facing each other.

50. The display substrate according to claim 49, wherein, The display substrate satisfies the following relationship: P=k0 (W / L) Uc, where k0 takes values ​​in the range [2.8]. E-07, 5.8 [E-06], Uc is the voltage across the light-emitting element, and P is the power consumption of the sub-pixel.

51. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate; The sub-pixels include: A pixel circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first plate and a second plate. The first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first plate of the driving transistor. A light-emitting element is electrically connected to the pixel circuit, and the pixel circuit is configured to drive the light-emitting element. The sub-pixel includes a pixel opening, which is configured to define the light-emitting area of ​​the sub-pixel. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed on the same layer as the channel of the driving transistor, and the second electrode plate is closer to the substrate than the first electrode plate. The display substrate further includes data lines, a first gate line, a second gate line, and a first initialization line. The pixel circuit further includes a data writing transistor and a first reset transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the driving transistor is connected to the second terminal of the data writing transistor, and the gate of the data writing transistor is connected to the first gate line. The first terminal of the first reset transistor is connected to the first initialization line, the second terminal of the first reset transistor is connected to the gate of the driving transistor, and the gate of the first reset transistor is connected to the second gate line. The display substrate has dummy sub-pixels near its edge. Each dummy sub-pixel has a dummy driving transistor and a first dummy reset transistor, the gates of which are connected. The first dummy reset transistor is disconnected from the first initialization line; The display substrate satisfies the following relationship: S2 / (W The value range of L is [2.82, 28.85]. Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode and the first electrode facing each other.

52. The display substrate according to claim 51, wherein, The display substrate satisfies the following relationship: P=k0 (W / L) Uc, where k0 takes values ​​in the range [2.8]. E-07, 5.8 [E-06], Uc is the voltage across the light-emitting element, and P is the power consumption of the sub-pixel.

53. A display substrate, comprising: A substrate and a plurality of sub-pixels disposed on the substrate; The sub-pixels include: A pixel circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first plate and a second plate. The first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the first plate of the driving transistor. A light-emitting element is electrically connected to the pixel circuit, and the pixel circuit is configured to drive the light-emitting element. The sub-pixel includes a pixel opening, which is configured to define the light-emitting area of ​​the sub-pixel. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the channel of the driving transistor on the substrate overlaps with the orthographic projection of the pixel opening on the substrate. The second electrode plate is disposed on the same layer as the channel of the driving transistor, and the second electrode plate is closer to the substrate than the first electrode plate. The display substrate further includes a pixel defining layer, wherein the pixel defining layer includes a defining portion, the pixel opening is defined by the defining portion, the light-emitting element includes a first electrode and a light-emitting functional layer, and the pixel defining layer is configured to expose at least a portion of the first electrode. The light-emitting functional layer covers the sidewall of the limiting portion. The display substrate satisfies the following relationship: S2 / (W The value range of L is [2.82, 28.85]. Wherein, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the area of ​​the second electrode and the first electrode facing each other.

54. The display substrate according to claim 53, wherein, The display substrate satisfies the following relationship: P=k0 (W / L) Uc, where k0 takes values ​​in the range [2.8]. E-07, 5.8 [E-06], Uc is the voltage across the light-emitting element, and P is the power consumption of the sub-pixel.

55. A display device comprising a display substrate according to any one of claims 1-54.

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