Signal compensation circuit, signal compensation method and display device

Abstract

The present application belongs to the field of display driver technology, and specifically relates to a signal compensation circuit, a signal compensation method and a display device. The signal compensation circuit includes a level detection module, which is used to output a first compensation signal when it detects that a first link maintenance signal on the first node is less than a second link maintenance signal on the second node, and is also used to output a second compensation signal when it detects that the first link maintenance signal is greater than the second link maintenance signal; a first compensation module, which is used to amplify the first link maintenance signal to meet a target range under the action of the first compensation signal; and a second compensation module, which is used to reduce the voltage of the first link maintenance signal to meet the target range under the action of the second compensation signal, so that the link maintenance signal received by the driver chip is not subject to external interference, thereby ensuring the handshake stability between the timing controller and the driver chip and improving the display effect of the display panel.

Description

Technical Field

[0001] The present disclosure belongs to the field of display driving technology, and particularly relates to a signal compensation circuit, a signal compensation method and a display device. Background Art

[0002] The architecture of an OLED (Organic Light-Emitting Diode) liquid crystal display device generally includes a system-on-chip (SOC), a timing controller (TCON), a driver chip, and a display panel. The timing controller and the driver chip achieve a handshake connection through a link maintenance signal generated by the timing controller. After the handshake is completed, display communication begins to send normal communication data signals.

[0003] However, in actual hardware circuits, the link hold signal is easily interfered by external factors, causing signal instability, resulting in handshake failure and poor display. Summary of the Invention

[0004] The present application provides a signal compensation circuit, a signal compensation method and a display device to solve the problem that a link hold signal is easily affected by external interference, resulting in a handshake failure between a timing controller and a driver chip.

[0005] In a first aspect, the present application provides a signal compensation circuit, which is applied to a display device, wherein the display device includes a timing controller, a signal transmission branch and at least one driver chip, wherein the first end of the signal transmission branch is connected to a first node, the second end of the signal transmission branch is connected to a link maintenance signal output end of the timing controller through a second node, and the link maintenance signal receiving end of the at least one driver chip is connected to a third node. The signal compensation circuit includes: a level detection module, wherein the input end of the level detection module is respectively connected to the first node and the second node, and is used to output a first compensation signal when it detects that the first link maintenance signal on the first node is less than the second link maintenance signal on the second node, and is also used to When it is detected that the first link maintenance signal is greater than the second link maintenance signal, a second compensation signal is output; a first compensation module, wherein the input end of the first compensation module is respectively connected to the first node and the first output end of the level detection module, and the output end of the first compensation module is connected to a third node, and is used to amplify the first link maintenance signal to meet the target range under the action of the first compensation signal; a second compensation module, wherein the input end of the second compensation module is respectively connected to the first node and the second output end of the level detection module, and the output end of the second compensation module is connected to the third node, and is used to reduce the voltage of the first link maintenance signal to meet the target range under the action of the second compensation signal.

[0006] Optionally, the signal compensation circuit also includes: an abnormal cut-off module, which is respectively connected to the link maintenance signal output end of the timing controller, the second node and the feedback output end of the driver chip, and is used to cut off the connection between the timing controller and the second node under the action of the abnormal feedback signal output by the driver chip.

[0007] Optionally, the level detection module includes: a first comparator, a first input end of the first comparator is connected to the first node, and a second input end of the first comparator is connected to the second node; a selector, an input end of the selector is connected to the output end of the first comparator, a first output end of the selector is connected to the input end of the first compensation module, and a second output end of the selector is connected to the input end of the second compensation module, and is used to select the first output end to output the first compensation signal or select the second output end to output the second compensation signal according to the comparison signal output by the first comparator.

[0008] Optionally, the first compensation module includes: a first transistor, an amplifier, a first resistor and a second resistor; wherein the first resistor is a variable resistor; the control end of the first transistor is connected to the first output end of the selector, the first end of the first transistor is connected to the first node, the second end of the first transistor is connected to the input end of the amplifier, and the output end of the amplifier is respectively connected to the first node and the third node; the first end of the first resistor is connected to the first connection end of the amplifier, the second end of the first resistor is connected to the first end of the second resistor, the first end of the second resistor is also connected to the second connection end of the amplifier, and the second end of the second resistor is grounded.

[0009] Optionally, the second compensation module includes: a second transistor, a third resistor, a fourth resistor, a second comparator and a triode; the control end of the second transistor is connected to the second output end of the selector, the first end of the second transistor is connected to the first node, and the second end of the second transistor is connected to the first input end of the second comparator through the third resistor; the first input end of the second comparator is also grounded through the fourth resistor, the second input end of the second comparator is connected to the reference voltage output end, the output end of the second comparator is connected to the base of the triode, the emitter of the triode is connected to the second node, and the collector of the triode is connected to the third node.

[0010] Optionally, the second comparator is used to output a corresponding base voltage according to the voltage difference between the first input terminal and the second input terminal; the transistor is in an amplification state under the action of the base voltage, and reduces the voltage of the first link maintenance signal to the target range.

[0011] Optionally, the abnormal cut-off module includes: an OR gate, the OR gate includes at least one input end, the input end of the OR gate is connected to the feedback output end of the driver chip; a third transistor, the control end of the third transistor is connected to the output end of the OR gate, the first end of the third transistor is connected to the link maintenance signal output end of the timing controller, and the second end of the third transistor is connected to the second node.

[0012] Optionally, the selector includes: a fourth transistor, the control end of the fourth transistor is connected to the output end of the first comparator, the first end of the fourth transistor is connected to the first power supply voltage output end, and the second end of the fourth transistor is connected to the input end of the first compensation module; a fifth transistor, the control end of the fifth transistor is connected to the output end of the first comparator, the first end of the fifth transistor is connected to the second power supply voltage output end, and the second end of the fifth transistor is connected to the input end of the second compensation module; wherein the turn-on voltages of the fourth transistor and the fifth transistor are opposite.

[0013] In a second aspect, the present application provides a signal compensation method, which is applied to the signal compensation circuit, and the signal compensation method includes: a level detection module detects whether the difference between a first link maintenance signal on a first node and a second link maintenance signal on a second node exceeds a preset range; when it exceeds the preset range and the first link maintenance signal is less than the second link maintenance signal, the level detection module drives the first compensation module to amplify the first link maintenance signal to meet the target range; when it exceeds the preset range and the first link maintenance signal is greater than the second link maintenance signal, the level detection module drives the second compensation module to reduce the voltage of the first link maintenance signal to meet the target range.

[0014] In a third aspect, the present application provides a display device, which includes: a timing controller for outputting a link maintenance signal; a signal transmission branch, wherein the first end of the signal transmission branch is connected to the first node, and the second end of the signal transmission branch is connected to the link maintenance signal output end of the timing controller through the second node, for transmitting the link maintenance signal to the first node; a signal compensation circuit, wherein the first end of the signal compensation circuit is connected to the first node, the second end of the signal compensation circuit is connected to the second node, and the third end of the signal compensation circuit is connected to the third node, for performing signal compensation on the link maintenance signal on the first node so that it meets the target range and then outputs it to the third node; at least one driving chip, the link maintenance signal receiving end of the driving chip is connected to the third node, and is used to maintain data communication with the timing controller under the action of the link maintenance signal on the third node.

[0015] The technical solution provided by this application has at least the following beneficial effects:

[0016] The present application uses a level detection module to detect whether the link maintenance signal after transmission through the signal transmission branch is too low or too high. When it is detected that the link maintenance signal after transmission is too low, the first compensation module is driven to perform amplification processing. When it is detected that the link maintenance signal after transmission is too high, the second compensation module is driven to perform voltage reduction processing, so that the link maintenance signal received by the driver chip is not subject to external interference, thereby ensuring the handshake stability between the timing controller and the driver chip and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0018] Figure 1 The figure shows a connection diagram of a timing controller and a driver chip in the related art.

[0019] Figure 2 Shown is a structural schematic diagram of the first signal compensation circuit provided in an embodiment of the present application.

[0020] Figure 3 Shown is a structural diagram of a second signal compensation circuit provided in an embodiment of the present application.

[0021] Figure 4 Shown is a circuit diagram of a signal compensation circuit provided in an embodiment of the present application.

[0022] Figure 5 Shown is a circuit diagram of a selector provided in an embodiment of the present application.

[0023] Figure 6 The figure is a flow chart of a signal compensation method provided in an embodiment of the present application.

[0024] Description of reference numerals:

[0025] 100, timing controller; 200, driver chip; 300, signal transmission branch;

[0026] 400, signal compensation circuit; 410, level detection module; 420, first compensation module; 430, second compensation module; 440, abnormality cutoff module;

[0027] N1, first node; N2, second node; N3, third node; U1, first comparator; U2, selector; U3, amplifier; U4, second comparator; U5, OR gate; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; Q, transistor. DETAILED DESCRIPTION

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0029] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0030] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0031] In current liquid crystal display devices, the connection diagram between the timing controller and the driver chip is as follows: Figure 1 As shown, the link maintenance signal between the timing controller 100 and the driver chip 200 is transmitted through the signal transmission branch 300, and the signal transmission branch 300 is usually a metal wire or a metal conductive layer; under normal circumstances, when the link maintenance signal is a fixed high-level signal, it indicates that the timing controller 100 has reached a handshake connection with the driver chip 200, and the timing controller 100 can send a communication data signal according to a preset communication protocol, so that the driver chip 200 drives the display panel to display according to the communication data signal; in special circumstances, when the link maintenance signal actively output by the timing controller 100 is a low level, it indicates that the timing controller 100 disconnects the handshake connection of the driver chip 200.

[0032] However, in actual hardware circuits, there are at least the following external factors: (1) voltage drop in the signal transmission branch 300; (2) the signal transmission branch 300 is set close to the voltage signal that jumps; (3) abnormal characteristics of circuit elements under abnormal conditions; under the interference of the above external factors, the link maintenance signal transmitted in the signal transmission branch 300 becomes unstable, being pulled up or / and pulled down, thereby causing the handshake between the timing controller 100 and the driver chip 200 to fail, affecting the display effect of the display panel.

[0033] In order to solve the problem of unstable link maintenance signal, the present application provides a signal compensation circuit 400, which specifically includes the following embodiments:

[0034] Figure 2 FIG. 1 is a schematic diagram showing the structure of a first signal compensation circuit provided in an embodiment of the present application; FIG. Figure 2 As shown, the signal compensation circuit 400 is applied to a display device, which includes a timing controller 100, a signal transmission branch 300 and at least one driver chip 200. The first end of the signal transmission branch 300 is connected to the first node N1, the second end of the signal transmission branch 300 is connected to the link maintenance signal output end of the timing controller 100 through the second node N2, and the link maintenance signal receiving end of at least one driver chip 200 is connected to the third node N3; it should be noted that the timing controller 100 outputs the link maintenance signal to the second node N2 through the link maintenance signal output end, and then transmits it to the first node N1 through the signal transmission branch 300. Due to interference from external factors, the link maintenance signals on the first node N1 and the second node N2 are quite different, which affects the handshake connection between the timing controller 100 and the driver chip 200. Therefore, the signal compensation circuit 400 of this embodiment stabilizes the link maintenance signal difference between the first node N1 and the second node N2 within an acceptable range.

[0035] In this embodiment, the signal compensation circuit 400 includes: a level detection module 410, a first compensation module 420, and a second compensation module 430. The input end of the level detection module 410 is respectively connected to the first node N1 and the second node N2, and is configured to output a first compensation signal when detecting that the first link holding signal on the first node N1 is less than the second link holding signal on the second node N2, and is further configured to output a second compensation signal when detecting that the first link holding signal is greater than the second link holding signal. The input end of the first compensation module 420 is respectively connected to the first node N1 and the first output end of the level detection module 410, and the output end of the first compensation module 420 is connected to the third node N3. Under the action of the first compensation signal, the first link holding signal is amplified to meet the target range. The input end of the second compensation module 430 is respectively connected to the first node N1 and the second output end of the level detection module 410, and the output end of the second compensation module 430 is connected to the third node N3. Under the action of the second selection signal, the voltage of the first link holding signal is reduced to meet the target range.

[0036] It should be noted that the working principle of the signal compensation circuit 400 of this embodiment is:

[0037] (1) The level detection module 410 determines in real time whether the difference between the first link maintenance signal and the second link maintenance signal is within a preset range. When the difference is within the preset range, the level detection module 410 does not output any compensation signal, so that the first link maintenance signal on the first node N1 is directly output to the driver chip 200 through the third node N3 for handshake connection.

[0038] (2) When the level detection module 410 detects that the difference between the first link maintenance signal and the second link maintenance signal exceeds a preset range, and the first link maintenance signal is less than the second link maintenance signal, it indicates that the link maintenance signal output by the timing controller 100 is pulled down by external interference. The level detection module 410 outputs a first compensation signal to the first compensation module 420, so that the first compensation module 420 amplifies the first link maintenance signal. When the first link maintenance signal is amplified to meet the target range, it is output to the driver chip 200 through the third node N3 for handshake connection.

[0039] (3) When the level detection module 410 detects that the difference between the first link maintenance signal and the second link maintenance signal exceeds a preset range, and the first link maintenance signal is greater than the second link maintenance signal, it indicates that the link maintenance signal output by the timing controller 100 is pulled up due to external interference. The level detection module 410 outputs the second compensation signal to the second compensation module 430, so that the second compensation module 430 performs a voltage reduction process on the first link maintenance signal. When the voltage of the first link maintenance signal is reduced to meet the target range, it is output to the driver chip 200 through the third node N3 for handshake connection.

[0040] It should be noted that the preset range can be adjusted according to the actual application scenario, for example, -0.5~+0.5V, and the target range can be based on the second link maintenance signal. After adding the preset range, the value of the target range can be obtained. For example, if the second link maintenance signal is +5V, the target range is 4.5~5.5V.

[0041] The technical solution provided by this application has at least the following beneficial effects:

[0042] The present application uses a level detection module 410 to detect whether the link maintenance signal after transmission through the signal transmission branch 300 is too low or too high. When it is detected that the link maintenance signal after transmission is too low, the first compensation module 420 is driven to perform amplification processing. When it is detected that the link maintenance signal after transmission is too high, the second compensation module 430 is driven to perform voltage reduction processing, so that the link maintenance signal received by the driver chip 200 is not subject to external interference, thereby ensuring the handshake stability between the timing controller 100 and the driver chip 200, and improving the display effect of the display panel.

[0043] Figure 3 FIG. 1 is a schematic diagram showing the structure of a second signal compensation circuit provided in an embodiment of the present application; FIG. Figure 3 As shown, the signal compensation circuit 400 also includes: an abnormal cut-off module 440, which is respectively connected to the link maintenance signal output terminal of the timing controller 100, the second node N2 and the feedback output terminal of the driver chip 200, and is used to cut off the connection between the timing controller 100 and the second node N2 under the action of the abnormal feedback signal output by the driver chip 200.

[0044] In this embodiment, the abnormal disconnection module 440 includes multiple input terminals, and each input terminal is connected to the feedback output terminal of a driving chip 200; under normal circumstances, when all the driving chips 200 output normal feedback signals, the abnormal disconnection module 440 is in a conducting state, enabling the timing controller 100 to output a link holding signal to the second node N2; in abnormal circumstances, when any one of the driving chips 200 outputs an abnormal feedback signal, the abnormal disconnection module 440 is in a disconnected state, cutting off the connection between the timing controller 100 and the second node N2, thereby disconnecting the handshake connection; wherein, the abnormal circumstances include data transmission abnormalities or data reception abnormalities at high speeds; therefore, in this embodiment, through the abnormal disconnection module 440, it is ensured that any driving chip 200 having a data reception abnormality can cut off the handshake connection, preventing problems such as poor display.

[0045] Figure 4 The following shows a circuit schematic diagram of a signal compensation circuit provided by an embodiment of the present application; as Figure 4 shown, the level detection module 410 includes: a first comparator U1 and a selector U2. The first input terminal of the first comparator U1 is connected to the first node N1, and the second input terminal of the first comparator U1 is connected to the second node N2; the input terminal of the selector U2 is connected to the output terminal of the first comparator U1. The first output terminal of the selector U2 is connected to the input terminal of the first compensation module 420, and the second output terminal of the selector U2 is connected to the input terminal of the second compensation module 430, for selecting to output a first compensation signal through the first output terminal or output a second compensation signal through the second output terminal according to the comparison signal output by the first comparator U1.

[0046] It should be noted that the first link holding signal Vt on the first node N1 is input to the inverting input terminal of the first comparator U1, and the second link holding signal Va on the second node N2 is input to the non-inverting input terminal of the first comparator U1. When the second link holding signal output by the timing controller 100 has a voltage drop due to the R-string of the load line, or when the link holding signal has a voltage drawdown or voltage jump due to interference, the first comparator U1 will output a level signal Vc.

[0047] In one embodiment, when V a > V t it indicates that the link holding signal is pulled down, and Vc output by the first comparator U1 is a high level; when Va < Vt, it indicates that the link holding signal is pulled up by the backend, and Vc output by the first comparator U1 is a low level.

[0048] In one embodiment, when (V a - V t ) > V0, it indicates that the link holding signal is pulled down and exceeds the preset range, and Vc output by the first comparator U1 is a high level; when (Vt -V a )>V0, it indicates that the link hold signal is pulled high by the back end and exceeds the preset range, and the Vc output by the first comparator U1 is a low level.

[0049] In one embodiment, V a =V t or |V a -V t When |≤V0, it indicates that the link holding signal is within the normal range, and the first comparator U1 does not output the Vc signal.

[0050] In this embodiment, when the Vc output by the first comparator U1 is a high level, the first output end of the selector U2 outputs a first compensation signal, so that the first compensation module 420 amplifies (i.e., boosts) the first link maintenance signal; when the Vc output by the first comparator U1 is a low level, the second output end of the selector U2 outputs a second compensation signal, so that the second compensation module 430 reduces the voltage of the first link maintenance signal.

[0051] In one embodiment, the level detection module 410 further includes a fifth resistor R5 , and the output terminal of the first comparator U1 is connected to the input terminal of the selector U2 via the fifth resistor R5 ; wherein the fifth resistor R5 has a current limiting function.

[0052] like Figure 5 As shown, the selector U2 includes: a fourth transistor T4 and a fifth transistor T5, the control end of the fourth transistor T4 is connected to the output end of the first comparator U1, the first end of the fourth transistor T4 is connected to the first power supply voltage output end, and the second end of the fourth transistor T4 is connected to the input end of the first compensation module 420; the control end of the fifth transistor T5 is connected to the output end of the first comparator U1, the first end of the fifth transistor T5 is connected to the second power supply voltage output end, and the second end of the fifth transistor T5 is connected to the input end of the second compensation module 430; wherein, the turn-on voltages of the fourth transistor T4 and the fifth transistor T5 are opposite.

[0053] It should be noted that the fourth transistor T4 is an N-type transistor and the fifth transistor T5 is a P-type transistor. When the Vc signal output by the first comparator U1 is at a high level, the fourth transistor T4 is turned on and the fifth transistor T5 is turned off, causing the first output terminal O1 of the selector U2 to output the first power supply voltage Vcc1 and no signal to be output from the second output terminal O2 of the selector U2. When the Vc signal output by the first comparator U1 is at a low level, the fourth transistor T4 is turned off and the fifth transistor T5 is turned on, causing the second output terminal O2 of the selector U2 to output the second power supply voltage Vcc2 and no signal to be output from the first output terminal O1 of the selector U2. In addition, when the first comparator U1 does not output the Vc signal, both the fourth transistor T4 and the fifth transistor T5 are turned off, causing no signal to be output from the first output terminal O1 and the second output terminal O2 of the selector U2.

[0054] In one embodiment, if Figure 4 As shown, the first compensation module 420 includes: a first transistor T1, an amplifier U3, a first resistor R1 and a second resistor R2; wherein the first resistor R1 is a variable resistor; the control end of the first transistor T1 is connected to the first output end of the selector U2, the first end of the first transistor T1 is connected to the first node N1, the second end of the first transistor T1 is connected to the input end of the amplifier U3, and the output end of the amplifier U3 is respectively connected to the first node N1 and the third node N3; the first end of the first resistor R1 is connected to the first connection end of the amplifier U3, the second end of the first resistor R1 is connected to the first end of the second resistor R2, the first end of the second resistor R2 is also connected to the second connection end of the amplifier U3, and the second end of the second resistor R2 is grounded.

[0055] It should be noted that when Va>Vt, Vc output by the first comparator U1 is a high level. After the selector U2 recognizes the high level, the first output terminal O1 outputs a high level, the first transistor T1 is turned on, and the pulled-down first link holding signal enters the amplifier U3 through the first transistor T1. The first link holding signal is amplified according to the amplification factor set in the amplifier U3 to obtain a target link holding signal. One target link holding signal output by the amplifier U3 is transmitted to the third node N3, and the other target link holding signal continues to enter the level detection module 410 through the first node N1 to be compared with the second link holding signal on the second node N2. Therefore, connecting the output terminal of the amplifier U3 to the first node N1 allows the target link holding signal obtained after amplification by the amplifier U3 to update the first link holding signal on the first node N1 in real time. By iteratively performing signal judgment, signal compensation, and signal update, it is ensured that the target link holding signal on the third node N3 can be stabilized within the target range in real time.

[0056] Optionally, the amplification factor of the amplifier U3 can be adjusted in real time by using the first resistor R1 and the second resistor R2, where the amplification factor N = 1 + R1 / R2. Since the first resistor R1 is a variable resistor, the amplification factor can be adjusted in real time by adjusting the resistance of the first resistor R1, thereby maintaining a rapid and consistent compensation effect between the first link holding signal and the reference signal (i.e., the second link holding signal). It should be noted that since the difference between Va and Vt detected each time is different, but the amplification factor set in the amplifier U3 is fixed, it is usually necessary to amplify Vt multiple times before reaching the target range. In addition, depending on different application scenarios, the difference range between Va and Vt may vary greatly. In scenarios with a larger difference, the amplification factor is adjusted to a larger value, so that the signal can be quickly amplified to the target range. In scenarios with a smaller difference, the amplification factor is adjusted to a smaller value, avoiding the problem of overshoot. Therefore, adjusting the amplification factor based on the first resistor R1 and the second resistor R2 can meet the amplification needs of different application scenarios.

[0057] Optionally, the first compensation module 420 also includes a sixth resistor R6 and a seventh resistor R7, the second end of the first transistor T1 is connected to the input end of the amplifier U3 through the sixth resistor R6, and the output end of the amplifier U3 is connected to the third node N3 through the seventh resistor R7; wherein the sixth resistor R6 and the seventh resistor R7 play a role in current limiting.

[0058] In one embodiment, if Figure 4 As shown, the second compensation module 430 includes; a second transistor T2, a third resistor R3, a fourth resistor R4, a second comparator U4 and a transistor; the control end of the second transistor T2 is connected to the second output end of the selector U2, the first end of the second transistor T2 is connected to the first node N1, and the second end of the second transistor T2 is connected to the first input end of the second comparator U4 through the third resistor R3; the first input end of the second comparator U4 is also grounded through the fourth resistor R4, the second input end of the second comparator U4 is connected to the reference voltage output end, the output end of the second comparator U4 is connected to the base of the transistor, the emitter of the transistor is connected to the second node N2, and the collector of the transistor is connected to the third node N3.

[0059] In this embodiment, the second comparator U4 is used to output a corresponding base voltage according to the voltage difference between the first input terminal and the second input terminal; the transistor is in an amplification state under the action of the base voltage, and reduces the voltage of the first link maintenance signal to the target link maintenance signal.

[0060] In this embodiment, the reference voltage Vs = Va×(R4 / (R3+R4)), and the voltage at point P, Vp = Vt×(R4 / (R3+R4)); when Va < Vt, Vc output by the first comparator U1 is at a low level. After the selector U2 recognizes the low level, its second output terminal 02 outputs a high level, and the second transistor T2 is turned on. The pulled-up first link hold signal enters the second comparator U4 through the second transistor T2. Since Va < Vt, Vp > Vs. The second comparator U4 outputs a corresponding base voltage according to the voltage difference between Vp and Vs, causing the triode to operate in the amplification region with relatively weak conduction ability, so that the second link hold signal on the emitter of the triode pulls down the first link hold signal on the collector of the triode. After multiple repeated adjustments, Vo = Va is achieved, realizing the adjustment of the load link hold signal, ensuring the stability of the link hold signal and not being affected by external interference.

[0061] In another embodiment, when Va < Vt, Vc output by the first comparator U1 is at a low level. After the selector U2 recognizes the low level, its second output terminal 02 outputs a high level, and the second transistor T2 is turned on. The pulled-up first link hold signal enters the second comparator U4 through the second transistor T2. Since Va < Vt, Vp > Vs. The second comparator U4 outputs a high level to the base of the triode, causing the triode to operate in the fully-conducted saturation region, so that the second link hold signal on the emitter of the triode is equal to the first link hold signal on the collector of the triode, that is, Vo = Va, realizing the adjustment of the load link hold signal, ensuring the stability of the link hold signal and not being affected by external interference.

[0062] In one embodiment, as Figure 4 shown, the abnormal cut-off module 440 includes: an OR gate and a third transistor T3. The OR gate includes at least one input terminal, and the input terminal of the OR gate is connected to the feedback output terminal of the driving chip 200; the control terminal of the third transistor T3 is connected to the output terminal of the OR gate, the first terminal of the third transistor T3 is connected to the link hold signal output terminal of the timing controller 100, and the second terminal of the third transistor T3 is connected to the second node N2; wherein, the third transistor T3 is a P-type thin-film transistor.

[0063] It should be noted that when the driving chip 200 does not have an abnormality, it outputs a low level to the OR gate, causing the OR gate to output a low level to turn on the third transistor T3, and the link hold signal output by the timing controller 100 enters the signal transmission branch 300 and the signal compensation circuit 400.

[0064] Optionally, when the output rate of the timing controller 100 is too high and an abnormal data transmission occurs, or a driver chip 200 receives data abnormally due to an output rate that is too high, the driver chip 200 outputs a high level to the OR gate. When the OR gate receives any number of high levels, it outputs a high level to the third transistor T3, so that the third transistor T3 is turned off, and the link maintenance signal output by the timing controller 100 is cut off, ensuring that the link maintenance signal will be automatically cut off as long as any driver chip 200 receives data abnormally, thereby avoiding affecting the display effect.

[0065] In one embodiment, the present application provides a signal compensation method, which is applied to the signal compensation circuit of the above embodiment, such as Figure 6 As shown, the signal compensation method specifically includes the following steps:

[0066] Step S100: The level detection module detects whether the difference between the first link maintenance signal on the first node and the second link maintenance signal on the second node exceeds a preset range; if it does not exceed the preset range, step S200 is executed; if it exceeds the preset range, step S300 is executed.

[0067] Step S200: The level detection module does not output the compensation signal, so that the first link maintaining signal on the first node is directly output to the driving chip through the third node for handshake connection.

[0068] Step S300: The level detection module determines whether the first link holding signal is less than the second link holding signal; if so, step S400 is executed; if not, step S500 is executed.

[0069] Step S400: The level detection module drives the first compensation module to amplify the first link holding signal to meet the target range.

[0070] Step S500: The level detection module drives the second compensation module to reduce the voltage of the first link holding signal to meet the target range.

[0071] It should be noted that the level detection module determines in real time whether the difference between the first link maintenance signal and the second link maintenance signal is within a preset range. When the difference is within the preset range, the level detection module does not output any compensation signal, so that the first link maintenance signal on the first node is directly output to the driver chip through the third node for handshake connection. When the level detection module detects that the difference between the first link maintenance signal and the second link maintenance signal exceeds the preset range, and the first link maintenance signal is less than the second link maintenance signal, it indicates that the link maintenance signal output by the timing controller has been pulled down by external interference. The level detection module outputs a first compensation signal to the first compensation module, so that the first compensation module amplifies the first link maintenance signal. When the first link maintenance signal is amplified to meet the target range, it is output to the driver chip through the third node for handshake connection. When the level detection module detects that the difference between the first link maintenance signal and the second link maintenance signal exceeds a preset range, and the first link maintenance signal is greater than the second link maintenance signal, it indicates that the link maintenance signal output by the timing controller has been pulled up due to external interference. The level detection module outputs a second compensation signal to the second compensation module, causing the second compensation module to reduce the voltage of the first link maintenance signal. When the voltage of the first link maintenance signal is reduced to meet the target range, it is output to the driver chip through the third node for handshake connection.

[0072] In one embodiment, the present application provides a display device, which includes: a timing controller, a signal transmission branch, the signal compensation circuit of the above embodiment, and at least one driver chip.

[0073] In this embodiment, the timing controller is used to output a link maintenance signal; the first end of the signal transmission branch is connected to the first node, and the second end of the signal transmission branch is connected to the link maintenance signal output end of the timing controller through the second node, for transmitting the link maintenance signal to the first node; the first end of the signal compensation circuit is connected to the first node, the second end of the signal compensation circuit is connected to the second node, and the third end of the signal compensation circuit is connected to the third node, for performing signal compensation on the link maintenance signal on the first node so that it meets the target range and then outputs it to the third node; the link maintenance signal receiving end of the driver chip is connected to the third node, for maintaining data communication with the timing controller under the action of the link maintenance signal on the third node.

[0074] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0075] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0076] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A signal compensation circuit, characterized in that: Applicable to a display device, the display device includes a timing controller, a signal transmission branch, and at least one driver chip, wherein a first end of the signal transmission branch is connected to a first node, a second end of the signal transmission branch is connected to a link maintenance signal output end of the timing controller via a second node, and a link maintenance signal receiving end of the at least one driver chip is connected to a third node, and the signal compensation circuit includes: a level detection module, wherein input terminals of the level detection module are connected to the first node and the second node, respectively, and configured to output a first compensation signal when detecting that a first link maintenance signal on the first node is less than a second link maintenance signal on the second node, and further configured to output a second compensation signal when detecting that the first link maintenance signal is greater than the second link maintenance signal; a first compensation module, wherein an input end of the first compensation module is respectively connected to the first node and the first output end of the level detection module, and an output end of the first compensation module is connected to a third node, and is configured to amplify the first link holding signal to meet a target range under the action of the first compensation signal; A second compensation module, wherein the input end of the second compensation module is respectively connected to the first node and the second output end of the level detection module, and the output end of the second compensation module is connected to the third node, and is used to reduce the voltage of the first link maintenance signal to meet the target range under the action of the second compensation signal.

2. The signal compensation circuit according to claim 1, wherein: The signal compensation circuit further includes: An abnormality cutting module is respectively connected to the link maintenance signal output terminal of the timing controller, the second node and the feedback output terminal of the driver chip, and is used to cut off the connection between the timing controller and the second node under the action of the abnormal feedback signal output by the driver chip.

3. The signal compensation circuit according to claim 1, wherein: The level detection module includes: a first comparator, wherein a first input terminal of the first comparator is connected to the first node, and a second input terminal of the first comparator is connected to the second node; A selector, wherein the input end of the selector is connected to the output end of the first comparator, the first output end of the selector is connected to the input end of the first compensation module, and the second output end of the selector is connected to the input end of the second compensation module, and is used to select the first output end to output the first compensation signal or select the second output end to output the second compensation signal according to the comparison signal output by the first comparator.

4. The signal compensation circuit according to claim 3, wherein: The first compensation module includes: A first transistor, an amplifier, a first resistor and a second resistor; wherein the first resistor is a variable resistor; The control terminal of the first transistor is connected to the first output terminal of the selector, the first terminal of the first transistor is connected to the first node, the second terminal of the first transistor is connected to the input terminal of the amplifier, and the output terminal of the amplifier is connected to the first node and the third node respectively; The first end of the first resistor is connected to the first connection end of the amplifier, the second end of the first resistor is connected to the first end of the second resistor, the first end of the second resistor is also connected to the second connection end of the amplifier, and the second end of the second resistor is grounded.

5. The signal compensation circuit according to claim 3, wherein: The second compensation module includes: a second transistor, a third resistor, a fourth resistor, a second comparator, and a triode; The control terminal of the second transistor is connected to the second output terminal of the selector, the first terminal of the second transistor is connected to the first node, and the second terminal of the second transistor is connected to the first input terminal of the second comparator through the third resistor; The first input terminal of the second comparator is also grounded through the fourth resistor, the second input terminal of the second comparator is connected to the reference voltage output terminal, the output terminal of the second comparator is connected to the base of the transistor, the emitter of the transistor is connected to the second node, and the collector of the transistor is connected to the third node.

6. The signal compensation circuit according to claim 5, characterized in that: The second comparator is configured to output a corresponding base voltage according to a voltage difference between the first input terminal and the second input terminal; The transistor is in an amplifying state under the action of the base voltage, and reduces the voltage of the first link holding signal to the target range.

7. The signal compensation circuit according to claim 2, wherein: The abnormality cutting module includes: An OR gate, the OR gate comprising at least one input terminal, the input terminal of the OR gate being connected to the feedback output terminal of the driver chip; a third transistor, wherein the control end of the third transistor is connected to the output end of the OR gate, the first end of the third transistor is connected to the link hold signal output end of the timing controller, and the second end of the third transistor is connected to the second node.

8. The signal compensation circuit according to claim 3, wherein: The selector includes: a fourth transistor, wherein a control terminal of the fourth transistor is connected to the output terminal of the first comparator, a first terminal of the fourth transistor is connected to the first power supply voltage output terminal, and a second terminal of the fourth transistor is connected to the input terminal of the first compensation module; a fifth transistor, wherein a control terminal of the fifth transistor is connected to the output terminal of the first comparator, a first terminal of the fifth transistor is connected to the second power supply voltage output terminal, and a second terminal of the fifth transistor is connected to the input terminal of the second compensation module; The turn-on voltages of the fourth transistor and the fifth transistor are opposite.

9. A signal compensation method, characterized in that: The signal compensation circuit according to any one of claims 1 to 8, wherein the signal compensation method comprises: The level detection module detects whether a difference between a first link maintaining signal on the first node and a second link maintaining signal on the second node exceeds a preset range; When the first link maintaining signal exceeds a preset range and is smaller than the second link maintaining signal, the level detection module drives the first compensation module to amplify the first link maintaining signal to meet a target range; When the voltage exceeds a preset range and the first link maintaining signal is greater than the second link maintaining signal, the level detection module drives the second compensation module to reduce the voltage of the first link maintaining signal to meet the target range.

10. A display device, characterized in that: The display device includes: A timing controller, used for outputting a link holding signal; a signal transmission branch, wherein a first end of the signal transmission branch is connected to a first node, and a second end of the signal transmission branch is connected to a link maintenance signal output end of the timing controller via a second node, and is configured to transmit the link maintenance signal to the first node; The signal compensation circuit according to any one of claims 1 to 8, wherein a first end of the signal compensation circuit is connected to the first node, a second end of the signal compensation circuit is connected to the second node, and a third end of the signal compensation circuit is connected to a third node, and is configured to perform signal compensation on the link hold signal on the first node so that the link hold signal meets a target range and is then output to the third node; At least one driver chip, a link maintenance signal receiving end of the driver chip is connected to the third node, and is used to maintain data communication with the timing controller under the action of the link maintenance signal on the third node.

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