Control Circuit of Buck Converter and Buck Converter

Abstract

The present application provides a control circuit for a buck converter and a buck converter. The control circuit includes an analog curve generation and calibration unit and a hysteresis logic control unit. The analog curve generation and calibration unit is configured to determine a first set voltage according to an input voltage, a preset reference voltage, and load current jump information, generate a peak analog curve or a valley analog curve representing the output voltage of the power switch circuit; and calibrate the peak analog curve or the valley analog curve according to the output voltage and the reference voltage after the load current jumps. The hysteresis logic control unit is configured to perform logical operation processing according to the output voltage, the node voltage at the switching node, the reference voltage, and the peak analog curve or the valley analog curve to generate a non-overlapping control signal to control the conduction or cutoff of the switching element in the power switch circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a control circuit for a buck converter and a buck converter. Background Art

[0002] In recent years, major industries in China have developed rapidly, and the demand for power supply has become higher and higher. As a DC / DC circuit topology, the buck-boost converter has been widely used in power supply fields such as aerospace, communication, and military weapons because of its advantages of low voltage / current stress of switching devices, wide input / output range, few passive components, high efficiency, reliability, and flexibility.

[0003] In the circuit of a switching converter, the control circuit controls the main switching transistor in the switching converter through a feedback loop, and converts the input voltage into a desired output voltage through the switching operation of the main switching transistor. The more commonly used feedback control method is the peak control mode. First, a compensation signal is obtained through an output feedback signal and a reference signal, the upper limit value of the inductor current is obtained according to the compensation signal, and then the sampled signal is compared with the upper limit value of the inductor current to generate a turn-off control signal for the main switching transistor. The conduction of the main switching transistor is controlled by a clock signal. This method can perform switching conversion to provide a stable output voltage or a stable output current in a normal working state.

[0004] However, in some transients, such as when the load changes from heavy load to light load or from light load to heavy load, due to its control limitations, the switching frequency of the main switching transistor cannot be adjusted in time, resulting in a slow transient response of the system, and the output voltage or current cannot be adjusted quickly, which may cause some overshoot phenomena. Therefore, the capacitor current detection technology has been proposed.

[0005] Currently, the widely used current detection methods include series sampling resistors, sampling of the on-resistance of MOSFETs themselves, and MOSFET current detection. Among them, the series sampling resistor has a large power consumption; sampling of the on-resistance of MOSFETs themselves is easily affected by factors such as temperature, process, and voltage, and has low accuracy. Compared with the series sampling resistor and sampling of the on-resistance of MOSFETs themselves, MOSFET current detection has less power consumption and is not sensitive to changes in process, voltage, and temperature (PVT).

[0006] The capacitor current detection technique achieves the theoretically optimal transient response of a buck converter. However, its design cost is high and the implementation difficulty is great. From the perspective of calibration logic, this technique requires calibrating three off-chip parameters separately. The calibration steps and process are complex, and the switching frequency needs to be changed or even the system loop needs to be disconnected during calibration, or a more complex and costly auxiliary circuit needs to be adopted. From the perspective of circuit implementation, the calibration of this technique requires the assistance of a high-precision inductor current detection circuit and a high-speed operational amplifier. Otherwise, the detection accuracy will be affected. At the same time, in order to calibrate the equivalent inductor, the inductor characteristics need to be realized through complex circuit design on the chip, and the accuracy is limited. Summary of the Invention

[0007] This application proposes a buck converter, which can solve the technical problems of the existing capacitor current detection circuit in the existing buck converter, such as complex design and calibration, and limited detection accuracy, when achieving the optimal transient response.

[0008] In a first aspect, an embodiment of this application provides a control circuit for a buck converter. The buck converter includes an input terminal for receiving an input voltage, an output terminal connected to a load, a power switch circuit connected between the input terminal and the output terminal, and a control circuit connected to the power switch circuit. The power switch circuit includes at least one switching element and an inductor connected to a switching node. The control circuit is configured to control the conduction or cutoff of the power switch circuit according to the input voltage and the output voltage to adjust the load current.

[0009] The control circuit includes:

[0010] An analog curve generation and calibration unit, connected to the input terminal and the output terminal. The analog curve generation and calibration unit is configured to determine a first set voltage according to the input voltage, a preset reference voltage, and load current jump information, generate a peak analog curve or a valley analog curve representing the output voltage of the power switch circuit, and calibrate the peak analog curve or the valley analog curve according to the output voltage and the reference voltage after the load current jumps. Wherein, the load current jump information includes jump type, jump occurrence time, peak or valley occurrence time, switching element flip time, and jump end time.

[0011] A hysteresis logic control unit, connected to the analog curve generation and calibration unit and the power switch circuit. The hysteresis logic control unit is configured to perform logic operation processing according to the output voltage, the node voltage at the switching node, the reference voltage, and the peak analog curve or the valley analog curve to generate non-overlapping control signals to control the conduction or cutoff of the switching element in the power switch circuit.

[0012] Second aspect, an embodiment of the present application provides a buck converter, including: an input terminal for receiving an input voltage;

[0013] an output terminal connected to a load for providing an output voltage;

[0014] a power switch circuit connected to the input terminal and the output terminal; the power switch circuit includes at least one switching element and an inductor connected to a switching node;

[0015] a control circuit as described in any embodiment herein, for generating non-overlapping control signals according to the input voltage and the output voltage, controlling the conduction or turn-off of the power switch circuit, and realizing the regulation of the load current.

[0016] The buck converter provided by the embodiment of the present application includes a power switch circuit and a control circuit. An analog curve generation and calibration unit is designed in the control circuit. When the current on the load jumps, based on the relationship between the input voltage and a preset reference voltage, a peak analog curve and a valley analog curve representing the peak output voltage of the power switch circuit are generated. At the same time, after the transient occurs, the peak analog curve or the valley analog curve is calibrated according to the output voltage, providing accurate peak / valley currents and their occurrence times for other units in the control circuit, and providing an accurate basis for the control circuit to control the conduction or turn-off of the power switch circuit. Compared with the prior art, the present application realizes accurate peak / valley time detection in the transient process of the buck converter at a lower cost and complexity, can more quickly adjust the turn-off time of the switching element in the power circuit, accelerate the rise or fall of the inductor current, thereby reducing the overshoot or undershoot of the output voltage, and improving the dynamic response speed of the load. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0018] Figure 1 is a schematic diagram of a conventional capacitor current detection circuit;

[0019] Figure 2 is a schematic structural diagram of a buck converter provided by an embodiment of the present application;

[0020] Figure 3 is a schematic structural diagram of a control circuit of a buck converter provided by an embodiment of the present application;

[0021] Figure 4 is a peak / valley analog curve provided by an embodiment of the present application;

[0022] Figure 5Circuit diagram of the analog curve generation and calibration unit provided by an embodiment of the present application;

[0023] Figure 6 Schematic diagram of the working process of the analog curve generation and calibration unit provided by an embodiment of the present application; wherein, Figure 6 (a) is the process of generating the peak analog curve, Figure 6 (b) is the process of generating the valley analog curve, Figure 6 (c) is the process of calibrating the peak / valley analog curve;

[0024] Figure 7 Waveform diagram of the output voltage of the buck converter for different first set voltages;

[0025] Figure 8 Schematic diagram of the structure of the hysteresis logic control unit provided by an embodiment of the present application;

[0026] Figure 9 Schematic diagram of the structure of the control circuit of the buck converter provided by another embodiment of the present application;

[0027] Figure 10 Circuit diagram of the double - boundary hysteresis control circuit provided by an embodiment of the present application;

[0028] Figure 11 Waveform diagram of the output of the double - boundary hysteresis control circuit provided by an embodiment of the present application;

[0029] Figure 12 Schematic diagram of the structure of the analog timer circuit provided by an embodiment of the present application;

[0030] Figure 13 Circuit diagram of the timing circuit provided by an embodiment of the present application;

[0031] Figure 14 Schematic diagram of the working principle of the analog timer circuit provided by an embodiment of the present application;

[0032] Figure 15 Transient response simulation result of the control circuit of the buck converter provided by an embodiment of the present application.

[0033] Through the above - mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0034] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific embodiments. Similar elements in different embodiments are denoted by related similar element numbers. In the following embodiments, many detailed descriptions are provided to enable a better understanding of the present application. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification to avoid inundating the core part of the present application with excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the descriptions in the specification and general technical knowledge in the art.

[0035] In addition, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can also be reordered or adjusted in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for clearly describing a certain embodiment and do not mean a necessary sequence, unless it is stated that a certain sequence must be followed.

[0036] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type and do not limit the number of objects. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after. And the "connection" and "coupling" mentioned in the present application, unless otherwise specified, both include direct and indirect connection (coupling).

[0037] As described in the background art, in some buck converters, a current detection circuit is adopted to improve the transient response of the buck converter. Figure 1 FIG. [Here should be the specific figure number if there is one] shows a schematic diagram of an existing capacitor current detection circuit, as Figure 1As shown, based on the equivalent circuit model of the off-chip capacitor (composed of capacitor Co, equivalent series inductance ESL, and equivalent series resistance ESR), a separately adjustable capacitor, resistor, and inductor are designed in series within the buck converter chip to form a capacitor current detection circuit, which is connected in parallel with the off-chip capacitor. The calibration module calibrates Co, ESL, and ESR respectively at different frequencies through the inductor current signal and the output voltage slope, so that the impedance of the in-chip series circuit matches that of the off-chip capacitor, and then the current of the output capacitor is obtained through the current of the in-chip series circuit. When the capacitor current is detected to be zero after a transient occurs, the output voltage reaches a peak or valley value at this moment, and precise transient control is performed based on this information.

[0038] However, the design cost of the capacitor current detection technology is high and the implementation difficulty is great. From the perspective of calibration logic, this technology needs to calibrate three off-chip parameters separately, and the calibration steps and processes are complex. Moreover, when calibrating, it is necessary to change the switching frequency or even disconnect the system loop, or use more complex and costly auxiliary circuits. From the perspective of circuit implementation, the calibration of this technology requires a high-precision inductor current detection circuit and the assistance of a high-speed operational amplifier. Otherwise, the detection accuracy will be affected. At the same time, in order to calibrate ESL, it is necessary to implement the inductor characteristics through complex circuit design on the chip, and the accuracy is limited.

[0039] Therefore, this application proposes a buck converter that does not require a capacitor current detection circuit. By determining the peak / valley moment through the peak / valley simulation curve, it can more quickly adjust the turn-off time of the switching element in the power circuit, accelerate the decline of the inductor current, thereby reducing the overshoot of the output voltage and improving the dynamic response speed of the load, so as to reduce the cost and complexity of the buck converter.

[0040] The technical solution of this application and how the technical solution of this application solves the above technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0041] Figure 2 It is a schematic structural diagram of a buck converter provided by an embodiment of this application. As Figure 2 shown, the buck converter provided by the embodiment of this application includes an input terminal 100, an output terminal 200, a power switch circuit 300, and a control circuit 400.

[0042] In this embodiment, the input terminal 100 is used to receive the input voltage V IN , the output terminal 200 is connected to the load and is used to provide the output voltage V OUT, the power switch circuit 300 is connected between the input terminal 100 and the output terminal 200. The power switch circuit 300 includes at least one switching element and an inductor connected to the switching node. The control circuit 400 is connected to the input terminal 100, the output terminal 200, and the power switch circuit 300, and generates non-overlapping control signals according to the input voltage V IN and the output voltage V OUT to control the conduction or cutoff of the switching element to regulate the current on the inductor, that is, to provide a stable and continuous output voltage V IN to the load according to the input voltage V OUT .

[0043] In some embodiments, the power switch circuit 300 includes a diode D, a bootstrap capacitor C BST , a first driver GD1, a second driver GD2, a first switch M1, a second switching transistor M2, an inductor L0, and an output capacitor C0. Among them, the positive electrode of the diode D is connected to the input terminal 100; the first end of the bootstrap capacitor C BST is connected to the negative electrode of the diode D; the first reference terminal of the first driver GD1 is connected to the negative electrode of the diode D, the second reference terminal of the first driver GD1 is connected to the second end of the bootstrap capacitor C BST , and the output terminal of the first driver GD1 is connected to the control terminal of the first switch M1; the control terminals of the first driver GD1 and the second driver GD2 are respectively connected to the output terminal of the control circuit 400 to receive the non-overlapping control signals output therefrom; the first end of the first switch M1 is connected to the input terminal 100 to receive the input voltage V IN , the second end of the first switch M1 is connected to both the second end of the bootstrap capacitor C BST and the first end of the second switching transistor M2. The connection point of the first switch M1 and the second switching transistor M2 is the switching node, and the voltage here is denoted as the node voltage V X ; the control terminal of the second switching transistor M2 is connected to the output terminal of the second driver GD2, and the second end of the second switching transistor M2 is grounded; the first end of the inductor L0 is connected to the switching node, and the second end of the inductor L0 is connected to the output terminal; the first end of the output capacitor C0 is connected to the second end of the inductor L0, and the second end of the output capacitor C0 is grounded. The output capacitor C0 is used to smooth and filter the output voltage V OUT .

[0044] It should be noted that since the main improvement point of this application is aimed at the drive control of the power switch circuit 300 by the control circuit 400, therefore, the control circuit 400 of this application can be used to control the power switch circuit 300 of any buck converter, and does not limit the specific structure of the buck converter. Other structures of the buck converter provided in this application will not be elaborated here.

[0045] The specific process of driving and controlling the control circuit 400 will be described below. Taking the above buck converter as an example, the control circuit 400 provided in the embodiments of the present application specifically refers to according to the input voltage V IN and the output voltage V OUT to control the conduction or cutoff of the power switch circuit 300, so as to adjust the load current I LOAD .

[0046] Figure 3 is a schematic structural diagram of the control circuit of the buck converter provided by an embodiment of the present application. As Figure 3 shown, the control circuit provided in the embodiments of the present application includes an analog curve generation and calibration unit 410 and a hysteresis logic control unit 420.

[0047] In this embodiment, the analog curve generation and calibration unit 410 is respectively connected to the input terminal 100 and the output terminal 200. The analog curve generation and calibration unit 410 is used to determine a first set voltage according to the input voltage V IN , a preset reference voltage V REF and the load current jump information, and generate a peak analog curve or a valley analog curve representing the output voltage V OUT of the power switch circuit 300; and after the load current jumps, calibrate the peak analog curve or the valley analog curve according to the output voltage V OUT and the reference voltage V REF ; wherein, the load current jump information includes the jump type, the jump occurrence time t0, the peak or valley occurrence time t1, the switching element flip time t2 and the jump end time t3.

[0048] Figure 4 is the peak / valley analog curve provided by an embodiment of the present application. As Figure 4 shown, when the load jumps, the charge and discharge imbalance of the output capacitor C0 causes the output voltage V OUT to overshoot or undershoot, and a voltage waveform is generated during the transient. Among them, when the load jumps down, the change curve of the output voltage V OUT is the peak analog curve, and when the load jumps up, the change curve of the output voltage V OUT is the valley analog curve.

[0049] According to the charge-voltage relationship of the output capacitor C0, the peak analog curve can be expressed as:

[0050]

[0051] wherein, C0 is the capacitance value of the output capacitor C0; L0 is the inductance value of the inductor L0.

[0052] The valley analog curve can be expressed as:

[0053]

[0054] Mathematical derivation can prove that for load jumps of different magnitudes, this curve always intersects the output voltage V OUT at its peak or trough moment. It can be seen from Equation (1) and Equation (2) that only the parameter C0×L0 needs to be calibrated, that is, both the peak simulation curve and the trough simulation curve can be calibrated according to the output voltage V OUT value at the moment of transient control completion, so that it is as close as possible to the reference voltage, thereby achieving accurate peak / trough moment detection.

[0055] Based on the above principle, the purpose of the simulation curve generation and calibration unit 410 in the embodiments of this application is to generate a voltage waveform during transient occurrence, and this waveform can satisfy the above peak simulation curve or trough simulation curve, that is, Equation (1) or Equation (2).

[0056] According to Equation (1) and Equation (2), the peak simulation curve or the trough simulation curve shows a quadratic function in the time domain. Therefore, in this embodiment, the method of charging a capacitor with a voltage-controlled current source combination is used to perform two integration operations on a fixed voltage, thereby generating a simulation curve. From Figure 4 it can be seen that the moment t0 when the load jump occurs, that is, the moment of transient occurrence, and the moment t1 when the simulation curve intersects the output voltage V OUT is the moment t1 when the peak or trough occurs. Thus, the embodiments of this application propose a structure of a simulation curve generation and calibration unit.

[0057] Figure 5 This is the circuit diagram of the simulation curve generation and calibration unit provided by an embodiment of this application. As Figure 5 shown, the simulation curve generation and calibration unit 410 provided in this embodiment includes a generation logic circuit 4101, a calibration logic circuit 4102, and a simulation curve generation circuit 4103.

[0058] In some embodiments, the generation logic circuit 4101 includes a subtractor, a voltage selection circuit, and a first logic circuit. Exemplarily, the first input terminal of the subtractor is connected to the input terminal 100 for receiving the input voltage V IN , the second input terminal of the subtractor is used to receive the reference voltage V REF , and the output terminal of the subtractor is used to output the difference between the voltage V OUT and the reference voltage V REF , that is, V IN -V REF ; the first input terminal of the voltage selection circuit is connected to the output terminal of the subtractor, and the second input terminal of the voltage selection circuit is used to receive the reference voltage V REF, the output terminal of the voltage selection circuit is used to output a first set voltage; the input terminal of the first logic circuit is used to receive load current jump information, the first output terminal of the first logic circuit is connected to the third input terminal of the voltage selection circuit, the second output terminal of the first logic circuit is used to output a first switch signal, and the third output terminal of the first logic circuit is used to output a second switch signal.

[0059] In some embodiments, the calibration logic circuit 4102 includes a sample and hold circuit, a comparator, and a second logic circuit. Exemplarily, the first input terminal and the output terminal of the sample and hold circuit are connected to 200, the second input terminal of the sample and hold circuit is used to receive load current jump information, and the output terminal of the sample and hold circuit is used to output the output voltage V at the end time t3 of the jump OUT ; the non-inverting input terminal of the comparator is connected to the output terminal of the sample and hold circuit, and the inverting input terminal of the comparator is used to receive the reference voltage V REF ; the first input terminal of the second logic circuit is connected to the output terminal of the comparator, the second input terminal of the second logic circuit is used to receive load current jump information, and the output terminal of the second logic circuit is used to output a first set voltage.

[0060] The analog curve generation circuit 4103 includes current sources g m1 , switch S1, capacitor C1, current sources g m2 , current sources g m3 , switch S2, and capacitor C E . Exemplarily, the first input terminal of the current source g m1 is connected to the external output power supply V DD , and the second input terminal of the current source g m1 is used to receive a first set voltage; the first terminal of the switch S1 is connected to the output terminal of the current source g m1 , the second terminal of the switch S1 is grounded, and the control terminal of the switch S1 is connected to the second output terminal of the generation logic circuit; the first terminal of the capacitor C1 is connected to the first terminal of the switch S1, and the second terminal of the capacitor C1 is grounded; the first input terminal of the current source g m2 is connected to the external output power supply V DD , and the second input terminal of the current source g m2 is connected to the first terminal of the capacitor C1; the first input terminal of the current source g m3 is connected to the output terminal of the current source g m2 , the second input terminal of the current source g m3 is connected to the first terminal of the capacitor C1, and the output terminal of the current source g m3 is grounded; the first terminal of the switch S2 is connected to the external output power supply V DD , the second terminal of the switch S2 is connected to the output terminal of the current source g m2 ; the capacitor C EThe first end is connected to the second end of the switch S2 and is used to output a peak analog curve or a valley analog curve representing the output voltage of the power switch circuit, and the capacitor C E The second end is grounded.

[0061] In some embodiments, the current source g m1 、the current source g m2 and the current source g m3 are all voltage-controlled current sources.

[0062] Figure 6 This is the schematic diagram of the working process of the analog curve generation and calibration unit provided by the embodiments of the present application. The analog curve generation and calibration unit 410 of the embodiments of the present application has three working modes, which are specifically as follows:

[0063] When the undershoot transient occurs, the circuit generates a peak analog curve. As shown in Figure 6 (a), in the analog curve generation circuit 4103, the first set voltage is the reference voltage V REF , and at this time, the driving voltage-controlled current source g m1 charges the capacitor C1 to generate a voltage signal V C1 that linearly rises from the ground potential in a linear function. V C1 then drives the voltage-controlled current source g m2 to charge the capacitor C E . The voltage on the capacitor C E starts to rise in a quadratic function form from V REF . According to the charge-voltage relationship, the peak analog curve can be expressed as:

[0064] v E,OS (t) = V REF + V REF × g m1 × g m2 / (C1 × C E ) × (t - t0) 2 (3)

[0065] where g m1 is the transconductance value of the current source g m1 ; g m2 is the transconductance value of the current source g m2 ; C1 is the capacitance value of the capacitor C1; C E is the capacitance value of C E ; t is the moment when the jump occurs; t0 is the moment when the peak or valley occurs.

[0066] Similarly, when the overshoot transient occurs, the circuit generates a valley analog curve. As shown in Figure 6 (b), in the analog curve generation circuit 4103, the first set voltage is the input voltage V INThe difference V from the reference voltage IN -V REF , at this time, the driving voltage-controlled current source g m1 charges the capacitor C1, generating a voltage signal V that linearly rises in a linear function starting from the ground potential C1 , V C1 further drives the voltage-controlled current source g m3 to discharge the capacitor C E , and the voltage on the capacitor C E starts to decrease in a quadratic function form from V REF . According to the charge-voltage relationship, the valley simulation curve can be expressed as:

[0067] v E,US (t) = V REF -(V IN -V REF )×g m1 ×g m3 / (C1×C E )×(t - t0) 2 (4)

[0069] where g m3 is the transconductance value of the current source g m3 , and the transconductance value of the current source g m2 is equal to the transconductance value of the current source g m3 , that is, g m2 = g m3 .

[0070] It can be seen from this that the circuit of the analog curve generation and calibration unit 410 provided in this embodiment can generate a peak analog curve when the load jumps down and a valley analog curve when the load jumps up. The circuit resources are reused, reducing the design difficulty.

[0071] Since the voltage of the current source g m1 is fixed, which is the reference voltage V REF , or the difference V between the input voltage V IN and the reference voltage IN -V REF . Comparing equations (1)-(4), when the transconductance value of the current source g m1 is adjusted to C O ×L O ×C1×C E / g m2 (or C O ×L O ×C1×C E / g m3) When this occurs, the circuit can output accurate peak curves and valley curves, that is, the buck converter can achieve precise peak / valley time detection and perform precise optimal transient control.

[0072] Figure 7 It is a waveform diagram of the output voltage of the buck converter for different first set voltages. As Figure 7 shown, when the first set voltage set by the voltage-controlled current source g m1 is too large, after the load jumps up, that is, at the end of the jump t3 (transient end time), the output voltage V OUT of the buck converter is less than the reference voltage V REF , and at the t3 moment after the down jump, the output voltage V OUT is greater than the reference voltage V REF . When the first set voltage set by the current source gm1 is too small, the magnitude relationship between the output voltage V OUT and the reference voltage V REF is opposite. Based on the theoretically optimal transient response of the buck converter, at the end of the jump t3, the output voltage V OUT should be equal to the reference voltage V REF .

[0073] Therefore, after each transient ends, the simulation curve generation and calibration unit 401 in this embodiment can compare the output voltage V OUT with the reference voltage V REF to calibrate the peak simulation curve or the valley simulation curve. In the steady state, first, the calibration logic circuit 4102 compares the output voltage V OUT at the end of the jump t3 with the reference voltage V REF to adjust the transconductance value of the voltage-controlled current source g m1 . At this time, as Figure 6 (c) shows, in the simulation curve generation circuit 4103, the capacitor C1 is short-circuited to ground, and the capacitor C E is short-circuited to the reference voltage V REF . At this time, the generated peak simulation curve or valley simulation curve is closer to the ideal state, that is, the generated peak simulation curve or valley simulation curve can be calibrated through this circuit to achieve precise peak / valley time detection, so as to perform precise optimal transient control.

[0074] As Figure 3 shown, in this embodiment, the hysteresis logic control unit 420 is respectively connected to the simulation curve generation and calibration unit 410 and the power switch circuit 300. The hysteresis logic control unit 410 is used to determine according to the output voltage V OUT , the node voltage V X at the switching node, and the reference voltage V REFAnd perform logical operation processing on the peak simulation curve or valley simulation curve to generate a non-overlapping control signal to control the conduction or turn-off of the switching element in the power switch circuit.

[0075] The control circuit of the buck converter provided by the embodiment of the present application, the simulation curve generation and calibration unit, generates a peak simulation curve and a valley simulation curve representing the output voltage peak value of the power switch circuit based on the relationship between the input voltage and the preset reference voltage when the current on the load jumps. At the same time, after the transient occurs, the peak simulation curve or valley simulation curve is calibrated according to the output voltage, providing the accurate peak / valley current and its occurrence time for other units in the control circuit, and providing an accurate basis for the control circuit to control the conduction or turn-off of the power switch circuit. Compared with the existing capacitor current detection circuit, the embodiment of the present application realizes the accurate peak / valley time detection in the transient process of the buck converter at a lower cost and complexity, can more quickly adjust the turn-off time of the switching element in the power circuit, accelerate the decline of the inductor current, thereby reducing the overshoot of the output voltage and improving the dynamic response speed of the load.

[0076] Figure 8 It is a schematic structural diagram of a hysteresis logic control unit provided by an embodiment of the present application. As Figure 8 shown, the hysteresis logic control unit 420 provided by the embodiment of the present application includes a double-boundary hysteresis control circuit 4201, an analog timer circuit 4202, a transient switch logic control circuit 4203, a signal selection circuit 4204, and a dead-time control circuit 4205.

[0077] In this embodiment, the double-boundary hysteresis control circuit 4201 is respectively connected to the output terminal 200 and the simulation curve generation and calibration unit 410, and is used to receive and generate a first selection control signal according to the output voltage V OUT , the node voltage V X of the power switch circuit, the reference voltage V REF , and the peak simulation curve or valley simulation curve, and determine the jump occurrence time t0 of the load current, the peak or valley occurrence time t1, and the jump type.

[0078] The analog timer circuit 4202 is respectively connected to the input terminal 100 and the double-boundary hysteresis control circuit 4201, and is used to generate a timing voltage according to the input voltage V IN and the reference voltage V REF . After the load current jump occurs, the timing capacitor is charged and discharged through the timing voltage, and the charge and discharge time is accumulated to obtain the switching element flip time t2 and the jump end time t3.

[0079] The transient switch logic control circuit 4203 is respectively connected to the double-boundary hysteresis control circuit 4201 and the analog timer circuit 4202, and is used to receive and perform logical operations on the switching moment t2 of the switching element, the end moment t3 of the jump, and the type of the jump, so as to generate a second selection control signal.

[0080] The signal selection circuit 4204 is respectively connected to the double-boundary hysteresis control circuit 4201 and the transient switch logic control circuit 4203, and is used to generate a switch control signal according to the first selection control signal and the second selection control signal.

[0081] The dead-time control circuit 4205 is connected to the signal selection circuit 4204, and is used to perform interleaving processing on the switch control signal to generate a non-overlapping control signal, so as to control the conduction or turn-off of the switching element in the power switch 300.

[0082] Figure 9 It is a schematic structural diagram of the control circuit of the buck converter provided in another embodiment of the present application. As Figure 9 shown, the working principle of the control circuit of the buck converter provided in this embodiment is as follows:

[0083] Taking the load up-jump as an example, the second selection control signal V output by the transient switch logic control circuit 4203 LT is pulled high, and the signal selection circuit 4204 outputs a switch control signal for controlling the conduction of the switching element in the power switch 300; at the same time, the analog curve generation and calibration unit 410 starts to generate a valley analog curve, and the double-boundary hysteresis control circuit 4201 quickly detects the jump occurrence moment t0 and the peak or valley occurrence moment t1. The analog timer circuit 4202 determines the switching moment t2 of the switching element and the jump end moment t3 according to the jump occurrence moment t0 and the peak or valley occurrence moment t1. At this time, the transient switch logic control circuit 4203 logically controls the second selection control signal V LT to flip at the switching moment t2 of the switching element, and outputs the voltage V at the jump end moment t3 OUT to return to the reference voltage V REF , the buck converter returns to the steady state, and the double-boundary hysteresis control circuit 4201 is responsible for the steady-state control to generate the first selection control signal V PWM to control the turn-off of the switching element in the power switch circuit 300.

[0084] Similarly, when the load current undershoots, the analog curve generation and calibration unit 410 and the hysteresis logic control unit 420 of the embodiment of the present application can control the power switch 300 by generating a peak analog curve.

[0085] Moreover, after each transient occurs, the simulation curve generation and calibration unit 410 can also calibrate the generated peak simulation curve or valley simulation curve to achieve accurate peak / valley moment detection, thereby performing accurate optimal transient control.

[0086] Figure 10 The following is the circuit diagram of a double-boundary hysteresis control circuit provided by an embodiment of the present application. As Figure 10 shown, the double-boundary hysteresis control circuit 4201 provided by the embodiment of the present application includes an oscillator OSC, a Type-Ⅲ compensation circuit, a comparator CMP1, a resistor RW1, a capacitor CW1, a comparator CMP2, a switch SW1, a switch SW2, a resistor RW2, a capacitor CW2, a comparator CMP3, a delay element DLY2, a resistor RW3, and a capacitor CW3.

[0087] Among them, the input end of the Type-Ⅲ compensation circuit is used to receive the reference voltage V REF ; the non-inverting input end of the comparator CMP1 is connected to the output end of the Type-Ⅲ compensation circuit, and the inverting input end of the comparator CMP1 is connected to the output end of the oscillator OSC; the first end of the resistor RW1 is connected to the output end of the comparator CMP1; the first end of the capacitor CW1 is connected to the second end of the resistor RW1.

[0088] The first end of the resistor RW2 is used to receive the node voltage V X , the second end of the resistor RW2 is connected to the first end of the capacitor CW2; the second end of the capacitor CW2 is used to receive the output voltage V OUT .

[0089] The first end of the switch SW1 is used to receive the output voltage V OUT ; the first end of the switch SW2 is used to receive the peak simulation curve or valley simulation curve; the non-inverting input end of the comparator CMP2 is connected to the second end of the switch SW2 and the second end of the resistor RW1, the inverting input end of the comparator CMP2 is connected to the second end of the switch SW1 and the second end of the resistor RW2, and the output end of the comparator CMP2 is used to output a first selection control signal.

[0090] The first end of the capacitor CW3 is used to receive the peak simulation curve or valley simulation curve; the non-inverting input end of the comparator CMP3 is connected to the second end of the resistor RW2, the inverting input end of the comparator CMP3 is connected to the second end of the capacitor CW3, and the output end of the comparator CMP3 is connected to the first end of the delay element DLY2; the first end of the resistor RW3 is connected to the second end of the delay element DLY2, and the second end of the resistor RW3 is connected to the second end of the capacitor CW3.

[0091] The double-boundary hysteresis control circuit 4201 of this embodiment processes the first selection control signal V through three groups of RC filters and comparatorsPWM , thus generating three triangular wave signals that follow each other.

[0092] Figure 11 This is the waveform diagram output by a dual-boundary hysteresis control circuit according to an embodiment of the present application. As Figure 11 shown, under steady state, under the modulation of the Type-III compensation circuit, the comparator CMP1 generates the first selection control signal V required by the system PWM , and through the RC filter, the corresponding triangular wave signal V is produced HYS1 , and another RC filter processes the node voltage V X to generate the triangular wave signal V HYS2 . The triangular wave signal V HYS1 and the triangular wave signal V HYS2 are compared by the comparator CMP1 to generate the first selection control signal V PWM , which controls the conduction or cutoff of the switching element in the power switch circuit 300; thereby controlling the node voltage V X . The node voltage V X and the first selection control signal V PWM have the same waveform, but there is a certain delay. Therefore, the triangular wave signal V HYS2 and the triangular wave signal V HYS1 are the same but have a delay. Through a similar principle, the circuit generates the triangular wave signal V HYS3 , which is the same as the triangular wave signal V HYS2 , but has a certain delay. Observing the waveforms of the three triangular wave signals V HYS1 ~V HYS3 in the time domain, they have the same waveform, but each has a certain delay.

[0093] When a transient occurs, the fluctuation of the output voltage V OUT will be coupled to the middle triangular wave signal V HYS2 , making it intersect with other signals, and the occurrence time t0 of the jump can be determined. After detecting the transient, the triangular wave signals V HYS1 and V HYS2 are respectively short-circuited to the analog curve and the output voltage V OUT . The moment when the comparator CMP1 flips again is the occurrence time t1 of the peak or valley.

[0094] Figure 12 This is the structural schematic diagram of an analog timer circuit provided by an embodiment of the present application. As Figure 12 shown, the analog timer circuit 4202 provided by the embodiment of the present application includes a timing voltage generation circuit 42021, a timing control circuit 42022, a timing circuit 42023, and a timing output circuit 42024.

[0095] In this embodiment, the first end of the timing voltage generation circuit 42021 is used to receive the reference voltage V REF , the second end is connected to the input end, the first output end is used to output the first timing voltage V R1 , the second output end is used to output the second timing voltage V R2 , and the third output end is used to output the third timing voltage V R3 . The input end of the timing control circuit 42022 is used to receive the information of the load current jump, and the output end is used to output the timing control signal. The input end of the timing circuit 42023 is used to receive the first timing voltage V R1 , the second timing voltage V R2 , the third timing voltage V R3 and the timing control signal, and charges and discharges the timing capacitor under the control of the timing control signal. The output end of the timing circuit is used to output the first charging voltage V C3 and the second charging voltage V C4 . The input end of the timing output circuit 42024 is used to receive the first charging voltage, the second charging voltage and the charging reference voltage V B , compares the first charging voltage, the second charging voltage and the charging reference voltage V B respectively, and performs a logical operation on the comparison results to obtain the power switch circuit turning moment t2 and the load current jump end moment t3.

[0096] Figure 13 is the circuit diagram of the timing circuit provided by an embodiment of the present application. As Figure 13 shown, the timing circuit 42023 provided by the embodiment of the present application includes switches S 11 - S 20 , current sources g m11 - g m16 , a charging capacitor C3 and a charging capacitor C4.

[0097] Among them, the first end of the switch S 11 is connected to the input power supply V DD ; the first end of the current source g m11 is connected to the second end of the switch S 11 , and the voltage setting end of the current source g m11 is used to receive the first timing voltage V R1 ; the first end of the current source g m12 is connected to the second end of the current source g m11 , and the voltage setting end of the current source g m12 is used to receive the first timing voltage V R1 ; the first end of the switch S 12 is connected to the second end of the current source g m11 , and the second end of the switch S 12 is grounded.

[0098] Switch S 17 The first end of is connected to the input power supply V DD ; The first end of the current source g m13 is connected to the second end of the switch S 17 ; The voltage setting terminal of the current source g m13 is used to receive the second timing voltage V R2 ; The first end of the current source g m14 is connected to the second end of the current source g m13 ; The voltage setting terminal of the current source g m14 is used to receive the second timing voltage V R2 ; Switch S 18 The first end of is connected to the second end of the current source g m14 ; The second end of the switch S 18 is grounded.

[0099] Switch S 19 The first end of is connected to the input power supply V DD ; The first end of the current source g m15 is connected to the second end of the switch S 19 ; The voltage setting terminal of the current source g m15 is used to receive the third timing voltage V R3 ; The first end of the current source g m16 is connected to the second end of the current source g m15 ; The voltage setting terminal of the current source g m16 is used to receive the third timing voltage V R3 ; Switch S 20 The first end of is connected to the second end of the current source g m16 ; The second end of the switch S 20 is grounded.

[0100] Switch S 13 The first end of is connected to the second end of the current source g m11 ; The first end of the charging capacitor C3 is connected to the second end of the switch S 13 ; The second end of the charging capacitor C3 is grounded; Switch S 14 The first end of is connected to the second end of the current source g m13 and the second end of the current source g m15 ; The second end of the switch S 14 is connected to the second end of the switch S 13 ; Switch S 15 The first end of is connected to the second end of the current source g m11 ; The first end of the charging capacitor C4 is connected to the second end of the switch S 15 ; The second end of the charging capacitor C4 is grounded; Switch S 16 The first end of is connected to the current source gm13 is connected to the second end of the switch S 16 The second end of is connected to the switch S 15 is connected to the second end.

[0101] In some embodiments, the first timing voltage V R1 , the second timing voltage V R2 , the third timing voltage V R3 satisfy:

[0102]

[0103]

[0104] In this embodiment, the analog timer circuit 4202 drives the current source through three timing voltages with a proportional relationship. After the load current jump occurs, it charges and discharges the capacitor and times to calculate the flip moment t2 of the switching element and the jump end moment t3.

[0105] In the analog timer circuit 4202, the timing voltage generation circuit 42021 first determines the first timing voltage V REF and the input voltage V IN , and determines the first timing voltage V R1 , the second timing voltage V R2 , the third timing voltage V R3 ; secondly, the timing control circuit 42022 receives the jump type of the load current and the jump occurrence moment t0, and generates the timing control signal of the switch S 11 -switch S 20 ; then, the timing circuit 42023 charges and discharges the capacitor and times after the load current jump occurs; finally, the timing output circuit 42024 compares the first charging voltage, the second charging voltage and the charging reference voltage V B , and performs a logical operation on the comparison result to obtain the flip moment t2 of the power switch circuit and the load current jump end moment t3.

[0106] Figure 14 is the working principle diagram of the analog timer circuit provided by an embodiment of the present application. As Figure 14 shown, taking the load up jump as an example, after the load current jump occurs, the timing control circuit 42022 controls the switches S17 and S16 to open, and the rest of the switches are turned off. At this time, the second timing voltage V R2 drives the voltage-controlled current source g m13 to charge the charging capacitor C4, and its voltage V C4 rises linearly at a certain slope. When the peak or valley occurrence moment t1 arrives, the switches S12 and S15 are opened, and the rest of the switches are turned off. The first timing voltage V R1 drives the voltage-controlled current source gm11 Discharge the charging capacitor C4, and its voltage V C4 linearly decreases at a certain slope, and the ratio of the rising slope to the falling slope is V R2 : V R1 , that is, the coefficient satisfying Equation (5). Therefore, the voltage V C4 will be discharged to the voltage before charging at the moment t2 when the power switch circuit flips. Therefore, when the discharge is completed, the timer finishes timing and outputs the moment t2 when the power switch circuit for the load to jump up. The calculations for the remaining moments are the same. This analog timer can perform switch control through the corresponding input and can calculate the moment t2 when the power switch circuit flips and the moment t3 when the load current jump ends under any load jump condition.

[0107] Based on the working principle of the above circuit, it can be obtained that:

[0108] When the load jumps up, the moment t2 when the power switch circuit flips and the moment t3 when the load current jump ends are respectively:

[0109]

[0110]

[0111] When the load jumps down, the moment t2 when the power switch circuit flips and the moment t3 when the load current jump ends are respectively:

[0112]

[0113]

[0114] In summary, compared with the prior art, the control circuit of the buck converter proposed in any embodiment of the present application realizes precise peak / trough moment detection during the transient process of the buck converter at a lower cost and complexity, can more quickly adjust the turn-off time of the switching element in the power circuit, accelerate the decrease of the inductor current, thereby reducing the overshoot of the output voltage and improving the dynamic response speed of the load. Moreover, during the calibration of the peak / trough moment, the calibration parameters are reduced from three to one, and at the same time, the calibration method is simplified, eliminating the need for an inductor current detection circuit and a high-speed operational amplifier.

[0115] Figure 15 For the transient response simulation results of the control circuit of the voltage drop converter provided by the embodiments of the present application. As Figure 15 shown, the test condition is that the input voltage V IN is 5V, the output voltage V OUT is 1.8V, the output inductor is 880 nH, and the output capacitor is 8 uF. Among them, from top to bottom, they are the waveform diagram of the output voltage V OUT and the switch node voltage V XWaveform diagram, load current I LOAD From the waveform diagram, it can be seen that the buck converter provided by any embodiment of the present application can complete the transient response within one switching cycle, achieving an overshoot / undershoot voltage close to the theoretical minimum and the shortest recovery time. The deviation between the test result and the theoretical optimal value is less than 5.5%.

[0116] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Those of ordinary skill in the art, under the inspiration of the present application, without departing from the purpose of the present application and the scope protected by the claims, can make several simple deductions, deformations or substitutions according to the idea of the present invention, which all fall within the protection scope of the present application.

Claims

1. A control circuit of a buck converter, the buck converter comprising an input terminal for receiving an input voltage, an output terminal connected to a load, a power switch circuit connected between the input terminal and the output terminal, and a control circuit connected to the power switch circuit; the power switch circuit comprises at least one switch element and an inductor connected to a switch node; the control circuit is used to control the on or off of the power switch circuit according to the input voltage and the output voltage, so as to adjust the load current; It is characterized in that The control circuit comprises: A simulation curve generation and calibration unit is connected to the input terminal and the output terminal; the simulation curve generation and calibration unit is used to determine a first set voltage according to the input voltage, a preset reference voltage and load current jump information, and generate a peak simulation curve or a valley simulation curve representing the output voltage of the power switch circuit; and after the load current jumps, calibrate the peak simulation curve or the valley simulation curve according to the output voltage and the reference voltage; wherein the load current jump information includes the jump type, the jump occurrence time, the peak or valley occurrence time, the switching element flipping time and the jump end time; A hysteresis logic control unit is connected to the simulation curve generation and calibration unit and the power switch circuit; the hysteresis logic control unit is used to perform logic operation processing according to the output voltage, the node voltage at the switch node, the reference voltage and the peak simulation curve or the valley simulation curve to generate a non-overlapping control signal to control the conduction or shutdown of the switch element in the power switch circuit.

2. The control circuit of the buck converter according to claim 1, characterized in that: The simulation curve generation and calibration unit includes a generation logic circuit, a calibration logic circuit and a simulation curve generation circuit; The generating logic circuit comprises a subtractor, a voltage selection circuit and a first logic circuit; wherein the first input end of the subtractor is connected to the input end, the second input end of the subtractor is used to receive the reference voltage, and the output end of the subtractor is used to output the difference between the output voltage and the reference voltage; the first input end of the voltage selection circuit is connected to the output end of the subtractor, the second input end of the voltage selection circuit is used to receive the reference voltage, and the output end of the voltage selection circuit is used to output a first set voltage; the input end of the first logic circuit is used to receive the load current jump information, the first output end of the first logic circuit is connected to the third input end of the voltage selection circuit, the second output end of the first logic circuit is used to output a first switch signal, and the third output end of the first logic circuit is used to output a second switch signal; The calibration logic circuit includes a sampling and holding circuit, a comparator and a second logic circuit; wherein the first input end of the sampling and holding circuit is connected to the output end, the second input end of the sampling and holding circuit is used to receive the load current jump information, and the output end of the sampling and holding circuit is used to output the output voltage at the end of the jump; the non-inverting input end of the comparator is connected to the output end of the sampling and holding circuit, and the inverting input end of the comparator is used to receive the reference voltage; the first input end of the second logic circuit is connected to the output end of the comparator, the second input end of the second logic circuit is used to receive the load current jump information, and the output end of the second logic circuit is used to output the first set voltage; The simulation curve generating circuit includes a current source g m1 , switch S1, capacitor C1, current source g m2 , current source g m3 , switch S2 and capacitor C E ; Wherein, the current source g m1 The first input terminal is connected to the external output power supply V DD connection, the current source g m1 The second input terminal of the switch S1 is connected to the current source g1 and is used to receive the first setting voltage; the first terminal of the switch S1 is connected to the current source g2 and is used to receive the first setting voltage; m1 The output end of the switch S1 is connected to the ground, the second end of the switch S1 is grounded, and the control end of the switch S1 is connected to the second output end of the generating logic circuit; the first end of the capacitor C1 is connected to the first end of the switch S1, and the second end of the capacitor C1 is grounded; the current source g m2 The first input terminal is connected to the external output power supply V DD connection, the current source g m2 The second input terminal of the current source g is connected to the first terminal of the capacitor C1; m3 The first input terminal is connected to the current source g m2 The output terminal is connected to the current source g m3 The second input terminal of the current source g is connected to the first terminal of the capacitor C1. m3 The output end of the switch S2 is connected to the external output power supply V DD The second end of the switch S2 is connected to the current source g m2 The output terminal is connected; the capacitor C E The first end of the capacitor C is connected to the second end of the switch S2, and is used to output a peak value simulation curve or a valley value simulation curve representing the output voltage of the power switch circuit. E The second end of is grounded; The current source g m1 , current source g m2 and current source g m3 Both are voltage-controlled current sources.

3. The control circuit of the buck converter according to claim 2, characterized in that: The peak simulation curve v E,OS (t) is: v E,OS (t)=V REF +V REF ×g m1 ×g m2 / (C1×C E )×(t-t0) 2 Among them, V REF is the reference voltage; g m1 is the current source g m1 The transconductance value; g m2 is the current source g m2 The transconductance value; C1 is the capacitance value of the capacitor C1; C E is the capacitance C E The capacitance value; t is the time when the jump occurs; t0 is the time when the peak or valley value occurs; The valley simulation curve v E,US (t) is: v E,US (t)=V REF -(V IN -V REF )×g m1 ×g m3 / (C1×C E )×(t-t0) 2 Among them, g m3 is the current source g m3 The transconductance value of g m2 =g m3 .

4. The control circuit of the buck converter according to claim 1, characterized in that: The hysteresis logic control unit includes a dual-boundary hysteresis control circuit, an analog timer circuit, a transient switch logic control circuit, a signal selection circuit and a dead time control circuit; The dual-boundary hysteresis control circuit is connected to the output terminal and the simulation curve generation and calibration unit; the dual-boundary hysteresis control circuit is used to generate a first selection control signal according to the output voltage, the node voltage of the power switch circuit, the reference voltage and the peak simulation curve or the valley simulation curve, and determine the jump occurrence time, peak or valley occurrence time and jump type of the load current; an analog timer circuit connected to the input terminal and the double-boundary hysteresis control circuit; the analog timer circuit is used to generate a timing voltage according to the input voltage and the reference voltage, and after the load current jump occurs, the timing capacitor therein is charged and discharged through the timing voltage, and the charging and discharging time is accumulated to obtain the switching element flipping moment and the jump end moment; A transient switch logic control circuit is connected to the dual-boundary hysteresis control circuit and the analog timer circuit; the transient switch logic control circuit is used to receive and perform logic operations on the switching element flipping moment, the transition end moment and the transition type to generate a second selection control signal; A signal selection circuit connected to the dual-boundary hysteresis control circuit and the transient switch logic control circuit; the signal selection circuit is used to generate a switch control signal according to the first selection control signal and the second selection control signal; A dead time control circuit is connected to the signal selection circuit; the dead time control circuit is used to perform interleaving processing on the switch control signal to generate a non-overlapping control signal to control the on or off of the switch element in the power switch circuit.

5. The control circuit of the buck converter according to claim 4, characterized in that: The dual-boundary hysteresis control circuit includes an oscillator OSC, a Type-III compensation circuit, a comparator CMP1, a resistor RW1, a capacitor CW1, a comparator CMP2, a switch SW1, a switch SW2, a resistor RW2, a capacitor CW2, a comparator CMP3, a delay device DLY2, a resistor RW3 and a capacitor CW3; The input end of the Type-III compensation circuit is used to receive the reference voltage; the non-inverting input end of the comparator CMP1 is connected to the output end of the Type-III compensation circuit, and the inverting input end of the comparator CMP1 is connected to the output end of the oscillator OSC; the first end of the resistor RW1 is connected to the output end of the comparator CMP1; the first end of the capacitor CW1 is connected to the second end of the resistor RW1; The first end of the resistor RW2 is used to receive the node voltage, and the second end of the resistor RW2 is connected to the first end of the capacitor CW2; the second end of the capacitor CW2 is used to receive the output voltage; The first end of the switch SW1 is used to receive the output voltage; the first end of the switch SW2 is used to receive the peak simulation curve or the valley simulation curve; the non-inverting input end of the comparator CMP2 is connected to the second end of the switch SW2 and the second end of the resistor RW1, the inverting input end of the comparator CMP2 is connected to the second end of the switch SW1 and the second end of the resistor RW2, and the output end of the comparator CMP2 is used to output the first selection control signal; The first end of the capacitor CW3 is used to receive the peak analog curve or the valley analog curve; the non-inverting input end of the comparator CMP3 is connected to the second end of the resistor RW2, the inverting input end of the comparator CMP3 is connected to the second end of the capacitor CW3, and the output end of the comparator CMP3 is connected to the first end of the delay device DLY2; the first end of the resistor RW3 is connected to the second end of the delay device DLY2, and the second end of the resistor RW3 is connected to the second end of the capacitor CW3.

6. The control circuit of the buck converter according to claim 4, characterized in that: The analog timer circuit includes a timing voltage generating circuit, a timing control circuit, a timing circuit and a timing output circuit; The first end of the timing voltage generating circuit is used to receive the reference voltage, the second end is connected to the input end, and the first output end is used to output the first timing voltage V R1 The second output terminal is used to output the second timing voltage V R2 The third output terminal is used to output the third timing voltage V R3 ; The input end of the timing control circuit is used to receive the information of the load current jump, and the output end is used to output the timing control signal; The input terminal of the timing circuit is used to receive the first timing voltage V R1 , the second timing voltage V R2 , the third timing voltage V R3 and the timing control signal, the timing capacitor is charged and discharged under the control of the timing control signal, and the output end of the timing circuit is used to output a first charging voltage V C3 and the second charging voltage V C4 ; The input end of the timing output circuit is used to receive the first charging voltage, the second charging voltage and the charging reference voltage, respectively compare the first charging voltage, the second charging voltage and the charging reference voltage, and perform logic operations on the comparison results to obtain the flipping moment of the power switch circuit and the end moment of the load current jump.

7. The control circuit of the buck converter according to claim 6, characterized in that: The timing circuit includes a switch S 11 -Switch S 20 , current source g m11 -Current source g m16 , charging capacitor C3 and charging capacitor C4; The switch S 11 The first end is connected to the input power supply V DD connection; the current source g m11 The first end of the switch S 11 The second terminal of the current source g m11 The voltage setting terminal is used to receive the first timing voltage V R1 The current source g m12 The first end of the current source g m11 The second end of the current source g m12 The voltage setting terminal is used to receive the first timing voltage V R1 ; The switch S 12 The first end of the current source g m11 The second end of the switch S 12 The second end of is grounded; The switch S 17 The first end is connected to the input power supply V DD connection; the current source g m13 The first end of the switch S 17 The second end of the current source g m13 The voltage setting terminal is used to receive the second timing voltage V R2 The current source g m14 The first end of the current source g m13 The second end of the current source g m14 The voltage setting terminal is used to receive the second timing voltage V R2 ; The switch S 18 The first end of the current source g m14 The second end of the switch S 18 The second end of is grounded; The switch S 19 The first end is connected to the input power supply V DD connection; the current source g m15 The first end of the switch S 19 The second end of the current source g m15 The voltage setting terminal is used to receive the third timing voltage V R3 The current source g m16 The first end of the current source g m15 The second end of the current source g m16 The voltage setting terminal is used to receive the third timing voltage V R3 ; The switch S 20 The first end of the current source g m16 The second end of the switch S 20 The second end of is grounded; The switch S 13 The first end of the current source g m11 The first end of the charging capacitor C3 is connected to the switch S 13 The second end of the switch S is connected to the ground, and the second end of the charging capacitor C3 is grounded; 14 The first end of the current source g m13 The second terminal and the current source g m15 The second end of the switch S 14 The second end of the switch S 13 The second end of the switch S 15 The first end of the current source g m11 The first end of the charging capacitor C4 is connected to the switch S 15 The second end of the switch S is connected to the ground, and the second end of the charging capacitor C4 is grounded; 16 The first end of the current source g m13 The second end of the switch S 16 The second end of the switch S 15 The second end of the connection.

8. The control circuit of the buck converter according to claim 7, characterized in that: When the load jumps, the power switch circuit flipping time t2 and the load current jump end time t3 are respectively: Among them, V IN is the input voltage; When the load jumps, the power switch circuit flipping time t2 and the load current jump end time t3 are respectively:

9. The control circuit of the buck converter according to claim 7, characterized in that: The first timing voltage V R1 , the second timing voltage V R2 , the third timing voltage V R3 satisfy:

10. A buck converter, characterized in that: include: An input terminal, used for receiving an input voltage; An output terminal connected to a load and used to provide an output voltage; A power switch circuit connected to the input terminal and the output terminal; the power switch circuit includes at least one switch element and an inductor connected to a switch node; The control circuit according to any one of claims 1 to 9 is used to generate non-overlapping control signals according to the input voltage and the output voltage, control the on or off of the power switch circuit, and achieve regulation of the load current.

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