Layer selection layout in memory devices

Abstract

The present application relates to level selection layouts in memory devices. In some implementations, a tile of a memory array may be associated with a level above a substrate and may include a set of memory cells, a set of digit lines, and a set of word lines. Select transistors associated with a tile of memory cells may be operable to couple the digit lines of the tile with circuitry external to the tile and may be activated by various configurations of one or more access lines, wherein the various configurations may be implemented to compromise or otherwise support design and performance characteristics, such as power consumption, layout complexity, operational complexity, and other characteristics. Such techniques may be implemented for other aspects of tile operation, including memory cell routing or balancing, tile selection or signal generation using transistors at different levels, or various combinations thereof.

Description

[0001] Cross Reference

[0002] This patent application is a national phase application of international patent application No. PCT / US2022 / 079405 filed by Vimercati on November 7, 2022, entitled “DECK SELECTION LAYOUTS IN A MEMORY DEVICE”, which claims priority to U.S. patent application No. 17 / 528,018 filed by Vimercati on November 16, 2021, entitled “DECK SELECTION LAYOUTS IN A MEMORY DEVICE”, each of which is assigned to its assignee, and the entire contents of each of which are expressly incorporated herein by reference.

[0003] The technical field relates to level selection layout in memory devices. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3D cross point memory (3D Xpoint), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of external power. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a tile of a memory array associated with a level above a substrate, the tile comprising: a plurality of memory cells; a plurality of digit lines each aligned in a first direction; a plurality of word lines each aligned in a second direction and each operable to activate a plurality of first transistors of the tile to couple a respective storage element of each memory cell of a respective row of memory cells with each digit line of the plurality of digit lines; and an activation line aligned in the second direction and operable to activate a plurality of second transistors of the tile, each of the plurality of second transistors being operable to couple a respective digit line of a set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate.

[0007] An apparatus is described. The apparatus may include: a first tile of a memory array associated with a first level above a substrate, the first tile comprising: a plurality of first memory cells; a plurality of first digit lines, each aligned along a first direction; and a plurality of first word lines, each aligned along a second direction and each operable to activate a plurality of first transistors of the first tile to couple a corresponding storage element of each first memory cell of a corresponding row of first memory cells to each first digit line of the plurality of first digit lines; a second tile of the memory array associated with a second level above the substrate, the second tile comprising: a plurality of second memory cells; a plurality of second digit lines, each aligned along the first direction; and a plurality of second word lines, each aligned along the second direction and each operable to activate a plurality of second transistors of the second tile to couple a corresponding storage element of each first memory cell of a corresponding row of first memory cells to each first digit line of the plurality of first digit lines a first activation line of the first level, which is aligned along the second direction and is operable to activate a plurality of third transistors of the first level, each of the plurality of third transistors being operable to couple a corresponding first digit line of a set of first digit lines of the plurality of first digit lines to a circuit system external to the first level above the substrate; and a second activation line of the first level, which is aligned along the second direction and is operable to activate a plurality of fourth transistors of the first level, each of the plurality of fourth transistors being operable to couple a corresponding second digit line of a set of second digit lines of the plurality of second digit lines to the circuit system external to the first level above the substrate.

[0008] A method is described. The method may include: performing an access operation on a row of memory cells of a level above a substrate of a memory die, wherein the access operation includes: biasing a word line to activate a plurality of first transistors of the level above the substrate for coupling a corresponding storage element of each memory cell of the row of memory cells with each digit line of a plurality of digit lines; biasing a first activation line to activate a plurality of second transistors of the level above the substrate for coupling a corresponding digit line of a first set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate; and biasing a second activation line to activate a plurality of third transistors of the level above the substrate for coupling a corresponding digit line of a second set of digit lines of the plurality of digit lines with the circuitry external to the level above the substrate.

[0009] A method is described. The method may include forming a tile of a memory array associated with a level above a substrate based at least in part on forming a plurality of memory cells, forming a plurality of digit lines each aligned along a first direction, forming a plurality of word lines each aligned along a second direction and each operable to activate a plurality of first transistors of the tile to couple a respective storage element of each memory cell of a respective row of memory cells with each digit line of the plurality of digit lines, and forming an activation line aligned along the second direction and operable to activate a plurality of second transistors of the tile, each of the plurality of second transistors operable to couple a respective digit line of a set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a memory device supporting a tier selection layout in a memory device according to examples as disclosed herein is described.

[0011] Figure 2 Examples of transistor structures supporting level selection layout in a memory device according to examples as disclosed herein are illustrated.

[0012] Figure 3 Examples of circuits supporting level selection placement in a memory device according to examples as disclosed herein are described.

[0013] Figure 4 and 5 An example of a memory structure supporting a level selection layout in a memory device according to examples as disclosed herein is described.

[0014] Figures 6 to 9 An example of a memory tile supporting a tier selection layout in a memory device according to examples as disclosed herein is illustrated.

[0015] Fig.10 and 11

[0013] A flowchart illustrating one or several methods of supporting tier selection layout in a memory device according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0016] A memory device may include a memory array distributed on one or more levels above a substrate of a memory die (e.g., a semiconductor die, a semiconductor wafer, or a chip), and may include circuitry configured to select a particular portion of the memory array. For example, memory cells of a memory die may be arranged into multiple tiles (e.g., tiles, sub-arrays) formed above a substrate of the memory die, where a tile may be defined by or otherwise include a first set of access lines (e.g., a set of word lines) aligned in a first direction and a second set of access lines (e.g., a set of digit lines) aligned in a second direction. A tile may be selected or enabled by a collection of transistors (e.g., a level select transistor, a tile select transistor, a tile's transistor, or a transistor otherwise associated with the tile) configured to couple a corresponding digital line of the tile with circuitry external to the tile (e.g., signal generation circuitry, sensing circuitry, or decoding circuitry, among other examples), at least some of which may be located on another level of the memory device (e.g., at the substrate level, at another level above the substrate). Select transistors such as level select transistors may be enabled by access lines (e.g., select lines, activation lines) coupled to the gates of the transistors, and activation of such access lines may be associated with power consumption or latency.

[0017] According to examples as disclosed herein, a select transistor of a memory cell, or a select transistor associated with a tile of memory cells, may be activated by various configurations of one or more access lines, wherein the various configurations may be implemented to trade off or otherwise support design and performance characteristics, such as power consumption, layout complexity, operational complexity, and other characteristics. The described techniques may be implemented for (e.g., combined with) other aspects of tile operation, including memory cell routing or balancing, tile selection or signal generation using different levels of transistors (e.g., by operating the select transistors according to a cascade configuration), or various combinations thereof.

[0018] Originally in reference Figures 1 to 5 Features of the present disclosure are described in the context of memory devices, memory structures, and related circuit systems described in reference to FIG. Figures 6 to 9 Features of the present disclosure are described in the context of an exemplary memory tile layout described in the accompanying drawings. These and other features of the present disclosure are further illustrated and described with reference to a flowchart related to a layer selection layout in a memory device, such as reference to Figures 10 to 11 describe.

[0019] Figure 1An example of a memory device 100 that supports a layer selection layout in a memory device according to an example as disclosed herein is described. The memory device 100 may also be referred to as a memory die or an electronic memory device. The memory device 100 may include memory cells 105 that are programmable to store different logical states. In some cases, the memory cell 105 is programmable to store two logical states represented as a logical 0 and a logical 1. In some cases, the memory cell 105 is programmable to store more than two logical states (e.g., as a multi-level cell). The set of memory cells 105 may be part of a memory array 110 of the memory device 100, where in some examples, the memory array 110 may refer to a contiguous tile of memory cells 105 (e.g., a group of contiguous elements of a semiconductor chip).

[0020] In some examples, the memory cell 105 may store a charge representing a programmable logic state (e.g., storing the charge in a capacitor, a capacitive memory element, or a capacitive storage element). In some examples, a charged and uncharged capacitor may represent two logic states, respectively. In some other examples, a positively charged (e.g., first polarity, positive polarity) and a negatively charged (e.g., second polarity, negative polarity) capacitor may represent two logic states, respectively. A DRAM or FeRAM architecture may use such a design, and the capacitor employed may include a dielectric material having a linear or parasitic polarization property as an insulator. In some examples, different charge levels of the capacitor may represent different logic states, which in some examples may support more than two logic states in the corresponding memory cell 105. In some examples such as the FeRAM architecture, the memory cell 105 may include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive) layer between the terminals of the capacitor. Different levels or polarities of polarization of the ferroelectric capacitor may represent different logic states (e.g., supporting two or more logic states in the corresponding memory cell 105).

[0021] In some examples, the memory cell 105 may include or otherwise be associated with a configurable material (which may be referred to as a material memory element, a material storage element, a material portion, etc.). The configurable material may have one or more variable and configurable characteristics or properties (e.g., material states) that may represent different logical states. For example, the configurable material may take different forms, different atomic configurations, different crystallinity, different atomic distributions, or otherwise maintain different characteristics that may be used to represent one logical state or another logical state. In some examples, such characteristics may be associated with different resistances, different threshold characteristics, or other properties that may be detected or distinguished during a read operation to identify a logical state written to or stored by the configurable material.

[0022] In some cases, the configurable material of the memory cell 105 may be associated with a threshold voltage. For example, when a voltage greater than the threshold voltage is applied across the memory cell 105, current may flow through the configurable material, and when a voltage less than the threshold voltage is applied across the memory cell 105, current may not flow through the configurable material, or may flow through the configurable material at a rate below a certain level (e.g., according to a leakage rate). Thus, depending on the portion of the configurable material of the memory cell 105 that is written with one logic state or another logic state, a voltage applied to the memory cell 105 may result in a different current flow, or a different perceived resistance, or a change in resistance (e.g., thresholding or switching event). Thus, the magnitude of the current or other characteristics associated with the current resulting from applying a read voltage to the memory cell 105 (e.g., thresholding behavior, resistance breakdown behavior, snapback behavior) may be used to determine the logic state written to or stored by the memory cell 105.

[0023] In the example of memory device 100, each row of memory cells 105 can be coupled with one or more word lines 120 (e.g., WL1 to WLM), and each column of memory cells 105 can be coupled with one or more digit lines 130 (e.g., DL1 to DLN). Each of the word lines 120 and digit lines 130 can be an example of an access line of the memory device 100. In general, one memory cell 105 can be located at (e.g., coupled with, coupled between) an intersection of a word line 120 and a digit line 130. This intersection can be referred to as the address of the memory cell 105. A target or selected memory cell 105 can be a memory cell 105 located at an intersection of a powered or otherwise selected word line 120 and a powered or otherwise selected digit line 130.

[0024] In some architectures, the storage components of the memory cells 105 may be electrically isolated (e.g., selectively isolated) from the digit lines 130 by a cell selection component (which in some examples may be referred to as a switching component or selector device of the memory cells 105 or otherwise associated with the memory cells 105). The word lines 120 may be coupled to the cell selection components (e.g., via a control node or terminal of the cell selection components) and may control the cell selection components of the memory cells 105. For example, the cell selection components may be transistors and the word lines 120 may be coupled to the gates of the transistors (e.g., where the gate nodes of the transistors may be the control nodes of the transistors). Activating the word lines 120 may result in an electrical connection or closed circuit between the respective logical storage components of one or more memory cells 105 and the one or more corresponding digit lines 130, which may be referred to as activating the one or more memory cells 105 or coupling the one or more memory cells 105 with the respective one or more digit lines 130. The digit lines 130 may then be accessed to read from or write to the respective memory cells 105.

[0025] In some examples, the memory cell 105 may also be coupled to one or more plate lines 140 (e.g., PL1 to PLN) or other configurations of plate nodes. In some examples, each of the plate lines 140 may be independently addressable (e.g., to support individual selection or biasing). In some examples, at least a subset of the plurality of plate lines 140 may represent or otherwise be functionally equivalent to a common plate or other common node (e.g., a plate node common to each or a subset of the memory cells 105 in the memory array 110). When the memory cell 105 employs a capacitor for storing a logic state, the digit line 130 may provide access to a first terminal or first plate of the capacitor, and the plate line 140 or other plate node may provide access to a second terminal or second plate of the capacitor. Although the plurality of plate lines 140 of the memory device 100 are shown as being substantially parallel to the plurality of digit lines 130, in other examples, the plurality of plate lines 140 may be substantially parallel to the plurality of word lines 120, or in any other configuration (e.g., a common planar conductor, a common plate layer, a common plate node).

[0026] Access operations (e.g., reading, writing, rewriting, and refreshing) may be performed on the memory cell 105 by activating or selecting a word line 120, a digit line 130, or a plate line 140 coupled to the memory cell 105, which may include applying a voltage, charge, or current to a corresponding access line. When a memory cell 105 is selected (e.g., in a read operation), the resulting signal may be used to determine the logic state stored by the memory cell 105. For example, a memory cell 105 having a capacitive memory element storing a logic state may be selected, and the resulting charge flow through the access line or the resulting voltage of the access line may be detected to determine the programmed logic state stored by the memory cell 105.

[0027] Access to memory cells 105 may be controlled using row component 125 (e.g., row decoder), column component 135 (e.g., column decoder), or plate component 145 (e.g., plate decoder), or a combination thereof. For example, row component 125 may receive a row address from memory controller 170 and activate corresponding word line 120 based on the received row address. Similarly, column component 135 may receive a column address from memory controller 170 and activate corresponding digit line 130. In some examples, such access operations may be accompanied by plate component 145 biasing one or more of plate lines 140 (e.g., biasing one of plate lines 140, biasing some or all of plate lines 140, biasing a common plate, biasing a plate node).

[0028] In some examples, the memory controller 170 may use one or more components (e.g., row components 125, column components 135, plate components 145, sense components 150) to control the operation (e.g., read operation, write operation, rewrite operation, refresh operation) of the memory cell 105. In some cases, one or more of the row components 125, column components 135, plate components 145, and sense components 150 may be co-located with or otherwise included within the memory controller 170. The memory controller 170 may generate row and column address signals to activate the desired word lines 120 and digit lines 130. The memory controller 170 may also generate or control various voltages or currents used during operation of the memory device 100.

[0029] When accessing memory cell 105 (e.g., in cooperation with memory controller 170) to determine the logic state written to or stored by memory cell 105, memory cell 105 may be read (e.g., sensed) by sense component 150. For example, sense component 150 may be configured to evaluate a current or charge transfer through or from memory cell 105, or a voltage resulting from coupling memory cell 105 with sense component 150, in response to a read operation. Sense component 150 may provide an output signal indicative of the logic state read from memory cell 105 to one or more components (e.g., to column component 135, input / output component 160, memory controller 170).

[0030] The sensing component 150 may include various switching components, selection components, transistors, amplifiers, capacitors, resistors, or voltage sources to detect or amplify differences in sense signals (e.g., differences between a read voltage and a reference voltage, a read current and a reference current, a read charge and a reference charge), which in some examples may be referred to as latches. In some examples, the sensing component 150 may include a set of components (e.g., circuit elements) that are repeated for each of a set or subset of digit lines 130 connected to the sensing component 150. For example, the sensing component 150 may include separate sensing circuits (e.g., separate or duplicate sense amplifiers, separate or duplicate signal generation components) for each of the set of digit lines 130 coupled to the sensing component 150, so that logic states can be separately detected for respective memory cells 105 coupled to respective ones of the set of digit lines 130.

[0031] Memory cell 105 may be set or written by activating (e.g., via memory controller 170) an associated word line 120, digit line 130, or plate line 140. In other words, a logic state may be stored in memory cell 105. Row component 125, column component 135, or plate component 145 may accept data to be written to memory cell 105, for example, via input / output component 160. In some examples, a write operation may be performed at least in part through sense component 150, or a write operation may be configured to bypass sense component 150.

[0032] In the case of a capacitive memory element, the memory cell 105 may be written by applying a voltage to or across the capacitor, and then isolating the capacitor (e.g., isolating the capacitor from the voltage source used to write the memory cell 105, floating the capacitor) to store charge in the capacitor associated with the desired logic state. In the case of a ferroelectric memory, the ferroelectric memory element (e.g., a ferroelectric capacitor) of the memory cell 105 may be written by applying a voltage of a magnitude high enough to polarize the ferroelectric memory element with the polarization associated with the desired logic state (e.g., applying a saturation voltage), and the ferroelectric memory element may be isolated (e.g., floating), or a zero net voltage or bias may be applied across the ferroelectric memory element (e.g., ground, virtual ground, or equalizing the voltage across the ferroelectric memory element). In the case of a material memory architecture, the memory cell 105 may be written by applying a current, voltage, or other heating or bias to the material memory element to configure the material according to the corresponding logic state.

[0033] In some examples, the memory device 100 may include a plurality of memory arrays 110 stacked arranged in a layer or tier relative to a substrate (e.g., a semiconductor substrate, a crystalline silicon substrate, a crystalline semiconductor substrate, a portion of a semiconductor wafer) of the memory device 100. In some examples, the memory cells 105 of the memory die may be arranged in a plurality of tiles (e.g., tiles, sub-arrays) above the substrate. For example, a tile may be defined by or otherwise include a set of word lines 120 aligned in a first direction and a set of digit lines 130 aligned in a second direction. In various examples, the tiles may be arranged in one or more layers or tiers relative to the substrate of the memory device 100.

[0034] Circuitry supporting access or operation of multiple memory arrays 110 may be positioned below one or more memory arrays 110, which may refer to a location at least partially between the memory array 110 and the substrate. For example, one or more row components 125, one or more column components 135, one or more plate components 145, one or more sense components 150, or one or more input / output components 160, or any combination thereof, may be positioned below the memory array 110, and in some examples may include transistors formed at least in part by doping portions of the substrate (e.g., substrate-based transistors, transistors having channels formed of doped crystalline silicon or other semiconductors). When scaling the memory device 100 with a greater number of levels or tiers of the memory array 110, the area of ​​the substrate used to support the circuitry may increase, which may lead to scaling limitations (e.g., related to the limited area of ​​the substrate used to support the circuitry used to access the growing number of levels or tiers of the memory array 110, and by extension the growing number and area for such decoders or other supporting circuitry), as well as other challenges.

[0035] According to examples as disclosed herein, the memory device 100 may include one or more stacked memory arrays 110 arranged as a layer formed above a substrate, and layer selection circuitry (e.g., layer selection transistors, layer decoding or addressing switches) or shunt circuitry (e.g., shunt transistors, equalization components) or a combination thereof may be distributed in the layers to utilize common substrate-based circuitry, such as logic or addressing circuitry, signal generation circuitry, sensing circuitry, or other circuitry. For example, each memory array 110 of the stack may include a set of digit lines 130 of a corresponding layer and layer selection circuitry, such as layer selection transistors or other switching circuitry (e.g., of a corresponding layer, another layer), which is operable to couple the set of digit lines 130 with a column decoder or other circuitry that may be shared in multiple layers (e.g., coupled with multiple layers). In some examples, each memory array 110 of the stack may additionally or alternatively include shunt circuitry, such as shunt transistors or other switching circuitry (e.g., of a corresponding level, another level), which is operable to couple a set of digit lines 130 with a plate node (e.g., an associated plate node, one or more associated plate lines 140) to thereby equalize the voltage across the memory cells 105 of the corresponding memory array 110.

[0036] In some examples, select transistors such as level select or shunt transistors may include thin film transistors utilizing thin film manufacturing techniques (e.g., above a substrate), such as various techniques for forming vertical transistors (e.g., transistors having vertical channels, transistors having channels oriented at least partially in a thickness or height direction relative to a substrate), or transistors having channel portions formed at least partially by polysilicon or crystalline silicon formed above a substrate, as well as other techniques. Implementing such selection circuitry at various levels of this memory device 100 may mitigate or alleviate area utilization challenges at the substrate level, such as moving some aspects of decoding or addressing into a level or tier above the substrate, or may support utilizing common logic signals or decoding circuitry, either or both of which may improve scaling of the memory device by supporting a larger number of levels for a given area of ​​substrate-based circuitry. In some examples, a select transistor of a memory cell, or a select transistor associated with a block of memory cells (e.g., a level select transistor, a shunt transistor), may be activated by various configurations of one or more access lines, wherein the various configurations may be implemented to trade off or otherwise support design and performance characteristics, such as power consumption, layout complexity, operational complexity, and other characteristics.

[0037] Figure 2An example of a transistor structure 200 supporting a level selection layout in a memory device according to an example as disclosed herein is illustrated. The transistor structure 200 illustrates an example of a transistor formed at least in part by a portion of a substrate 220 (e.g., a doped portion 240 of the substrate 220), and may illustrate an arrangement of features of the transistor configured as a planar transistor arrangement. The substrate 220 may be a portion of a semiconductor chip, such as a silicon chip (e.g., crystalline silicon, single crystal silicon) of a memory die. For illustrative purposes, aspects of the transistor structure 200 may be described with reference to the x-direction, y-direction, and z-direction (e.g., height direction) of a coordinate system 210. In some examples, the z-direction may illustrate a direction perpendicular to a surface of the substrate 220 (e.g., a surface in an xy plane, a surface on or above which other materials may be deposited), and each of the structures illustrated by their respective cross-sections in the xz plane may extend a distance (e.g., length) along the y-direction.

[0038] The transistor structure 200 illustrates an example of a transistor channel electrically coupled between a terminal 270-a-1 and a terminal 270-a-2, which may include one or more doped portions 240 of a substrate 220. In various examples, one of the terminals 270-a-1 or 270-a-2 may be referred to as a source terminal, and the other of the terminals 270-a-1 or 270-a-2 may be referred to as a drain terminal, where such designation or naming may be based on a configuration or relative biasing of a circuit that includes the transistor structure 200. A channel or channel portion of a transistor may include or refer to one or more portions of a transistor structure that are operable to open or close a conductive path (e.g., modulate conductivity, form a channel, open a channel, close a channel) between a source and a drain (e.g., between terminal 270-a-1 and terminal 270-a-2) based at least in part on a voltage of a gate (e.g., a gate terminal, gate portion 250). In other words, the channel portion of the transistor structure can be configured to activate, deactivate, become conductive, or non-conductive based at least in part on a voltage of a gate portion, such as gate portion 250. In some examples of transistor structure 200 (e.g., a planar transistor arrangement), the channel portion formed by one or more doped portions 240 of substrate 220 can support a conductive path in a substantially horizontal or in-plane direction (e.g., along the x-direction, in the xy plane, within a surface of substrate 220, or in a direction parallel to the surface).

[0039] In some examples, the gate portion 250 can be physically separated from the channel portion (e.g., separated from the substrate 220, separated from one or more of the doped portions 240) by a gate insulating portion 260 (e.g., a gate dielectric). Each of the terminals 270 can be in contact with or otherwise coupled (e.g., electrically, physically) to a corresponding doped portion 240-a, and each of the terminals 270 and the gate portion 250 can be formed of a conductive material (e.g., a metal or metal alloy) or a polycrystalline semiconductor (e.g., polysilicon) and other conductor or semiconductor arrangements formed above the substrate 220.

[0040] In some examples, transistor structure 200 can be operated as an n-type or n-channel transistor, where a relatively positive voltage above a threshold voltage (e.g., an applied voltage having a positive magnitude relative to the source terminal, which is greater than the threshold voltage) applied to gate portion 250 activates a channel portion or otherwise enables a conductive path between terminals 270-a-1 and 270-a-2 (e.g., in a direction generally aligned with the x-direction within substrate 220). In some such examples, doped portion 240-a can refer to a portion having an n-type doping or an n-type semiconductor, and doped portion 240-b can refer to a portion having a p-type doping or a p-type semiconductor (e.g., a channel portion having an NPN configuration along the x-direction or channel direction).

[0041] In some examples, transistor structure 200 can be operated as a p-type or p-channel transistor, where a relatively negative voltage above a threshold voltage (e.g., an applied voltage having a negative magnitude relative to the source terminal that is greater than the threshold voltage) applied to gate portion 250 activates a channel portion or otherwise enables a conductive path between terminals 270-a-1 and 270-a-2. In some such examples, doped portion 240-a can refer to a portion having a p-type doping or a p-type semiconductor, and doped portion 240-b can refer to a portion having an n-type doping or an n-type semiconductor (e.g., a channel portion having a PNP configuration along the x-direction or channel direction).

[0042] In some examples, circuitry operable to support access operations to memory cells 105 (e.g., row components 125, column components 135, plate components 145, sensing components 150, memory controller 170, or various combinations thereof) may be formed to include respective sets of transistors each having an arrangement of transistor structures 200, wherein each of the transistors may have a channel portion formed by a respective doped portion 240 of substrate 220. In some examples, such transistors may utilize the crystalline semiconductor material of substrate 220 to achieve various performance characteristics or manufacturing characteristics of such materials or arrangements. Some examples of such arrangements may be implemented in a complementary metal oxide semiconductor (CMOS) configuration, which may refer to various examples of complementary and symmetric pairs of p-type transistors and n-type transistors (e.g., for logic functions). However, such structures or arrangements of substrate-based transistors may be limited by the available area of ​​substrate 220 (e.g., below memory array 110 or a stack of levels or layers of memory array 110).

[0043] According to examples as disclosed herein, various aspects of the column components 135 and other circuitry (e.g., shunt circuitry, signal generation circuitry) may alternatively be located away from the substrate 220 (e.g., located above the substrate 220), including distributing various components or circuitry to stacked levels or layers of the memory array 110. For example, some circuitry (e.g., transistors supporting aspects of decoding or addressing associated with the column components 135, or transistors supporting aspects of voltage equalization between the digit lines 130 and the plate nodes (e.g., plate lines 140) of the non-selected memory array 110) may be formed in one or more layers or levels above the substrate 220, where such transistors may include or be referred to as thin film transistors or vertical transistors, among other configurations or terms. In some examples, activation of such transistors may be associated with power consumption or latency, and various activation configurations may be implemented to trade off or otherwise support design and performance characteristics, such as power consumption, layout complexity, operational complexity, and other characteristics.

[0044] Figure 3 An example of a circuit 300 supporting a level selection layout in a memory device according to an example as disclosed herein is illustrated. The circuit 300 may include a plurality of j memory arrays 110-a (e.g., memory arrays 110-a-1 through 110-aj), each of which may be associated with a level (e.g., a layer, a vertical position, a height) above a substrate (e.g., substrate 220) of a memory die. For clarity of illustration, the components of the memory array 110-a are described with reference to the first memory array 110-a-1, but each of the memory arrays 110-a-1 through 110-aj of the circuit 300 may be associated with corresponding components or functionality that are similar, different, or some combination thereof.

[0045] The first memory array 110-a-1 may include a set of memory cells 105-a that may be arranged according to m columns and n rows (e.g., memory cells 105-a-11 to 105-a-mn, a set of memory cells 105 associated with the first memory array 110-a-1). In the example of the circuit 300, each of the memory cells 105-a includes a corresponding capacitor 320-a and a corresponding cell selection component 330-a (e.g., a cell selection transistor). In some examples, one or more of the capacitors 320-a may be a ferroelectric capacitor operable to store a charge or polarization corresponding to a logic state (e.g., for the ferroelectric memory cell 105-a, according to a ferroelectric memory architecture). The ferroelectric material used in the ferroelectric capacitor 320 may be characterized by an electrical polarization, in which the material maintains a non-zero charge in the absence of an electric field. The electrical polarization within the ferroelectric capacitor 320 results in a net charge at the surface of the ferroelectric material, and attracts opposite charges through the terminals of the ferroelectric capacitor 320. Thus, charge can be stored at the interface of the ferroelectric material and the capacitor terminal. In some examples, the memory cell 105-a can include storage elements of different memory architectures, such as linear capacitors (e.g., in DRAM applications), transistors (e.g., in NAND applications, in SRAM applications), or material memory elements (e.g., chalcogenide memory elements, resistive memory elements, thresholded memory elements), as well as other types of memory elements.

[0046] Each of the memory cells 105-a may be coupled to a word line 120 (e.g., one of word lines 120-a-1 to 120-an), a digit line 130 (e.g., one of digit lines 130-a-1 to 130-am), and a plate line 140-a. In some illustrative examples, memory cells 105-a-11 to 105-a-1n may represent a set or column of memory cells 105 coupled to or between a digit line 130 (e.g., digit line 130-a-1) and a plate line 140-a (e.g., a plate node). In some illustrative examples, memory cells 105-a-11 to 105-a-m1 may represent a set or row of memory cells 105 coupled to a word line 120 (e.g., word line 120-a-1). Although the memory array 110-a-1 is illustrated as including a common plate line 140-a for all of the memory cells 105-a, some instances of the circuit 300 may include a separate plate line 140 for each row of memory cells 105-a or each subset of rows of memory cells 105-a (e.g., an independently accessible plate line 140 associated with each of the word lines 120-a) or a separate plate line 140 for each column of memory cells 105-a or each subset of columns of memory cells 105-a (e.g., an independently accessible plate line 140 associated with each of the digit lines 130-a), as well as other configurations.

[0047] Each of the word lines 120-a (eg, word lines WL1 to WL n Each of the word lines may be connected to a corresponding word line voltage V WL 1 and 12. The row components 125-a and 125-b are associated with each other and may be coupled to a row component 125-a (e.g., a row decoder). The row component 125-a may couple one or more of the word lines 120-a with various voltage sources (not shown). In some illustrative examples, the row component 125-a may selectively couple one or more of the word lines 120-a with a voltage source having a relatively high voltage (e.g., a selection voltage, which may be a voltage greater than 0V) or a voltage source having a relatively low voltage (e.g., a deselection voltage, which may be a ground voltage of 0V or a negative voltage). Each of the digit lines 130-a (e.g., digit lines DL1 to DL m Each of the digital lines may be connected to the corresponding digital line voltage V DL 3. The memory cell 105-a or capacitor 320-a or other storage element thereof may be coupled to the digit line 130-a based at least in part on the activation or activation voltage of the associated word line 120-a.

[0048] In some examples, row components 125-a may be shared among (e.g., coupled to, for decoding, addressing, or accessing) memory arrays 110-a-1 through 110-aj. In various examples, activation of a word line 120-a of memory array 110-a-1 may or may not be accompanied by corresponding activation of word lines 120 of one or more of the other memory arrays 110-a (e.g., activating a row in each of memory arrays 110-a-1 through 110-aj, activating a row in a subset of memory arrays 110-a-1 through 110-aj). For example, each output terminal or node of the row component 125-a may be coupled to a corresponding word line 120 of one or more of the memory arrays 110-a-1 to 110-aj or a subset thereof, which may include interconnects (e.g., vias, trenches, through-silicon vias (TSVs)) through a level or layer of the memory device 100 or a memory die including the circuit 300 to interconnect the word lines 120 of different levels or layers (e.g., different ones of the memory array 110-a).

[0049] The plate line 140 - a (eg, plate line PL) may be connected to a plate line voltage V as described above. PL The plate line 140-a is associated with the plate component 145-a (e.g., a plate decoder). The plate component 145-a can couple the plate line 140-a with various voltage sources (not shown). In one example, the plate component 145-a can selectively couple the plate line 140-a with a voltage source having a relatively high voltage (e.g., a plate high voltage, which can be a voltage greater than 0V) or a voltage source having a relatively low voltage (e.g., a plate low voltage, which can be a ground voltage of 0V or a negative voltage).

[0050] In some examples, plate components 145-a may be shared among (e.g., coupled to, for decoding, addressing, or accessing) memory arrays 110-a-1 through 110-aj. In various examples, activation of plate line 140-a of memory array 110-a-1 may or may not be accompanied by corresponding activation of plate lines 140 of one or more of the other memory arrays 110-a (e.g., activating a common plate in each of memory arrays 110-a-1 through 110-aj, activating a common plate in a subset of memory arrays 110-a-1 through 110-aj). For example, each output terminal or node of plate component 145-a may be coupled with a corresponding plate line 140 of one or more of memory arrays 110-a-1 through 110-aj, or some subset thereof, which may include interconnects (e.g., vias, slots, TSVs) through a layer or tier of memory device 100 or a memory die including circuit 300 to interconnect plate lines 140 of different layers or tiers. In some examples, one or more plate lines 140 of each of memory arrays 110-a may be independently addressable or may otherwise be biased independently of one another by plate component 145-a.

[0051] The sensing component 150-a may include various components for accessing (e.g., reading, writing) the memory cells 105 of the memory array 110-a-1 to 110-aj. For example, the sensing component 150-a may include a set of i sense amplifiers 340-a (e.g., sense amplifiers 340-a-1 to 340-ai) respectively coupled between corresponding signal lines 345-a and reference lines 355. Each sense amplifier 340-a may include various transistors or amplifiers to detect, convert, or amplify differences in signals (which may be referred to as latching). For example, the sense amplifier 340-a may include a sense signal voltage (e.g., V sig ) and a reference signal voltage (e.g., V ref) circuit elements. The output of sense amplifier 340 can be driven to a higher (e.g., positive) voltage or a lower voltage (e.g., negative voltage, ground voltage) based on the comparison at sense amplifier 340. To support such sensing, circuit 300 may include various instances of signal generating circuitry, such as voltage sources, switching components, capacitors (e.g., integrating capacitors, capacitors different from capacitor 320 of memory cell 105-a), amplifiers (e.g., charge transfer sense amplifiers, transistors operating in a cascade configuration, transistors operating in a voltage control or regulation configuration), or other circuitry, which may be distributed across various locations of circuit 300 (e.g., within sensing component 150-a, between sensing component 150-a and memory cell 105-a, coupled to intermediate line 365-a or digital line 130-a).

[0052] In some examples, electrical signals associated with this latching may be communicated between the sensing component 150-a (e.g., the sense amplifier 340-a) and the input / output component 160, for example, via an I / O line (not shown). In some examples, the sensing component 150-a may communicate with a memory controller (not shown) (e.g., reference Figure 1 150-a, which can control various operations of the sensing component 150-a). In some examples, the activation logic signal SE can be referred to as "enabling" or "activating" the sensing component 150-a or its sense amplifier 340-a. In some examples, the activation logic signal SE can be referred to as or part of an operation called "latching" the result of accessing the memory cell 105.

[0053] The circuit 300 may implement various techniques for multiplexing the digit lines 130 with the sense amplifiers 340-a to support accessing the memory cells 105-a. For example, the number of sense amplifiers 340-a of the sense component 150-a may be less than the number of digit lines 130 in the memory arrays 110-a-1 through 110-aj, and a particular one of the digit lines 130 of the memory arrays 110-a-1 through 110-aj may be coupled with a particular one of the sense amplifiers 340-a for a given duration of time in which an access operation is performed. According to examples as disclosed herein, the circuit 300 may support such multiplexing using a combination of a column decoder 360 and a plane decoder 370, which may be referred to as reference numerals. Figure 1 The distribution or separation of components or functionality of column component 135 is described.

[0054] The column decoder 360 may be configured to support i sense amplifiers 340-a or i signal lines 345-a (eg, signal lines 345-a-1 to 345-ai, SL1 to SL2). i) and m intermediate lines 365 (e.g., intermediate lines 365-a-1 to 365-am, IL1 to IL m ) multiplexing or coupling between. In some examples, m can be greater than i, such as m is an integer multiple of i. In some examples, m can be equal to the number of digit lines 130 or columns in each of the memory arrays 110-a-1 to 110-aj.

[0055] The plane decoder 370 is operable to select from the memory arrays 110-a, which may include selective coupling or isolation of respective transistors 380-a (e.g., plane select transistors) between the intermediate lines 365-a and the digit lines 130-a of one or more selected memory arrays 110-a. In the example of the circuit 300, each memory array 110-a may be associated with a respective row of transistors 380-a that may be activated using respective plane select lines 375-a. For example, the memory array 110-a-1 may be associated with transistors 380-a-11 through 380-a-1m and the plane select line 375-a-1, the memory array 110-aj may be associated with transistors 380-a-j1 through 380-a-jm and the plane select line 375-aj, and so on. In some examples, the number of memory arrays 110-a and layer select lines 375-a (e.g., the number j) may be equal to the number of layers or levels of the circuit 300 (e.g., the memory device 100 or a memory die including the circuit 300). In some examples (e.g., when multiple memory arrays 110-a are positioned on the same layer or level), the number of memory arrays 110-a and layer select lines 375-a may be greater than the number of layers or levels (e.g., an integer multiple of the layers or levels).

[0056] In some examples, when an access operation is to be performed on a memory cell 105-a of the memory array 110-a-1, the level decoder 370 may activate the level select line 375-a-1. Activating the level select line 375-a-1 may activate each of the transistors 380-a-11 to 380-a-1m, thereby coupling the digital lines 130-a-1 to 130-am with the column decoder 360 (e.g., via the intermediate lines 365-a-1 to 365-am). The column decoder 360 may accordingly operate to couple one or more of the digital lines 130-a-1 to 130-am of the selected memory array 110-a-1 with the sense amplifiers 340-a-1 to 340-ai to support various access operations (e.g., read operations, write operations).

[0057] In some examples, when an access operation is to be performed on a memory cell 105-a of the memory array 110-a-1, the plane decoder 370 may deactivate other plane select lines 375 (e.g., plane select line 375-aj, etc.), which may deactivate each of the other transistors 380 (e.g., transistors 380-a-j1 through 380-a-jm, etc.), thereby decoupling the digit lines 130 of the other memory arrays 110-a from the column decoder 360 (e.g., from the middle lines 365-a-1 through 365-am). In some examples, such isolation may improve read margins, power consumption, or other operations of the circuit 300 due to reduced intrinsic capacitance or reduced charge leakage or dissipation (e.g., through the unselected memory array 110-a) from the perspective of the sense amplifier 340-a, among other phenomena. In addition, this isolation can support simplified row decoding (for example, when the word lines 120 of different memory arrays 110-a are coupled to the same or common output of the row component 125-a) because the rows of multiple memory arrays 110-a can be activated while only the digit lines 130 of a particular selected memory array 110-a can be coupled to the circuit system supporting a given access operation.

[0058] In some examples, the plane decoder 370 and transistor 380 may be operable to support aspects of both decoding functionality and signal generation functionality (e.g., for generating a read signal from accessing memory cell 105-a). For example, under a first operating condition, the plane decoder 370 may bias the plane select line 375-a with a first voltage (e.g., a deselect voltage), which may be associated with the isolation of the corresponding digital line 130-a from the intermediate line 365-a (e.g., operating transistor 380-a in an "off" or open circuit mode, in a digital switching mode). In some examples, such operation may be associated with deselecting the memory array 110-a (e.g., deselecting a plane), which may support performing an access operation on another memory array 110-a selected, or other examples where the memory device does not perform an access operation. In some examples, the first voltage may be associated with a ground voltage or another voltage associated with a logic 0 or deactivation of digital signaling or other logic or switching operations of the memory device 100. In some examples, the first voltage can be a negative voltage, which can be associated with reduced leakage across transistor 380 (eg, compared to ground or zero gate voltage at transistor 380 ).

[0059] In a second operating condition, the plane decoder 370 may bias the plane select line 375-a with a second voltage (e.g., a signal generation voltage), which may be associated with at least one temporary coupling between the corresponding digit line 130-a and the intermediate line 365-a, including such coupling in a subthreshold mode (e.g., in a signal generation mode, in an analog cascade, or in a voltage control mode) of the transistor 380. In some examples, such an operation may be associated with selecting the memory array 110-a (e.g., to perform a read operation on the digit line 130-a). In some examples, the second operating condition may support read signal generation (e.g., at the intermediate line 365-a, at the signal line 345-a) based at least in part on the state stored at the corresponding memory cell 105 and the magnitude of the second voltage. In the second operating condition, transistor 380 may be operated or otherwise referred to as a cascode, voltage controller, voltage regulator, or charge transfer sense amplifier, which is related to how transistor 380 can regulate the flow of charge in response to a voltage change across transistor 380 (e.g., between a source node of transistor 380 and a gate node of transistor 380). For example, biasing the gate of transistor 380 with the second voltage may throttle or otherwise control the flow of charge (e.g., current) between the corresponding digit line 130-a and the corresponding intermediate line 365-a. In some examples, the second voltage may be configured based on various conditions of the memory device 100. For example, the plane decoder 370 may be operated to generate the second voltage based on a voltage level (e.g., power supply voltage, regulated voltage) provided to or by the memory device 100, the temperature of the memory device 100, or a combination thereof, which may support adapting the operation of signal generation to various process, voltage, or temperature variability between memory devices 100.

[0060] In a third operating condition, the plane decoder 370 may bias the plane select line 375-a with a third voltage (e.g., a select voltage), which may be associated with coupling of the corresponding digit line 130-a with the intermediate line 365-a (e.g., in a "closed" or closed-loop mode, in a digital switching mode), which may include such coupling in a saturation mode of the transistor 380-a. In some examples, such operation may be associated with selecting the memory array 110-a (e.g., selecting a plane), such as to perform a write operation on the corresponding digit line 130-b. In some examples, the third voltage may have a level associated with a logic 1 or activation of digital signaling or other logic or switching operations of the memory device 100. In some examples, the third voltage may be a relatively large voltage (e.g., greater than the second voltage) that modulates the conductivity of the channel of the transistor 380 to a relatively high value (e.g., low resistivity). For some aspects of access operations (e.g., during write operations), this condition may support relatively low impedance or low latency.

[0061] In some examples, circuit 300 may include one or more capacitors (e.g., integrating capacitors, not shown) that may support cascade or charge transfer sense amplification functionality of transistor 380-a. In some examples, each of intermediate lines 365-a may be associated with a respective capacitor that may be associated with a number of capacitors in circuit 300 equal to the number of columns of memory cells 105-a in each memory array 110-a. In some other examples, each of signal lines 345-a may be associated with a respective capacitor that may be associated with a number of capacitors in the circuit equal to the number of sense amplifiers 340-a in sense component 150-a.

[0062] In some examples, the plane decoder 370 or some other decoder circuitry may also be operable to support shunting of the memory array 110-a, which may include coupling (e.g., direct connection, shorting) of or between the digit lines 130-a of the memory array 110-a and one or more plate lines 140-a of the memory array 110-a. Such shunting may equalize the voltage between the digit lines 130-a and one or more plate lines 140-a of the memory array 110-a, which may equalize the voltage across the memory cells 105 of the memory array 110-a (e.g., equalizing the voltage across the capacitor 320 when the corresponding cell selection component 330 is activated during the shunting or equalizing operation). Voltage equalization across memory cells 105 that are not targeted for access operations may support preventing or mitigating voltage disturbances that may affect the stored polarization at the respective memory cells 105, as well as other purposes.

[0063] In some examples, the shunt functionality may include selective coupling or isolation of respective transistors 390-a (e.g., shunt transistors) between the digit lines 130-a and plate lines 140-a via one or more non-selected memory arrays 110-a (e.g., one or more memory arrays 110-a that are not selected for access operations). In the example of circuit 300, each memory array 110-a may be associated with a respective row of transistors 390-a that may be activated using respective level shunt lines 385-a. For example, memory array 110-a-1 may be associated with transistors 390-a-11 through 390-a-1m and level shunt lines 385-a-1, memory array 110-aj may be associated with transistors 390-a-j1 through 390-a-jm (not shown) and level shunt lines 385-aj, and so on. In various examples, the number of level-shunt lines 385 - a (eg, number j) may be equal to or greater than the number of levels or tiers of the circuit 300 .

[0064] In some examples, when an access operation is to be performed on a memory cell 105 of a memory array 110-aj (e.g., a selected or designated memory array 110-a), the plane decoder 370 may activate the plane branch line 385-a-1, etc. (e.g., each of the plane branch lines 385-a-1 to 385-a-(j-1), which may correspond to the memory array 110-a that is also decoupled from the column decoder 360 via the corresponding transistor 380-a). In some examples, activating the plane branch line 385-a-1 may activate each of the transistors 390-a-11 to 390-a-1m, thereby coupling the digit lines 130-a-1 to 130-am with the plate line 140-a. In addition, the plane decoder can deactivate the plane shunt line 385-aj, which can deactivate each of the transistors 390-a-j1 through 390-a-jm of the memory array 110-aj, thereby opening or disconnecting the direct connection between the digit lines 130-j-1 through 130-jm and the plate line 140-j (not shown) connecting the memory array 110-aj. In some examples, each of the plane shunt lines 385-a-1 through 385-aj can be activated when the circuit 300 is operating in an idle or standby condition.

[0065] In some examples, the level decoder 370 may operate the level select lines and level shunt lines using common logic signals and other techniques for coordinating activation and deactivation. For example, activation of the level select line 375-a-1 may be associated with deactivation of the level shunt line 385-a-1, or deactivation of the level select line 375-a-1 may be associated with activation of the level shunt line 385-a-1, or both. In some examples, such techniques may be based on a common logic signal for the memory array 110-a, where activation of this common logic signal for the memory array 110-a-1 may be associated with both activation of the level select line 375-a-1 and deactivation of the level shunt line 385-a-1, or vice versa. In some examples, the common logic signal may be applied to the gate of each of the transistors 380 and 390 (e.g., when the transistor 380 is associated with a different channel type than the transistor 390). In some other examples, a common logic signal may be applied to the gate of transistor 380 or transistor 390, and an inversion may be applied to the common logic signal before being applied to the gate of the other of transistors 380 or 390 (e.g., when transistors 380 and 390 are associated with the same channel type). In some examples, activation of transistor 380 or 390 may be delayed relative to deactivation of the other of transistors 380 or 390, which may reduce or eliminate the duration that both transistors 380 and transistor 390 are in a conductive state, which may reduce power consumption, charge leakage, or signal interference, among other benefits. Although the example of circuit 300 includes transistor 390, various examples of circuit systems and techniques according to examples as disclosed herein may or may not implement transistor 390, or may implement shunting or cell balancing according to other techniques.

[0066] The configuration of components in circuit 300 may support improved flexibility in the layout or formation of memory device 100 or a memory die including circuit 300. For example, row components 125-a, plate components 145-a, sense components 150-a, reference components 350, or column decoders 360, or various combinations thereof, may be formed at least in part by circuitry below memory array 110-a or on another level or layer other than memory array 110-a. In some examples, such circuitry may be formed at least in part on a substrate (e.g., substrate 220, a crystalline semiconductor substrate, or a portion thereof) and may include various configurations of substrate-based transistors (e.g., including one or more sets of transistors in a CMOS configuration according to transistor structure 200).

[0067] According to examples as disclosed herein, transistors 380 and transistors 390 may be positioned above the substrate, including various locations in a layer or level of memory array 110 (e.g., distributed in one or more of the multiple layers or levels above the substrate). For example, thin film fabrication techniques may be used to form transistors 380 and 390, such as including respective channel portions formed of polycrystalline semiconductor material or crystalline semiconductor material (e.g., deposited above substrate 220). In some examples, transistors 380 and 390 may be formed as vertical transistors (e.g., transistors having channel portions aligned in a height direction relative to substrate 220), including various configurations utilizing one or more pillars having a channel material having a conductivity modulatable based on a voltage of a respective gate portion. In some instances, the memory cells 105 of the memory die may be arranged into multiple tiles above the substrate 220, wherein various configurations of transistors 380, layer select lines 375, transistors 390, or layer shunt lines 385 may be implemented for one or more tiles of the memory cells 105 to compromise or otherwise support design and performance characteristics that may achieve, for example, power consumption, layout complexity, operational complexity, and other characteristics, as well as other benefits.

[0068] Figure 4 An example of a memory structure 400 that supports layer selection layout in a memory device according to an example disclosed herein is illustrated. The memory structure 400 may be illustrated as being able to be connected to a substrate 220-a (which may be a reference Figure 2 2 and 3. The memory structure 400 may be used to illustrate an implementation of the memory device 100 or a portion of a memory die formed together with or above the substrate 220-a. Figure 3 300. For illustrative purposes, aspects of memory structure 400 may be described with reference to the x-, y-, and z-directions of coordinate system 401. The z-direction may describe a direction perpendicular to a surface of substrate 220-a (e.g., a surface in an xy plane, a surface on or over which other materials may be deposited), and each of the related structures described by their respective cross-sections in the xz plane may extend a certain distance along the y-direction, or repeat a certain amount (e.g., according to a pitch dimension), or both. In some examples, for illustrative purposes, the x-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells), and the y-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells 105).

[0069] Memory structure 400 illustrates an example of memory arrays 110 associated with different levels 420 (e.g., different layers, a stack of layers, a stack of levels). For example, memory array 110-b-1 may be associated with level 420-a-1 at a first height or position relative to substrate 220-a, and memory array 110-b-2 may be associated with level 420-a-2 at a second (e.g., different) height or position relative to substrate 220-a (e.g., above level 420-a-1 relative to substrate 220-a). Although memory structure 400 illustrates an example with two levels 420-a, the techniques described herein may be applied to memory structures with any number of one or more levels 420.

[0070] At least some, if not all, of the memory arrays 110-b may include respective sets of memory cells 105-b arranged or addressed according to rows (e.g., aligned in the y-direction, addressed according to positions in the x-direction) and columns (e.g., aligned in the x-direction, addressed according to positions in the y-direction). For example, a column of the memory array 110-b-1 may include n memory cells 105-b-11 through 105-b-1n and may be associated with (e.g., formed on, in contact with, coupled to) a digit line conductor 410-a-11 (e.g., an instance of a digit line 130). In some examples, a column of the memory array 110-b-2 may include the same number of memory cells 105-b, which may or may not be physically aligned (e.g., in the z-direction) or overlap (e.g., when viewed in the xy plane) with the memory cells 105-b of the memory array 110-b-1. A certain number (m) of columns may be formed by repeating the illustrated memory cells 105 and digit line conductors 410-a, as well as other features, along the y-direction.

[0071] At least some, if not every, of the memory cells 105-b in the memory structure 400 may include a respective capacitor 320-b and a respective cell selection component 330-b (e.g., a transistor). In the example of the memory structure 400, each of the cell selection components 330-b may be formed as a vertical transistor that may include a channel portion (e.g., a vertical channel) formed at least in part by a respective pillar 430-a or a portion thereof (e.g., along the z-direction), and a gate portion formed at least in part by a respective word line conductor 440-a (e.g., an example of a word line 120). In some examples, the gate portion of the cell selection component 330-b may be a portion or region of a word line 120 or word line conductor 440-a operable to activate the channel portion of the cell selection component 330-b (e.g., to modulate the conductivity of the channel portion). The word line conductor 440-a may extend from one memory cell 105-b to another memory cell 105-b along a direction, such as the y-direction (e.g., the row direction, along a row of memory cells 105-b) and may be coupled to a row component 125 (not shown) for selecting or activating the row of memory cells 105-b (e.g., by biasing the word line conductor 440-a).

[0072] In some examples, word line conductors 440-a of one memory array 110-b (e.g., memory array 110-b-1) may be coupled or connected with word line conductors 440-a of another memory array 110-b (e.g., memory array 110-b-2) so that rows of memory cells 105-b may be activated in common across multiple memory arrays 110-b or multiple levels 420-a (e.g., by sharing a common node or output of row components 125, not shown). In some examples, interconnects between word line conductors 440-a of different levels 420-a may be formed at least in part along the z-direction through one or more vias, trenches, or TSVs, which may be positioned at or near a boundary of the memory array 110-b (e.g., along the y-direction) as well as at other locations relative to the memory array 110-b.

[0073] Each capacitor 320-b for a memory cell 105-b may include a respective dielectric portion 450-a formed between a pillar 430-a associated with the memory cell 105-b or a portion otherwise aligned with the pillar (e.g., a portion aligned in the z-direction, an inner portion of the capacitor 320-b) and a plate conductor 460-a (e.g., an example of a plate line 140, a plate node, or a common plate, an outer portion of the capacitor 320-b). For example, each capacitor 320-b may include a respective inner portion aligned in the z-direction with the pillar 430-a or otherwise coincident with the pillar 430-a, and a respective outer portion separated from the inner portion by a respective dielectric portion 450-a (e.g., at least partially concentric around the inner portion). In some examples, the outer portions of two or more capacitors 320-b may be a contiguous material, such as a contiguous metal or other conductor of a plate line or a common plate node (e.g., of the plate conductor 460-a). In some examples, a portion of the pillar 430-a of the capacitor 320-b may be the same material or combination of materials as a portion of the pillar 430-a of the corresponding cell selection component 330-b (e.g., a doped semiconductor material, a polycrystalline semiconductor). In some examples, a portion of the pillar 430-a of the capacitor 320-b may be or include a different material or combination of materials than a portion of the pillar 430-a of the corresponding cell selection component 330-b (e.g., a metal or conductor portion, a metal layer deposited on or over a surface of the pillar 430-a). In some examples, the dielectric portion 450-a may be formed of a ferroelectric material operable to maintain a non-zero charge or polarization (e.g., corresponding to a stored logic state) in the absence of an electric field.

[0074] In the example of memory structure 400, memory array 110-b-1 may be associated with plate conductor 460-a-1 (e.g., coupled with, including, accessed using plate conductor 460-a-1) and memory array 110-b-2 may be associated with plate conductor 460-a-2. Each of plate conductors 460-a may be coupled with plate component 145 (not shown) for biasing plate conductor 460-a. In the example of memory structure 400, each plate conductor 460-a may be associated with at least one column of memory cells 105-b. In some examples, each of plate conductors 460-a may also extend along the row of memory cells 105-b or some portion thereof in the y-direction, in which case each of plate conductors 460-a may be associated with all memory cells 105-b of the respective memory array 110-b or some subset of the columns of the respective memory array 110-b. In some examples, the plate conductor 460-a may be a metal or other conductor formed over or between the dielectric portions 450-a of the memory cells 105-b of the corresponding memory array 110-b.

[0075] In the example of memory structure 400, each column of memory cells 105-b of each memory array 110-b can be associated with a corresponding transistor 380-b (e.g., a layer select transistor) that can also be formed as a vertical transistor. Each transistor 380-b can be operable to couple a corresponding digit line conductor 410-a with an intermediate line conductor 465-a (e.g., an example of intermediate line 365). In the example of memory structure 400, each intermediate line conductor 465-a can be a combination of a horizontal metal layer formed in contact with pillars 470-a (e.g., above, opposite to digit line conductors 410-a) and a vertical portion coupled to a column decoder 360-a that can be formed by one or more vias, slots, or TSVs. In the example of the memory structure 400, to support m columns of each memory array 110-b, m middle line conductors 465-a can be formed along the y direction, and each middle line conductor 465-a can be coupled or connected to the transistor 380-b of each memory array 110-b or each level 420-a (for example, the middle line conductor 465-a-1 is coupled to transistors 380-b-11 and 380-b-21).

[0076] At least some, if not every, transistor 380-b may include a channel portion (e.g., a vertical channel) formed at least in part by one or more respective pillars 470-a and a gate portion formed at least in part by one or more respective level select conductors 475-a (e.g., instances of level select lines 375). In some examples, the gate portion of transistor 380-b may be a portion or region of level select line 375 operable to activate the channel portion of transistor 380-b (e.g., modulate the conductivity of the channel portion). Level select conductor 475-a may extend from a column of memory cells 105-b to another column, or from one transistor 380-b to another transistor, along a direction, such as the y-direction (e.g., along the row direction, parallel to the rows of memory cells 105), and may be coupled with a level decoder 370 (not shown) for selecting or activating memory array 110-b (e.g., by biasing level select conductor 475-a, by activating a row or other set of transistors 380-b).

[0077] The set of m middle line conductors 465-a may be coupled to a column decoder 360-a, which in turn may be coupled to a sense component 150-b (e.g., via a plurality of signal lines 345). Thus, the combination of a plane decoder 370 (not shown) and a column decoder 360-a may be used to multiplex, address, or otherwise selectively couple the digit line conductors 410-a of the memory arrays 110-b-a and 110-b-2 with the sense component 150-b or its sense amplifier 340 to support various access operations.

[0078] In the example of memory structure 400, each column of memory cells 105-b of each memory array 110-b may also be associated with a corresponding transistor 390-b (e.g., a shunt transistor) that may also be formed as a vertical transistor. Each transistor 390-b may be operable to couple a corresponding digit line conductor 410-a with a conductor portion 490-a (e.g., a corresponding conductor portion 490-a of digit line conductor 410-a, a conductor portion 490-a common to digit line conductors 410-a of memory array 110-b, a plate connection), which conductor portion 490-a may connect or shunt the corresponding digit line conductor 410-a with plate conductor 460-a.

[0079] At least some, if not every, transistor 390-b may include a channel portion (e.g., a vertical channel) formed at least in part by one or more respective pillars 480-a and a gate portion formed at least in part by one or more respective shunt select conductors 485-a (e.g., instances of level shunt line 385). In some examples, the gate portion of transistor 390-b may be a portion or region of level shunt line 385 operable to activate (e.g., modulate the conductivity of) the channel portion of transistor 390-b. The shunt select conductor 485-a may extend from a column of memory cells 105-b to another column, or from one transistor 390-b to another transistor, along a direction, such as the y-direction (e.g., along the row direction, parallel to the rows of memory cells 105), and may be coupled with a level decoder 370 (not shown) for shunting the memory array 110-b (e.g., by biasing the shunt select conductor 485-a, by activating the row of transistors 390-b).

[0080] Conductor portion 490-a or its functionality may be provided by various types of structures. In an example of memory structure 400, each of conductor portions 490-a may include a horizontal conductor portion (e.g., a metal layer, at least a portion aligned along the x-direction) formed in contact with one or more pillars 480-a (e.g., above, opposite to digit line conductor 410-a) and in contact with one or more plate conductors 460-a. In various examples, conductor portion 490-a may be formed using one or more processes or materials common to the formation of intermediate line conductor 465-a or the formation of plate conductor 460-a, or both. In some examples, conductor portion 490-a may include multiple horizontal conductor portions, one or more vertical conductor portions (e.g., slots, vias), or any combination thereof.

[0081] In some examples, the functionality of conductor portion 490 may be provided by a "short" or dummy cell or capacitor (not shown). For example, conductor portion 490 may include a portion aligned with and in contact with one or more pillars 480, or a material portion or extension of pillar 480 that may have similar material, similar size, or other aspects similar to the inner portion of capacitor 320. Additionally or alternatively, conductor portion 490 may include a portion having similar material, similar size, or other aspects similar to the outer portion of capacitor 320. In such cases, conductor portion 490-a may be formed with one or more processes also used to form capacitor 320, but dielectric portion 450 may be omitted. Although examples of memory structure 400 include shunt functionality through transistor 390-b, in some examples, the shunt functionality may be omitted (e.g., omitting transistor 390-b and conductor portion 490), or may be supported by other techniques.

[0082] In various examples, each of pillars 430, 470, and 480 may be operable to support at least a portion of a channel of a corresponding transistor (e.g., a channel aligned in the z-direction or an operable conductive path that supports electrical coupling or a conductive path between source and drain terminals based at least in part on a voltage of a corresponding gate portion, gate terminal, or gate conductor), and may include one or more doped semiconductor portions. For example, to support an n-type transistor, pillar 430, pillar 470, or pillar 480 may include at least one p-type semiconductor portion, or may include an n-type semiconductor, a stack of a p-type semiconductor, and an n-type semiconductor (e.g., in the z-direction) (e.g., in an NPN arrangement in the z-direction), as well as other component materials or arrangements. To support a p-type transistor, pillar 430, pillar 470, or pillar 480 may include at least one n-type semiconductor portion, or may include a stack of a p-type semiconductor, an n-type semiconductor, and a p-type semiconductor (e.g., in the z-direction) (e.g., in a PNP arrangement in the z-direction), as well as other component materials or arrangements. In some examples, a pillar as described herein (e.g., pillar 430, pillar 470, pillar 480) may include one or more electrodes or electrode portions, such as electrodes at one or both ends of the pillar (e.g., the top end, the bottom end, or both).

[0083] Each of pillars 430, 470, and 480 may be associated with a height or height dimension relative to the substrate (e.g., a lower range in the z-direction, an upper range in the z-direction, a span in the z-direction), which may be defined as part of balancing various performance criteria of memory array 110. In some examples, the height dimension or range in the z-direction of pillars 430 and pillars 470, or pillars 430 and pillars 480, or pillars 470 and pillars 480, or pillars 430, 470, and 480 may be the same as or at least partially overlap with the height dimension or range in the z-direction. For example, various combinations of pillars 430, 470, and 480 may have a common height dimension relative to the substrate (e.g., a common upper range, a common lower range, or both). In some examples, pillar 430 may have a height or height dimension different from pillars 470 or pillars 480 or both, such as pillar 430 having an extended height along the z-direction to support one or more features of capacitor 320. Pillars 430, 470 and 480 can be formed to have various cross-sectional shapes (e.g., in the xy plane), such as square, rectangular, circular, oval or polygonal, etc., wherein pillars 430, 470 and 480 can have common or different shapes, or common or different sizes.

[0084] Pillars 430, 470, and 480 may be formed according to various techniques. In some examples, one or more layers or layer stacks of doped semiconductor material may be deposited on or over a substrate (e.g., deposited on or in contact with digit line conductor 410 or a corresponding metal layer), and portions of the deposited layers positioned between respective pillars 430, 470, and 480 (e.g., along the x-direction, along the y-direction) may be etched or grooved to form respective pillars. In some examples, pillars 430, 470, and 480 may be formed of the same material or combination of materials (e.g., formed of the same layer or layer stack to support a common type of transistor channel). In some examples, such layers may include one or more electrode layers, such as an electrode layer above the doped semiconductor material layer stack, an electrode layer below the doped semiconductor material layer stack, or both, and such electrode layers may or may not be etched or grooved along with the pillar formation process. Additionally or alternatively, in some examples, holes or trenches may be etched through the material (e.g., in the z-direction, through the dielectric material, through the gate dielectric material) and the material for pillars 430, 470, or 480 (e.g., one or more doped semiconductor materials, one or more electrode materials) may be deposited in the etched holes or trenches. In examples where the pillar material is deposited into the holes, trenches, or other recesses, pillars 430, 470, and 480 may or may not be formed of the same material or combination of materials.

[0085] In various examples, the number or configuration of pillars 430, 470, and 480 for the respective transistors may be defined or selected for particular characteristics, such as the associated drive strength (e.g., drive current), impedance, activation threshold, or leakage characteristics of a particular transistor or set of transistors. In some examples, multiple pillars 430, multiple pillars 470, or multiple pillars 480 may be described or configured as parallel physical structures (e.g., parallel channels) of a common transistor or transistor component. For example, as illustrated, each of transistors 380-b may include or otherwise be formed to have two pillars 470-a, and each of transistors 390-b may include or otherwise be formed to have two pillars 480-a. However, in other examples, transistor 380, transistor 390, or cell select component 330 may include or otherwise be formed to have any number of one or more pillars 470, 480, or 430, respectively. Similarly, in various examples, capacitor 320 may be formed to have or be formed over any number of one or more pillars 430. In some instances, each pillar 430, 470, or 480 of a set configured in parallel (e.g., activated together) may be described or configured as a component of a single transistor such that the corresponding cell selection, level selection, or level branching may be described or configured as having multiple transistors arranged in parallel.

[0086] In some examples, various combinations of word line conductors 440, level select conductors 475, and shunt select conductors 485 for a given memory array 110 may be formed using one or more common operations, one or more common materials, or otherwise share various aspects of formation or configuration. For example, word line conductors 440, level select conductors 475, and shunt select conductors 485 may be formed using one or more common conductor formation processes (e.g., a common masking process, a common etching process, a common deposition process, or various combinations thereof). In some examples, word line conductors 440, level select conductors 475, and shunt select conductors 485 may be formed to have height dimensions that are within or overlap with height dimensions of at least doped semiconductor portions of pillars 430, 470, and 480 (e.g., to support the function of modulating conductivity through channel portions of cell select element 330, transistor 380, and transistor 390, respectively).

[0087] In various examples, the word line conductor 440, the level select conductor 475, or the shunt select conductor 485 may be formed of a metal or metal alloy (e.g., copper, tungsten, gold, silver, tin, aluminum, or alloys thereof). Such conductors may be separated from the pillars 430, 470, or 480 (in the x-direction, in the y-direction, in the x-direction and the y-direction, in the radial direction) by a gate dielectric that is in contact with the conductor and a portion of the respective pillar. In some examples, the gate conductor may be positioned beside the respective pillar (e.g., as a lateral gate, as a bypass gate, as a pair of gate conductors on either or both sides of the pillar), including a conductor that extends between the pillars in the y-direction and is separated from the pillars in the x-direction by the gate dielectric. In some examples, the gate conductor may include at least a portion that (e.g., partially, completely) surrounds the respective pillar (e.g., as a wrap-around gate, as a circumferential gate, as a concentric gate, as a fully wrap-around gate), wherein at least the respective pillar may be wrapped (e.g., partially wrapped, completely wrapped) with a circumferential gate dielectric that is in contact with the pillar and the conductor. In various instances, the digital line conductor 410 or the intermediate line conductor 465 and other components (e.g., conductors) may be formed from a metal or metal alloy, which may be the same material or a different material as the conductors used to support the gate portion of the transistor (e.g., the word line conductor 440, the level select conductor 475, the branch select conductor 485).

[0088] In some examples, the circuitry of the level decoder 370 (not shown), the column decoder 360-a, or the sensing component 150-b, or any combination thereof, may be substrate based, such as including transistors formed at least in part by doped portions of the substrate 220-b (e.g., transistors configured in a CMOS arrangement according to the transistor structure 200). By including transistors 380-b and 390-b at locations above the substrate 220-a, the memory structure 400 may support improved flexibility in distributing the decoding and shunt circuitry throughout the memory die, which may improve area utilization or semiconductor substrate material utilization, among other benefits.

[0089] In some examples, memory array 110-b or memory cells 105-b may be arranged as a plurality of tiles (e.g., tiles, sub-arrays) above substrate 220-a, which may refer to a set of memory cells 105-b associated with a set of word line conductors 440-a (e.g., a set of word line conductors 440-a arranged or distributed along the x-direction), and a set of digit line conductors 410-a (e.g., arranged or distributed along the y-direction) that may be coupled to the set of memory cells 105-b by activation of this set of word line conductors 440-a. For example, memory array 110-ba may be associated with a first tile, and memory array 110-b-2 may be associated with a second tile. A tile or a portion thereof may be selected or enabled by a set of transistors (e.g., a set or subset of transistors 380-b along the y-direction) that may be configured to couple a corresponding digit line conductor 410-a with circuitry external to the tile (e.g., via a corresponding middle line conductor 465-a) based at least in part on activating (e.g., biasing) a level select conductor 475-a. In some examples, a tile or a portion thereof may be shunted by a set of transistors (e.g., a set or subset of transistors 390-b along the y-direction) that may be configured to couple a corresponding digit line conductor 410-a with one or more plate conductors 460-a based at least in part on activating (biasing) a shunt select conductor 485-a.

[0090] Activation of a level select conductor 475 (e.g., for selecting a level or tile of memory cells 105, or for performing a signal generating operation, such as when transistor 380 is operated in a cascade configuration) or a shunt select conductor 485 may be associated with power consumption or delay, which may be related to the formation of charge on the respective conductor during such activation. In some examples, a relatively long level select conductor 475 or shunt select conductor 485 (e.g., along the y-direction) may be associated with relatively greater power consumption or relatively greater delay, which may be due to relatively greater intrinsic capacitance or relatively greater charge leakage associated with the relatively longer length, among other phenomena. According to examples as disclosed herein, various configurations of level select conductors 475 and shunt select conductors 485 and other features may be implemented to trade off or otherwise support design and performance characteristics, such as power consumption, layout complexity, operational complexity, and other characteristics. For example, for a set of rows of memory cells 105 (e.g., a tile, associated with a set of word line conductors 440-a along the x-direction), columns of memory cells 105 along the y-direction may be arranged or subdivided into one or more sets along the y-direction so that each of the one or more sets of columns may be independently addressed. In some examples, such techniques may be supported by subdividing the level select conductors 475, the shunt select conductors 485, or both into shorter and independently addressable segments along the y-direction that may be shorter than the extent of the word line conductors 440 associated with the tile along the y-direction. In other words, the tiles may be arranged such that the word line conductors 440 of the tile may activate a first number of cell select elements 330 (e.g., along a row of memory cells 105), the level select conductors 475 of the tile may activate a second number of transistors 380 less than or equal to the first number, and the shunt select conductors 485 of the tile (where applicable) may activate a third number of transistors 390 less than or equal to the first number, where the third number may be the same as or different from the second number. Such techniques may support relatively short level select conductors 475 or shunt select conductors 485 (e.g., along the y-direction), which may reduce power consumption or latency in an associated memory device or memory die, among other benefits.

[0091] Although the example of the memory structure 400 illustrates an example in which each level 420-a is associated with one memory array 110-a, the techniques described herein may be implemented to support a memory device or memory die having multiple memory arrays 110 on a given level 420, which may include various common or independent addressing or access techniques, as well as other techniques. Various level layout configurations are implemented. In addition, although the implementation of transistors 380-b and transistors 390-b associated with a given memory array 110-b shows pillars 470-a and 480-a as being within the same level 420-a, other implementations may be provided according to the techniques disclosed herein. For example, such as when level selection, signal generation, or decoding for multiple levels 420 is implemented in a common level (e.g., level 420, substrate level), and shunts are implemented in the respective level 420 of each memory array 110, transistors 380 or transistors 390 may be positioned or placed in a level 420 different from the associated memory array 110.

[0092] Figure 5 An example of a memory structure 500 that supports layer selection layout in a memory device according to an example disclosed herein is illustrated. The memory structure 500 may be illustrated as being able to be connected to a substrate 220-b (which may be a reference Figure 2 20-b) is formed together with or above the substrate 220-b. The memory structure 500 may illustrate an implementation of the reference Figure 3 300 . For illustrative purposes, aspects of memory structure 500 may be described with reference to the x-direction, y-direction, and z-direction of coordinate system 501. The z-direction may describe a direction perpendicular to a surface of substrate 220-b (e.g., a surface in an xy plane, a surface on or over which other materials may be deposited), and each of the related structures described by their respective cross-sections in the xz plane may extend a certain distance along the y-direction, or repeat a certain amount (e.g., according to a pitch dimension), or both. In some examples, for illustrative purposes, the x-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells 105), and the y-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells 105). In some examples, memory structure 500 may include alternative arrangements of components similar to those described with reference to memory structure 400 (including components with similar element numbers), and the description of such components or their formation with reference to memory structure 400 may apply to components of memory structure 500.

[0093] Memory structure 500 illustrates an example of memory arrays 110 associated with different tiers 420. For example, memory arrays 110-c-1 and 110-c-3 may be associated with tier 420-b-1 at a first height or position relative to substrate 220-b, and memory arrays 110-c-2 and 110-c-4 may be associated with tier 420-b-2 at a second (e.g., different) height or position relative to substrate 220-b (e.g., above tier 420-d-1 relative to substrate 220-b). Although memory structure 500 illustrates an example with two tiers 420-b, the described techniques may be applied to memory structures with any number of two or more tiers 420.

[0094] Memory structure 500 also illustrates examples of memory arrays 110 associated with different sets 510 of memory arrays 110 (e.g., different subsets of memory arrays 110 that may have different locations above substrate 220 along the x-direction, along the y-direction, or both). For example, memory arrays 110-c-1 and 110-c-2 may be associated with set 510-a-1 and memory arrays 110-c-3 and 110-c-4 may be associated with set 510-a-2. In some examples, memory arrays 110 of sets 510 may be coupled with or otherwise share the same column decoder 360 (e.g., column decoder 360-b), but different sets 510 may be located on different sides or locations relative to a common center line conductor 465 or other circuitry. For example, the set 510-a-1 may be positioned on a first side (eg, left side) of the middle wire conductor 465-b and the set 510-a-2 may be positioned on a second side (eg, right side) of the middle wire conductor 465-b.

[0095] At least some, if not every, memory array 110-c may include respective sets of memory cells 105-c arranged or addressed according to rows (e.g., aligned in the y-direction, addressed according to positions in the x-direction) and columns (e.g., aligned in the x-direction, addressed according to positions in the y-direction). For example, the columns of each of the memory arrays 110-c may include n memory cells, and each may be associated with (e.g., formed on, formed in contact with, coupled with) a digit line conductor 410-b (e.g., an instance of digit line 130). A certain number (m) of columns may be formed by repeating the illustrated memory cells 105-c and digit line conductor 410-b, as well as other features, in the y-direction.

[0096] At least some, if not every, of the memory cells 105-c in the memory structure 500 may include a respective capacitor 320-c and a respective cell select component 330-c (e.g., a transistor). In the example of the memory structure 500, each of the cell select components 330-c may be formed as a vertical transistor that may include a channel portion (e.g., a vertical channel) formed at least in part by a respective pillar 430-b or a portion thereof (e.g., along the z-direction), and a gate portion formed at least in part by a respective word line conductor 440-b (e.g., an example of a word line 120). In some examples, the gate portion of the cell select component 330-c may be a portion or region of a word line 120 or word line conductor 440-b operable to activate the channel portion of the cell select component 330-c (e.g., to modulate the conductivity of the channel portion). The word line conductor 440-b may extend from one memory cell 105-c to another memory cell 105-c along a direction, such as the y-direction (e.g., the row direction, along a row of memory cells 105-c), and may be coupled to a row component 125 (not shown) for selecting or activating the row of memory cells 105-c (e.g., by biasing the word line conductor 440-b).

[0097] In some examples, word line conductors 440-b of one memory array 110-c may be coupled or connected with word line conductors 440-b of another memory array 110-c such that rows of memory cells 105-c may be activated commonly across multiple memory arrays 110-c, including memory arrays 110-c across multiple levels 420-b or memory arrays 110-c across multiple sets 510-a, or both (e.g., by sharing a common node or output of a row component 125, not shown). In examples that support common, shared, or otherwise concurrent activation across memory arrays 110-c across multiple levels 420-b, word line conductors 440-b-11 and 440-b-21 may be coupled to each other, or to a common or shared output of a row component 125, or word line conductors 440-b-31 and 440-b-41 may be coupled to each other, or to a common or shared output of a row component 125, and so forth. In examples supporting common, shared, or otherwise concurrent activation of the memory array 110-c across multiple sets 510-a, word line conductors 440-b-11 and 440-b-31 may be coupled to each other, or to a common or shared output of the row component 125, or word line conductors 440-b-21 and 440-b-41 may be coupled to each other, or to a common or shared output of the row component 125, etc. In examples supporting common, shared, or otherwise concurrent activation of the memory array 110-c across multiple levels 420-d and sets 510-a, word line conductors 440-b-11, 440-b-21, 440-b-31, and 440-b-41 may be coupled to each other, or to a common or shared output of the row component 125, etc.

[0098] In some examples, interconnections between word line conductors 440-b of different levels 420-b may be formed at least in part along a direction (e.g., z-direction) through one or more vias, slots, or TSVs, which may be positioned at or near a boundary of memory array 110-c (e.g., along the y-direction) and at other locations relative to memory array 110-c. In some examples, interconnections between word line conductors 440-b of different sets 510-a may be formed at least in part along an x-direction through one or more wiring levels or layers, which may be positioned at locations different from memory array 110-c along the z-direction, such as locations above, below, or between memory array 110-c, and at other locations.

[0099] Each capacitor 320-c for a memory cell 105-c may include a respective dielectric portion 450-b formed between a pillar 430-b associated with the memory cell 105-c and a plate conductor 460-b (e.g., an example of a plate line 140, a plate node, or a common plate). In some examples, a portion of the pillar 430-b of the capacitor 320-c may be the same material or combination of materials as a portion of the pillar 430-c of the corresponding cell selection component 330-c (e.g., a doped semiconductor material, a polycrystalline semiconductor). In some examples, a portion of the pillar 430-b of the capacitor 320-c may be or include a different material or combination of materials than a portion of the pillar 430-b of the corresponding cell selection component 330-c (e.g., a metal or conductor portion, a metal layer deposited over a surface of the pillar 430-b). In some examples, the dielectric portion 450-b may be formed with a ferroelectric material operable to maintain a non-zero charge (e.g., corresponding to a stored logic state) in the absence of an electric field.

[0100] In the example of the memory structure 500, each of the memory arrays 110-c may be associated with (e.g., coupled with, including, accessed using, a respective plate conductor 460-b). Each of the plate conductors 460-b may be coupled with a plate component 145 (not shown) for respectively biasing the plate conductors 460-b. In the example of the memory structure 500, each plate conductor 460-b may be associated with at least one column of the memory cells 105-c. In some examples, each of the plate conductors 460-b may also extend along the rows of memory cells 105-c or some portion thereof in the y-direction, in which case each of the plate conductors 460-b may be associated with all of the memory cells 105-c of the respective memory array 110-c or some subset of the columns of the respective memory array 110-c.

[0101] In the example of memory structure 500, at least some (if not every) columns of memory cells 105-c of at least some (if not every) memory array 110-c may be associated with respective transistors 380-c, which may also be formed as vertical transistors. At least some (if not every) transistors 380-c may be operable to couple respective digit line conductors 410-b with middle line conductors 465-b (e.g., an example of middle line 365). In the example of memory structure 500, to support m columns of each memory array 110-c, m middle line conductors 465-b may be formed along the y-direction, and each middle line conductor 465-b may be coupled or connected to transistors 380-c of each memory array 110-c associated with each of the levels 420-d and each of the sets 510-a (e.g., middle line conductor 465-b-1 is coupled to transistors 380-c-11, 380-c-21, 380-c-31, and 380-c-41). The set of m middle line conductors 465-b may be coupled to a column decoder 360-c, which in turn may be coupled to or otherwise operable to be coupled to a sensing component 150-c. In some examples, memory structure 500 may include additional vertical transistors (e.g., as described with reference to FIG. 1 ). Figure 4 Transistor 390 is depicted (not shown) which enables the shunt functionality of memory structure 500.

[0102] At least some, if not every, transistor 380-c may include a channel portion (e.g., a vertical channel) formed at least in part by one or more respective pillars 470-b and a gate portion formed at least in part by one or more respective level select conductors 475-b (e.g., instances of level select lines 375). In some examples, the gate portion of transistor 380-c may be a portion or region of level select line 375 operable to activate the channel portion of transistor 380-c (e.g., modulate the conductivity of the channel portion). Level select conductor 475-b may extend from a column of memory cells 105-c to another column, or from one transistor 380-c to another transistor, along a direction, such as the y-direction (e.g., along a row direction, along a row of memory cells 105), and may be coupled with a level decoder 370 (not shown) for selecting or activating memory array 110-c (e.g., by biasing level select conductor 475-b, by activating a row or other set of transistors 380-c).

[0103] The example of memory structure 500 illustrates a configuration in which each of transistors 380 may be located on the same level 420. For example, each of transistors 380-c-11, 380-c-21, 380-c-31, and 380-c-41 and corresponding repetitions for a certain number of columns along the y-direction may be located within or otherwise associated with level 420-b-1. In some examples, this configuration may support pillars 470-b and level select conductors 475-b for all transistors 380-c of memory structure 500 formed using a common process, or otherwise formed concurrently.

[0104] In some examples, the configuration of memory structure 500 may be supported by respective conductors 540 operable for coupling between middle line conductor 465-b and digit line conductor 410-b of level 420-b-1. For example, conductor 540-a-11 may be operable for coupling between middle line conductor 465-b-1 (e.g., via transistor 380-c-11) and digit line conductor 410-b-11 (e.g., via transistor 520-a-11 or other circuitry), conductor 540-a-31 may be operable for coupling between middle line conductor 465-b-1 (e.g., via transistor 380-c-31) and digit line conductor 410-b-31 (e.g., via transistor 520-a-31 or other circuitry), and so forth.

[0105] In some examples, conductor 540 can be formed as part of a metal layer process that can include various deposition operations or etching operations or both. In some examples, this process can also include forming a conductor portion 550 coupled to or otherwise associated with each of the digit line conductors 410-b of the second level 420-b-2. Each of the conductor portions 550 can be coupled (e.g., along the z-direction) to the respective digit line conductor 410-b by a respective conductor portion 555 (e.g., a vertical conductor), which can include one or more vias, slots, or TSVs between the digit line conductor 410-b and the respective conductor portion 550. In some instances, to ease dimensional tolerance or precision requirements for connections between levels 420-b (e.g., "pitch" tolerances associated with spacing or repetitions (e.g., column spacing) between digit line conductors 410-b or memory cells 105-c along the y-direction), conductor portions 555 may be implemented in different approaches (e.g., staggered approaches), where conductor portions 555 of columns adjacent to each other along the y-direction may be positioned at different locations along the x-direction according to various staggering techniques or repetitions. Among other benefits, the staggered approaches may improve interconnection accuracy or tolerances for interconnections between levels 420-b, or may support a relatively larger cross-sectional area (e.g., in the xy plane) of the top of conductor portion 555 (e.g., an end relatively farther from substrate 220-b) compared to the bottom of conductor portion 555, which may be associated with an etching process for etching holes for depositing conductive material for conductor portion 555 (e.g., where such an etching process may expand the upper cross-section in the xy plane as etching proceeds downward along the z-direction).

[0106] At least some, if not every, transistor 520-a may include a channel portion (e.g., a vertical channel) formed at least in part by one or more respective pillars 530 and a gate portion formed at least in part by one or more respective conductors 525. In some examples, the gate portion of transistor 520-a may be a portion or region of conductor 525 operable to activate (e.g., modulate the conductivity of) the channel portion of transistor 520-a. Conductor 525 may extend from a column of memory cells 105-c to another column, or from one transistor 520-a to another transistor, along a direction, such as the y-direction (e.g., along a row direction, along a row of memory cells 105).

[0107] In some examples, pillar 530 may be formed as pillar 470-b using a common process or common materials, in which case transistor 520-a may be formed as the same type of transistor as transistor 380-c (e.g., an n-type transistor or a p-type transistor). In some examples, pillar 530 and pillar 470-b may be formed using different processes or different materials, in which case transistor 520-a may be formed as a different type of transistor than transistor 380-c. Although the example of memory structure 500 illustrates an example in which transistor 380-c is coupled to middle line conductor 465-b (e.g., formed on middle line conductor 465-b) and transistor 520-a is coupled to digit line conductor 410-b (e.g., formed on digit line conductor 410-b), in some examples, the relative positions may be swapped such that transistor 380-c may be coupled to digit line conductor 410-b (e.g., formed on digit line conductor 410-b) and transistor 520-a may be coupled to middle line conductor 465-b (e.g., formed on middle line conductor 465-b).

[0108] In some examples, transistor 520-a may be activated according to various techniques to support operation of memory structure 500. In some examples, the transistor may be configured in an "always on" configuration, where conductor 525 may be activated whenever power or voltage is applied or provided to memory structure 500, or whenever memory structure 500 is operable to support an access operation (e.g., operating in an active mode). In some examples, transistor 520-a may be configured to activate during access of a first memory array, a second memory array, a third memory array, or a fourth memory array, or any combination thereof. In some examples, transistor 520-a may be activated when a corresponding memory array 110-c is selected for an access operation, in which case corresponding transistor 380-c and corresponding transistor 520 may be activated (e.g., during access of memory array 110-c-1, transistor 380-c-11 and 520-a-11 are activated, and corresponding repeating transistors along the y-direction). In some examples, this combination or concurrent activation may be performed using the layer decoder 370 and other circuitry. Although the example of the memory structure 500 includes a transistor 520-a, in some examples, the transistor 520-a may be replaced with a metal conductor (e.g., a via, a slot, a TSV) that electrically connects the digit line conductor 410-b with the corresponding conductor 540-a.

[0109] In some examples, the circuitry of the level decoder 370 (not shown), the column decoder 360-b, or the sensing component 150-c, or any combination thereof, may be substrate-based, such as including transistors formed at least in part by doped portions of the substrate 220-b (e.g., transistors configured in a CMOS arrangement according to the transistor structure 200). By including the transistor 380-c at a location above the substrate 220-b, the memory structure 500 may support improved flexibility in level selection layout, which may improve area utilization or semiconductor substrate material utilization, among other benefits. Furthermore, in some examples, such a configuration may support an auxiliary circuitry area 560 (e.g., within or otherwise associated with the level 420-b-2) to be allocated to other circuitry that supports operation of the memory structure 500. For example, the auxiliary circuitry area 560 may provide an area for forming power or voltage supply circuitry, such as capacitors that support power or voltage regulation or other signal conditioning for operation of the memory structure 500. In some examples, the auxiliary circuitry area 560 can provide a location for a capacitor (eg, a CTSA capacitor, an integrating capacitor) that can support the operation of the transistor 380 for access operation signal generation.

[0110] Memory structure 500 illustrates another example in which memory arrays 110-c or memory cells 105-c may be arranged as multiple tiles (e.g., tiles, sub-arrays) above substrate 220-b, which may refer to a set of memory cells 105-b associated with a set of word line conductors 440-a (e.g., a set of word line conductors 440-a along the x-direction), and a set of digit line conductors 410-a that may be coupled to the set of memory cells 105-b by activation of this set of word line conductors 440-a (e.g., along the y-direction). For example, memory array 110-c-1 may be associated with a first tile, memory array 110-c-2 may be associated with a second tile, memory array 110-c-3 may be associated with a third tile, and memory array 110-c-4 may be associated with a fourth tile. According to examples as disclosed herein, various configurations of level select conductors 475 or conductors 525 (or, where applicable, shunt select conductors 485) and other features may be implemented to trade off or otherwise support design and performance characteristics, such as power consumption, layout complexity, operational complexity, and other characteristics. For example, for a set of rows of memory cells 105 (e.g., a tile, associated with a set of word line conductors 440-a along the x-direction), columns of memory cells 105 along the y-direction may be arranged or subdivided into one or more independently addressable sets along the y-direction, which may reduce power consumption or latency in an associated memory device or memory die, among other benefits.

[0111] The examples of memory structures 400 and 500 illustrate various techniques for implementing level selection according to examples as disclosed herein, including techniques schematically illustrated in circuit 300. In some examples, memory device 100 or an associated memory die may implement multiple instances of one of memory structures 400 or 500. For example, either of memory structures 400 or 500 may be associated with a cross-sectional area (e.g., span or extent along the x-direction and the y-direction, span or extent in the xy plane) or a pitch (e.g., repeat distance along the x-direction, repeat distance along the y-direction), and one or more aspects of the respective memory structure may be repeated or extended along the x-direction or the y-direction or both to expand the storage capacity of memory device 100 or an associated memory die. In some examples, each such repetition may be independently operable or addressable, which may support various aspects of parallel or otherwise concurrent access operations in the repetitions of the respective memory structure. In some examples, memory device 100 or an associated memory die may implement an instance of either or both of memory structures 400 or 500, or may combine aspects of two or more other respective memory structures.

[0112] Figure 6 An example of a memory tile 600 supporting a layer selection layout in a memory device according to an example as disclosed herein is illustrated. The memory tile 600 may be formed on a substrate (eg, a substrate such as ... Figure 2 , 4 5 and 5) above the substrate 220) of the memory device 100 or the portion of the memory die. The memory block 600 may illustrate an implementation of the reference Figure 3 300. The memory slice 600 may be used with reference to Figure 4 and 5 4. The memory tile 600 of FIG. 4 is associated with (e.g., located at) the described level 420 (e.g., illustrating the relative locations of features for implementing aspects of the memory structure 400 or 500, at a level above the substrate 220), and may include or otherwise be associated with circuitry configured to couple the memory tile 600 with circuitry external to the memory tile 600. In some cases, the memory tile 600 may be coupled with circuitry located at one or more other levels 420. For illustrative purposes, aspects of the memory tile 600 may be described with reference to the x-direction, y-direction, and z-direction of a coordinate system 601. The z-direction may illustrate a direction perpendicular to the surface of the substrate 220, such that the illustration of the memory tile 600 may be interpreted as a top view. In some examples, for illustrative purposes, the x-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells 105), and the y-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells 105).

[0113] Memory tile 600 illustrates an example of a layout of digit lines 130 aligned along a first direction (e.g., digit lines 130-b-1 through 130-bm aligned along the x-direction) and word lines 120 aligned along a second direction (e.g., word lines 120-b-1 through 120-bn aligned along the y-direction). In some examples, word line 120-b may span memory tile 600 along the y-direction, and digit line 130-b may span memory tile 600 along the x-direction. In some examples, word line 120 may include one or more conductors (e.g., word line conductor 440) that may extend between consecutive columns of memory cells 105, or between consecutive cell select components 330. The memory tile 600 may also include a plurality of memory cells 105 (not shown) that may be positioned (e.g., physically, electrically, logically) between or otherwise addressed at respective intersections of each of the digit lines 130-b and each of the word lines 120-b. In some examples, the word lines 120-b may each be operable to activate a plurality of transistors (e.g., cell select components 330, not shown) of the memory tile 600 to couple respective storage elements of each memory cell 105 of respective rows of memory cells 105 (e.g., along the y-direction) with each digit line 130-b (e.g., each of the digit lines 130-b of the memory tile 600).

[0114] According to examples as disclosed herein, a memory tile 600 may be selected or enabled by a set of transistors 380 (e.g., a plane select transistor, a slice select transistor, a transistor of or otherwise associated with the memory tile 600, not shown), which may be configured to couple a corresponding digit line 130-b of the memory tile 600 with circuitry external to the memory tile 600 (e.g., a column decoder 360 or a sense component 150, among other circuitry, not shown). In some examples, at least some such transistors 380 may be activated (e.g., for slice selection, for access operation signal generation in a cascade arrangement) by an activation line 605-a-1, which may be an example of at least a portion of a plane select line 375 or a plane select conductor 475 as described herein. The example of activation line 605-a-1 may be implemented in a layout where a single activation line 605 activates an entire row of transistors 380 (e.g., one transistor 380 for each of digit lines 130-b-1 through 130-bm). In some examples, memory tile 600 may include a second activation line 605-a-2, which may be implemented in a layout where multiple activation lines 605 are used to activate transistors 380 of memory tile 600 (e.g., respective subsets of transistors 380 of memory tile 600) (e.g., where activation line 605-a-1 activates a respective transistor 380 of each of a first subset of digit lines 130-b-1 through 130-bm (e.g., each transistor 380 of a right half of digit lines 130-b), and activation line 605-a-2 activates a respective transistor 380 of each of a second subset of digit lines 130-b-1 through 130-bm (e.g., the left half of digit lines 130-b)). In various examples, the activation line 605 can include or refer to one or more conductors (eg, the layer select conductors 475 ) that can extend between consecutive layer select transistors 380 (eg, along the y-direction).

[0115] In some examples, digit line 130-b may be coupled to circuitry external to memory tile 600 according to coupling region 615, which may be an example of a cross-sectional area (e.g., in an xy plane) in which center line conductor 465 may be positioned (e.g., a slot region, a via region). Thus, coupling region 615 may illustrate a region that supports coupling between digit line 130-b and circuitry external to memory tile 600. In various examples, coupling region 615 may be included in memory tile 600, or may be positioned between memory tile 600 and an adjacent memory tile (not shown), or may be shared with one or more other memory tiles (e.g., when multiple memory tiles share a common coupling region (e.g., a common slot or via region) or are otherwise associated with a common coupling region).

[0116] In some examples, the memory tile 600 may include a first coupling region 615-a-1 and a second coupling region 615-a-2, which may be positioned at an end of the memory tile 600 opposite the coupling region 615-a-1 (e.g., along the x-direction). In some examples, the first coupling region 615-a-1 may support coupling a first subset of the digit lines 130-b of the memory tile 600 with circuitry external to the memory tile 600, and the coupling region 615-a-2 may support coupling a second subset of the digit lines 130-b of the memory tile 600 with circuitry external to the memory tile 600. In some examples, digit lines 130-b associated with activation line 605-a-1 (e.g., digit lines 130-b on the right side of memory tile 600) can be coupled to external circuitry via coupling region 615-a-1, and digit lines 130-b associated with activation line 605-a-2 (e.g., digit lines 130-b on the left side of memory tile 600) can be coupled to external circuitry via coupling region 615-a-2. In some examples, digit lines 130-b can be cut (e.g., electrically isolated) at their ends opposite to coupling with external circuitry, which can provide isolation from adjacent structures (e.g., digit lines 130 of adjacent memory tiles) or can provide space for other structures (e.g., vias or slot features between memory tiles), or both, as well as other configurations.

[0117] The memory slice 600 may include or otherwise be associated with a plate node, which may be an example of a plate line 140, a plate conductor 460, or another type of plate node or conductor. In some examples, the plate node may be a common plate for the memory slice 600, and may be coupled to each of the memory cells 105 associated with all of the digit lines 130-b-1 through 130-bm. Using a common plate node for all of the memory cells 105 of the memory slice may support relatively simple decoding or biasing, or relatively fewer components for operating the memory slice, among other benefits.

[0118] In some examples, the memory tile 600 may include at least a first plate node and a second plate node that may be independently biased or addressed. For example, in some cases, the first plate node may be coupled to memory cells 105 associated with a first set of digit lines 130-b, and the second plate node may be coupled to memory cells 105 associated with a second set of digit lines 130-b. In some examples, the first set of digit lines 130-b may be digit lines coupled to external circuitry via coupling region 615-a-1 (e.g., digit lines 130-b on the right side of the memory tile 600), and the second set of digit lines 130-b may be digit lines coupled to external circuitry via coupling region 615-a-2 (e.g., digit lines 130-b on the left side of the memory tile 600). Using two independently controlled plate nodes may be associated with relatively high performance (e.g., relatively low latency, relatively low cell disturbance) or relatively high efficiency, as well as other benefits, compared to using a single plate node.

[0119] In some examples, the memory tile 600 may also include an activation line 610-a, which may be an example of at least a portion of a level shunt line 385 or a shunt select conductor 485 as described herein. The activation line 610-a may be an example of an activation line aligned along the y-direction and operable to activate a row of transistors 390 (e.g., shunt transistors, not shown), each of which is operable to couple a respective digit line 130-b of the digit lines 130-b-1 through 130-bm with a plate node of or otherwise associated with the memory tile 600. In some examples, the activation line 610-a may include one or more conductors (e.g., shunt select conductors 485) that may extend between consecutive shunt transistors 390 (e.g., along the y-direction).

[0120] According to examples as disclosed herein, the layout of the activation lines (e.g., activation lines 605-a, activation lines 610) represented by the memory tile 600 can be implemented to trade off or otherwise support design and performance characteristics, such as power consumption, layout complexity, operational complexity, and other characteristics. In some examples, the activation line 605-a-1 can be the only activation line configured for level selection or tile selection in the memory tile 600, which can support relatively low manufacturing or operational complexity. In some examples, the memory tile 600 can include the activation line 605-a-1 near a first end of the memory tile 600 along the x-axis (e.g., near a more positive position along the x-axis), and in some examples, the activation line 605-a-2 near a second end of the memory tile 600 along the x-axis (e.g., opposite the first end, near a less positive position along the x-axis). In some instances, such techniques may support a more compact layout of the memory tile 600 or supporting circuitry (e.g., a row decoder, a column decoder) by supporting coupling regions 615 for implementing digital lines 130-b of the memory tile 600 at opposite ends of the memory tile 600 along a given direction.

[0121] In some examples, placing the activation line 610-a along the x-direction may affect the operating characteristics of the memory tile 600, which may be used for various design tradeoffs. For example, the activation line 610-a may be positioned relatively close to an edge of the memory tile 600 (e.g., between the end word lines 120-b and the edge of the memory tile 600, along the x-direction) such that the word lines 120-b are all located on the side of the activation line 610-a (e.g., along the x-direction). This arrangement may be associated with some memory cells 105 along the digit lines 130-b being relatively far from the activation line 610-a (e.g., at opposite ends of the memory tile 600 along the x-direction), which may be associated with relatively slower or less efficient shunting or equalization of such memory cells 105, or may be associated with asymmetry because the shunting may be relatively close to the coupling region 615 of some digit lines 130-b and relatively far from the coupling region 615 of some other digit lines 130-b. However, such a position of the activation line 610 may support advantageous layout or decoding characteristics. In some other examples, the activation line 610-a may be positioned closer to the middle of the memory tile 600 (e.g., along the x-direction) such that the activation line 610-a is positioned between a subset of the word lines 120-b along the x-direction. Positioning the activation line 610-a in the middle portion of the memory tile 600 along the x-direction (e.g., between a subset of the word lines 120-b) may reduce shunt delays or improve shunting for equalization effects, for example, by reducing or limiting the distance between the shunt transistors 390 and the memory cells 105 at opposite ends of the memory tile 600 along the x-direction.

[0122] Figure 7An example of a memory tile 700 supporting a layer selection layout in a memory device according to an example as disclosed herein is illustrated. The memory tile 700 may be formed in reference Figure 2 , 4 5 and 5. The memory chip block 700 may illustrate an implementation of the reference Figure 3 300. The memory slice 700 may be used with reference to Figure 4 and 5 4. The memory tile 700 of FIG. 4 is associated with the described level 420 (e.g., illustrating the relative locations of features for implementing aspects of the memory structure 400 or 500, at a level above the substrate 220), and may include or otherwise be associated with circuitry configured to couple the memory tile 700 with circuitry external to the memory tile 700. In some cases, the memory tile 700 may be coupled with circuitry located at one or more other levels 420. For illustrative purposes, aspects of the memory tile 700 may be described with reference to the x-direction, y-direction, and z-direction of the coordinate system 701. The z-direction may illustrate a direction perpendicular to the surface of the substrate 220, such that the illustration of the memory tile 700 may be interpreted as a top view. In some examples, for illustrative purposes, the x-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells 105), and the y-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells 105). Memory tile 700 illustrates an example of a layout of digit lines 130 aligned along a first direction (e.g., digit lines 130-c-1 through 130-cm aligned along an x-direction) and word lines 120 aligned along a second direction (e.g., word lines 120-c-1 through 120-cn aligned along a y-direction), which may be examples of digit lines 130 and word lines 120 as described herein.

[0123] According to examples as disclosed herein, a memory tile 700 may be selected or enabled by a set of transistors 380 (not shown) that may be configured to couple respective digit lines 130-c of the memory tile 700 with circuitry external to the memory tile 700. In the example of the memory tile 700, at least some such transistors 380 may be activated by an activation line 605-b-1 or an activation line 605-b-2, which may be an example of at least a portion of a level select line 375 or a level select conductor 475 as described herein. The example of two activation lines 605-b-1 and 605-b-2 may be implemented in a layout in which each of the activation lines 605-b activates a separate row of transistors 380 (e.g., a first row of transistors 380 at one end of the memory tile 700 in the x-direction and a second row of transistors 380 at the opposite end of the memory tile 700 in the x-direction). For example, activation line 605-b-1 may activate a corresponding transistor 380 for each of a first subset of digital lines 130-c-1 to 130-cm, such as the right half of digital lines 130-c (e.g., for coupling via coupling region 615-b-1), and activation line 605-b-2 may activate a corresponding transistor 380 for each of a second subset of digital lines 130-c-1 to 130-cm, such as the left half of digital lines 130-c (e.g., for coupling via coupling region 615-b-2).

[0124] In some examples, memory tile 700 may include activation lines 605-b-3 and 605-b-4, which may be examples of activation lines 605-b of one level configured to couple digit lines 130 of another level 420 (e.g., another level of memory tiles, above or below memory tile 700 relative to substrate 220, not shown) with circuitry on another level 420. This layout of memory tile 700 may be an example of a memory tile at level 420-b-1 as described with reference to memory structure 500. For example, for digital line 130-c associated with coupling region 615-b-1, activation line 605-b-1 may be an instance of a level selection conductor 475-b associated with transistor 380-c-11 (e.g., and other transistors 380 along the y direction) and activation line 605-b-3 may be an instance of a conductor 457-b associated with transistor 380-c-21 (e.g., and other transistors 380 along the y direction), which may be associated with digital line 130 of a memory block on another level 420. Aspects of the memory structure 500 may be reflected for the digital line 130-c associated with the coupling region 615-b-2 such that the activation line 605-b-2 may be an instance of the level selection conductor 475-b associated with the transistor 380-c-11 and the activation line 605-b-4 may be an instance of the conductor 457-b associated with the transistor 380-c-21, which may be associated with the digital line 130 of the memory block on another level 420.

[0125] The memory tile 700 may include or otherwise be associated with a plate node, which may be an example of a plate line 140, a plate conductor 460, or another type of plate node or conductor. In some examples, the plate node may be a common plate for the memory tile 700 and may be coupled to each of the memory cells 105 associated with all of the digit lines 130-c-1 through 130-cm. In some examples, the memory tile 700 may include at least a first plate node and a second plate node that may be independently biased or addressed. For example, the first plate node may be coupled to the memory cells 105 associated with a first set of digit lines 130-c (e.g., digit lines 130-c associated with coupling region 615-b-1) and the second plate node may be coupled to the memory cells 105 associated with a second set of digit lines 130-c (e.g., digit lines 130-c associated with coupling region 615-b-2).

[0126] The memory tile 700 may also include activation lines 610-b-1 and 610-b-2, which may be examples of at least a portion of a level shunt line 385 or a shunt select conductor 485 as described herein. The activation line 610-b may be an example of an activation line aligned in the y-direction and operable to activate a respective row of transistors 390 (e.g., shunt transistors, not shown) operable to couple a respective digit line 130-c of the digit lines 130-c-1 through 130-cm with a plate node of or otherwise associated with the memory tile 700 (e.g., a plate node common to the digit lines 130-c of the memory tile 700 or the memory cells 105). Each of the activation lines 610-b may include one or more conductors (e.g., shunt select conductors 485) that may extend between consecutive shunt transistors 390 (e.g., in the y-direction). Such activation lines 610-b may be associated with respective rows of transistors 390 or some portion thereof that span the entire memory tile 700 along the y-direction (e.g., respectively associated with transistors 390 of each of the digit lines 130-c-1 to 130-cm) (e.g., activation lines 610-b-1 associated with transistors 390 of each of the digit lines 130-c coupled via coupling regions 615-b-1, activation lines 610-b-2 associated with transistors 390 of each of the digit lines 130-c coupled via coupling regions 615-b-2). In some other examples of the memory tile 700, a single activation line 610 may be implemented that may be positioned relatively close to an edge of the memory tile 700 (e.g., along the x-direction), or positioned between a subset of the word lines 120-c (e.g., at an intermediate position along the x-direction).

[0127] In some examples, the memory tile 700 can include one or more activation lines 715-a, which can be examples of at least a portion of a conductor 525 as described herein. The activation lines 715-a can be examples of activation lines aligned along the y-direction and operable to activate a corresponding row of transistors 520 (e.g., transistors configured in an "always on" configuration, or when the memory tile 700 is operating in an active mode, not shown), the transistors 520 being operable to couple a corresponding digit line 130-c of the digit lines 130-c-1 through 130-cm with a corresponding conductor 540, as described with reference to FIG. Figure 56. Description. Each of the activation lines 715-a may include one or more conductors that may extend between consecutive transistors 520 (e.g., along the y-direction). Such activation lines 715-a may be associated with respective rows of transistors 520 that span a portion of the memory tile 700 (e.g., activation line 715-a-1 associated with transistors 520 for each of the digit lines 130-c coupled via coupling region 615-b-1, activation line 715-a-2 associated with transistors 520 for each of the digit lines 130-c coupled via coupling region 615-b-2). In some examples, activation line 715-a may be omitted, such as when the connection between the digit lines 130-c and the respective conductors 540 is implemented via metal conductors rather than transistors 520.

[0128] According to examples as disclosed herein, the layout of the activation lines (e.g., activation lines 605-a, 610-b, 715-a) represented by the memory tile 700 can be implemented to trade off or otherwise support design and performance characteristics, such as power consumption, layout complexity, operational complexity, and other characteristics. For example, including two activation lines 610-b-1 and 610-b-2 can improve shunt symmetry (e.g., manufacturing symmetry, operational symmetry) compared to techniques in which the memory tile includes a single activation line 610 positioned near the edge of the memory tile 700. However, such techniques can involve relatively higher power consumption than when a single activation line 610 is implemented. In addition, by including activation line 715-a, memory tile 700 may include transistor 380 that is operable to couple more than one memory tile with circuit systems external to the respective memory tiles, which may support utilization of common manufacturing operations on a single level, or may support an area of ​​auxiliary circuit systems on another level (e.g., in auxiliary circuit system area 560), among other benefits.

[0129] Figure 8 An example of a memory tile 800 supporting a layer selection layout in a memory device according to an example as disclosed herein is illustrated. The memory tile 800 may be formed in reference Figure 2 , 4 5 and 5. The memory chip block 800 may illustrate an implementation of the reference Figure 3 300. The memory slice 800 may be used with reference to Figure 4 and 54. The memory tile 800 of FIG. 4 is associated with (e.g., located at) the described level 420 (e.g., illustrating the relative locations of features for implementing aspects of the memory structure 400 or 500, at a level above the substrate 220), and may include or otherwise be associated with circuitry configured to couple the memory tile 800 with circuitry external to the memory tile 800. In some cases, the memory tile 800 may be coupled with circuitry located at one or more other levels 420. For illustrative purposes, aspects of the memory tile 800 may be described with reference to the x-direction, y-direction, and z-direction of a coordinate system 801. The z-direction may illustrate a direction perpendicular to the surface of the substrate 220, such that the illustration of the memory tile 800 may be interpreted as a top view. In some examples, for illustrative purposes, the x-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells 105), and the y-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells 105).

[0130] The memory tile 800 illustrates an example of a layout of digit lines 130 aligned along a first direction (e.g., digit lines 130-d-1 to 130-dm aligned along the x-direction) and word lines 120 aligned along a second direction (e.g., word lines 120-d-1 to 120-dn aligned along the y-direction), which may be examples of digit lines 130 and word lines 120 as described herein. The memory tile 800 may also include activation lines 605-c-1, 605-c-2, 605-c-3, 605-c-4, 610-c-1, 610-c-2, 715-b-1, and 715-b-2, which may be examples of digit lines 130 and word lines 120 as described herein. Figure 7 700. However, in some examples, any one or more of such activation lines may be omitted from other memory slice layouts that support the described techniques. Furthermore, while some aspects of memory slice 800 are described with respect to aspects of memory slice 700, such techniques may be implemented according to any example as disclosed herein, including techniques with respect to memory slice 600, etc.

[0131] The example of memory tile 800 illustrates an example in which a cut region 805 may be implemented to shorten one or more of the activation lines as described herein (e.g., relative to the corresponding activation lines as described with reference to memory tile 600 or 700). For example, memory tile 800 may include a cut region 805-a-1, which may be implemented to shorten the operable portions of activation lines 605-c-1 and 610-c-1, and where applicable, activation lines 605-c-3 and 715-b-1 (e.g., portions toward the right side of the illustrated layout). Memory tile 800 may also include a cut region 805-a-2, which may be implemented to shorten the operable portions of activation lines 605-c-2 and 610-c-2, and where applicable, activation lines 605-c-4 and 715-b-2 (e.g., portions toward the left side of the illustrated layout).

[0132] In some implementations, after forming each of the respective activation lines (e.g., after forming activation lines 605, 610, and 715 along the y-direction by one or more deposition or removal operations), cut region 805 can be implemented as an etching operation, a slotting operation, or some other removal operation that can leave electrically isolated (e.g., floating, inactive) portions of the material associated with the formation of the respective activation lines. For example, after implementing cut region 805-a-1, the portion of the activation line to the left of cut region 805-a-1 can be electrically isolated or floating, and after implementing cut region 805-a-2, the portion of the activation line to the right of cut region 805-a-2 can be electrically isolated or floating. In other examples, activation line 605, activation line 610, or activation line 715, or any combination thereof, may be formed without such isolated or floating portions (e.g., with or without cut region 805), and may otherwise be formed to have respective electrical terminals along the y-direction that are not proximate to opposite edges of the memory tile 800 along the y-direction (e.g., having electrical terminals along the y-direction between a pair of digital lines 130-d, such as terminals between the boundary between digital lines 130-d associated with coupling region 615-c-1 and coupling region 615-c-2).

[0133] In the example of memory tile 800, the respective activation lines can be long enough in the y-direction to support respective operations of the digit line 130-d coupled via the respective coupling region 615. For example, activation lines 605-c-1 and 610-c-1 and, where applicable, activation lines 605-c-3 and 715-b-1 can span a distance in the y-direction long enough to perform respective operations for a digit line 130-c coupled with external circuitry via coupling region 615-c-1, and activation lines 605-c-2 and 610-c-2 and, where applicable, activation lines 605-c-4 and 715-b-2 can span a distance in the y-direction long enough to perform respective operations for a digit line 130-c coupled with external circuitry via coupling region 615-c-1. In various instances, such operations may be supported by a plate node common to all memory cells 105 of the memory slice 800, or by multiple plate nodes (e.g., a first plate node associated with a memory cell 105 coupled via coupling region 615-c-1 and a second plate node associated with a memory cell 105 coupled via coupling region 615-c-2).

[0134] In some examples, memory tile 800 can provide improved performance by isolating or otherwise removing unnecessary or inoperable lengths of activation lines 605, 610, or 715. For example, a shorter length along the y-direction can be associated with reduced intrinsic capacitance or reduced charge leakage potential, either or both of which can be associated with reduced power consumption or reduced latency, among other advantages. In some examples, such improvements can outweigh the manufacturing, design, or operational complexity that can be associated with cutting regions 805 or other techniques for shortening activation lines 605, 610, or 715.

[0135] Fig. 9 An example of a memory tile 900 supporting a layer selection layout in a memory device according to an example as disclosed herein is illustrated. The memory tile 900 may be formed in reference Figure 2 , 4 5 and 5. The memory chip block 900 may illustrate an implementation of the reference Figure 3 300. The memory slice 900 may be used with reference to Figure 4 and 520. The memory tile 900 of FIG. 4 is described in connection with (e.g., located at) a level 420 (e.g., illustrating relative locations of features for implementing aspects of the memory structure 400 or 500, at a level above the substrate 220), and may include or otherwise be associated with circuitry configured to couple the memory tile 900 with circuitry external to the memory tile 900. In some cases, the memory tile 900 may be coupled with circuitry located at one or more other levels 420. For illustrative purposes, aspects of the memory tile 900 may be described with reference to the x-direction, y-direction, and z-direction of a coordinate system 901. The z-direction may illustrate a direction perpendicular to a surface of the substrate 220, such that the illustration of the memory tile 900 may be interpreted as a top view. In some examples, for illustrative purposes, the x-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells 105), and the y-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells 105).

[0136] Memory slice 900 illustrates an example of a layout of digit lines 130 aligned along a first direction (e.g., digit lines 130-e-1 to 130-em aligned along an x-direction) and word lines 120 aligned along a second direction (e.g., word lines 120-e-1 to 120-en aligned along a y-direction), which can be examples of digit lines 130 and word lines 120 as described herein. Memory slice 800 also includes a subdivision (e.g., physically, spatially, logically) into independently controllable portions (e.g., relative to reference numerals as described herein). Figure 8 800) of the memory slice 800 described above. Although some aspects of memory slice 900 are described with respect to aspects of memory slice 800, such techniques may be implemented according to any example as disclosed herein, including memory slices 600 and 700, among others.

[0137] Memory tile 900 illustrates an example in which activation lines associated with respective coupling regions 615 may be subdivided to increase addressing flexibility and performance. For example, for coupling region 615-d-1, memory tile 900 illustrates implementations of activation lines 605-d-11 and 605-d-12 for level or tile activation (e.g., for selection or signal generation of memory tile 900) and activation lines 610-d-11 and d10-d-12 for shunting (e.g., for memory cells 105 of memory tile 900). Where applicable, for coupling region 615-d-1, memory tile 900 illustrates exemplary implementations of activation lines 605-d-31 and 605-d-32 for level or tile activation (e.g., for another memory tile different from memory tile 900, which may be located above or below memory tile 900 relative to the substrate). In addition, where applicable, for coupling region 615-d-1, memory tile 900 illustrates exemplary implementations of activation lines 715-c-11 and 715-c-12 for coupling digit line 130-e with respective conductors 540 (e.g., in an "always on" configuration). Memory tile 900 illustrates that similar techniques may be implemented for other coupling regions (e.g., coupling region 615-d-2). Although respective activation lines are illustrated as spanning approximately half of memory tile 900 in the y-direction (e.g., for implementations in which respective access lines are formed across half of memory tile 900), in other examples, such activation lines may initially be cut or slotted (e.g., according to the embodiments described in reference to FIG. 1 ). Figure 8 The one or more cut regions 805 described previously span the entire dimension of the memory tile 900. Furthermore, while the memory tile 900 illustrates an example where half of the memory tile 900 (e.g., associated with the respective coupling regions 615) is subdivided into two groups and two plate nodes, the activation lines may be subdivided into any number of two or more groups according to the described techniques.

[0138] In various examples, the layout of the memory tile 900 may be accompanied by a plate node that is common to all memory cells 105 of the memory tile 900, or by multiple plate nodes. As illustrated, the memory tile 900 may include four plate regions 905 (e.g., plate regions 905-a-1 through 905-a-4), which may illustrate respective cross-sectional areas (e.g., in the xy plane) or memory cells 105 associated with a given plate node. The example of plate regions 905 illustrates that the described techniques may be supported by employing multiple plate nodes for a given coupling region 615, or employing respective plate nodes for each set of subdivided activation lines (e.g., subdivided activation lines 605, 610, or 715, where applicable). In other examples of the described techniques for activation line subdivision, each of the coupling regions 615 may be associated with a common plate node (e.g., according to two plate regions 905, not shown), as well as other examples.

[0139] In some examples, memory tile 900 can provide further improved performance by isolating or otherwise removing unnecessary or inoperable lengths of the activation lines 605, 610, or 715, and also by further subdividing the operable lengths of the activation lines 605, 610, or 715 into independently addressable segments (e.g., and in some examples, corresponding independently addressable plate nodes). The combination of such techniques can be associated with further reductions in intrinsic capacitance or further reductions in charge leakage potential, either or both of which can be associated with further reductions in power consumption or reduced latency, among other advantages (e.g., relative to the techniques described with reference to memory tile 800). In some examples, such further improvements can outweigh the manufacturing, design, or operational complexity that can be associated with such subdivision of the activation lines 605, 610, or 715.

[0140] Fig.10 A flowchart illustrating a method 1000 for supporting layer selection layout in a memory device according to an example as disclosed herein is shown. The operations of the method 1000 may be implemented by a memory device or components thereof as described herein. For example, the method 1000 may be implemented by a memory device or components thereof as described herein. Figures 1 to 9 The described memory device 100 or associated components or circuitry performs the operations of method 1000. In some examples, the memory device may execute instruction sets to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0141] At 1005, the method may include performing an access operation on a row of memory cells at a level above a substrate of a memory die. The operation of 1005 may be performed according to examples as disclosed herein. In some examples, the operation may be performed as described in reference to Figure 1 Aspects of the operations of memory controller 170 performing 1005 are described.

[0142] In some examples, performing an access operation may include biasing a word line to activate a plurality of first transistors of a level above the substrate for coupling a corresponding storage element of each memory cell of a row of memory cells with each digit line of a plurality of digit lines. In some examples, the access operation may be performed by, for example, referring to Figure 1 and 3 The described row component 125 performs aspects of such operations.

[0143] In some examples, performing the access operation may include biasing the first activation line to activate a plurality of second transistors of the level above the substrate for coupling a corresponding digit line of the first set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate. In some examples, the access operation may be performed by, for example, referring to Figure 3 The described layer decoder 370 performs aspects of such operations.

[0144] In some examples, performing the access operation may include biasing the second activation line to activate a plurality of third transistors of the level above the substrate for coupling corresponding digit lines of the second set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate. In some examples, the access operation may be performed by, as in reference to Figure 3 The described layer decoder 370 performs aspects of such operations.

[0145] In some examples, an apparatus as described herein may perform one or several methods, such as method 1000. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing access operations on rows of memory cells of a level above a substrate of a memory die, or any combination thereof. In some examples, the access operation may include biasing a word line to activate a plurality of first transistors of the level above the substrate for coupling a corresponding storage element of each memory cell of the row of memory cells with each digit line of a plurality of digit lines. In some examples, the access operation may include biasing a first activation line to activate a plurality of second transistors of the level above the substrate for coupling a corresponding digit line of a first set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate. In some examples, the access operation may include biasing a second activation line to activate a plurality of third transistors of the level above the substrate for coupling a corresponding digit line of a second set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate.

[0146] Fig.11A flow chart illustrating a method 1100 for supporting layer selection layout in a memory device according to examples as disclosed herein is shown. The operations of the method 1100 may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, the one or more controllers may execute instruction sets to control functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may use dedicated hardware to perform aspects of the described functions.

[0147] At 1105, the method may include forming a tile of a memory array associated with a level above a substrate. The operations of 1105 may be performed according to examples and techniques as disclosed herein, including reference to Figures 1 to 10 One or more aspects of the description.

[0148] In some examples, forming a tile may include forming a plurality of memory cells.

[0149] In some examples, forming a tile can include forming a plurality of digit lines that are each aligned along a first direction.

[0150] In some examples, forming the tile can include forming a plurality of word lines that are each aligned along the second direction and that are each operable to activate a plurality of first transistors of the tile to couple a respective storage element of each memory cell of a respective row of memory cells with each digit line of the plurality of digit lines.

[0151] In some examples, forming the tile may include forming an activation line of a plurality of second transistors aligned along the second direction and operable to activate the tile, each of the plurality of second transistors operable to couple a corresponding digit line in a set of digit lines in a plurality of digit lines with circuitry external to a level above the substrate.

[0152] In some examples, an apparatus as described herein may perform one or several methods, such as method 1100. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for forming a tile of a memory array associated with a level above a substrate, or any combination thereof. In some examples, forming the tile may include forming a plurality of memory cells. In some examples, forming the tile may include forming a plurality of digit lines each aligned along a first direction. In some examples, forming the tile may include forming a plurality of word lines each aligned along a second direction and each operable to activate a plurality of first transistors of the tile to couple a respective storage element of each memory cell of a respective row of memory cells with each digit line of a plurality of digit lines. In some examples, forming the tile may include forming an activation line aligned along the second direction and operable to activate a plurality of second transistors of the tile, each of the plurality of second transistors operable to couple a respective digit line of a set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate.

[0153] It should be noted that the methods described herein are possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more methods may be combined.

[0154] An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

[0155] Aspect 1: An apparatus comprising: a tile of a memory array associated with a level above a substrate, the tile comprising: a plurality of memory cells; a plurality of digit lines, each aligned in a first direction; a plurality of word lines, each aligned in a second direction and each operable to activate a plurality of first transistors of the tile to couple a respective storage element of each memory cell of a respective row of memory cells with each digit line of the plurality of digit lines; and an activation line aligned in the second direction and operable to activate a plurality of second transistors of the tile, each of the plurality of second transistors being operable to couple a respective digit line of a set of digit lines in the plurality of digit lines with a circuit system external to the level above the substrate.

[0156] Aspect 2: An apparatus according to aspect 1, wherein the tile further includes: a second activation line aligned along the second direction and operable to activate a plurality of third transistors, each of the plurality of third transistors being operable to couple a corresponding digit line in a second set of digit lines in the plurality of digit lines with the circuit system.

[0157] Aspect 3: The apparatus of aspect 2, wherein the activation line has a terminal end along the second direction positioned between a first pair of digit lines of the plurality of digit lines and the second activation line has a terminal end along the second direction positioned between a second pair of digit lines of the plurality of digit lines.

[0158] Aspect 4: An apparatus according to any one of Aspects 2 to 3, wherein the tile further comprises: a first plate node coupled to the storage element of the memory cell associated with the set of digital lines; and a second plate node coupled to the storage element of the memory cell associated with the second set of digital lines, wherein the second plate node is operable to be biased independently of the first plate node.

[0159] Aspect 5: An apparatus according to Aspect 4, wherein the tile further includes: a third activation line, which is aligned along the second direction and is operable to activate a plurality of fourth transistors, each of the plurality of fourth transistors being operable to couple a corresponding digit line in the set of digit lines with the first plate node; and a fourth activation line, which is aligned along the second direction and is operable to activate a plurality of fifth transistors, each of the plurality of fifth transistors being operable to couple a corresponding digit line in the second set of digit lines with the second plate node.

[0160] Aspect 6: An apparatus according to any one of Aspects 2 to 5, wherein the digital lines of the set of digital lines are configured for the corresponding coupling with the circuit system via a first end of the block along the first direction and the digital lines of the second set of digital lines are configured for the corresponding coupling with the circuit system via a second end of the block along the first direction opposite to the first end.

[0161] Aspect 7: An apparatus according to Aspect 6, wherein the block further includes: a fifth activation line, which is aligned along the second direction and is operable to activate a plurality of sixth transistors, each of the plurality of sixth transistors being operable to couple a corresponding digit line in a third set of digit lines in the plurality of digit lines to the circuit system via the first end of the block along the first direction; a sixth activation line, which is aligned along the second direction and is operable to activate a plurality of seventh transistors, each of the plurality of seventh transistors being operable to couple a corresponding digit line in a fourth set of digit lines in the plurality of digit lines to the circuit system via the second end of the block along the first direction.

[0162] Aspect 8: An apparatus according to aspect 7, wherein the tile further includes: a first plate node, which is coupled to the storage elements of the memory cells associated with the set of digit lines; and a second plate node, which is coupled to the storage elements of the memory cells associated with the second set of digit lines; and a third plate node, which is coupled to the storage elements of the memory cells associated with the third set of digit lines; and a fourth plate node, which is coupled to the storage elements of the memory cells associated with the fourth set of digit lines, wherein each of the first plate node, the second plate node, the third plate node and the fourth plate node is operable to be biased independently of the other of the first plate node, the second plate node, the third plate node and the fourth plate node.

[0163] Aspect 9: The apparatus of any of aspects 1 to 8, wherein each of the plurality of word lines has a respective height dimension relative to the substrate that overlaps a height dimension of the activation line.

[0164] Aspect 10: The apparatus of any of aspects 1-9, wherein the tile further comprises: a common plate node coupled to the storage element of each memory cell of the plurality of memory cells.

[0165] Aspect 11: An apparatus according to aspect 10, wherein the tile further includes: a seventh activation line aligned along the second direction and operable to activate a plurality of eighth transistors, each of the plurality of eighth transistors being operable to couple a corresponding digit line of the plurality of digit lines to the common plate node.

[0166] Aspect 12: The apparatus of aspect 11, wherein the seventh activation line is positioned between a pair of word lines of the plurality of word lines along the first direction.

[0167] Aspect 13: The apparatus of any of aspects 1 to 12, wherein the circuitry external to the level above the substrate includes one or more column decoders or one or more arrays of sense amplifiers, or a combination thereof.

[0168] Aspect 14: The apparatus of any of aspects 1 to 13, wherein the circuitry external to the level above the substrate includes a plurality of transistors formed at least in part from a doped portion of the substrate.

[0169] An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

[0170] Aspect 15: An apparatus comprising: a first tile of a memory array associated with a first level above a substrate, the first tile comprising: a plurality of first memory cells; a plurality of first digit lines, each aligned in a first direction; and a plurality of first word lines, each aligned in a second direction and each operable to activate a plurality of first transistors of the first tile to couple a corresponding storage element of each first memory cell of a corresponding row of first memory cells to each first digit line of the plurality of first digit lines; a second tile of the memory array associated with a second level above the substrate, the second tile comprising: a plurality of second memory cells; a plurality of second digit lines, each aligned in the first direction; and a plurality of second word lines, each aligned in the second direction and each operable to activate a plurality of second transistors of the second tile to couple a corresponding storage element of each first memory cell of a corresponding row of first memory cells to each first digit line of the plurality of first digit lines A corresponding storage element of each second memory cell of a corresponding row of storage cells is coupled to each second digit line of the plurality of second digit lines; a first activation line of the first level, which is aligned along the second direction and is operable to activate a plurality of third transistors of the first level, each of the plurality of third transistors being operable to couple a corresponding first digit line in a set of first digit lines in the plurality of first digit lines to a circuit system outside the first level above the substrate; and a second activation line of the first level, which is aligned along the second direction and is operable to activate a plurality of fourth transistors of the first level, each of the plurality of fourth transistors being operable to couple a corresponding second digit line in a set of second digit lines in the plurality of second digit lines to the circuit system outside the first level above the substrate.

[0171] Aspect 16: The apparatus according to Aspect 15, further comprising: a third activation line of the first level, which is aligned along the second direction and is operable to activate a plurality of fifth transistors of the first level, each of the plurality of fifth transistors being operable to couple a corresponding first digital line of a second set of first digital lines of the plurality of first digital lines with the circuit system outside the first level above the substrate; and a fourth activation line of the first level, which is aligned along the second direction and is operable to activate a plurality of sixth transistors of the first level, each of the plurality of sixth transistors being operable to couple a corresponding second digital line of a second set of second digital lines of the plurality of second digital lines with the circuit system outside the first level above the substrate.

[0172] Aspect 17: The apparatus according to aspect 16, wherein: the first activation line, the second activation line, the third activation line and the fourth activation line each have a respective terminal along the second direction positioned between a pair of respective first digit lines in the plurality of first digit lines.

[0173] Aspect 18: An apparatus according to any one of Aspects 16 to 17, wherein: the first slice includes a first plate node coupled to the storage elements of the memory cells associated with the set of first digital lines and a second plate node coupled to the storage elements of the memory cells associated with the second set of first digital lines; the second slice includes a third plate node coupled to the storage elements of the memory cells associated with the set of second digital lines and a fourth plate node coupled to the storage elements of the memory cells associated with the second set of second digital lines, wherein each of the first plate node, the second plate node, the third plate node and the fourth plate node is operable to be biased independently of the other of the first plate node, the second plate node, the third plate node and the fourth plate node.

[0174] Aspect 19: The apparatus of any of aspects 15 to 18, wherein: each of the plurality of first word lines has a respective height dimension relative to the substrate that overlaps a height dimension of the first activation line and a height dimension of the second activation line.

[0175] Aspect 20: An apparatus according to any one of Aspects 15 to 19, further comprising: a fifth activation line of the first level, which is aligned along the second direction and is operable to activate a plurality of seventh transistors of the first level, each of the plurality of seventh transistors being operable to couple a corresponding first digital line of the plurality of first digital lines to a plate node of the first block; and a sixth activation line of the second level, which is aligned along the second direction and is operable to activate a plurality of eighth transistors of the second level, each of the plurality of eighth transistors being operable to couple a corresponding second digital line of the plurality of second digital lines to a plate node of the second block.

[0176] Aspect 21: An apparatus according to any one of Aspects 15 to 20, further comprising: a seventh activation line of the first level, which is aligned along the second direction and is operable to activate multiple ninth transistors of the first level, wherein the corresponding ones of the multiple third transistors are operable to combine with the corresponding ones of the multiple ninth transistors to couple the corresponding first digital lines of the set of first digital lines of the multiple first digital lines to the circuit system outside the first level above the substrate.

[0177] Aspect 22: The apparatus of any of aspects 15 to 21, wherein the circuitry external to the first level above the substrate includes one or more column decoders or one or more arrays of sense amplifiers, or a combination thereof.

[0178] Aspect 23: The apparatus of any of aspects 15 to 22, wherein the circuitry external to the first level above the substrate includes a plurality of transistors formed at least in part from a doped portion of the substrate.

[0179] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0180] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports a signal flow between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if there is any conductive path between the components that can readily support a signal flow between the components. At any given time, the conductive paths between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be interrupted for a period of time using, for example, one or more intermediate components such as switches or transistors.

[0181] The term "coupling" refers to a condition that moves from an open circuit relationship between components where signals cannot currently be passed between components via a conductive path to a closed circuit relationship between components where signals can be passed between components via a conductive path. When a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not allow signals to flow.

[0182] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between the components, the components are isolated from each other. For example, two components separated by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0183] As used herein, the term "layer" or "level" refers to a layer or sheet of a geometric structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may overwrite at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer or level may include different elements, components, or materials. In some examples, a layer or level may be composed of two or more sub-layers or sub-levels.

[0184] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0185] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0186] The descriptions set forth herein and the accompanying drawings describe exemplary configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The embodiments include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0187] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description may apply to any of the similar components having the same first reference label, regardless of the second reference label.

[0188] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0189] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0190] As used herein, including in the claims, "or" used in a list of items (for example, a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0191] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Those skilled in the art will appreciate the various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: A tile of a memory array, associated with a level above a substrate, the tile comprising: a plurality of memory cells; a plurality of digital lines, each of which is aligned along a first direction; a plurality of word lines each aligned in a second direction and each operable to activate a plurality of first transistors of the tile to couple a respective storage element of each memory cell of a respective row of memory cells with each digit line of the plurality of digit lines; and an activation line aligned along the second direction and operable to activate a plurality of second transistors of the tile, each of the plurality of second transistors being operable to couple a corresponding digit line of the set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate.

2. The apparatus of claim 1, wherein the tile further comprises: A second activation line is aligned along the second direction and is operable to activate a plurality of third transistors, each of the plurality of third transistors being operable to couple a corresponding digit line of a second set of digit lines of the plurality of digit lines with the circuitry.

3. The apparatus of claim 2, wherein the activation line has a terminal end along the second direction positioned between a first pair of digit lines in the plurality of digit lines and the second activation line has a terminal end along the second direction positioned between a second pair of digit lines in the plurality of digit lines.

4. The apparatus of claim 2, wherein the tile further comprises: a first plate node coupled to the storage elements of the memory cells associated with the set of digit lines; and A second plate node is coupled to the storage elements of the memory cells associated with the second set of digit lines, wherein the second plate node is operable to be biased independently of the first plate node.

5. The apparatus of claim 4, wherein the tile further comprises: a third activation line aligned along the second direction and operable to activate a plurality of fourth transistors, each fourth transistor of the plurality of fourth transistors being operable to couple a corresponding digit line of the set of digit lines with the first plate node; and A fourth activation line aligned along the second direction and operable to activate a plurality of fifth transistors, each fifth transistor of the plurality of fifth transistors operable to couple a corresponding digit line of the second set of digit lines with the second plate node.

6. The apparatus of claim 2 , wherein the digit lines of the set of digit lines are configured for the corresponding coupling with the circuit system via a first end of the tile along the first direction and the digit lines of the second set of digit lines are configured for the corresponding coupling with the circuit system via a second end of the tile along the first direction opposite to the first end.

7. The apparatus of claim 6, wherein the tile further comprises: a fifth activation line aligned along the second direction and operable to activate a plurality of sixth transistors, each of the plurality of sixth transistors operable to couple a corresponding digit line of a third set of digit lines of the plurality of digit lines to the circuitry via the first end of the tile along the first direction; and a sixth activation line aligned along the second direction and operable to activate a plurality of seventh transistors, each of the plurality of seventh transistors being operable to couple a corresponding digit line of a fourth set of digit lines of the plurality of digit lines to the circuit system via the second end of the tile along the first direction.

8. The apparatus of claim 7, wherein the tile further comprises: a first plate node coupled to the storage elements of the memory cells associated with the set of digit lines; a second plate node coupled to the storage elements of the memory cells associated with the second set of digit lines; a third plate node coupled to the storage elements of the memory cells associated with the third set of digit lines; and a fourth plate node coupled to the storage elements of the memory cells associated with the fourth set of digit lines, Wherein each of the first plate node, the second plate node, the third plate node, and the fourth plate node is operable to be biased independently of the others of the first plate node, the second plate node, the third plate node, and the fourth plate node.

9. The apparatus of claim 1, wherein each of the plurality of word lines has a respective height dimension relative to the substrate that overlaps a height dimension of the activation line.

10. The apparatus of claim 1, wherein the tile further comprises: A common plate node is coupled to the storage element of each memory cell of the plurality of memory cells.

11. The apparatus of claim 10, wherein the tile further comprises: A seventh activation line is aligned along the second direction and is operable to activate a plurality of eighth transistors, each of the plurality of eighth transistors being operable to couple a corresponding digit line of the plurality of digit lines to the common plate node.

12. The apparatus of claim 11, wherein the seventh activation line is positioned between a pair of word lines of the plurality of word lines along the first direction.

13. The apparatus of claim 1, wherein the circuitry external to the level above the substrate comprises one or more column decoders or one or more arrays of sense amplifiers, or a combination thereof.

14. The apparatus of claim 1, wherein the circuitry external to the level above the substrate comprises a plurality of transistors formed at least in part from a doped portion of the substrate.

15. An apparatus comprising: A first tile of a memory array is associated with a first level above a substrate, the first tile comprising: a plurality of first memory cells; a plurality of first digit lines, each of which is aligned along a first direction; and a plurality of first word lines each aligned in a second direction and each operable to activate a plurality of first transistors of the first tile to couple a respective storage element of each first memory cell of a respective row of first memory cells with each first digit line of the plurality of first digit lines; a second tile of the memory array associated with a second level above the substrate, the second tile comprising: a plurality of second memory cells; a plurality of second digit lines, each of which is aligned along the first direction; and a plurality of second word lines each aligned along the second direction and each operable to activate a plurality of second transistors of the second tile to couple a respective storage element of each second memory cell of a respective row of second memory cells with each second digit line of the plurality of second digit lines; a first activation line of the first level aligned in the second direction and operable to activate a plurality of third transistors of the first level, each of the plurality of third transistors being operable to couple a corresponding first digit line of a set of first digit lines of the plurality of first digit lines to circuitry external to the first level above the substrate; and A second activation line of the first level is aligned along the second direction and is operable to activate a plurality of fourth transistors of the first level, each of the plurality of fourth transistors being operable to couple a corresponding second digital line in a set of second digital lines in the plurality of second digital lines with the circuit system outside the first level above the substrate.

16. The apparatus of claim 15, further comprising: a third activation line of the first level aligned in the second direction and operable to activate a plurality of fifth transistors of the first level, each of the plurality of fifth transistors being operable to couple a respective first digit line of a second set of first digit lines of the plurality of first digit lines to the circuitry external to the first level above the substrate; and A fourth activation line of the first level is aligned along the second direction and is operable to activate a plurality of sixth transistors of the first level, each of the plurality of sixth transistors being operable to couple a corresponding second digital line of a second set of second digital lines of the plurality of second digital lines with the circuit system outside the first level above the substrate.

17. The apparatus of claim 16, wherein: The first activation line, the second activation line, the third activation line, and the fourth activation line each have a respective terminal end along the second direction positioned between a pair of respective first digit lines among the plurality of first digit lines.

18. The apparatus of claim 16, wherein: The first tile includes a first plate node coupled to the storage elements of the memory cells associated with the set of first digit lines and a second plate node coupled to the storage elements of the memory cells of the second set of first digit lines; and the second tile comprising a third plate node coupled to the storage elements of the memory cells associated with the set of second digit lines and a fourth plate node coupled to the storage elements of the memory cells associated with the second set of second digit lines, Wherein each of the first plate node, the second plate node, the third plate node, and the fourth plate node is operable to be biased independently of the others of the first plate node, the second plate node, the third plate node, and the fourth plate node.

19. The apparatus of claim 15, wherein: Each of the plurality of first word lines has a respective height dimension relative to the substrate that overlaps a height dimension of the first activation line and a height dimension of the second activation line.

20. The apparatus of claim 15, further comprising: a fifth activation line of the first level aligned in the second direction and operable to activate a plurality of seventh transistors of the first level, each seventh transistor of the plurality of seventh transistors being operable to couple a corresponding first digit line of the plurality of first digit lines to a plate node of the first tile; and A sixth activation line of the second level is aligned along the second direction and is operable to activate a plurality of eighth transistors of the second level, each of the plurality of eighth transistors being operable to couple a corresponding second digit line of the plurality of second digit lines to a plate node of the second tile.

21. The apparatus of claim 15, further comprising: A seventh activation line of the first level, which is aligned along the second direction and is operable to activate multiple ninth transistors of the first level, wherein corresponding ones of the multiple third transistors are operable to combine with corresponding ones of the multiple ninth transistors to couple the corresponding first digital lines of the set of first digital lines of the multiple first digital lines to the circuit system outside the first level above the substrate.

22. The apparatus of claim 15, wherein the circuitry external to the first level above the substrate comprises one or more column decoders or one or more arrays of sense amplifiers, or a combination thereof.

23. The apparatus of claim 15, wherein the circuitry external to the first level above the substrate comprises a plurality of transistors formed at least in part from a doped portion of the substrate.

24. A method comprising: performing an access operation on a row of memory cells at a level above a substrate of a memory die, wherein the access operation comprises: biasing a word line to activate a plurality of first transistors of the level above the substrate for coupling a respective storage element of each memory cell of the row of memory cells with each digit line of a plurality of digit lines; biasing a first activation line to activate a plurality of second transistors of the level above the substrate for coupling corresponding digit lines of a first set of digit lines of the plurality of digit lines with circuitry external to the level above the substrate; and A second activation line is biased to activate a plurality of third transistors of the level above the substrate for coupling corresponding digit lines of a second set of digit lines of the plurality of digit lines with the circuitry external to the level above the substrate.

25. A method comprising: A tile of a memory array associated with a level above a substrate is formed based at least in part on: forming a plurality of memory cells; forming a plurality of digital lines each aligned along a first direction; forming a plurality of word lines each aligned along a second direction and each operable to activate a plurality of first transistors of the tile to couple a respective storage element of each memory cell of a respective row of memory cells with each digit line of the plurality of digit lines; and An activation line is formed that is aligned along the second direction and is operable to activate a plurality of second transistors of the tile, each of the plurality of second transistors being operable to couple a corresponding digit line in a set of digit lines in the plurality of digit lines with circuitry external to the level above the substrate.

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