A memory expansion based computing device, system and computing method

Abstract

This application discloses a computing device, system, and method based on memory expansion, relating to the field of computer technology. The device includes: flash memory, a flash memory controller, a data stream processing module, a sub-protocol multiplexing and arbitration module, a protocol controller, memory, and a memory controller. The flash memory stores file data, enabling direct file loading into memory within the computing device. The flash memory controller is connected to the data stream processing module via a data path. The flash memory controller acquires file read or write tasks sent by the host processor and initiates file read or write operations via a memory-mapped bus. The data stream processing module accesses the flash memory through the flash memory controller and / or accesses the memory through the memory controller according to the computing task. This shortens the data exchange path, improves the flexibility of computing tasks on memory data, avoids latency caused by frequent file loading, and improves computing efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a computing device, system, and computing method based on memory expansion. Background Technology

[0002] Currently, computer systems have increasingly higher demands for memory capacity, leading to the use of memory expansion devices to increase memory capacity. Furthermore, many new computational problems involve terabyte (TB) level file data; for example, training data for graph neural networks can reach up to 100TB. During execution, applications load files from the host side into the memory of the memory expansion device in minimum units (2KB / 4KB) before executing computational tasks. A complete computational task often requires loading files at different stages, ultimately traversing the entire file range. Frequent file loading and writing processes consume significant time and reduce computational efficiency. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a computing device, system, and method based on memory expansion, which can shorten the data exchange path and improve computing efficiency. The specific solution is as follows:

[0004] In a first aspect, this application discloses a memory-expanded computing device, including flash memory, a flash memory controller, a data stream processing module, a protocol controller, a sub-protocol multiplexing and arbitration module, memory, and a memory controller; wherein, the flash memory is used to store file data so that the operation of loading the file into memory can be completed directly within the memory-expanded computing device; the flash memory controller is connected to the data stream processing module through a data path so that the data stream processing module can access the file data through the flash memory controller;

[0005] The flash memory controller is used to acquire file read tasks or file write tasks sent by the host processor, and initiate file read operations or file write operations through the memory-mapped bus.

[0006] The data stream processing module is used to access data in the flash memory through the flash memory controller and perform data calculations according to the computing task, and / or to access data in the memory through the memory controller and perform data calculations according to the computing task.

[0007] Optionally, the protocol controller is used to obtain file read / write tasks issued by the host processor and forward the file read / write tasks to the sub-protocol multiplexing and arbitration module;

[0008] The sub-protocol multiplexing and arbitration module is used to modify the value of the control status register of the flash controller according to the file read / write task, so that the flash controller can execute the step of initiating a file read operation or a file write operation through the memory-mapped bus by reading the value of the control status register.

[0009] Optionally, the flash memory controller is connected to the sub-protocol multiplexing and arbitration module via a data path; the data path is used for bidirectional file data transmission.

[0010] The flash memory controller is connected to the sub-protocol multiplexing and arbitration module via a control path; the control path is used to access the control status register of the flash memory controller.

[0011] Optionally, the sub-protocol multiplexing and arbitration module includes a sub-protocol arbitration sub-module and a sub-protocol multiplexing sub-module;

[0012] The sub-protocol arbitration submodule is used to decompose transaction layer messages into memory access transactions, configuration transactions, input / output transactions, and message transactions according to the header;

[0013] The sub-protocol multiplexing submodule is used to encode the responses corresponding to the requests of the memory access transaction, the configuration transaction, the input / output transaction, and the message transaction, and generate transaction layer messages.

[0014] Optionally, the sub-protocol multiplexing and arbitration module includes an interrupt signal input interface for receiving interrupt signals;

[0015] The sub-protocol multiplexing and arbitration module is also used to generate a signal interruption message transaction based on the interruption signal and send it to the protocol controller.

[0016] Optionally, the sub-protocol multiplexing and arbitration module includes a first memory access channel, a second memory access channel, and a third memory access channel constructed for memory access transactions;

[0017] The first memory access channel is a control channel, and the first memory access channel is used to access the control status register of the flash memory controller in conjunction with the first control path;

[0018] The second memory access channel is a control channel, which is used to access the control status register in the data stream processing module in conjunction with the second control path;

[0019] The third memory access channel is a data channel, which is used to perform bidirectional file data transmission with the flash memory controller in conjunction with the first data path.

[0020] Optionally, the data stream processing module includes a data stream processing engine and an instruction set processor; the data stream processing engine is an integrated circuit built on a field-programmable gate array (FPGA).

[0021] The data stream processing engine is connected to the protocol controller via a second data path; the second data path is used to transmit read / write access requests to memory sent by the host processor.

[0022] The data stream processing engine is connected to the instruction set processor via a third data path; the third data path is used for data interaction between the data stream processing engine and the instruction set processor.

[0023] The data stream processing engine is connected to the instruction set processor via a third control path, which is used by the instruction set processor to access the control status register of the data stream processing engine.

[0024] The data stream processing engine is connected to the flash memory controller via a fourth data path; the fourth data path is used by the data stream processing engine to access file data in the flash memory.

[0025] The data stream processing engine is connected to the memory controller via a fifth data path; the fifth data path is used by the data stream processing engine to access metadata in the memory.

[0026] The instruction set processor and the memory controller are connected via a sixth data path; the sixth data path is used for data transmission between the instruction set processor and the memory controller.

[0027] Optionally, the data stream processing module further includes an interrupt manager;

[0028] The interrupt manager is used to receive interrupt signals sent by the data stream processing engine, receive interrupt signals sent by the instruction set processor, and forward the target interrupt signal sent by the data stream processing engine to the instruction set processor.

[0029] The interrupt manager is used to submit the received interrupt signal to the sub-protocol multiplexing and arbitration module.

[0030] Optionally, the data stream processing engine includes a write data stream processing path and a read data stream processing path;

[0031] The write data stream processing path is constructed in the order of first-in-first-out memory, downlink stream processing core, and first-in-first-out memory; the write data stream processing path is used to process memory write transactions;

[0032] The read data stream processing path is constructed in the order of first-in-first-out memory, uplink stream processing core, and first-in-first-out memory; the read data stream processing path is used to process memory read transactions.

[0033] Optionally, both the downlink stream processing core and the uplink stream processing core are connected to the interconnect bus via an external storage interface, and the interconnect bus is connected to the flash memory controller and the memory controller, respectively.

[0034] Optionally, both the downlink stream processing core and the uplink stream processing core include a control status register interface for status control and status query.

[0035] Optionally, the computing device further includes a message manager, which is used to process interrupt signals from the data stream processing module and the conversion of sub-protocol messages in the transaction layer of the protocol controller.

[0036] Optionally, the configuration information of the computing device includes flash memory information and memory information so that the computing device can be recognized by the connected host as a hard disk and memory device.

[0037] Secondly, this application discloses a memory-expanded computing system, including a host and the aforementioned memory-expanded computing device, wherein the host is connected to the memory-expanded computing device.

[0038] Thirdly, this application discloses a calculation method, including:

[0039] File data is stored in flash memory so that the file loading into memory can be completed directly within a memory-expanded computing device;

[0040] The flash controller obtains file read or file write tasks sent by the host processor and initiates file read or file write operations through the memory-mapped bus.

[0041] The data stream processing engine in the data stream processing module accesses data in the flash memory through the flash memory controller to perform computational tasks;

[0042] The data stream processing engine in the data stream processing module accesses data in memory through the memory controller to perform computational tasks.

[0043] In this application, the memory-extended computing device includes flash memory, a flash memory controller, a data stream processing module, a sub-protocol multiplexing and arbitration module, a protocol controller, memory, and a memory controller. The flash memory is used to store file data. The flash memory controller and the data stream processing module are connected via a data path. The flash memory controller is used to acquire file read or write tasks sent by the host processor and initiate file read or write operations via a memory-mapped bus. The data stream processing module is used to access the flash memory through the flash memory controller according to the computing task, and / or, access the memory through the memory controller according to the computing task. Therefore, the computing device proposed in this application adds flash memory and a flash memory controller, and the computing device is recognized by the host as a hard drive and memory, enabling it to support TB-level file storage functionality based on the memory extension device. Furthermore, the internal computing architecture of the device can simultaneously access the file area in the flash memory and the memory extension area, thereby transferring the process of frequently loading files to the memory area and frequently writing files from the host side to the computing device itself. This greatly shortens the data exchange path, improves the flexibility of computing tasks on memory data, avoids latency caused by frequent file loading, and improves computing efficiency. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0045] Figure 1 A schematic diagram of a computing device structure based on memory expansion provided in this application;

[0046] Figure 2 A schematic diagram of a specific memory-expansion-based computing device structure provided for this application;

[0047] Figure 3 This application provides a schematic diagram of a specific data stream processing engine structure;

[0048] Figure 4 A flowchart of a calculation method provided in this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] In related technologies, many novel computing problems involve terabyte-scale file data during computation. During execution, the application loads files from the host side into the memory of a memory extension device in the smallest units before executing the computation task. A complete computation task often requires loading files at different stages, ultimately traversing the entire file range. Frequent file loading and writing processes consume significant time and reduce computational efficiency. To overcome these technical problems, this application proposes a memory extension-based computing device that can shorten data exchange paths and improve computational efficiency.

[0051] This application discloses a computing device based on memory expansion, see [link to relevant documentation]. Figure 1 As shown, the computing device may include flash memory 11, flash memory controller 12, data stream processing module 13, subprotocol multiplexing and arbitration module 14, protocol controller 15, memory 16, and memory controller 17.

[0052] The flash memory 11 is used to store file data. That is, by adding flash memory to the memory expansion device, the flash memory supports terabyte-level file storage, thus storing the file data required for computation in the flash memory. The flash memory controller 12 is connected to the data stream processing module 13 via a data path. That is, the flash memory controller and the data stream processing module are connected via a data path, and the data stream processing module is used to perform data processing operations according to the computation task; when the data stream processing module performs the computation task, it can access the memory controller through the data path to read and write file data in memory.

[0053] The flash memory controller 12 is used to acquire file read or file write tasks sent by the host processor and initiate file read or file write operations via the memory-mapped bus. After receiving a file read task from the host processor, the flash memory controller performs the file read operation via the internal memory-mapped bus and sends feedback to the host side. After receiving a file write task from the host processor, the flash memory controller performs the file write operation via the internal memory-mapped bus. The flash memory controller 12 is used to implement reading and writing of the Flash Translation Layer (FTL) and flash memory chips.

[0054] The data stream processing module 13 is used to access the flash memory 11 through the flash memory controller 12 according to the computing task, and / or access the memory 16 through the memory controller 17 according to the computing task. The memory is mapped as a file storage area to the address space of the data stream processing module, thereby allowing the data stream processing module to access both memory and flash memory simultaneously.

[0055] The configuration information of the aforementioned computing device includes flash memory and memory information, so that the computing device can be recognized by the connected host as both a hard disk and a memory device. In other words, by configuring the computing device's configuration information, after connecting to the host, the computing device will be recognized not only as memory but also as a hard disk, allowing the host to store file data in the computing device's flash memory.

[0056] In some embodiments, the protocol controller is configured to acquire file read / write tasks issued by the host processor and forward the file read / write tasks to the sub-protocol multiplexing and arbitration module. The sub-protocol multiplexing and arbitration module is configured to modify the value of the control status register (SCR) of the flash memory controller according to the file read / write task, so that the flash memory controller can execute the step of initiating a file read operation or file write operation through the memory-mapped bus by reading the value of the control status register. It is understood that memory expansion is typically implemented based on the CXL (Compute Express Link) protocol. The protocol controller is a CXL protocol controller, which includes a physical layer, a data link layer, and a transaction layer. The physical layer mainly implements the encoding and decoding of various FLIT data packets; the data link layer is an intermediate media layer between the physical layer and the transaction layer, mainly responsible for providing a reliable mechanism for data exchange between the physical layer and the transaction layer. The transaction layer provides the bus for the CXL.IO sub-protocol and the CXL.MEM sub-protocol. The CXL.MEM protocol is a memory access protocol primarily used to access the extended memory of the device. Other instructions are issued through the CXL.IO sub-protocol. The CXL.IO protocol data flow bus is divided into a memory transaction bus, a configuration bus, and a message flow bus within the multiplexing module. The aforementioned sub-protocol multiplexing and arbitration module is the CXL.IO sub-protocol multiplexing and arbitration module. Access to flash memory is handled by the CXL.IO sub-protocol; that is, the protocol controller forwards file read / write tasks issued by the host processor to the sub-protocol multiplexing and arbitration module. Through this configuration, flash memory, as a file storage area, supports I / O semantic read / write, facilitating host access to file data.

[0057] In this embodiment, the flash memory controller and the sub-protocol multiplexing and arbitration module are connected via a data path; the data path is used for bidirectional file data transmission; the flash memory controller and the sub-protocol multiplexing and arbitration module are connected via a control path; the control path is used to access the control status register of the flash memory controller. It can be understood that when the host processor submits a file read / write task, it first accesses the control status register of the flash memory controller via the control path. Then, after accessing the flash memory, the flash memory controller transmits data with the sub-protocol multiplexing and arbitration module via the data path to report the data to the host.

[0058] As can be seen from the above, the memory-extended computing device in this embodiment includes flash memory, a flash memory controller, a data stream processing module, a sub-protocol multiplexing and arbitration module, a protocol controller, memory, and a memory controller. The flash memory is used to store file data. The flash memory controller and the data stream processing module are connected via a data path. The flash memory controller is used to acquire file read or write tasks sent by the host processor and initiate file read or write operations through a memory-mapped bus. The data stream processing module is used to access the flash memory through the flash memory controller according to the computing task, and / or access the memory through the memory controller according to the computing task. Therefore, by adding flash memory and a flash memory controller, the computing device is recognized by the host as a hard drive and memory, enabling it to support TB-level file storage capabilities based on the memory extension device. Furthermore, the internal computing architecture of the device can simultaneously access the file area in the flash memory and the memory extension area, thereby transferring the process of frequently loading and writing files from the host side to the computing device itself. This significantly shortens the data exchange path, improves the flexibility of computing tasks on memory data, avoids latency caused by frequent file loading, and improves computing efficiency.

[0059] Based on the above embodiments, this application discloses a specific computing device based on memory expansion, for example... Figure 2 As shown, it includes flash memory, flash memory controller, data stream processing module, IO sub-protocol multiplexing and arbitration module, CXL protocol controller, memory, and memory controller. The host processor is connected to the computing device through the CXL interface.

[0060] The IO sub-protocol multiplexing and arbitration module specifically includes a sub-protocol arbitration sub-module and a sub-protocol multiplexing sub-module. The sub-protocol arbitration sub-module decomposes transaction layer packets into memory access transactions, configuration transactions, input / output transactions, and message transactions according to the header. The sub-protocol multiplexing sub-module encodes the responses corresponding to the requests of the memory access transactions, configuration transactions, input / output transactions, and message transactions to generate transaction layer packets. The message transaction provides an interrupt signal input interface and generates an interrupt message transaction based on the interrupt signal, which is then sent to the protocol controller. In other words, the IO protocol arbitration of the IO sub-protocol multiplexing and arbitration module refers to decomposing the transaction layer packet (TLP) into four types of requests according to the header: memory access transactions, configuration transactions, IO transactions, and message transactions. The IO protocol multiplexing of the IO sub-protocol multiplexing and arbitration module refers to encoding the responses corresponding to the requests of these four types of transactions into corresponding transaction layer packets. The message transaction provides an interrupt signal input interface to the outside world. The module internally generates an MSI / MSI-X (Message Signaled Interrupt) transaction and submits it to the CXL controller.

[0061] Memory access transactions are further divided into three memory access channels according to the base address space (BAR): the first memory access channel, the second memory access channel, and the third memory access channel. The first and second memory access channels, acting as control channels, utilize a memory-mapped bus and can access the control status registers of various internal modules. The third memory access channel, acting as a data channel, uses a data stream bus for bidirectional file stream transmission with the flash memory controller. For example... Figure 2As shown, the first memory access channel corresponding to memory B, combined with the first control path (control path 1), is used to access the control status register of the flash memory controller. The second memory access channel corresponding to memory A, combined with the second control path (control path 2), is used to access the control status register in the data stream processing module. The host processor accesses the CSR interconnect bus through control path 2, accesses the programmable stream processing engine through control path 4, and the reduced instruction set processor through control path 5. The third memory access channel corresponding to memory C, combined with the first data path (data path 1) and the memory map master (MMM) on the flash memory controller, is used for bidirectional file data transfer with the flash memory controller. That is, when the host processor submits a file read / write task, it accesses the control and status registers of the flash memory controller through control path 1; after the host processor submits a file read / write task through control path 1, the flash memory controller initiates DMA (Direct Memory Access). During a read task, the memory map master of the flash memory controller initiates a DMA write operation; during a write task, the memory map master of the flash memory controller initiates a DMA read operation.

[0062] The aforementioned data stream processing module specifically includes a data stream processing engine and an instruction set processor. The data stream processing engine is an integrated circuit built on a field-programmable gate array (FPGA). Specifically, the data stream processing engine is a programmable data stream processing engine, and the instruction set processor is a reduced instruction set processor (RISC). The programmable data stream processing engine is based on RTL (register-transfer level) and achieves online processing of the data stream with extremely low latency. The RISC processor, on the other hand, uses a pipelined approach to achieve offline processing of data blocks and can use various standard software libraries, offering convenience and flexibility. The data stream processing engine is connected to the protocol controller via a second data path, which is used to transmit read / write access requests to memory sent by the host processor; for example... Figure 2 In this process, read and write accesses to the extended memory region submitted by the host processor are routed to the upstream port of the programmable stream processing engine via data path 2. The stream processing engine is connected to the instruction set processor via a third data path, which is used for data interaction between the stream processing engine and the instruction set processor, i.e., as shown in the example. Figure 2 Data path 3 is the data path between the downstream port of the programmable stream processing engine and the reduced instruction set processor (RISC). The data stream processing engine and the instruction set processor are connected via a third control path, which is used by the instruction set processor to access the control status register of the data stream processing engine; that is, as shown in the example... Figure 2Control path 3 is used by the RISC processor to access the control and status registers of the programmable stream processing engine. The stream processing engine is connected to the flash memory controller via a fourth data path. This fourth data path is used by the stream processing engine to access file data in the flash memory, specifically through the Memory Map Stream Data (MMS) bus connected to the flash memory controller. Figure 2 Data path 4 is the data path for the programmable stream processing engine to access the file storage area. The stream processing engine is connected to the memory controller via a fifth data path, which is used by the stream processing engine to access metadata in memory; that is... Figure 2 Data path 5 is the data path between the programmable stream processing engine and the metadata storage area. Memory write data submitted by the host processor is stored in the metadata area before stream processing. The instruction set processor and the memory controller are connected via a sixth data path, which is used for data transfer between the instruction set processor and the memory controller; that is... Figure 2 Data path 6 is the data path between the RISC processor and the memory extension area. It can be seen that the above data path design enables the processing engine to access both flash memory and main memory simultaneously, as well as the host to read and write file data in flash memory. The above control path design enables anti-spoofing of control and status registers between different modules, and allows for the configuration of status and control information for each module. The data computation process is realized through the cooperation of the control path and the data path.

[0063] In this embodiment, the aforementioned data stream processing engine specifically includes a write data stream processing path and a read data stream processing path. The write data stream processing path is constructed in the order of first-in-first-out (FIFO) memory, downlink stream processing core, and FIFO memory. The write data stream processing path is used to process memory write transactions. The read data stream processing path is constructed in the order of first-in-first-out (FIFO) memory, uplink stream processing core, and FIFO memory. The read data stream processing path is used to process memory read transactions. Both the downlink stream processing core and the uplink stream processing core are connected to the interconnect bus through an external storage interface. The interconnect bus is connected to the flash memory controller and the memory controller, respectively. Both the downlink stream processing core and the uplink stream processing core include a control status register interface for status control and status query.

[0064] For example Figure 3As shown, the programmable data stream processing engine is located upstream of the entire heterogeneous data stream processing core. It is an IP core implemented based on a Field-Programmable Gate Array (FPGA). Data requests from the host side are directly submitted to the data stream processing engine after passing through the CXL protocol controller. On the data plane, the engine's upstream data port (UP) uses a memory-mapped bus and acts as a slave device. Both write and read channels have corresponding stream processing paths. Memory write transactions pass through a FIFO (First Input First Output) memory, the downlink stream processing core, and the FIFO again, finally connecting to the downstream port (DP). Memory read transactions pass through a FIFO, the uplink stream processing core, and the FIFO again, finally connecting to the downstream port. Furthermore, both the downlink and uplink stream processing cores access metadata and files via external storage ports (EM) and the interconnect bus, respectively accessing memory and flash memory. The metadata interface is mainly used to access user-written metadata (i.e., raw data), while the file access interface is mainly used to access file data written to the flash memory area by the user using I / O semantics. In the control plane design, both the uplink and downlink stream processing cores provide CSR interfaces for status control and querying. In addition, both the uplink and downlink stream processing cores provide interrupt signals to submit interrupt requests to external modules (such as instruction set processors).

[0065] The instruction set processor (ISP), as a downstream engine, differs from the data stream processing engine in that its data processing methods are more flexible. On one hand, the ISP's processing objects are not limited to the current data stream but also include the entire memory region and user file storage region. On the other hand, its programming methods are more flexible, utilizing different library functions in the operating system environment and the multi-threading mechanism of the reduced instruction set processor (RISC) for data processing. Specifically, the ISP includes a microprocessor and a cache coherency unit. The cache coherency unit receives memory access transactions sent by the data stream processing engine. When the memory access transaction does not require cache coherency maintenance, the cache coherency unit directly forwards the memory access transaction to the memory controller; when the memory access transaction requires cache coherency maintenance, it caches the memory access transaction using the cache area in the microprocessor. In other words, in the data plane design, the ISP provides a memory-mapped interface and acts as a slave device. External modules (i.e., the stream processing engine) access the RISC's cache coherency unit through this interface, and the sideband signals of the memory-mapped bus can be used to mark whether a memory access transaction requires cache coherency maintenance. When cache coherency maintenance is not required, the memory access transaction is directly forwarded to the memory controller, resulting in lower latency. When maintaining cache consistency is required, there will be a certain latency, but flexible handling of memory access is supported. The instruction set processor can perform status control by accessing the control status register inside the data stream processing engine. In addition, the instruction set processor is also used to receive interrupt signals from external modules (i.e., the data stream processing engine). When the instruction set processor receives an interrupt signal, it accesses the control status register of the data stream processing engine; the instruction set processor is also used to output interrupt signals to notify external modules that an interrupt event has occurred.

[0066] In this embodiment, the data stream processing module further includes an interrupt manager; the interrupt manager is used to receive interrupt signals sent by the data stream processing engine, receive interrupt signals sent by the instruction set processor, and forward the target interrupt signal sent by the data stream processing engine to the instruction set processor; the interrupt manager is also used to submit the received interrupt signals to the sub-protocol multiplexing and arbitration module. That is, as follows... Figure 2 As shown, interrupt 1 is the interrupt signal output by the programmable stream processing engine, interrupt 2 is the interrupt signal output by the reduced instruction set processor; interrupt 3 is interrupt 1 output by the programmable stream processing engine, which will be selectively forwarded to the reduced instruction set processor; interrupt 4 is the interrupt signal submitted by the interrupt manager of the heterogeneous data stream processing core to the IO protocol multiplexing and arbitration module.

[0067] In some embodiments, the computing device further includes a message manager, which processes interrupt signals from the microprocessor in the data stream processing module and converts sub-protocol messages in the transaction layer of the protocol controller. Specifically, when the host sets the interrupt register to a valid value via the CXL.IO protocol, the message manager submits a trigger event through the interrupt interface of the reduced instruction set processor; after the reduced instruction set processor completes the computation process, it modifies the corresponding interrupt register via the memory-mapped bus, and then the message manager generates an MSI / MSI-X message and submits it to the external host via the IO sub-protocol of the transaction layer of the CXL protocol controller.

[0068] As can be seen from the above, the memory capacity requirement of the memory expansion device cannot meet the requirement of loading a file into the memory expansion at once, and the cost of memory expansion is very high. Under such circumstances, related technologies require frequent loading and writing of files from the host side to the memory area, which consumes a lot of time and reduces computing efficiency. This embodiment improves computing efficiency by adding flash memory and a flash memory controller, allowing flash memory and memory to coexist in the same computing device. By using flash memory to store file data, the exchange path for loading files into memory is shortened.

[0069] Accordingly, this application also discloses a memory-expanded computing system, comprising a host and the aforementioned memory-expanded computing device, wherein the host is connected to the memory-expanded computing device. The memory-expanded computing device includes flash memory, a flash memory controller, a data stream processing module, a sub-protocol multiplexing and arbitration module, a protocol controller, memory, and a memory controller. It is evident that by storing file data in flash memory and storing metadata in memory, the data stream processing module performs computing tasks by accessing both memory and flash memory, thereby improving computing efficiency.

[0070] Accordingly, this application also discloses a calculation method applied to the aforementioned memory-expansion-based computing device, see [link to relevant documentation]. Figure 4 As shown, the method includes:

[0071] Step S11: Store file data in flash memory so that the file loading into memory can be completed directly within the memory-expanded computing device;

[0072] Step S12: Obtain the file read task or file write task sent by the host processor through the flash memory controller, and initiate the file read operation or file write operation through the memory-mapped bus;

[0073] Step S13: The data stream processing engine in the data stream processing module accesses data in the flash memory through the flash memory controller to perform computing tasks; the data stream processing engine in the data stream processing module accesses data in memory through the memory controller to perform computing tasks.

[0074] In this embodiment, the memory-extended computing device includes flash memory, a flash memory controller, a data stream processing module, a sub-protocol multiplexing and arbitration module, a protocol controller, memory, and a memory controller. The flash memory is used to store file data. The flash memory controller and the data stream processing module are connected via a data path. The flash memory controller is used to acquire file read or write tasks sent by the host processor and initiate file read or write operations via a memory-mapped bus. The data stream processing module is used to access the flash memory through the flash memory controller according to the computing task, and / or access the memory through the memory controller according to the computing task. Therefore, by adding flash memory and a flash memory controller, the computing device is recognized by the host as a hard drive and memory, enabling it to support terabyte-level file storage capabilities based on the memory extension device. Furthermore, the internal computing architecture of the device can simultaneously access the file area in the flash memory and the memory extension area, thereby transferring the process of frequently loading and writing files from the host side to the computing device itself. This significantly shortens the data exchange path, improves the flexibility of computing tasks on memory data, avoids latency caused by frequent file loading, and improves computing efficiency.

[0075] In some specific embodiments, the protocol controller obtains the file read / write task issued by the host processor and forwards the file read / write task to the sub-protocol multiplexing and arbitration module; according to the file read / write task, the sub-protocol multiplexing and arbitration module modifies the value of the control status register of the flash memory controller, so that the flash memory controller can execute the step of initiating a file read operation or a file write operation through the memory-mapped bus by reading the value of the control status register.

[0076] In some specific embodiments, the flash memory controller is connected to the sub-protocol multiplexing and arbitration module via a data path; the data path is used for bidirectional file data transmission; the flash memory controller is connected to the sub-protocol multiplexing and arbitration module via a control path; the control path is used to access the control status register of the flash memory controller.

[0077] In some specific embodiments, the sub-protocol multiplexing and arbitration module includes a sub-protocol arbitration sub-module and a sub-protocol multiplexing sub-module. The sub-protocol arbitration sub-module is used to decompose transaction layer messages into memory access transactions, configuration transactions, input / output transactions, and message transactions according to the header. The sub-protocol multiplexing sub-module is used to encode the responses corresponding to the requests of the memory access transactions, configuration transactions, input / output transactions, and message transactions to generate transaction layer messages. The message transactions are used to provide an interrupt signal input interface and generate interrupt message transactions based on the interrupt signal to send to the protocol controller. The memory access transactions include a first memory access channel as a control channel, a second memory access channel as a control channel, and a third memory access channel as a data channel. The first memory access channel is used to access the control status register of the flash memory controller in conjunction with a first control path. The second memory access channel is used to access the control status register in the data stream processing module in conjunction with a second control path. The third memory access channel is used to perform bidirectional file data transmission with the flash memory controller in conjunction with the first data path.

[0078] In some specific embodiments, the data stream processing module includes a data stream processing engine and an instruction set processor; the data stream processing engine is an integrated circuit built on a field-programmable gate array (FPGA); the data stream processing engine is connected to the protocol controller via a second data path; the second data path is used to transmit read / write access requests to memory sent by the host processor; the data stream processing engine is connected to the instruction set processor via a third data path; the third data path is used for data interaction between the data stream processing engine and the instruction set processor; the data stream processing engine is connected to the instruction set processor via a third control path; the third control path is used for the instruction set processor to access the control status register of the data stream processing engine; the data stream processing engine is connected to the flash memory controller via a fourth data path; the fourth data path is used for the data stream processing engine to access file data in the flash memory; the data stream processing engine is connected to the memory controller via a fifth data path; the fifth data path is used for the data stream processing engine to access metadata in the memory; the instruction set processor is connected to the memory controller via a sixth data path; the sixth data path is used for data transmission between the instruction set processor and the memory controller.

[0079] In some specific embodiments, the data stream processing engine includes a write data stream processing path and a read data stream processing path; the write data stream processing path is constructed in the order of first-in-first-out (FIFO) memory, downlink stream processing core, and FIFO memory; the write data stream processing path is used to process memory write transactions; the read data stream processing path is constructed in the order of FIFO memory, uplink stream processing core, and FIFO memory; the read data stream processing path is used to process memory read transactions; both the downlink stream processing core and the uplink stream processing core are connected to an interconnect bus via an external storage interface, and the interconnect bus is connected to the flash memory controller and the memory controller, respectively; both the downlink stream processing core and the uplink stream processing core include a control status register interface for status control and status query.

[0080] In some specific embodiments, the data stream processing module further includes an interrupt manager; the interrupt manager is used to receive interrupt signals sent by the data stream processing engine, receive interrupt signals sent by the instruction set processor, and forward target interrupt signals sent by the data stream processing engine to the instruction set processor; the interrupt manager is used to submit the received interrupt signals to the sub-protocol multiplexing and arbitration module.

[0081] In some specific embodiments, prior to performing calculations, the method further includes configuring configuration information for the computing device, the configuration information including flash memory information and memory information, so that the computing device can be recognized by the connected host as a hard disk and memory device.

[0082] Furthermore, this application also discloses a computer storage medium storing computer-executable instructions. When the computer-executable instructions are loaded and executed by a processor, they implement the calculation method steps disclosed in any of the foregoing embodiments.

[0083] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the apparatus disclosed in the embodiments; relevant parts can be found in the method section.

[0084] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0085] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0086] The foregoing has provided a detailed description of a memory-expansion-based computing device, system, and computing method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A computing device based on memory expansion, characterized in that, The system includes flash memory, a flash memory controller, a data stream processing module, a sub-protocol multiplexing and arbitration module, a protocol controller, memory, and a memory controller. The flash memory is used to store file data, enabling the file to be loaded into memory directly within the memory-extended computing device. The flash memory controller is connected to the data stream processing module via a data path, allowing the data stream processing module to access the file data through the flash memory controller. The flash memory controller is used to acquire file read or file write tasks sent by the host processor, and initiate file read or file write operations through the memory-mapped bus; the flash memory controller is used to read and write the flash conversion layer and flash memory chips; The data stream processing module is used to access data in the flash memory through the flash memory controller and perform data calculations according to the computing task, and / or to access data in the memory through the memory controller and perform data calculations according to the computing task; The data stream processing module includes a data stream processing engine and an instruction set processor; the data stream processing engine is an integrated circuit built on a field-programmable gate array. The data stream processing engine is connected to the protocol controller via a second data path; the second data path is used to transmit read / write access requests to memory sent by the host processor. The data stream processing engine is connected to the instruction set processor via a third data path; the third data path is used for data interaction between the data stream processing engine and the instruction set processor. The data stream processing engine is connected to the instruction set processor via a third control path; the third control path is used by the instruction set processor to access the control status register of the data stream processing engine. The data stream processing engine is connected to the memory-mapped data stream bus of the flash memory controller via a fourth data path; the fourth data path is used by the data stream processing engine to access file data in the flash memory. The data stream processing engine is connected to the memory controller via a fifth data path; the fifth data path is used by the data stream processing engine to access metadata in the memory. The instruction set processor and the memory controller are connected via a sixth data path; the sixth data path is used for data transmission between the instruction set processor and the memory controller. The configuration information of the computing device includes flash memory information and memory information, so that the computing device can be identified as a hard disk and memory device by the connected host. The protocol controller is used to obtain file read / write tasks issued by the host processor and forward the file read / write tasks to the sub-protocol multiplexing and arbitration module. The sub-protocol multiplexing and arbitration module is used to modify the value of the control status register of the flash controller according to the file read / write task, so that the flash controller can execute the step of initiating a file read operation or a file write operation through the memory-mapped bus by reading the value of the control status register. The flash memory controller is connected to the sub-protocol multiplexing and arbitration module via a data path; the data path is used for bidirectional file data transmission. The flash memory controller is connected to the sub-protocol multiplexing and arbitration module via a control path; the control path is used to access the control status register of the flash memory controller.

2. The computing device based on memory expansion according to claim 1, characterized in that, The sub-protocol reuse and arbitration module includes a sub-protocol arbitration sub-module and a sub-protocol reuse sub-module; The sub-protocol arbitration submodule is used to decompose transaction layer messages into memory access transactions, configuration transactions, input / output transactions, and message transactions according to the header; The sub-protocol multiplexing submodule is used to encode the responses corresponding to the requests of the memory access transaction, the configuration transaction, the input / output transaction, and the message transaction, and generate transaction layer messages.

3. The computing device based on memory expansion according to claim 2, characterized in that, The sub-protocol multiplexing and arbitration module includes an interrupt signal input interface for receiving interrupt signals; The sub-protocol multiplexing and arbitration module is also used to generate a signal interruption message transaction based on the interruption signal and send it to the protocol controller.

4. The computing device based on memory expansion according to claim 2, characterized in that, The sub-protocol multiplexing and arbitration module includes a first memory access channel, a second memory access channel, and a third memory access channel constructed for memory access transactions; The first memory access channel is a control channel, and the first memory access channel is used to access the control status register of the flash memory controller in conjunction with the first control path; The second memory access channel is a control channel, which is used to access the control status register in the data stream processing module in conjunction with the second control path; The third memory access channel is a data channel, which is used to perform bidirectional file data transmission with the flash memory controller in conjunction with the first data path.

5. The computing device based on memory expansion according to claim 1, characterized in that, The data stream processing module also includes an interrupt manager; The interrupt manager is used to receive interrupt signals sent by the data stream processing engine, receive interrupt signals sent by the instruction set processor, and forward the target interrupt signal sent by the data stream processing engine to the instruction set processor. The interrupt manager is used to submit the received interrupt signal to the sub-protocol multiplexing and arbitration module.

6. The computing device based on memory expansion according to claim 1, characterized in that, The data stream processing engine includes a write data stream processing path and a read data stream processing path; The write data stream processing path is constructed in the order of first-in-first-out memory, downlink stream processing core, and first-in-first-out memory; The write data stream processing path is used to process memory write transactions; The read data stream processing path is constructed in the order of first-in-first-out memory, uplink stream processing core, and first-in-first-out memory; The read data stream processing path is used to handle memory read transactions.

7. The computing device based on memory expansion according to claim 6, characterized in that, Both the downlink stream processing core and the uplink stream processing core are connected to the interconnect bus via an external storage interface. The interconnect bus is connected to the flash memory controller and the memory controller, respectively.

8. The computing device based on memory expansion according to claim 6, characterized in that, Both the downlink stream processing core and the uplink stream processing core include a control status register interface for status control and status query.

9. The computing device based on memory expansion according to claim 1, characterized in that, It also includes a message manager, which is used to handle interrupt signals from the data stream processing module and the conversion of sub-protocol messages in the transaction layer of the protocol controller.

10. A computing system based on memory expansion, characterized in that, The system includes a host computer and a computing device as described in any one of claims 1 to 9, wherein the host computer is connected to the computing device.

11. A calculation method, characterized in that, Applied to the computing device as described in any one of claims 1 to 9, comprising: File data is stored in flash memory so that the file loading into memory can be completed directly within a memory-expanded computing device; The flash controller obtains file read or file write tasks sent by the host processor and initiates file read or file write operations through the memory-mapped bus. The data stream processing engine in the data stream processing module accesses data in the flash memory through the flash memory controller to perform computing tasks; the data stream processing engine in the data stream processing module accesses data in memory through the memory controller to perform computing tasks.

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