Electronic packaging component and packaging substrate and manufacturing method thereof

Abstract

An electronic package and its packaging substrate and manufacturing method. An insulating layer inside the packaging substrate of the electronic package is made of ABF material, so as to facilitate the use of RDL process to manufacture the circuit structure, so that the circuit layer is conducive to meeting the requirements of high-density fine circuits / fine spacing.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging process, in particular to an electronic packaging component with ABF and a packaging substrate and a manufacturing method thereof. Background Art

[0002] As the functional requirements of terminal products increase, semiconductor chips need to have more input / output (I / O) contacts, so the number of external pads on the package substrate used to carry the semiconductor chip also increases accordingly.

[0003] There are many technologies currently used in the field of chip packaging, such as chip scale package (CSP), direct chip attached package (DCA) or multi-chip module package (MCM) and other flip chip packaging modules, or three-dimensional chip stacking to integrate into a three-dimensional integrated circuit (3D IC) chip stacking technology.

[0004] Figure 1 FIG. 1 is a cross-sectional schematic diagram of an existing semiconductor package 1. Figure 1 As shown, the method for manufacturing the semiconductor package 1 first provides a through silicon interposer (TSI) 10, the silicon interposer 10 having a die side 10a and a transfer side 10b opposite to each other and a plurality of conductive through silicon vias (TSV) 100 connecting the die side 10a and the transfer side 10b, and the die side 10a has a circuit redistribution layer (RDL) electrically connected to the conductive through silicon vias 100. Then, a semiconductor chip 11 is electrically connected to the redistribution layer 12 by its electrode pad 110 through a plurality of solder bumps 111, and an underfill 112 is filled between the semiconductor chip 11 and the silicon interposer 10 to cover the solder bumps 111; thereafter, a packaging substrate 16 is electrically connected to the conductive silicon via 100 by its pad 160 through a plurality of C4-specification conductive elements 15 such as solder bumps or copper pillars, and another underfill 17 is filled between the silicon interposer 10 and the packaging substrate 16 to cover the conductive elements 15; finally, a plurality of solder balls 19 are connected to the bottom side of the packaging substrate 16 to connect to a circuit board (not shown).

[0005] However, in the existing semiconductor package 1, a silicon interposer 10 is used as a medium for signal transmission between the semiconductor chip 11 and the circuit board. Therefore, when manufacturing the silicon interposer 10, it is necessary to manufacture the existing conductive silicon vias 100 and the C4 specification conductive elements 15, thereby greatly increasing the process difficulty and manufacturing cost. In addition, the packaging substrate 16 needs to conduct electrical signals and dissipate heat through the conductive elements 15, resulting in poor conductive performance and heat dissipation performance of the packaging substrate 16.

[0006] Furthermore, the silicon interposer 10 needs to be disposed on the package substrate 16 via the conductive elements 15 , which makes it difficult to reduce the overall thickness of the semiconductor package 1 , and causes the electronic product using the semiconductor package 1 to be difficult to meet the requirements of miniaturization.

[0007] In addition, during the manufacturing process of the conventional semiconductor package 1, the coefficient of thermal expansion (CTE) between the package substrate 16 and the silicon interposer 10 does not match, so that uneven thermal stress is easily generated, causing the package substrate 16 to have a large warpage when the solder bumps 111, the conductive elements 15 and the solder balls 19 are subsequently reflowed, resulting in reliability problems such as poor ball implantation (i.e., the solder balls 19 fall off), non-wetting of the solder balls 19 or cracking of the package substrate 16, thereby causing reliability problems in terminal electronic products (such as computers, mobile phones, etc.) using the semiconductor package 1.

[0008] In addition, the bonding property between silicon and metal is not good, which is not conducive to manufacturing the RDL 12 , and the RDL 12 and the silicon interposer 10 are prone to separation.

[0009] Therefore, how to overcome the various problems of the above-mentioned existing manufacturing methods has become a topic that is urgently needed to be solved. Summary of the invention

[0010] In view of the above-mentioned deficiencies of the prior art, the present invention provides an electronic package and a package substrate and a manufacturing method thereof, which can at least partially solve the problems of the prior art.

[0011] The packaging substrate of the present application includes: a wiring structure having a first side and a second side opposite to each other, wherein the wiring structure includes at least one insulating layer and a wiring layer arranged on the insulating layer, and the material forming the insulating layer is an Ajinomoto build-up film; a first circuit structure, which is arranged on the first side of the wiring structure, wherein the first circuit structure includes at least one first dielectric layer formed on the insulating layer and a first circuit layer arranged on the first dielectric layer and electrically connected to the wiring layer, and the material forming the first dielectric layer is different from the material forming the insulating layer; and a second circuit structure, which is arranged on the second side of the wiring structure, wherein the second circuit structure includes at least one second dielectric layer formed on the insulating layer and a second circuit layer arranged on the second dielectric layer and electrically connected to the wiring layer, and the material forming the second dielectric layer is different from the material forming the insulating layer.

[0012] In the aforementioned packaging substrate, the first circuit structure is bonded to a core board body, and the core board body has a first surface and a second surface relative to each other, so that the first circuit structure is bonded to the first surface of the core board body, and the core board body has a plurality of conductive through holes connecting the first and second surfaces, so that the conductive through holes are electrically connected to the first circuit layer.

[0013] The present invention also provides an electronic package, comprising: the aforementioned package substrate; and an electronic component, which is disposed on the second circuit structure and electrically connected to the second circuit layer.

[0014] The present invention further provides a method for manufacturing a packaging substrate, comprising: forming a wiring structure on a carrier, the wiring structure having a first side and a second side opposite to each other, so that the wiring structure is combined with the carrier with its second side, wherein the wiring structure includes at least one insulating layer and a wiring layer disposed on the insulating layer, and the material forming the insulating layer is an Ajinomoto build-up film; forming a first circuit structure on the first side of the wiring structure, wherein the first circuit structure includes at least one first dielectric layer formed on the insulating layer and a first circuit layer disposed on the first dielectric layer and electrically connected to the wiring layer, and the material forming the first dielectric layer is different from the material forming the insulating layer; removing the carrier to expose the second side of the wiring structure; and forming a second circuit structure on the second side of the wiring structure, wherein the second circuit structure includes at least one second dielectric layer formed on the insulating layer and a second circuit layer disposed on the second dielectric layer and electrically connected to the wiring layer, and the material forming the second dielectric layer is different from the material forming the insulating layer.

[0015] The present invention also provides a method for manufacturing a packaging substrate, comprising: providing a core board having a first surface and a second surface opposite to each other, and the core board having a plurality of conductive through holes connecting the first and second surfaces; forming a first circuit structure on the first surface of the core board, wherein the first circuit structure includes at least one first dielectric layer formed on the core board and a first circuit layer disposed on the first dielectric layer and electrically connected to the conductive through holes; forming a wiring structure on the first circuit structure, and the wiring structure has a first side and a second side opposite to each other, so that the wiring structure is combined with the first circuit structure with its first side, wherein the wiring structure includes at least one insulating layer formed on the first dielectric layer and a wiring layer disposed on the insulating layer, and the material forming the insulating layer is Ajinomoto build-up film (Ajinomoto build-up film). The invention relates to a method for manufacturing a wiring structure of an insulating layer, wherein the first dielectric layer is formed of a material different from that of the first dielectric layer; and forming a second wiring structure on a second side of the wiring structure, wherein the second wiring structure comprises at least one second dielectric layer formed on the insulating layer and a second wiring layer disposed on the second dielectric layer and electrically connected to the wiring layer, and the material forming the second dielectric layer is different from that forming the insulating layer.

[0016] In the aforementioned packaging substrate and the two manufacturing methods thereof, the materials of the first and second dielectric layers are different.

[0017] The present invention further provides a method for manufacturing an electronic package, comprising: providing the aforementioned package substrate; and arranging an electronic element on the second circuit structure, wherein the electronic element is electrically connected to the second circuit layer.

[0018] The aforementioned electronic package and its manufacturing method further include forming an external element on the first circuit structure, and the external element is electrically connected to the first circuit layer.

[0019] As can be seen from the above, the electronic package and its packaging substrate and manufacturing method of the present invention mainly use ABF as an insulating layer to replace the existing silicon board, and use the wiring layer as a medium for signal transmission between electronic components and circuit boards. Therefore, compared with the existing technology, the present invention does not need to manufacture the processes related to conductive silicon vias and C4 specification conductive components of the existing silicon interposer, thereby greatly reducing the process difficulty and manufacturing cost, and the conductive performance and heat dissipation performance of the packaging substrate are greatly improved.

[0020] Furthermore, the present invention uses the design of directly connecting the wiring structure to the first circuit structure to replace the existing silicon interposer and C4 specification conductive elements, so that the thickness of the package substrate of the present invention is conducive to the thinning requirement.

[0021] In addition, by using a material different from that of the first and second dielectric layers to form the insulating layer, thermal stress can be dispersed, so that the packaging substrate of the present invention can effectively avoid warping in subsequent manufacturing processes.

[0022] In addition, the present invention uses ABF as the insulating layer design to facilitate the use of RDL process to manufacture the second circuit structure, so that the second circuit layer is conducive to meeting the requirements of high-density fine circuits / fine pitches and reducing the risk of separation between the second circuit structure and the wiring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a cross-sectional view of a conventional semiconductor package.

[0024] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing an electronic package of the present invention.

[0025] FIG. 3A to FIG. 3D It is a cross-sectional schematic diagram of a second embodiment of the method for manufacturing an electronic package of the present invention.

[0026] The reference numerals are described as follows:

[0027] 1Semiconductor Package

[0028] 10Silicon interposer

[0029] 10a Chip side

[0030] 10b transfer side

[0031] 100 conductive silicon vias

[0032] 11Semiconductor Chips

[0033] 110,400 electrode pads

[0034] 111 solder bump

[0035] 112,17 Primer

[0036] 12 line redistribution layers

[0037] 15 Conductive elements

[0038] 16, 2a, 3a package substrate

[0039] 160 welding pad

[0040] 19 solder balls

[0041] 2,3 Electronic packaging

[0042] 20, 220, 320 wiring layers

[0043] 21, 31a, 31b first line structure

[0044] 210, 310 first circuit layer

[0045] 211, 311 first dielectric layer

[0046] 22, 32 wiring structure

[0047] 22a, 32a first side

[0048] 22b, 32b second side

[0049] 221, 321, 322 insulation layer

[0050] 23, 33 Second line structure

[0051] 230, 330 second circuit layer

[0052] 231, 331 second dielectric layer

[0053] 27, 29 External components

[0054] 30 core board

[0055] 30a first surface

[0056] 30b Second surface

[0057] 300 conductive vias

[0058] 300a plug material

[0059] 301, 302 inner circuit layer

[0060] 40, 41, 42, 43 Electronic components

[0061] 40a action surface

[0062] 40b Non-active surface

[0063] 44 conductive bumps

[0064] 45 Passive Components

[0065] 9 bearing parts

[0066] 90 plate body

[0067] 91 metal layers DETAILED DESCRIPTION

[0068] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0069] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of people familiar with this technology, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0070] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing an electronic package 2 of the present invention.

[0071] like Figure 2A As shown, a wiring layer 20 is formed on a carrier 9 .

[0072] In this embodiment, the carrier 9 is a temporary carrier, such as a copper foil substrate or other plate materials. For example, the carrier 9 is a copper foil substrate, and the two opposite sides of the plate body 90 thereof have metal layers 91 .

[0073] Furthermore, the wiring layer 20 is made into a patterned circuit by electroplating metal (such as copper) on the metal layer 91 or by other methods.

[0074] like Figure 2B As shown, a wiring structure 22 is symmetrically formed on two opposite sides of the carrier 9 , and a first circuit structure 21 is formed on the wiring structure 22 .

[0075] In this embodiment, each of the wiring structures 22 is defined with a first side 22 a and a second side 22 b opposite to each other, and the wiring structure 22 is combined with the carrier 9 at its second side 22 b , and the first circuit structure 21 is formed on the first side 22 a of the wiring structure 22 .

[0076] Furthermore, the wiring structure 22 includes at least one insulating layer 221 covering the wiring layer 20, and another wiring layer 220 formed on the insulating layer 221, so that the another wiring layer 220 is electrically connected to the wiring layer 20 on the metal layer 91, that is, the another wiring layer 220 is electrically connected to the wiring layer 20 on the metal layer 91 by the conductor plated in the laser blind hole formed on the insulating layer 221. For example, the material forming the insulating layer 221 is Ajinomoto build-up film (ABF), whose coefficient of thermal expansion (CTE) is 13 to 17 ppm / °C, and the wiring layer 220 is made into a patterned circuit by electroplating metal (such as copper) or other methods. It should be understood that by using the build-up process method, the wiring structures 22 can add multiple insulating layers 221 as needed to make a multi-layer wiring layer 220.

[0077] In addition, the first circuit structure 21 includes at least one first dielectric layer 211 formed on the insulating layer 221, and a first circuit layer 210 formed on the first dielectric layer 211, so that the first circuit layer 210 is electrically connected to the wiring layer 220, that is, the first circuit layer 210 is electrically connected to the wiring layer 220 by the conductor plated in the laser blind hole formed on the first dielectric layer 211. For example, the first circuit structure 21 is manufactured by a build-up method, so that the first circuit structure 21 can add multiple layers of first dielectric layers 211 according to needs to manufacture multiple layers of first circuit layers 210, and the material forming the first dielectric layer 211 is polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials. Therefore, the material forming the first dielectric layer 211 and the material forming the insulating layer 221 may be different. For example, the material forming the first dielectric layer 211 is prepreg (PP), and its coefficient of thermal expansion (CTE) is 10 ppm / °C.

[0078] In addition, the line width / line spacing of the first circuit layer 210 is about 50 / 50 micrometers (um) at most, and the line width / line spacing of the wiring layer 220 is about 10 / 10 micrometers (um) at most.

[0079] like Figure 2C As shown, the carrier 9 is removed to expose the second side 22 b of the wiring structure 22 and the wiring layer 20 therein.

[0080] In this embodiment, the plate body 90 may be peeled off or ground first, and then the metal layer 91 may be removed by etching, so that the wiring layer 20 is flush with or slightly concave on the surface of the second side 22 b of the wiring structure 22 .

[0081] like Figure 2D As shown, a second circuit structure 23 is formed on the second side 22 b of the wiring structure 22 to form a packaging substrate 2 a , and the wiring layer 20 is electrically connected to the second circuit structure 23 .

[0082] In this embodiment, the second circuit structure 23 can be formed on the second side 22b of the wiring structure 22 by using a build-up method, so that the second circuit structure 23 can be provided with multiple second dielectric layers 231 as required to form multiple second circuit layers 230. For example, the second circuit structure 23 includes at least one second dielectric layer 231 formed on the insulating layer 221, and a second circuit layer 230 formed on the second dielectric layer 231, so that the second circuit layer 230 is electrically connected to the wiring layer 20.

[0083] Furthermore, the second circuit layer 230 is a circuit redistribution layer (RDL) specification, and its line width / line spacing is about 2 / 2 to 5 / 5um micrometers (um), and the material forming the second dielectric layer 231 is poly (p-oxadiazole benzene) (PBO), polyimide (PI), prepreg (PP) with glass fiber or other dielectric materials. For example, the material forming the second dielectric layer 231 is polyimide (PI), and its CTE is 30-35ppm / ℃, so that the material of the second dielectric layer 231 is different from the material of the first dielectric layer 211 and the insulating layer 221.

[0084] like Figure 2E As shown, at least one electronic component 40, 41, 42, 43 is disposed on the second circuit structure 23, so that the electronic component 40, 41, 42, 43 is electrically connected to the second circuit layer 230. In addition, a packaging colloid (not shown) covering the electronic components 40, 41, 42, 43 may also be formed.

[0085] In the present embodiment, the electronic component 40 is an active component, a passive component or a combination of the two, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor or an inductor. For example, if the electronic component 40 is a semiconductor chip, it has an active surface 40a and an inactive surface 40b opposite to each other, and the active surface 40a has a plurality of electrode pads 400, which are electrically connected to the second circuit layer 230 through a plurality of conductive bumps 44 with the active surface 40a facing downward (such as a flip chip method); or, the electronic component 40 can also be electrically connected to the second circuit layer 230 by a plurality of welding wires (not shown) in a wire bonding manner; or, the electronic component 40 can directly contact the second circuit layer 230. However, the method for electrically connecting the electronic component 40 to the second circuit layer 231 is not limited to the above.

[0086] Furthermore, the electronic components 41, 42, 43 may also be electronic components of different types. For example, an electronic component 41 such as a control chip is disposed on the package substrate 2a through a plurality of conductive bumps 44, and at least one electronic component 42, 43 of a high bandwidth memory (HBM) chip is stacked thereon, and the electronic component 41 is electrically connected to the second circuit layer 230.

[0087] In addition, the two opposite sides of the package substrate 2a have different uses. For example, the second circuit structure 23 is used as a die placement side for receiving a semiconductor chip, and the first circuit structure 21 is used as a ball implantation side for receiving a circuit board, so the outermost first circuit layer 210 of the first circuit structure 21 can be combined with a plurality of external components 27 such as solder balls to connect an electronic device such as a circuit board (not shown).

[0088] In addition, the ball implantation side of the package substrate 2a can also be configured with electronic components, such as passive components 45, as required.

[0089] Therefore, the manufacturing method of the present invention replaces the existing silicon board with the ABF insulating layer 221, and utilizes the wiring layers 20, 220 as the medium for signal transmission between the electronic components 40, 41, 42, 43 and the circuit board. Therefore, there is no need to manufacture the processes related to conductive silicon vias and C4 specification conductive components of the existing silicon interposer, thereby greatly reducing the process difficulty and manufacturing cost.

[0090] Furthermore, by directly contacting and connecting the first circuit layer 210 and the wiring layer 220 (i.e., electrically conducting the conductor plated in the laser blind hole), the conduction of the existing C4 specification conductive element is replaced, so that the conductive performance and heat dissipation performance of the packaging substrate 2a are greatly improved compared to the existing packaging substrate.

[0091] Furthermore, by embedding the wiring layer 20 in the insulating layer 221 and adopting a coreless design of the first circuit structure 21 and the wiring structure 22 to replace the existing silicon interposer, the thickness of the package substrate 2a is reduced to meet the thinning requirement.

[0092] In addition, the arrangement of the dielectric layers of the package substrate 2a is gradually increased or decreased according to the CTE value to avoid the problem of warping of the package substrate 2a. Figure 2EAs shown in the bottom-up direction, the CTE of the first dielectric layer 211 is the smallest, and the CTE of the second dielectric layer 231 is the largest. Therefore, when performing subsequent thermal processes such as reflow soldering of the external component 27 or reflow soldering of the conductive bump 44, the packaging substrate can be effectively prevented from warping, so as to avoid the external component 27 (or the conductive bump 44) from peeling off, cracking, shifting, or other conditions that affect the yield.

[0093] In addition, by using ABF as the insulating layer 221 and the wiring layer 20 embedded in the insulating layer 221, it is convenient to adopt the RDL process to manufacture the second circuit layer 230, so that the second circuit layer 230 can meet the requirements of high-density fine lines / fine pitches and reduce the risk of the second circuit layer 230 and the wiring structure 22 being separated (peeled).

[0094] FIG. 3A to FIG. 3D 1 is a cross-sectional view of a second embodiment of the method for manufacturing an electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the form of the package substrate 3a, so the same points will not be described in detail below.

[0095] like Figure 3A As shown, a core board 30 is provided, which has a first surface 30a and a second surface 30b relative to each other, and internal circuit layers 301, 302 are arranged on the first surface 30a and the second surface 30b of the core board 30, and the core board 30 has a plurality of conductive through holes 300 connecting the first surface 30a and the second surface 30b, so that the conductive through holes 300 are electrically connected to the internal circuit layers 301, 302.

[0096] In this embodiment, the core board 30 may be an organic polymer board or other board including Bismaleimide triazine (BT), glass fiber prepreg (PP), and the conductive through hole 300 is a hollow column, which can be filled with plugging material 300a in the hollow, wherein the plugging material 300a is of various types, such as conductive glue, ink, etc., and is not particularly limited. It should be understood that in other embodiments, the conductive through hole 300 may also be a solid metal column without filling the plugging material 300a.

[0097] Furthermore, first circuit structures 31a, 31b are formed on the first surface 30a and the second surface 30b of the core board 30, respectively. The first circuit structures 31a, 31b include at least one first dielectric layer 311 formed on the core board 30, and a first circuit layer 310 formed on the first dielectric layer 311, so that the first circuit layer 310 is electrically connected to the inner circuit layers 301, 302. For example, the first circuit structures 31a, 31b are manufactured by a build-up method, and the first dielectric layer 311 is made of dielectric materials such as polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0098] like Figure 3B As shown, a patterning process is performed to form a wiring structure 32 on the first circuit structure 31 a on one surface (eg, the first surface 30 a ) of the core board 30 .

[0099] In this embodiment, each of the wiring structures 32 is defined with a first side 32 a and a second side 32 b opposite to each other, and the wiring structure 32 is connected to the first circuit structure 31 a at the first side 32 a thereof.

[0100] Furthermore, the wiring structure 32 includes at least one insulating layer 321 and a wiring layer 320 formed on the insulating layer 321, so that the wiring layer 320 is electrically connected to the first circuit layer 310. For example, the material forming the insulating layer 321 is Ajinomoto build-up film (ABF), and the wiring layer 320 is made into a patterned circuit by electroplating metal (such as copper) or other methods. It should be understood that by using the build-up process method, the wiring structures 32 can add multiple layers of the insulating layer 321 according to needs to make a multi-layer wiring layer 320.

[0101] In addition, the wiring structure 32 forms another insulating layer 322 on the outermost wiring layer 320 to make the wiring layer 320 flush with the insulating layer 322 and expose the wiring layer 320 outside the insulating layer 322 .

[0102] like Figure 3C As shown, a second circuit structure 33 is formed on the second side 32 b of the wiring structure 32 to form an asymmetric packaging substrate 3 a , and the wiring layer 320 is electrically connected to the second circuit structure 33 .

[0103] In this embodiment, the second wiring structure 33 may be formed by a build-up method on the second side 32b of the wiring structure 32. For example, the second wiring structure 33 includes at least one second dielectric layer 331 formed on the insulating layer 321, and a second wiring layer 330 formed on the second dielectric layer 331, so that the second wiring layer 330 is electrically connected to the wiring layer 320.

[0104] Furthermore, the second circuit layer 330 is a circuit redistribution layer (RDL) specification, and the material forming the second dielectric layer 331 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP) with glass fiber, or other dielectric materials. For example, the material forming the second dielectric layer 331 is polyimide (PI), so that the material of the second dielectric layer 331 is different from the material of the first dielectric layer 311 and the insulating layer 321.

[0105] like Figure 3D As shown, at least one electronic component 40, 41, 42, 43 is disposed on the second circuit structure 33, so that the electronic component 40, 41, 42, 43 is electrically connected to the second circuit layer 330. In addition, a packaging colloid (not shown) covering the electronic components 40, 41, 42, 43 may also be formed.

[0106] In this embodiment, the two opposite sides of the package substrate 3a have different uses. For example, the second circuit structure 33 is used as a die placement side for receiving a semiconductor chip, and the first circuit structure 31b is used as a ball implantation side for receiving a circuit board. Therefore, the outermost first circuit layer 310 of the first circuit structure 31b can be combined with a plurality of external components 29 such as solder balls to connect an electronic device such as a circuit board (not shown).

[0107] Therefore, the manufacturing method of the present invention replaces the existing silicon board with the ABF insulating layer 321, and uses the wiring layer 320 as a medium for signal transmission between the electronic components 40, 41, 42, 43 and the circuit board. Therefore, there is no need to manufacture the processes related to conductive silicon vias and C4 specification conductive components of the existing silicon interposer, thereby greatly reducing the process difficulty and manufacturing cost.

[0108] Furthermore, by directly contacting and connecting the first circuit layer 310 and the wiring layer 320 (i.e., electrically conducting the conductor plated in the laser blind hole), the conduction of the existing C4 specification conductive element is replaced, so that the conductive performance and heat dissipation performance of the packaging substrate 3a are greatly improved compared to the existing packaging substrate.

[0109] Furthermore, by directly combining the wiring structure 32 with the first circuit structure 31 a , the existing C4 specification conductive element is not required, so the thickness of the packaging substrate 2 a is reduced to meet the requirement of thinning.

[0110] In addition, the arrangement of the dielectric layers of the packaging substrate 3 a is gradually increased or decreased according to the CTE value, so as to avoid the problem of warping of the packaging substrate 3 a.

[0111] In addition, by using ABF as the insulating layer 321, it is convenient to adopt the RDL process to manufacture the second circuit layer 330, so that the second circuit layer 330 can meet the requirements of high-density fine circuits / fine spacing.

[0112] The present invention also provides a packaging substrate 2a, 3a, comprising: a wiring structure 22, 32, a first circuit structure 21, 31a, and a second circuit structure 23, 33.

[0113] The wiring structures 22, 32 have opposite first sides 22a, 32a and second sides 22b, 32b, wherein the wiring structures 22, 32 include at least one insulating layer 221, 321, 322 and wiring layers 220, 320 disposed on the insulating layers 221, 321, 322, and the material forming the insulating layers 221, 321, 322 is Ajinomoto build-up film.

[0114] The first circuit structure 21, 31a is arranged on the first side 22a, 32a of the wiring structure 22, 32, wherein the first circuit structure 21, 31a includes at least one first dielectric layer 211, 311 formed on the insulating layer 221, 321 and a first circuit layer 210, 310 arranged on the first dielectric layer 211, 311 and electrically connected to the wiring layer 220, 320, and the material forming the first dielectric layer 211, 311 is different from the material forming the insulating layer 221, 321, 322.

[0115] The second circuit structure 23, 33 is arranged on the second side 22b, 32b of the wiring structure 22, 32, wherein the second circuit structure 23, 33 includes at least one second dielectric layer 231, 331 formed on the insulating layer 221, 322 and a second circuit layer 230, 330 arranged on the second dielectric layer 231, 331 and electrically connected to the wiring layer 220, 320, and the material forming the second dielectric layer 231, 331 is different from the material forming the insulating layer 221, 321, 322.

[0116] In one embodiment, the first dielectric layer 211 , 311 and the second dielectric layer 231 , 331 are made of different materials.

[0117] In one embodiment, the first circuit structure 31a is bonded to a core board 30, and the core board 30 has a first surface 30a and a second surface 30b relative to each other, so that the first circuit structure 31a is bonded to the first surface 30a of the core board 30, and the core board 30 has a plurality of conductive through holes 300 connecting the first and second surfaces 30a, 30b, so that the conductive through holes 300 are electrically connected to the first circuit layer 310.

[0118] The present invention further provides an electronic package 2, 3, comprising: the aforementioned package substrate 2a, 3a, and electronic components 40, 41, 42, 43 disposed on the second circuit structure 23, 33 and electrically connected to the second circuit layer 230, 330.

[0119] In one embodiment, the electronic package 2 , 3 further includes an external component 27 formed on the first circuit structure 21 , 31 b and electrically connected to the first circuit layer 210 , 310 .

[0120] In summary, the electronic package and its packaging substrate and manufacturing method of the present invention use ABF as an insulating layer to replace the existing silicon board, and use the wiring layer as a medium for signal transmission between the electronic components and the circuit board. Therefore, the present invention does not need to manufacture the processes related to conductive silicon vias and C4 specification conductive components of the existing silicon interposer, thereby greatly reducing the process difficulty and manufacturing cost, and the conductive performance and heat dissipation performance of the packaging substrate are greatly improved.

[0121] Furthermore, by directly connecting the wiring structure to the first circuit structure, the existing silicon interposer and C4 standard conductive element are replaced, so that the thickness of the package substrate can be reduced to meet the thinning requirement.

[0122] In addition, the arrangement of the dielectric layers of the package substrate is gradually increased or decreased according to the CTE value, so as to avoid the problem of warping of the package substrate in subsequent processes.

[0123] In addition, by using ABF as the insulating layer, it is convenient to adopt the RDL process to manufacture the second circuit structure, so that the second circuit layer can meet the requirements of high-density fine circuits / fine pitches and reduce the risk of separation between the second circuit structure and the wiring structure.

[0124] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Anyone skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A packaging substrate, include: A wiring structure having a first side and a second side opposite to each other, wherein the wiring structure comprises at least one insulating layer and a wiring layer disposed on the insulating layer, and the insulating layer is formed of a material of a miso build-up film; A first circuit structure is disposed on a first side of the wiring structure, wherein the first circuit structure comprises at least a first dielectric layer formed on the insulating layer and a first circuit layer disposed on the first dielectric layer and electrically connected to the wiring layer, and the material forming the first dielectric layer is a prepreg; and A second circuit structure is disposed on a second side of the wiring structure, wherein the second circuit structure comprises at least a second dielectric layer formed on the insulating layer and a second circuit layer disposed on the second dielectric layer and electrically connected to the wiring layer, and the material forming the second dielectric layer is polyimide; Among them, the second circuit structure is used as the die placement side for connecting the semiconductor chip, and the first circuit structure is used as the ball planting side for connecting the circuit board. The first dielectric layer, the insulating layer and the second dielectric layer are arranged according to the size of the thermal expansion coefficient. The thermal expansion coefficient of the first dielectric layer is the smallest, and the thermal expansion coefficient of the second dielectric layer is the largest.

2. The packaging substrate according to claim 1, in, The first circuit structure is bonded to a core board having a first surface and a second surface relative to each other, so that the first circuit structure is bonded to the first surface of the core board, and the core board has a plurality of conductive through holes connecting the first surface and the second surface, so that the conductive through holes are electrically connected to the first circuit layer.

3. An electronic package, include: The packaging substrate according to any one of claims 1 to 2; as well as The electronic component is disposed on the second circuit structure and electrically connected to the second circuit layer.

4. The electronic package as claimed in claim 3, in, The electronic package also includes an external component formed on the first circuit structure and electrically connected to the first circuit layer.

5. A method for manufacturing a packaging substrate, include: A wiring structure is formed on a carrier, wherein the wiring structure has a first side and a second side opposite to each other, so that the wiring structure is combined with the carrier by its second side, wherein the wiring structure comprises at least one insulating layer and a wiring layer disposed on the insulating layer, and the insulating layer is formed of a material of a glutinous rice flour build-up film; Forming a first circuit structure on the first side of the wiring structure, wherein the first circuit structure comprises at least one first dielectric layer formed on the insulating layer and a first circuit layer disposed on the first dielectric layer and electrically connected to the wiring layer, and the material forming the first dielectric layer is a prepreg; removing the carrier to expose the second side of the wiring structure; and Forming a second circuit structure on the second side of the wiring structure, wherein the second circuit structure comprises at least a second dielectric layer formed on the insulating layer and a second circuit layer disposed on the second dielectric layer and electrically connected to the wiring layer, and the material forming the second dielectric layer is polyimide; Among them, the second circuit structure is used as the die placement side for connecting the semiconductor chip, and the first circuit structure is used as the ball planting side for connecting the circuit board. The first dielectric layer, the insulating layer and the second dielectric layer are arranged according to the size of the thermal expansion coefficient. The thermal expansion coefficient of the first dielectric layer is the smallest, and the thermal expansion coefficient of the second dielectric layer is the largest.

6. A method for manufacturing a packaging substrate, include: Providing a core board having a first surface and a second surface opposite to each other, and the core board having a plurality of conductive through holes connecting the first surface and the second surface; Forming a first circuit structure on the first surface of the core board, wherein the first circuit structure includes at least one first dielectric layer formed on the core board and a first circuit layer disposed on the first dielectric layer and electrically connected to the conductive via, and the material forming the first dielectric layer is a prepreg; A wiring structure is formed on the first circuit structure, and the wiring structure has a first side and a second side opposite to each other, so that the wiring structure is combined with the first circuit structure by its first side, wherein the wiring structure includes at least one insulating layer formed on the first dielectric layer and a wiring layer disposed on the insulating layer, and the material forming the insulating layer is a glutinous rice flour build-up film; and Forming a second circuit structure on the second side of the wiring structure, wherein the second circuit structure comprises at least a second dielectric layer formed on the insulating layer and a second circuit layer disposed on the second dielectric layer and electrically connected to the wiring layer, and the material forming the second dielectric layer is polyimide; Among them, the second circuit structure is used as the die placement side for connecting the semiconductor chip, and the first circuit structure is used as the ball planting side for connecting the circuit board. The first dielectric layer, the insulating layer and the second dielectric layer are arranged according to the size of the thermal expansion coefficient. The thermal expansion coefficient of the first dielectric layer is the smallest, and the thermal expansion coefficient of the second dielectric layer is the largest.

7. A method for manufacturing an electronic package, include: Providing a packaging substrate as claimed in claim 1; as well as The electronic element is arranged on the second circuit structure, and the electronic element is electrically connected to the second circuit layer.

8. The method for manufacturing an electronic package as claimed in claim 7, in, The manufacturing method further includes forming an external element on the first circuit structure, and the external element is electrically connected to the first circuit layer.

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