Signal modulation circuit for solid state electronic devices and circuit comprising the same

Abstract

A circuit includes first and second solid state electronic devices arranged in a bridge leg configuration. Each of the first and second solid state electronic devices can selectively operate as a control switch and a synchronization switch, respectively, and can selectively operate in an on state and an off state, respectively. The circuit further includes a driver circuit and a signal modulation circuit. The driver circuit is operably connected with at least the first solid state electronic device for controlling at least operation of the first solid state electronic device. The signal modulation circuit is operably connected with or between the driver circuit and the first solid state electronic device. The signal modulation circuit includes an input operably connected with the driver circuit, an output operably connected with the first solid state electronic device, and a variable resistance circuit operably connected between the input and the output and operably connected with the driver circuit. A resistance of the variable resistance circuit can be adjusted by the driver circuit to prevent misoperation of the first solid state electronic device.

Description

Technical Field

[0001] This invention relates to a signal modulation circuit for solid-state electronic devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). The invention also relates to circuits incorporating this signal modulation circuit. Background Technology

[0002] In existing power electronic systems (such as low-power DC / DC converters with synchronous rectification and high-power multilevel systems), circuits employing a bridge-leg configuration for switching devices can be found. A basic version of the bridge-leg configuration can be constructed by connecting two switching devices in series. These two switching devices can switch alternately, introducing a dead time to prevent breakdown. Depending on the current direction at the midpoint of the bridge arm, each switching device operates accordingly as either a control switch or a synchronous switch.

[0003] Crosstalk can occur when the control switch is turned on and the synchronous switch is turned off due to parasitic elements and circuit layout of the switching device. The basic mechanism using a solid-state electronic device with gate, source, and drain as the switching device is as follows: First, after the control switch is turned on, the drain-source voltage of the synchronous switch rises sharply. A displacement current is induced and injected into the gate of the synchronous switch (through the gate-source capacitance). Then, when the synchronous switch transitions to the blocking state, its drain current decreases sharply. A negative voltage is induced across the inductance associated with the source of the synchronous switch (e.g., the source inductance of the switch and the inductance of the printed circuit board traces). This phenomenon can cause undesirable parasitic voltage pulses in the gate-source voltage of the synchronous switch, which can lead to false triggering and excessive switching losses, network oscillations, and / or intermittent breakdown.

[0004] Existing techniques for solving crosstalk effects can be divided into two main approaches.

[0005] The first method is based on limiting the amplitude of a parasitic voltage pulse to the gate-source voltage. Since the induced voltage can be... To approximate, where R g C is the gate resistance. gd It is the gate-drain capacitance, and The rate of change of the gate-source voltage for a synchronous switch can be reduced in several ways, such as by using a small off-state gate resistor, connecting a capacitor or diode in parallel across the gate resistor, or by using a bipolar junction transistor (BJT) or a metal-oxide-semiconductor field-effect transistor (MOSFET) to introduce a low-impedance path between the gate and source during turn-off. The gate drive circuit is designed with worst-case operating conditions in mind.

[0006] The second approach is based on superimposing a negative offset voltage onto the gate-source voltage to counteract the effects of parasitic voltage pulses. Existing methods for generating this negative offset voltage include using an additional voltage source for the totem-pole driver output, passive circuitry, active circuitry, or charge pump circuitry. However, high negative gate-source voltages can shorten the lifespan of switching devices. For silicon carbide (SiC) MOSFETs, the gate oxide layer is relatively thin. If a SiC MOSFET is subjected to a high negative gate-source voltage, the electric field within the gate oxide and between the drain and source will increase. Additionally, during reverse conduction, the forward voltage drop of the body diode increases with increasing voltage amplitude. Some existing multilevel gate drive techniques can counteract the effects of parasitic voltage pulses and keep the static negative gate-source voltage stress low, thereby reducing the forward voltage drop of the body diode. However, they generally require additional power supplies, fast switching devices, etc. Summary of the Invention

[0007] Some embodiments of the present invention aim to address one or more of the aforementioned needs. Some embodiments of the present invention aim to overcome or improve one or more of the aforementioned disadvantages. Some embodiments of the present invention aim, more generally, to provide signal modulation circuitry for solid-state electronic devices. Some embodiments of the present invention may include one or more objectives not specifically described or explained.

[0008] In a first aspect, the present invention provides a circuit comprising a first solid-state electronic device and a second solid-state electronic device arranged in a bridge arm configuration, and a driver circuit operatively connected at least to the first solid-state electronic device for at least controlling the operation of the first solid-state electronic device. Each of the first and second solid-state electronic devices is selectively operable as a control switch and a synchronous switch, respectively, and is selectively operable in an ON state and an OFF state, respectively. The circuit further includes a signal modulation circuit operatively connected to or between the driver circuit and the first solid-state electronic device. The signal modulation circuit includes: an input operatively connected to the driver circuit, an output operatively connected to the first solid-state electronic device, and a variable resistor circuit operatively connected between the input and the output and operatively connected to the driver circuit. The resistance of the variable resistor circuit can be adjusted by the driver circuit to prevent malfunction of the first solid-state electronic device. In other words, the driver circuit is operable to adjust the resistance of the variable resistor circuit to prevent malfunction of the first solid-state electronic device. The circuit may include additional circuit components, such as additional solid-state electronic devices (one or more). The driver circuitry may be further operatively connected to one or more additional solid-state electronic devices (e.g., a second solid-state electronic device) to further control its operation. In some embodiments, signal modulation circuitry may be considered part of the driver circuitry.

[0009] In some embodiments, the signal modulation circuit is a first signal modulation circuit and the variable resistor circuit is a first variable resistor circuit, and the circuit further includes a second signal modulation circuit. The second signal modulation circuit is operatively connected to or between the driver circuit and the second solid-state electronic device. The second signal modulation circuit includes: an input operatively connected to the driver circuit, an output operatively connected to the second solid-state electronic device, and a second variable resistor circuit operatively connected between the input and output of the second signal modulation circuit and operatively connected to the driver circuit. The resistance of the second variable resistor circuit can be adjusted by the driver circuit to prevent malfunction of the second solid-state electronic device. In other words, the driver circuit is also operable to adjust the resistance of the second variable resistor circuit to prevent malfunction of the second solid-state electronic device. In some embodiments, the second signal modulation circuit may be considered part of the driver circuit.

[0010] Optionally, the resistance of the variable resistor circuit is adjusted by the driver circuit to affect the signal at the output of the signal modulation circuit, thereby preventing the first solid-state electronic device from being falsely activated (changed to the on state) when or only when the first solid-state electronic device is in the off state. Alternatively, the resistance of the variable resistor circuit is adjusted by the driver circuit to affect the signal at the output of the signal modulation circuit, thereby preventing the first solid-state electronic device from being falsely activated (changed to the on state) when or only when the first solid-state electronic device operates as a synchronous switch and is in the off state.

[0011] Optionally, the resistance of the variable resistor circuit can be adjusted by the driver circuit to affect the signal (e.g., voltage signal) at the output of the signal modulation circuit, thereby preventing malfunction of the first solid-state electronic device.

[0012] In some implementations, the resistance of the variable resistor circuit can be adjusted in a stepped manner by the driver circuit. In other implementations, the resistance of the variable resistor circuit can be adjusted in a stepless manner by the driver circuit.

[0013] Optionally, the resistance of the second variable resistor circuit is adjusted by the driver circuit to affect the signal at the output of the second signal modulation circuit, thereby preventing the second solid-state electronic device from being falsely activated (changed to the on state) when or only when the second solid-state electronic device is in the off state. Alternatively, the resistance of the second variable resistor circuit is adjusted by the driver circuit to affect the signal at the output of the second signal modulation circuit, thereby preventing the second solid-state electronic device from being falsely activated (changed to the on state) when or only when the second solid-state electronic device operates as a synchronous switch and is in the off state.

[0014] Optionally, the resistance of the variable resistor circuit can be adjusted by the driver circuit to affect the signal (e.g., voltage signal) at the output of the second signal modulation circuit, thereby preventing malfunction of the second solid-state electronic device.

[0015] In some embodiments, the resistance of the second variable resistor circuit can be adjusted in steps by the driver circuit. In some embodiments, the resistance of the second variable resistor circuit can be adjusted steplessly by the driver circuit.

[0016] Optionally, the first solid-state electronic device includes a field-effect transistor having a gate, a drain, and a source. Optionally, the field-effect transistor includes a MOSFET. In some embodiments, the MOSFET is a SiC MOSFET.

[0017] Optionally, the second solid-state electronic device includes a field-effect transistor having a gate, a drain, and a source. Optionally, the field-effect transistor includes a MOSFET. In some embodiments, the MOSFET is a SiC MOSFET. The types of the first solid-state electronic device and the second solid-state electronic device can be the same or different.

[0018] Optionally, the driver circuit includes a gate drive circuit for the field-effect transistor (first solid-state electronic device), and a signal modulation circuit is operatively connected between the gate drive circuit and the field-effect transistor (first solid-state electronic device).

[0019] Optionally, the gate driving circuit is a first gate driving circuit, and the driver circuit further includes a second gate driving circuit for the field-effect transistor (second solid-state electronic device), and the signal modulation circuit is operatively connected between the gate driving circuit and the field-effect transistor (second solid-state electronic device).

[0020] Optionally, the output of the signal modulation circuit is directly or indirectly connected across the gate and source terminals of the field-effect transistor (the first solid-state electronic device).

[0021] Optionally, the output of the second signal modulation circuit is directly or indirectly connected across the gate and source terminals of the field-effect transistor (second solid-state electronic device).

[0022] Optionally, the driver circuitry further includes a detector circuit operable to detect the gate-source voltage of the field-effect transistor (first solid-state electronic device). Optionally, the driver circuitry also includes a control circuit operable to compare the detected gate-source voltage with a reference voltage and, based on the comparison, provide a control signal for controlling the resistance of the variable resistor circuitry. The reference voltage may be fixed or adjustable (e.g., adjusted by or via the control circuitry).

[0023] The resistance of the variable resistor circuit can affect the gate-source voltage of the field-effect transistor (the first solid-state electronic device). The resistance of the second variable resistor circuit can affect the gate-source voltage of the field-effect transistor (the second solid-state electronic device).

[0024] Optionally, the control circuit is arranged to provide a control signal during circuit operation, when or only when the first solid-state electronic device is in an off state. In some embodiments, the control circuit may also be arranged to provide a control signal during circuit operation when the first solid-state electronic device is in an on state. Optionally, the control circuit is arranged to provide a control signal during circuit operation, when or only when the first solid-state electronic device operates as a synchronous switch and is in an off state. In some embodiments, the control circuit may also be arranged to provide a control signal during circuit operation when the first solid-state electronic device operates as a synchronous switch and is in an on state.

[0025] Optionally, the detector circuitry includes an amplifier operatively connected to the gate and source of a field-effect transistor (a first solid-state electronic device).

[0026] Optionally, the control circuitry includes: a comparator operatively connected to the amplifier for comparing the detected gate-source voltage with a reference voltage, and a controller operatively connected to the comparator for providing a control signal.

[0027] Optionally, the control circuit further includes a latch circuit operatively connected to or between the comparator and the controller. The latch circuit is configured to be in a first state when it is determined that the detected gate-source voltage is greater than a reference voltage, and in a second state when it is determined that the detected gate-source voltage is less than the reference voltage. Optionally, the controller is arranged to detect the state of the latch circuit and provide a control signal based on the detected state of the latch circuit. In some embodiments, the first state may be high (level) and the second state may be low (level). In some embodiments, the first state may be low (level) and the second state may be high (level).

[0028] Optionally, the controller is configured to detect the state of the latching circuit and provide a control signal when or only when the first solid-state electronic device is in the off state. Alternatively, the controller is configured to detect the state of the latching circuit and provide a control signal when or only when the first solid-state electronic device operates as a synchronous switch and is in the off state.

[0029] Optionally, the controller is arranged to repeatedly (e.g., periodically) detect the state of the latch circuit and provide continuous control signals to dynamically or adaptively adjust the resistance of the variable resistor circuit.

[0030] Optionally, the controller is arranged to repeatedly (e.g., periodically) detect the state of the latching circuit and provide continuous control signals to dynamically or adaptively adjust the resistance of the variable resistor circuit when or only when the first solid-state electronic device is in the off state. Alternatively, the controller is arranged to repeatedly (e.g., periodically) detect the state of the latching circuit and provide continuous control signals to dynamically or adaptively adjust the resistance of the variable resistor circuit when or only when the first solid-state electronic device operates as a synchronous switch and is in the off state.

[0031] Optionally, the controller is configured to: provide a first control signal for decreasing the resistance of the variable resistor circuit when the latch circuit is detected to be in a first state, and provide a second control signal (different from the first control signal) for increasing the resistance of the variable resistor circuit when the latch circuit is detected to be in a second state.

[0032] Optionally, the first control signal is configured to reduce the resistance of the variable resistor circuit by a predetermined amount. This predetermined amount can be fixed or adjustable.

[0033] Optionally, the second control signal is configured to increase the resistance of the variable resistor circuit by a predetermined amount. This predetermined amount can be fixed or adjustable.

[0034] Optionally, the driver circuit also includes another detector circuit and another control circuit for the field-effect transistor (the second solid-state electronic device), which are similar to or the same as the detector circuit and control circuit for the field-effect transistor (the first solid-state electronic device) (preferably having one or more of the features described above).

[0035] Optionally, the variable resistor circuit includes a rheostat that can be controlled by a driver circuit to adjust the resistance.

[0036] Optionally, the rheostat may include a digital rheostat.

[0037] Optionally, the signal modulation circuit includes: a first resistor-capacitor circuit, a second resistor-capacitor circuit, and a diode circuit. The variable resistor circuit is part of the second resistor-capacitor circuit. Optionally, the diode circuit is connected between the first resistor-capacitor circuit and the second resistor-capacitor circuit.

[0038] The first resistor-capacitor circuit may include one or more resistors and one or more capacitors connected in parallel with the resistors. In one example, the first resistor-capacitor circuit consists of only a single capacitor and a single resistor connected in parallel with the single capacitor.

[0039] A diode circuit may include one or more diodes. In one example, the diode circuit consists of only a single diode.

[0040] The second resistor-capacitor circuit may include one or more resistors, one or more capacitors connected in parallel with the one or more resistors, and a variable resistor connected in parallel with the one or more capacitors. In one example, the second resistor-capacitor circuit consists only of a first resistor, a second resistor, a variable resistor, and a single capacitor, wherein the first resistor and the variable resistor are connected in series, the second resistor and the single capacitor are connected in parallel, and a combination of the first resistor and the variable resistor is connected in parallel with the second resistor and the single capacitor, respectively.

[0041] Optionally, the second variable resistor circuit may have the same or similar structure as the variable resistor circuit.

[0042] Optionally, the circuit also includes a processor for determining the health status of the first solid-state electronic device, particularly the health status of its gate oxide, based on the resistance of the variable resistor circuit. Optionally, the processor can also determine the health status of the second solid-state electronic device, particularly the health status of its gate oxide, based on the resistance of the second variable resistor circuit.

[0043] Optionally, the circuit further includes a monitoring device or circuit for monitoring the resistance change of the variable resistor circuit over time, and the processor is arranged to determine the health status of the first solid-state electronic device, particularly the health status of its gate oxide, based on the monitored resistance change of the variable resistor circuit over time. In one example, the processor may compare the monitored resistance values ​​(one or more) with predetermined values, thresholds, or patterns stored, for example, in a lookup table, to determine the health status of the first solid-state electronic device, particularly the health status of its gate oxide. Optionally, the monitoring device or circuit may also monitor the resistance change of the second variable resistor circuit over time, and the processor is also arranged to determine the health status of the second solid-state electronic device, particularly the health status of its gate oxide, based on the monitored resistance change of the second variable resistor circuit over time. In one example, the processor may compare the monitored resistance values ​​(one or more) with predetermined values, thresholds, or patterns stored, for example, in a lookup table, to determine the health status of the second solid-state electronic device, particularly the health status of its gate oxide.

[0044] Optionally, the circuit may include either a converter circuit or an inverter circuit, comprising a first solid-state electronic device and a second solid-state electronic device. For example, the converter circuit may be a synchronous buck converter circuit, a half-bridge converter circuit, a full-bridge converter circuit, etc. For example, the inverter circuit may be a half-bridge inverter circuit or a full-bridge inverter circuit.

[0045] Secondly, the present invention provides a signal modulation circuit in the circuit of the first aspect. The signal modulation circuit may be provided separately from other parts of the circuit.

[0046] Thirdly, the present invention provides a signal modulation circuit and a driver circuit in the circuit of the first aspect. The signal modulation circuit and the driver circuit can be provided separately from other parts of the circuit. The signal modulation circuit and the driver circuit can be arranged at least partially on an integrated circuit.

[0047] In a fourth aspect, the present invention provides a signal modulation circuit for a solid-state electronic device for use in a circuit. The circuit includes a first solid-state electronic device and a second solid-state electronic device arranged in a bridge arm configuration, and a driver circuit operatively connected at least to the first solid-state electronic device for at least controlling the operation of the first solid-state electronic device. Each of the first and second solid-state electronic devices is selectively operable as a control switch and a synchronization switch, respectively, and is selectively operable in an on-state and an off-state, respectively. The signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device. The signal modulation circuit includes an input operatively connected to the driver circuit, an output operatively connected to the first solid-state electronic device, and a variable resistor circuit operatively connected between the input and the output and operatively connected to the driver circuit. When the signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device, the resistance of the variable resistor circuit can be adjusted by the driver circuit to prevent malfunction of the first solid-state electronic device. In other words, when the signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device, the driver circuit is operable to adjust the resistance of the variable resistor circuit to prevent malfunction of the first solid-state electronic device. The circuit may include additional circuit components, such as additional solid-state electronic devices (one or more). The driver circuit may further be operatively connected to one or more additional solid-state electronic devices (e.g., a second solid-state electronic device) for controlling its operation.

[0048] Optionally, when the signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device: the resistance of the variable resistor circuit can be adjusted by the driver circuit to affect the signal at the output, thereby preventing the false activation (change to the on state) of the first solid-state electronic device when or only when the first solid-state electronic device is in the off state. Alternatively, when the signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device: the resistance of the variable resistor circuit can be adjusted by the driver circuit to affect the signal at the output, thereby preventing the false activation (change to the on state) of the first solid-state electronic device when or only when the first solid-state electronic device operates as a synchronous switch and is in the off state.

[0049] Optionally, when the signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device: the resistance of the variable resistor circuit can be adjusted by the driver circuit to affect the signal at the output (e.g., a voltage signal) thereby preventing malfunction of the first solid-state electronic device. In some embodiments, the resistance of the variable resistor circuit can be adjusted in a stepwise manner. In some embodiments, the resistance of the variable resistor circuit can be adjusted in a stepless manner.

[0050] Optionally, the first solid-state electronic device includes a field-effect transistor having a gate, a drain, and a source. Optionally, the field-effect transistor includes a MOSFET. In some embodiments, the MOSFET is a SiC MOSFET.

[0051] Optionally, the driver circuit includes a gate drive circuit for the field-effect transistor (first solid-state electronic device), and a signal modulation circuit is operatively connected between the gate drive circuit and the field-effect transistor (first solid-state electronic device).

[0052] Optionally, the output of the signal modulation circuit can be directly or indirectly connected across the gate and source terminals of the field-effect transistor (the first solid-state electronic device).

[0053] Optionally, the driver circuitry further includes a detector circuit operable to detect the gate-source voltage of the field-effect transistor (first solid-state electronic device). Optionally, the driver circuitry also includes a control circuit operable to compare the detected gate-source voltage with a reference voltage and, based on the comparison, provide a control signal for controlling the resistance of the variable resistor circuitry. The reference voltage may be fixed or adjustable (e.g., adjusted by or via the control circuitry).

[0054] The resistance of a variable resistor circuit can affect the gate-source voltage of a field-effect transistor (the first solid-state electronic device).

[0055] Optionally, when the signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device, the signal modulation circuit is operable to receive from the driver circuit a continuous control signal for dynamically or adaptively adjusting the resistance of the variable resistor circuit.

[0056] Optionally, when the signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device, the signal modulation circuit is operable to receive from the driver circuit: a first control signal for decreasing the resistance of the variable resistor circuit and a second control signal (different from the first control signal) for increasing the resistance of the variable resistor circuit. Optionally, the first control signal is arranged to decrease the resistance of the variable resistor circuit by a predetermined amount. This predetermined amount may be fixed or adjustable. Optionally, the second control signal is arranged to increase the resistance of the variable resistor circuit by a predetermined amount. This predetermined amount may be fixed or adjustable.

[0057] Optionally, the variable resistor circuit includes a rheostat that can be controlled by a driver circuit to adjust the resistance. Optionally, the rheostat includes a digital rheostat.

[0058] Optionally, the signal modulation circuit includes: a first resistor-capacitor circuit, a second resistor-capacitor circuit, and a diode circuit. The variable resistor circuit is part of the second resistor-capacitor circuit. Optionally, the diode circuit is connected between the first resistor-capacitor circuit and the second resistor-capacitor circuit.

[0059] The first resistor-capacitor circuit may include one or more resistors and one or more capacitors connected in parallel with the resistors. In one example, the first resistor-capacitor circuit consists of only a single capacitor and a single resistor connected in parallel with the single capacitor.

[0060] A diode circuit may include one or more diodes. In one example, the diode circuit consists of only a single diode.

[0061] The second resistor-capacitor circuit may include one or more resistors, one or more capacitors connected in parallel with the one or more resistors, and a variable resistor connected in parallel with the one or more capacitors. In one example, the second resistor-capacitor circuit consists only of a first resistor, a second resistor, a variable resistor, and a single capacitor, wherein the first resistor and the variable resistor are connected in series, the second resistor and the single capacitor are connected in parallel, and a combination of the first resistor and the variable resistor is connected in parallel with the second resistor and the single capacitor, respectively.

[0062] Optionally, the circuit may include either a converter circuit or an inverter circuit, comprising a first solid-state electronic device and a second solid-state electronic device. For example, the converter circuit may be a synchronous buck converter circuit, a half-bridge converter circuit, a full-bridge converter circuit, etc. For example, the inverter circuit may be a half-bridge inverter circuit or a full-bridge inverter circuit.

[0063] Other features and aspects of the invention will become apparent from consideration of the detailed description and accompanying drawings. Where appropriate and applicable, any one or more features described herein with respect to one aspect or embodiment may be combined with any one or more other features described herein with respect to any one or more other aspects or embodiments.

[0064] In this document, depending on the context, degree terms related to quantity or condition (e.g., “generally,” “approximately,” “about,” “roughly,” etc.) are used to consider at least one of the following: manufacturing tolerances, degradation, aging, trends, tendencies, imperfect realities, etc. In some examples, when degree terms (such as “about”) are used to modify numerical values, this expression may include the stated numerical value and its ±20%, ±15%, ±10%, ±5%, ±2%, or ±1%.

[0065] In this document, unless otherwise stated, the terms “connection,” “link,” “installation,” etc. are intended to cover direct and indirect, mechanical and / or electrical connections, linkages, installations, etc. Attached Figure Description

[0066] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, wherein:

[0067] Figure 1A This is a circuit diagram showing a test setup for short-circuit current stress testing of different SiC MOSFETs in one example;

[0068] Figure 1B This shows what was detected during the short-circuit current stress test. Figure 1A Circuit voltage v g and current i SC A graph of the waveform;

[0069] Figures 2A to 2G This is a graph showing the changes in the intrinsic parameters of different SiC MOSFETs before and after short-circuit current stress testing, where: Figure 2A The threshold voltage V is shown. th Changes, Figure 2B The on-resistance R is shown. ds,on Changes, Figure 2C The drain-source leakage current I is shown. dss Changes, Figure 2D The gate-source leakage current I is shown. gss Changes, Figure 2E The gate-source capacitance C is shown. gs Changes, Figure 2F The drain-source capacitance C is shown. ds The changes, and Figure 2G The gate-drain capacitance C is shown. gd Changes;

[0070] Figure 3 This is a circuit diagram illustrating a gate drive circuit with an adaptive level converter (including gate voltage detection) according to one embodiment of the present invention.

[0071] Figure 4A This shows the operation of switching device M1 in mode 1 (ON state). Figure 3 Voltage v in the gate drive circuit g ,v CN ,v CP ,v o,LS A graph of the waveform;

[0072] Figure 4B This shows the operation of switching device M1 in mode 2 (off state). Figure 3 Voltage v in the gate drive circuit g ,v CN ,v CP ,v o,LS A graph of the waveform;

[0073] Figure 5A This shows the operation of switching device M1 in mode 1 (ON state). Figure 3 The circuit diagram showing the operation of the gate drive circuit;

[0074] Figure 5B This shows the operation of switching device M1 in mode 2 (off state). Figure 3 The circuit diagram showing the operation of the gate drive circuit;

[0075] Figure 6 It is shown Figure 3 A flowchart of the control method for the gate drive circuit;

[0076] Figure 7A It is shown in Figure 3 The gate drive circuit uses different V REF The duty cycle d of the switching device M1 and the resistance R are related. v A diagram of the relationships;

[0077] Figure 7B It is shown in Figure 3 The gate drive circuit uses different R gss The duty cycle d of the switching device M1 and the resistance R are related. v A diagram of the relationships;

[0078] Figure 7C It is shown in Figure 3 The gate drive circuit uses different capacitors ΔC gsWhen the value (which connects the gate and source of switching device M1) is given, the duty cycle d of switching device M1 is related to the resistance R. v A diagram of the relationships;

[0079] Figure 8A A full-bridge inverter of one embodiment of the present invention is shown (which utilizes...) Figure 3 Circuit diagram of the level shifter (to switching device M2) of the gate drive circuit;

[0080] Figure 8B This illustrates a full-bridge inverter circuit (which includes) an embodiment of the present invention. Figure 3 A top view of a level shifter in a gate drive circuit;

[0081] Figure 8C This illustrates a full-bridge inverter circuit (which includes) an embodiment of the present invention. Figure 3 A bottom view image of a level converter in a gate drive circuit;

[0082] Figure 9A This illustrates the situation when the gate drive circuit is deactivated and capacitors ΔC of different values ​​are selectively connected between the gate and drain of the switching device M2. gd At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the turn-on waveform;

[0083] Figure 9B This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and drain of switching device M2. gd At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the conduction waveform;

[0084] Figure 9C This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and drain of switching device M2. gd At that time, the drain current i of switching device M2 d,2 A graph of the conduction waveform;

[0085] Figure 10A This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and drain of switching device M2. gd At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the turn-off waveform;

[0086] Figure 10BThis illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and drain of switching device M2. gd At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the off-waveform;

[0087] Figure 10C This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and drain of switching device M2. gd At that time, the drain current i of switching device M2 d,2 A graph of the off-waveform;

[0088] Figure 11A This illustrates when the gate drive circuit is activated and capacitors ΔC of different values ​​are selectively connected between the gate and drain of the switching device M2. gd At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the conduction waveform;

[0089] Figure 11B This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and drain of the switching device M2. gd At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the conduction waveform;

[0090] Figure 11C This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and drain of the switching device M2. gd At that time, the drain current i of switching device M2 d,2 A graph of the conduction waveform;

[0091] Figure 12A This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and drain of the switching device M2. gd At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the off-waveform;

[0092] Figure 12B This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and drain of the switching device M2. gd At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the off-waveform;

[0093] Figure 12C This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and drain of the switching device M2.gd At that time, the drain current i of switching device M2 d,2 A graph of the off-waveform;

[0094] Figure 13A This illustrates how resistors R are selectively connected between the gate and source of switching device M2 when the gate drive circuit is disabled. gss At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the conduction waveform;

[0095] Figure 13B This illustrates how resistors R are selectively connected between the gate and source of switching device M2 when the gate drive circuit is disabled. gss At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the conduction waveform;

[0096] Figure 13C This illustrates how resistors R are selectively connected between the gate and source of switching device M2 when the gate drive circuit is disabled. gss At that time, the drain current i of switching device M2 d,2 A graph of the conduction waveform;

[0097] Figure 14A This illustrates how resistors R are selectively connected between the gate and source of switching device M2 when the gate drive circuit is disabled. gss At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the off-waveform;

[0098] Figure 14B This illustrates how resistors R are selectively connected between the gate and source of switching device M2 when the gate drive circuit is disabled. gss At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the off-waveform;

[0099] Figure 14C This illustrates how resistors R are selectively connected between the gate and source of switching device M2 when the gate drive circuit is disabled. gss At that time, the drain current i of switching device M2 d,2 A graph of the off-waveform;

[0100] Figure 15A This illustrates that when the gate drive circuit is enabled and resistors R of different resistance values ​​are selectively connected between the gate and source of the switching device M2. gss At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the conduction waveform;

[0101] Figure 15B This illustrates that when the gate drive circuit is enabled and resistors R of different resistance values ​​are selectively connected between the gate and source of the switching device M2. gss At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the conduction waveform;

[0102] Figure 15C This illustrates that when the gate drive circuit is enabled and resistors R of different resistance values ​​are selectively connected between the gate and source of the switching device M2. gss At that time, the drain current i of switching device M2 d,2 A graph of the conduction waveform;

[0103] Figure 16A This illustrates that when the gate drive circuit is enabled and resistors R of different resistance values ​​are selectively connected between the gate and source of the switching device M2. gss At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the off-waveform;

[0104] Figure 16B This illustrates that when the gate drive circuit is enabled and resistors R of different resistance values ​​are selectively connected between the gate and source of the switching device M2. gss At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the off-waveform;

[0105] Figure 16C This illustrates that when the gate drive circuit is enabled and resistors R of different resistance values ​​are selectively connected between the gate and source of the switching device M2. gss At that time, the drain current i of switching device M2 d,2 A graph of the off-waveform;

[0106] Figure 17A This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and source of switching device M2. gs At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the conduction waveform;

[0107] Figure 17B This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and source of switching device M2. gs At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the conduction waveform;

[0108] Figure 17CThis illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and source of switching device M2. gs At that time, the drain current i of switching device M2 d,2 A graph of the conduction waveform;

[0109] Figure 18A This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and source of switching device M2. gs At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the off-waveform;

[0110] Figure 18B This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and source of switching device M2. gs At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the off-waveform;

[0111] Figure 18C This illustrates how, when the gate drive circuit is disabled and capacitors ΔC of different values ​​are selectively connected between the gate and source of switching device M2. gs At that time, the drain current i of switching device M2 d,2 A graph of the off-waveform;

[0112] Figure 19A This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and source of the switching device M2. gs At that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the conduction waveform;

[0113] Figure 19B This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different values ​​are selectively connected between the gate and source of the switching device M2,... gs At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the conduction waveform;

[0114] Figure 19C This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and source of the switching device M2. gs At that time, the drain current i of switching device M2 d,2 A graph of the conduction waveform;

[0115] Figure 20A This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and source of the switching device M2. gsAt that time, the gate-source voltage v of the switching device M2 gs,2 A graph of the off-waveform;

[0116] Figure 20B This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and source of the switching device M2. gs At that time, the drain-source voltage v of switching device M2 ds,2 A graph of the off-waveform;

[0117] Figure 20C This illustrates that when the gate drive circuit is enabled and capacitors ΔC of different capacitance values ​​are selectively connected between the gate and source of the switching device M2. gs At that time, the drain current i of switching device M2 d,2 A graph of the off-waveform;

[0118] Figure 21A This shows the gate-source voltage v during one line cycle of switching device M2 when the gate drive circuit is disabled. gs,2 and inverter output current i o A graph of the waveform;

[0119] Figure 21B This indicates when the inverter output current i o When the gate-source voltage v of the switching device M2 in control mode is approximately 2A and the gate drive circuit is disabled, gs,2 A graph of the waveform;

[0120] Figure 21C This indicates when the inverter output current i o The gate-source voltage v of the switching device M2 in control mode is approximately 10A and the gate drive circuit is disabled. gs,2 A graph of the waveform;

[0121] Figure 21D This indicates when the inverter output current i o The gate-source voltage v of the switching device M2 in synchronous mode is approximately 2A and the gate drive circuit is disabled. gs,2 A graph of the waveform;

[0122] Figure 21E This indicates when the inverter output current i o The gate-source voltage v of the switching device M2 in synchronous mode is approximately 10A and the gate drive circuit is disabled. gs,2 A graph of the waveform;

[0123] Figure 22A This shows the gate-source voltage v during one line cycle of switching device M2 when the gate drive circuit is enabled. gs,2 and inverter output current io A graph of the waveform;

[0124] Figure 22B This indicates when the inverter output current i o When the gate-source voltage v of the switching device M2 in control mode is approximately 2A and the gate drive circuit is enabled, gs,2 A graph of the waveform;

[0125] Figure 22C This indicates when the inverter output current i o When the gate-source voltage v of the switching device M2 in control mode is approximately 10A and the gate drive circuit is enabled. gs,2 A graph of the waveform;

[0126] Figure 22D This indicates when the inverter output current i o When the gate-source voltage v of the switching device M2 in synchronous mode is approximately 2A and the gate drive circuit is enabled. gs,2 A graph of the waveform;

[0127] Figure 22E This indicates when the inverter output current i o The gate-source voltage v of the switching device M2 in synchronous mode is approximately 10A and the gate drive circuit is enabled. gs,2 A graph of the waveform; and

[0128] Figure 23 This is a functional block diagram of a data processing system according to one embodiment of the present invention. Detailed Implementation

[0129] Through research, experimentation, and testing, the inventors of this invention have discovered that the amplitude of spurious voltage pulses can depend on various intrinsic and extrinsic factors, such as parasitic elements, drain current, and the aging condition of the switch. The inventors have realized that, if properly arranged, the gate driver or gate drive circuit can adaptively change the negative gate-source voltage in the off-state to reduce or minimize voltage stress on the gate oxide, thereby extending the lifespan of the switching device.

[0130] The following disclosure comprises several parts. One part presents experimental results on the drift of intrinsic parameters of eight different solid-state electronic devices before and after 4000 short-circuit current stress cycles. The experimental results show that the amplitude of parasitic voltage pulses decreases after aging. Another part describes gate drivers of some embodiments of the present invention, which can dynamically adjust the negative gate-source voltage in the off-state to counteract the effects of parasitic voltage pulses. Changes in the negative gate-source voltage in the off-state can be monitored to indirectly determine the aging or health status of the solid-state electronic device switch. Another part describes inverter circuits with gate drivers of some embodiments of the present invention.

[0131] A review of the intrinsic parameter changes of solid-state electronic devices after cycling.

[0132] To investigate the effects of aging on solid-state electronic devices, short-circuit current stress tests (including 4000 short-circuit current stress cycles) were performed on eight different solid-state electronic devices (in this example, silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs)) to determine the drift of seven operating parameters associated with these SiC MOSFETs. These parameters include the threshold voltage Vt. th On-state resistance R ds,on Drain-source leakage current I dss Gate-source leakage current I gss Gate-source capacitance C gs Drain-source capacitance C ds And the gate-drain capacitance C gd .

[0133] Table I lists the eight different SiC MOSFETs used in the tests. The testing procedure was based on the one described in the following article:

[0134] ·Fu et al., “Experimental study of 600V GaN transistor under the short-circuit aging tests”

[0135] ·Mbarek et al., “Gate oxide degradation of SiC MOSFET under short-circuit aging tests,”

[0136] ·Fu et al, "Evolution of CV and IV characteristics for a commercial600 V GaN GIT power device under repetitive short-circuit tests"

[0137] ·Douzi et al, "Conducted EMI evolution of power SiC MOSFET in a Buckconverter after short-circuit aging tests"

[0138] Figure 1A The setup used to evaluate each of the eight SiC MOSFETs (each SiC MOSFET corresponds to a device under test (DUT)) is shown. During testing, the MOSFETs were turned on for 1000 microseconds and then off for 4.999 seconds per cycle to reduce the effects of self-heating. In other words, each DUT required 5.56 hours to complete the cycle test. Parameters before and after the cycle were recorded. Figure 1B This shows the detection of [something] in the short-circuit current stress test. Figure 1A Voltage V in the settings g and current i SC The waveform.

[0139] Table I: List of power devices tested

[0140]

[0141]

[0142] In the test, the threshold voltage V th By using the drain-source voltage V ds 10V and drain current I d The gate-source voltage and leakage current were recorded at 5mA for measurement. Figure 2A The threshold voltage V is shown. th The changes ranged from 2.7% to 19%. Figure 2A In the chart, for each device AH, the left bar represents the value before testing and the right bar represents the value after testing (aging).

[0143] In the test, the on-state resistance R ds,on Through V gs For 15V and I d The voltage and current of the SiC MOSFET were recorded indirectly at a current of 20A. Figure 2B The on-state resistance R is shown. ds,on The changes ranged from 11.7% to 33.1%. Figure 2B In the chart, for each device AH, the left bar represents the value before testing and the right bar represents the value after testing (aging).

[0144] In the test, the drain-source leakage current I dss It is in V ds The measurement was taken at 100V. Figure 2C The drain-source leakage current I is shown. dss The changes were observed. An increase of over 36 times was found. In Figure 2C In the chart, for each device AH, the left bar represents the value before testing and the right bar represents the value after testing (aging).

[0145] In the test, the gate-source leakage current I gss It is in V gs The measurement was taken at 15V. Figure 2D The gate-source leakage current I is shown. gss The change showed a significant percentage increase. In Figure 2D In the chart, for each device AH, the left bar represents the value before testing and the right bar represents the value after testing (aging).

[0146] In the test, the gate-source capacitance C gs It is in V ds The value was measured at 0V using a power device analyzer (Keysight Technologies, B1506A). Figure 2E The gate-source capacitance C is shown. gs The change ranged from -3.4% to 61%. Figure 2E In the chart, for each device AH, the left bar represents the value before testing and the right bar represents the value after testing (aging).

[0147] In the test, the drain-source capacitance C ds Also in V ds The value was measured at 0V using a power device analyzer (Keysight Technologies, B1506A). Figure 2F The drain-source capacitance C is shown. ds The variation ranges from -1.6% to 5.5%. Excluding the variation in device A, the variations in the remaining devices primarily vary between -1.6% and 0.5%. Figure 2F In the chart, for each device AH, the left bar represents the value before testing and the right bar represents the value after testing (aging).

[0148] In the test, the gate-drain capacitance C gd Also in V dsThe value was measured at 0V using a power device analyzer (Keysight Technologies, B1506A). Figure 2G The gate-drain capacitance C is shown. gd The variation ranges from 0% to -24%. Figure 2G In the chart, for each device AH, the left bar represents the value before testing and the right bar represents the value after testing (aging).

[0149] Based on the obtained test results, it can be determined that all investigated parameters changed to varying degrees after cycling. Therefore, the aging of solid-state electronic devices can be monitored on either the power processing side or the gate driving side. However, monitoring the aging of solid-state electronic devices on the power processing side requires complex circuitry (e.g., high-voltage and high-current sensing circuitry), and monitoring the aging of solid-state electronic devices on the gate driving side may also require complex circuitry to extract the individual parameters.

[0150] The inventors of this invention have realized that the combined effect of changes in gate-related parameters on the magnitude of parasitic voltage can be used to monitor the aging of solid-state electronic devices, particularly the health of the gate oxide. These parameters include I gss C gd and C gs After the loop, I gss It will increase C gd and C gs This will decrease, thus reducing the amplitude of the parasitic voltage. This information can be used to adjust the negative off-state voltage and monitor device aging.

[0151] Circuit with adaptive level shifter

[0152] Figure 3 A circuit 300 according to one embodiment of the present invention is shown. Circuit 300 includes a solid-state electronic device M1, a driver circuit operatively connected to the solid-state electronic device M1 to control its operation, and a signal modulation circuit 302 operatively connected to or between the driver circuit and the solid-state electronic device M1. In this example, the solid-state electronic device M1 can selectively operate as a control switch and a synchronization switch and can selectively operate in an ON state and an OFF state. The solid-state electronic device M1 may be a MOSFET (e.g., a SiC MOSFET). In this example, the driver circuit and the signal modulation circuit 302 can be considered together as a gate drive circuit. Although not shown, it should be noted that circuit 300 may include at least one additional solid-state electronic device operatively connected to the solid-state electronic device M1, at least one additional signal modulation circuit for the at least one additional solid-state electronic device, and the driver circuit may be further operatively connected to the at least one additional solid-state electronic device to control its operation.

[0153] refer to Figure 3 The signal modulation circuit 302 includes: an input 302A connected to a driver circuit, an output 302B connected to a solid-state electronic device M1, and a variable resistor circuit 302C connected between the input 302A and the output 302B and operably connected to the driver circuit. The resistance of the variable resistor circuit 302C can be adjusted by the driver circuit to prevent malfunction of the solid-state electronic device M1. In this embodiment, the variable resistor circuit 302C employs a rheostat, particularly a digital rheostat R. v To implement.

[0154] The resistance of the variable resistor circuit 302C can be adjusted by the driver circuit to affect the signal at the output 302B, preventing the solid-state electronic device M1 from being falsely activated (turned on) when (or only when) it is in the off state (e.g., the first solid-state electronic device operates as a synchronous switch and is in the off state). The resistance of the variable resistor circuit 302C can also be adjusted by the driver circuit to affect the signal at the output 302B (e.g., a voltage signal) to prevent malfunction of the solid-state electronic device M1.

[0155] In this example, the driver circuit includes a gate drive circuit for the solid-state electronic device M1, and a signal modulation circuit 302 is operatively connected between the gate drive circuit and the solid-state electronic device M1. Specifically, the output 302B of the signal modulation circuit 302 is connected across the gate and source of the solid-state electronic device M1.

[0156] like Figure 3 As shown, the signal modulation circuit 302 includes two resistor-capacitor (RC) circuits and a diode circuit connected between the two RC circuits. One of the RC circuits includes a resistor R connected in parallel. N and capacitor C N A diode circuit includes diode D. P Another RC circuit includes capacitor C. P Two fixed resistors R A ,R B and digital rheostats R v Resistance R B and rheostat R v Series connection. Resistor R A and capacitor C P Parallel connection. Resistor R B and rheostat R v Together with resistor R A and capacitor C P Parallel connection. The signal modulation circuit 302 can be considered an adaptive level converter.

[0157] like Figure 3 As shown, the driver circuit includes: a detector circuit operable to detect the gate-source voltage of the solid-state electronic device M1; and a circuit operable to compare the detected gate-source voltage with a reference voltage V. REF Comparison and provide for comparison-based control of the variable resistor R v The control circuit for the control signal of the resistor. R variable resistor. v The resistance affects the gate-source voltage of the solid-state electronic device M1. In this embodiment, the detector circuit includes an amplifier 304 operatively connected to the gate and source of the solid-state electronic device M1. In this embodiment, the control circuit includes a component operatively connected to the amplifier 304 for comparing the detected gate-source voltage with a reference voltage V. REF The circuit includes a comparator 306 for comparison and a controller 308 operatively connected to the comparator 306 to provide a control signal to the signal modulation circuit 302. In this embodiment, the control circuit also includes a latch circuit 310 operatively connected between the comparator 306 and the controller 308. In this embodiment, the controller 308 is a converter controller. In this embodiment, the circuit also includes an isolated gate driver 312 (in the form of an isolated gate driver integrated circuit (IC)) electrically connected between the controller 308 and the signal modulation circuit 302. The controller 308 is arranged to provide a gate signal to the isolated gate driver 312. The isolated gate driver 312 can be considered part of the control circuit. The control circuit can operate when the solid-state electronic device M1 is turned on and / or when the solid-state electronic device M1 is turned off.

[0158] The latch circuit 310 is configured to: when it is determined that the detected gate-source voltage is greater than the reference voltage V REF It is in the first state (e.g., high level) when the detected gate-source voltage is determined to be less than the reference voltage V. REF The latch circuit 310 is in a second state (e.g., low level). The controller 308 can detect the state of the latch circuit 310 and provide a control signal accordingly based on the detected state of the latch circuit 310. In one example, the controller 308 is arranged to detect the state of the latch circuit 310 and provide a control signal when (or only when) the solid-state electronic device M1 is in an off state (e.g., the solid-state electronic device M1 operates as a synchronous switch and is in an off state). The controller 308 can repeatedly (e.g., periodically) detect the state of the latch circuit 310 and provide continuous control signals to dynamically or adaptively adjust the resistance of the variable resistor circuit 302C. In this embodiment, the controller 308 is arranged to provide a control signal to decrease the resistance of the variable resistor circuit 302C when the latch circuit 310 is detected to be in a first state, and to provide a control signal to increase the resistance of the variable resistor circuit 302C when the latch circuit 310 is detected to be in a second state.

[0159] Although not shown, in some embodiments, circuit 300 may further include a processor for determining the health status of solid-state electronic device M1 (particularly gate oxide) based on the resistance of variable resistor circuit 302C. Although not shown, in some embodiments, circuit 300 may further include a monitoring device or circuitry for monitoring changes in the resistance of variable resistor circuit 302C over time, and the processor may determine the health status of solid-state electronic device M1 (particularly gate oxide) based on the resistance of the variable resistor circuit monitored over time. In some embodiments, the processor may further determine the health status of at least one additional solid-state electronic device (particularly gate oxide) based on the resistance of a variable resistor circuit associated with at least one other solid-state electronic device.

[0160] Return to reference Figure 3 In this embodiment, C P The total resistance at both ends is R P It is equal to

[0161]

[0162] When R v When R varies between zero (short-circuit state) and infinity (open-circuit state), P In R P,min and R P,max The changes between them. Based on equation (1):

[0163]

[0164] R P,max =R A (3)

[0165] Driver output v g It can be in 0 and V GG Switching between them. To simplify the analysis, the following was adopted. Figure 3 R shown gss -C gs The circuit is used to simulate the gate of the switching device M1.

[0166] As mentioned earlier, R gss It is initially large and then decreases with age. Therefore, R gss -C gs The impedance of the circuit is typically greater than the gate resistance R. g (For simplicity, it will not be considered in the following analysis).

[0167] Set d and T to the duty cycle and switching period of M1, respectively.

[0168] Figure 4A and Figure 4B The diagrams show the operation of switching device M1 in mode 1 (on state) and mode 2 (off state), respectively. Figure 3 Voltage v in the gate drive circuit g ,、C N Voltage v across the terminals CN C P Voltage v across the terminals CP and the output voltage v of the level converter o,LS The waveform.

[0169] Figure 5A and Figure 5B The diagrams show the operation of switching device M1 in mode 1 (on state) and mode 2 (off state), respectively. Figure 3 The operation of the gate drive circuit.

[0170] Mode 1 corresponds to the on state operation.

[0171] Specifically, when M1 is turned on, v g =V GG And D P Conduction. Let D be... P The positive decrease is zero. Figure 5A The equivalent circuit is shown. CN v CP and v o,LS They can be represented as:

[0172]

[0173]

[0174] v o,LS (R v ,t)=v o,LS,ON (R v ,t)=v CP,ON (R v ,t) (6)

[0175] Where t∈[0 dT], V CN (0 + ) and V CP (0 + ) are respectively C N and C P The initial voltage, τ ON =C eq,ON R eq,ON C eq,ON =C N +C P,ON , C P,ON =C P +Cgs as well as

[0176] At the end of mode 1, v CN =v CN,ON,f ,v CP =v CP,ON,f and v o,LS =v o,LS,ON,f They can be represented as:

[0177] V CN,ON,f =v CN,ON (R v ,dT) (7)

[0178] V o,LS,ON,f =V CP,ON,f =v CP,ON (R v ,dT) (8)

[0179] Mode 2 corresponds to the off state operation.

[0180] Specifically, when M1 is turned off, v g =0 and D P Block. Figure 5B The equivalent circuit is shown. CN ,v CP and v o,LS They can be represented as:

[0181]

[0182]

[0183] v o,LS (t)=v o,LS,OFF (t)=-v CN,OFF (t) (11)

[0184] Where t∈[0 dT], V CN (dT + ) and V CP (dT + ) are respectively C N and C P The initial voltage, τ OFF =C eq,OFF R eq,OFF C eq,OFF =C N +C gs , and τ CP =C P R P .

[0185] At the end of mode 2, vCN =v CN,OFF,f ,v CP =v CP,OFF,f and v o,LS =v o,LS,OFF,f They can be represented as:

[0186] V o,LS,OFF,f =-V CN,OFF,f =-v CN,OFF (R v ,(1-d)T) (12)

[0187] V CP,OFF,f =v CP,OFF (R v ,(1-d)T) (13)

[0188] Figure 4A and Figure 4B The initial and final states of the capacitor voltage are shown. The initial state of a mode is obtained from the final state of its previous mode.

[0189] For mode 1, applying the law of conservation of charge, V CN (0 + ) and V CP (0 + ) can be represented as:

[0190]

[0191]

[0192] Where V o,LS (0 + ) represents the initial output voltage of the level converter when in mode 1.

[0193] For mode 2, V CN (dT + ) and V CP (dT + ) can be represented as:

[0194]

[0195] V CP (dT + ) = V CP,ON,f (17)

[0196] Where V o,LS (dT + ) represents the initial output voltage of the level converter when in mode 2.

[0197] If V CN (0 +) <V CN,ON,f Then when the gate signal is V GG At that time, C N The voltage will increase (e.g.) Figure 4A (As shown). If V CN (0 + )>V CN,ON,f Then when the gate signal is V GG At that time, C N The voltage will decrease (e.g.) Figure 4B (As shown).

[0198] In this embodiment, the off-state voltage of device M1 can be adjusted.

[0199] Specifically, by changing R v Change the value of v o,LS The shift level can make the parasitic voltage less than the threshold voltage of M1. Parasitic voltages typically occur when complementary power devices are turned on. That is, it occurs after M1 enters mode 2 and the dead time is t. d Based on equation (9):

[0200]

[0201] like Figure 3 As shown, when M1 enters mode 2, the gate-source voltage v gs Sensed and compared with reference voltage V REF A comparison is performed. The comparator's output is latched to provide the signal v. L The peak parasitic voltage is regulated at V using peak voltage control. REF nearby.

[0202] Figure 6 It shows Figure 3 The control method 600 for the gate drive circuit. In this embodiment, during two dead time intervals (i.e., 2t) d After that, the controller 308 will check the v of the input pin IN1. L Once. If v L A high level means v gs >V REF Controller 308 will R v The value decreases by ΔR v It is equal to R v The unit change. For example, the maximum value of the 8-bit rheostat used in the experiment is 20kΩ. Therefore, ΔR v =20kΩ / 255 = 78.43Ω. If v L A low level means v gs <V REF Controller 308 will Rv The value increases by ΔR v .

[0203] Figure 3 The gate drive circuit further allows or facilitates monitoring of the state of the switching device M1.

[0204] Generally, for healthy switching devices, the parasitic voltages under certain load conditions are consistent, while the R required to control the gate-source voltage is... v It is consistent. When I gss When increased, it decreases the gate-source voltage. An adaptive level shifter will increase R. v To compensate I gss The impact. Therefore, by monitoring R v The value of I can be monitored. gss This involves increasing the number of devices and monitoring their health status.

[0205] Table II lists the components used in an example and their part numbers or values.

[0206] Table II: Parts List

[0207]

[0208]

[0209] Figure 7A It shows that for different V REF Values ​​of duty cycle d and R v The relationship between R. gss The value of is assumed to be infinite (in a healthy state). The information in Table II applies. v The value of R can be adjusted to control the off-state voltage, thereby satisfying the condition of equation (18). For the same duty cycle and load conditions, R v It increases as the parasitic voltage amplitude decreases. For example, the C of aging switching devices... gd The value is less than the C value of the switching device in a healthy state. gd This results in a lower parasitic voltage.

[0210] Figure 7B d and R are shown v The relationship between R gss Equal to infinity, 10kΩ, 5kΩ, 1kΩ, and 100Ω to represent different degrees of aging. V REF The value is set to -4V. Because R gss With C P Parallel connection, therefore under the same duty cycle, R v The required value will vary with R gssIt increases as it decreases.

[0211] Figure 7C d and R are shown v The relationship between the additional capacitance ΔC gs It is connected between the gate and the source. ΔC gs Equal to 0pF, 50pF, 150pF, 250pF, and 350pF to represent different levels of aging. V REF The value was set to -4V while R gss Infinite. R v The required value depends on C gs The decrease leads to an increase.

[0212] based on Figures 7A to 7C It can be determined by observing R under the considered duty cycle and load conditions. v Changes in these changes can be used to monitor the status of switching devices.

[0213] Now let's introduce Figure 3 Example design process of signal modulation circuit 302.

[0214] In one implementation, C is designed by considering the following design criteria. N C P ,R N ,R A and R B Value:

[0215] 1)V o,LS,inf (dT + ): When R v →∞ (i.e., R) v Initial turn-off state gate-source voltage during open-circuit fault

[0216] 2)V o,LS,max (dT + ):R v =R v,max (R v Initial turn-off state gate-source voltage (at maximum value)

[0217] 3)V o,LS,min (dT + ):R v =0(R) v Initial turn-off state gate-source voltage (at minimum value)

[0218] The first step in the design process includes designing R N ,R A and R B By utilizing different R v Considering the steady-state gate-source voltage using the value of , it can be proven that:

[0219]

[0220]

[0221]

[0222] Therefore, R N ,R A and R B It can be determined by solving equations (19), (20) and (21).

[0223] Step 2 of the design process includes designing C. P In this example, C P The value is chosen to be at least greater than C. gs Ten times larger, so that the operation of the level converter will not be affected by C. gs Dominate (in mode 1 operation).

[0224] Step 3 of the design process includes designing C. N In this example, C N The value is determined by considering R. v Design nominal value R v,norm This is determined by [the specific conditions]. Therefore, the time constants of the two RC circuits are designed to be approximately the same. Therefore:

[0225]

[0226] Experimental verification

[0227] Figure 3 The performance of the 300 level shifter circuit was evaluated on a 1kW, 400Vdc / 115Vac full-bridge inverter. The output LC filter consists of inductor L. o =0.7mH and capacitor C o =1μF constitutes the composition.

[0228] Figure 8A A full-bridge inverter is shown, in which Figure 3 A level shifter (not shown) of the gate drive circuit is applied to the switching device M2. Figure 8B and Figure 8C A full-bridge inverter circuit is shown, which includes Figure 3 Level shifter for the gate drive circuit.

[0229] In this example, the load resistance R LThe nominal resistance is 13.7Ω. The switching frequency is 45kHz. All switching devices are CREE C3M0065090J, with a threshold voltage of 2.1V and a maximum permissible reverse gate-source voltage of -8V. The gate driver is Skyworks SI8233, with a supply voltage of 15V.

[0230] In this example, switching device M2 is connected to a level shifter, while the remaining switching devices are driven by a gate driver with an RCD level shifter (where the voltage is shifted down by 6V). For more information on RCD level shifters, please refer to the following article (the entire contents of which are incorporated herein by reference):

[0231] ·Wang et.al, "A Novel RCD Level Shifter for Elimination of SpuriousTurn-on in the Bridge-Leg Configuration"

[0232] The level shifter for M2 is designed according to the design steps described above, and Table II lists the values ​​for the components.

[0233] Different degrees of crosstalk effects were simulated by increasing the equivalent gate-drain capacitance and reducing the equivalent gate-source resistance and capacitance using an external capacitor. The system was tested with and without dynamic gate-source voltage control.

[0234] For C gd The impact was studied.

[0235] The off-state voltage was shifted down by 6V using an RCD level converter. Figures 9A to 9C The following are examples of capacitor C. gd When connected between the gate and drain of M2 (when the gate drive circuit is disabled), the gate-source voltage v of M2 is... gs,2 Drain-source voltage v ds,2 and drain current i d,2 The conduction waveform. The measured ΔC gd The values ​​include 10pF, 20pF, 30pF, 40pF, and 50pF, respectively. Figures 10A to 10C The following are examples of capacitor C. gd When connected between the gate and drain of M2 (when the gate drive circuit is disabled), the gate-source voltage v of M2 is... gs,2 Drain-source voltage v ds,2 and drain current i d,2The turn-off waveform is shown. The parasitic voltage amplitudes are 0.7V, 1.6V, 2.2V, 2.9V, 3.7V, and 4.1V, respectively. Thus, when the external capacitor is 50pF, the gate-source voltage in the turn-off state reaches -2V. Therefore, with further increases in the gate-drain capacitance, undesirable breakdown may occur.

[0236] Figures 11A to 11C The following are examples of capacitor C. gd When connected between the gate and drain of M2 (when the gate drive circuit is enabled), the gate-source voltage v of M2 is... gs,2 Drain-source voltage v ds,2 and drain current i d,2 The conduction waveform. Figures 12A to 12C The following are examples of capacitor C. gd When connected between the gate and drain of M2 (when the gate drive circuit is enabled), the gate-source voltage v of M2 is... gs,2 Drain-source voltage v ds,2 and drain current i d,2 The turn-off waveform shows that, with gate-source voltage control enabled in the turn-off state, the parasitic voltage is regulated to below -1V, i.e., V. REF It is -1V.

[0237] Through the Figures 9A to 9C and Figures 11A to 11C By comparison, we can see that the gate-source voltage curves are roughly similar, and both approach zero near the end of the switching cycle.

[0238] Figures 12A to 12C As shown, according to ΔC gd The value of v after being turned off gs,2 It changes immediately between -3.5V and -6.4V. By reducing R v The peak off-state gate voltage caused by crosstalk can be maintained at -1V. It is gradually increased until the end of the switching cycle. Therefore, this reduces the average voltage stress on the gate oxide.

[0239] Table III shows a comparison of the M2 power loss measured under dynamic and fixed (non-dynamic) off-state voltage control, respectively.

[0240] Table III: At different ΔC gd Power loss of M2

[0241] <![CDATA[ΔC gd (pF)]]> <![CDATA[P L,act *(W)]]> <![CDATA[P L,deact *(W)]]> <![CDATA[ΔP L (%)]]> 0 12.5 12.8 2.2 10 12.4 12.6 1.4 20 12.2 12.7 3.6 30 12.3 12.8 3.4 40 12.9 13.3 3.3 50 13.8 14.5 4.5

[0242] *Note:

[0243] P L,act Power loss of M2 when dynamic gate-source voltage control is enabled.

[0244] P L,deact Power loss of M2 when dynamic gate-source voltage control is disabled

[0245] ΔP L Percentage difference

[0246] The results show that the dynamic method has lower power loss than the fixed method (gate-source voltage control). When ΔC gd At 50pF, the gate-source voltages for dynamic turn-off voltage control and fixed turn-off voltage control are designed to be the same in this worst-case scenario. When the switch is in control mode, the power loss of dynamic turn-off voltage control is lower than that of fixed turn-off voltage control because both on-resistance and turn-off voltage stress are reduced.

[0247] Dynamic control can reduce power loss for at least two reasons. First, the gate-source voltage in the on-state can change with C. gd Dynamic changes. With C gd As the on-resistance decreases, the gate-source voltage increases. Therefore, power loss decreases as the on-resistance decreases. Secondly, since the gate-source voltage is dynamically reduced in the off-state, reverse conduction losses can also be reduced.

[0248] For R gss The impact was studied.

[0249] Figures 13A to 13C It shows that when the resistance R gss The conduction waveform when connected between the gate and source of M2 (when the gate drive circuit is disabled). R gss The values ​​are 10kΩ, 4.7kΩ, 1kΩ, 470Ω, and 100Ω, respectively. With R... gss If the voltage is reduced, the amplitude of the parasitic voltage will decrease slightly.

[0250] Figures 14A to 14C It shows that when the resistance R gss The turn-off waveform when connected between the gate and source of M2 (when the gate drive circuit is disabled). When R... gss When the resistance is 100Ω, the gate-source voltage drops to 6V in the on-state and to -8V in the off-state. This is mainly due to R... gss The load effect on the level shifter. Therefore, the off-state voltage stress on the gate oxide of the switching device increases.

[0251] Figures 15A to 15C It shows that when the resistance R gss The conduction waveform when connected between the gate and source of M2 (when the gate drive circuit is enabled). Figures 16A to 16C The diagram shows when the resistance R gssThe turn-off waveform when connected between the gate and source of M2 (when the gate drive circuit is enabled).

[0252] Through the Figures 15A to 15C and Figures 13A to 13C By comparison, we can see that: in different R gss The gate-source voltage curves are similar, and both approach zero near the end of the switching cycle. Figures 15A to 15C The diagram shows that the gate-source voltage control in the off-state immediately after the switch is turned off will reduce the voltage by v. gs,2 Maintained at -2.4V (where R gss (Variation between 470Ω and 10kΩ), thus producing a lower turn-off state voltage on the gate oxide. The peak turn-off state gate-source voltage caused by crosstalk is also reduced by R v The adjustment is at -1V. In R... gss When R = 100Ω (extreme case), the control cannot perform this adjustment. Therefore, by observing R... v The value of R can be monitored. gss The changes.

[0253] Table IV shows when R gss Comparison of M2 power loss measured under dynamic and fixed (non-dynamic) off-state voltage control when decreasing from ∞ (infinity) to 100Ω.

[0254] Table IV: In different R gss Power loss of M2

[0255] <![CDATA[R gss (Oh)]]> <![CDATA[P L,act *(W)]]> <![CDATA[P L,deact *(W)]]> <![CDATA[ΔP L (%)]]> ∞ 11.8 12.2 3.4 10k 11.7 12.6 7.7 4.7k 11.8 12.5 5.9 1k 11.8 12.8 8.5 470 11.8 12.9 9.3 100 13.3 14.5 9

[0256] *Note:

[0257] P L,act Power loss of M2 when dynamic gate-source voltage control is enabled.

[0258] P L,deact Power loss of M2 when dynamic gate-source voltage control is disabled

[0259] ΔP L Percentage difference

[0260] Dynamic gate-source voltage control results in lower power loss than fixed gate-source voltage control, for at least two reasons. First, the gate-source voltage in the on-state varies with R. gss It changes dynamically. In R gss When R decreases, v The gate-source voltage is increased to regulate its operation. The gate-source voltage is higher in the on-state, resulting in lower power loss. Furthermore, since the gate-source voltage is dynamically reduced in the off-state, reverse conduction losses can also be reduced.

[0261] For C gs The impact was studied.

[0262] Figures 17A to 17C The conduction waveform is shown when the capacitor is connected between the gate and source of M2 (when the gate drive circuit is disabled). Figures 18A to 18C The diagram shows the turn-off waveform when a capacitor is connected between the gate and source of M2 (when the gate drive circuit is disabled). The measured ΔC... gs The values ​​are 0pF, 50pF, 150pF, 250pF, and 350pF, respectively. It has little effect on the amplitude of the parasitic voltage. In all cases, the gate-source voltage remains at 10V during the on-state at the end of the switching cycle. Due to C... P Designed to be much larger than the gate-source capacitance, therefore ΔC gs The value of has little effect on the equivalent capacitance in Mode 1.

[0263] Figures 19A to 19C The conduction waveform is shown when the capacitor is connected between the gate and source of M2 (when the gate drive circuit is enabled). Figures 20A to 20C The diagram shows the turn-off waveform when a capacitor is connected between the gate and source of M2 (when the gate drive circuit is enabled). The parasitic voltage is regulated to below -1V. This is achieved by... Figures 19A to 19C and Figures 17A to 17C By comparison, it can be seen that the gate-source voltage curves are similar, and both approach zero near the end of the switching cycle. Through analysis of... Figures 20A to 20C and Figures 18A to 18C By comparison, we can see that: regardless of ΔC gs The fact that the gate-source voltage curves are all similar indicates that ΔC gs The load effect on the circuit is limited.

[0264] Table V shows a comparison of the M2 power loss measured under dynamic and fixed (non-dynamic) off-state voltage control, respectively. With ΔC gs The increase in voltage increases both the on and off times, leading to higher switching losses. Since dynamic off-state voltage control does not alter the on and off waveforms, the power losses are minimally affected by dynamic and fixed off-state voltage control.

[0265] Table V: For variable C gs Power loss on the switch

[0266]

[0267]

[0268] *Note:

[0269] PL,act Power loss of M2 when dynamic gate-source voltage control is enabled.

[0270] P L,deact Power loss of M2 when dynamic gate-source voltage control is disabled

[0271] ΔP L Percentage difference

[0272] Figures 21A to 21E The case where there is no gate driver (or it is not operating) is shown. Figure 21A This shows v within one line cycle. gs,2 and inverter output current i o The waveform. Figure 21B and Figure 21C They respectively show when and And the waveform of M2 when it is in control mode. Figure 21D and Figure 21E They respectively show when and The waveform of M2 in synchronous mode. Due to the change in load current, the amplitude of the parasitic voltage also changes. Due to the different duty cycles, Figure 21C It shows a ratio Figure 21B A more negative off-state voltage. Figure 21D The peak parasitic voltage is shown to be below V. REF and Figure 21E The peak parasitic voltage and V are shown. REF same.

[0273] Figures 22A to 22E The corresponding waveforms are shown (in the case of gate driver operation). R v Therefore, v gs,2 It was modified to regulate the peak parasitic voltage in the off-state to V. REF . Figure 22B and Figure 22C This shows that the gate-source voltage is adjusted to -1V after a dead time (i.e., 400 nanoseconds). Figure 22D and Figure 22E They respectively show when and The waveform of M2 in synchronous mode. In both cases, the peak parasitic voltage is V. REF .when and time v gs,2 The amplified waveform confirms this voltage regulation control.

[0274] The above embodiments of the present invention provide a circuit, such as an adaptive gate driver, that can adjust the off-state gate-source voltage to counteract parasitic voltages caused by crosstalk effects. The above embodiments of the present invention also provide a circuit, such as an adaptive gate driver, that can directly monitor the health status of solid-state electronic devices (e.g., switches) by observing changes in voltage levels. An appropriate off-state gate-source voltage for the switch can resolve crosstalk problems and potentially improve the expected lifespan of the switch. This technique was evaluated using a 1kW inverter. By introducing different gate-drain capacitance values, gate-source resistance values, and gate-source capacitance values, the results disclosed above demonstrate that the peak parasitic voltage caused by crosstalk is regulated, and the power loss is less than that of a driver with a fixed off-state gate-source voltage.

[0275] Figure 23 An example data processing system 2300 according to one embodiment of the present invention is shown. The data processing system 2300 can be used to process data, such as measured resistance R. v This is used to determine or facilitate the determination of the health status of solid-state electronic devices (e.g., switching devices in the above embodiments). The data processing system 2300 generally includes appropriate components required for receiving, storing, and executing appropriate computer instructions, commands, and / or code. The main components of the data processing system 2300 are processor 2302 and memory 2304. Processor 2302 may include one or more central processing units, one or more microcontroller units, one or more controllers, one or more logic circuits, one or more Raspberry Pi chips, one or more digital signal processors (DSPs), one or more application-specific integrated circuits (ASICs), one or more field-programmable gate arrays (FPGAs), or any one or more other digital or analog circuits arranged to interpret and / or execute program instructions and / or process information and / or data. Memory 2304 may include one or more volatile memories (e.g., RAM, DRAM, SRAM), one or more non-volatile memories (e.g., ROM, PROM, EPROM, EEPROM, FRAM, MRAM, FLASH, SSD, NAND, NVDIMM), or any combination thereof. Appropriate computer instructions, commands, codes, information, and / or data may be stored in memory 2304. Computer instructions for performing or facilitating the performance of method embodiments of the present invention may be stored in memory 2304. Processor 2302 and memory 2304 may be integrated together or separate (but operatively connected). Those skilled in the art will understand that... Figure 23 The data processing system 2300 shown is merely an example, and in other embodiments, the data processing system 2300 may have different configurations (e.g., including additional components, having fewer components, etc.).

[0276] Some embodiments of the present invention provide a circuit that guarantees or ensures the normal operation of solid-state electronic devices in a converter / inverter circuit under parasitic voltages. Some embodiments of the present invention provide a circuit that optimizes voltage to extend the lifespan of solid-state electronic devices and monitors their health status. Some embodiments of the present invention can be adapted to the load conditions of solid-state electronic devices (or converters incorporating solid-state electronic devices) to provide optimized voltage. Some embodiments of the present invention can provide built-in health monitoring of solid-state electronic devices (or converters incorporating solid-state electronic devices) without requiring additional or numerous components.

[0277] The circuit of this invention can be applied to various power electronic circuits and devices, such as solar inverters and power supplies.

[0278] Those skilled in the art will understand that various changes and / or modifications can be made to the invention as illustrated in certain embodiments to provide other embodiments of the invention. Therefore, the described embodiments of the invention should be considered illustrative rather than restrictive in all respects. Example optional features of some aspects of the invention are set forth in the Summary of the Invention section. Some embodiments of the invention may include one or more of these optional features (some of which are not specifically shown in the drawings). Some embodiments of the invention may lack one or more of these optional features (some of which are not specifically shown in the drawings). One or more features in one embodiment and one or more features in another embodiment may be combined to provide further embodiments of the invention. For example, the circuits and methods of the invention can be applied to other solid-state electronic devices (i.e., not limited to MOSFETs or SiC MOSFETs). For example, the circuit components shown can be implemented using equivalent circuit arrangements or components. For example, signal modulation circuitry can be used in different types of converter or inverter circuits of solid-state electronic devices (two or more) with bridge arm configurations. Variable resistor circuitry can be implemented using switches and resistors (i.e., not necessarily using digital rheostats or variable resistors).

Claims

1. A circuit comprising: A first solid-state electronic device and a second solid-state electronic device are arranged in a bridge arm configuration, each of the first solid-state electronic device and the second solid-state electronic device being selectively operable as a control switch and a synchronization switch, and being selectively operable in an on state and an off state, respectively; the first solid-state electronic device includes a field-effect transistor having a gate, a drain, and a source. A driver circuit, which is operatively connected to at least the first solid-state electronic device for at least controlling the operation of the first solid-state electronic device; The driver circuit includes a gate drive circuit for the field-effect transistor; The driver circuit includes: A detector circuit operable to detect the gate-source voltage of the field-effect transistor; and Control circuit; A signal modulation circuit operatively connected between the gate drive circuit and the field-effect transistor; the signal modulation circuit includes: The input is operatively connected to the driver circuitry. The output is operatively connected to the first solid-state electronic device; First resistor-capacitor circuit; The second resistor-capacitor circuit; and Diode circuit; A variable resistor circuit operatively connected between the input and the output and operatively connected to the driver circuit, wherein the variable resistor circuit is part of the second resistor-capacitor circuit; The resistance of the variable resistor circuit can be adjusted by the driver circuit to prevent malfunction of the first solid-state electronic device. The control circuit is operable to compare the detected gate-source voltage with a reference voltage and, based on the comparison result, provide a control signal for controlling the resistance of the variable resistor circuit.

2. The circuit according to claim 1, wherein, The resistance of the variable resistor circuit is adjusted by the driver circuit to affect the signal at the output, thereby preventing the first solid-state electronic device from being falsely activated when it is in a turned-off state.

3. The circuit according to claim 2, wherein, The resistance of the variable resistor circuit is adjusted by the driver circuit to affect the signal at the output, thereby preventing the first solid-state electronic device from being falsely activated when the first solid-state electronic device operates as a synchronous switch and is in the off state.

4. The circuit according to claim 1, wherein, The resistance of the variable resistor circuit can be adjusted by the driver circuit to affect the signal at the output, thereby preventing malfunction of the first solid-state electronic device.

5. The circuit according to claim 1, wherein, The field-effect transistor includes a MOSFET.

6. The circuit according to claim 5, wherein, The field-effect transistor includes a SiC MOSFET.

7. The circuit according to claim 1, wherein, The output of the signal modulation circuit is connected across the gate and source of the field-effect transistor.

8. The circuit according to claim 1, wherein, The detector circuit includes an amplifier operatively connected to the gate and source of the field-effect transistor.

9. The circuit according to claim 8, wherein, The control circuit includes: A comparator, operatively connected to the amplifier, for comparing the detected gate-source voltage with the reference voltage; and A controller, which is operatively connected to the comparator to provide the control signal.

10. The circuit according to claim 9, wherein, The control circuit also includes: A latching circuit, which is operatively connected to or between the comparator and the controller. The latch circuit is arranged such that it is in a first state when it is determined that the detected gate-source voltage is greater than the reference voltage, and in a second state when it is determined that the detected gate-source voltage is less than the reference voltage. The controller is configured to detect the state of the latch circuit and provide the control signal based on the detected state of the latch circuit.

11. The circuit according to claim 10, wherein, The controller is configured to repeatedly detect the state of the latch circuit, thereby providing continuous control signals to dynamically or adaptively adjust the resistance of the variable resistor circuit.

12. The circuit according to claim 10, wherein, The controller is configured as follows: When the latching circuit is detected to be in the first state, a first control signal is provided to reduce the resistance of the variable resistor circuit; as well as When the latching circuit is detected to be in the second state, a second control signal is provided to increase the resistance of the variable resistor circuit.

13. The circuit according to claim 12, wherein: The first control signal is configured to reduce the resistance of the variable resistor circuit by a predetermined amount; and The second control signal is configured to increase the resistance of the variable resistor circuit by a predetermined amount.

14. The circuit according to claim 1, wherein, The variable resistor circuit includes a rheostat that can be controlled by the driver circuit to adjust the resistance.

15. The circuit according to claim 14, wherein, The rheostat includes a digital rheostat.

16. The circuit according to claim 1, wherein, The diode circuit is operatively connected between the first resistor-capacitor circuit and the second resistor-capacitor circuit.

17. The circuit according to claim 1, further comprising: A processor for determining the health status of the gate oxide of the first solid-state electronic device based on the resistance of the variable resistor circuit.

18. The circuit according to claim 17, further comprising: A monitoring device or circuit for monitoring the change in resistance of the variable resistor circuit over time; as well as The processor is configured to determine the health status of the gate oxide of the first solid-state electronic device based on the monitored change in resistance of the variable resistor circuit over time.

19. The circuit according to claim 1, wherein, The circuit includes a conversion circuit or an inverter circuit, which comprises the first solid-state electronic device and the second solid-state electronic device.

20. A signal modulation circuit for a solid-state electronic device used in a circuit, wherein: The circuit includes: A first solid-state electronic device and a second solid-state electronic device are arranged in a bridge arm configuration, each of the first solid-state electronic device and the second solid-state electronic device being selectively operable as a control switch and a synchronization switch, and being selectively operable in an on state and an off state, respectively; and A driver circuit operatively connected to the first solid-state electronic device for controlling the operation of the first solid-state electronic device; and The signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device, and the signal modulation circuit includes: The input is operatively connected to the driver circuitry. The output is operatively connected to the first solid-state electronic device; First resistor-capacitor circuit; The second resistor-capacitor circuit; and Diode circuit; A variable resistor circuit is operatively connected between the input and the output and operatively connected to the driver circuit; wherein the variable resistor circuit is part of the second resistor-capacitor circuit; Wherein, when the signal modulation circuit is operably connected to or between the driver circuit and the first solid-state electronic device, the resistance of the variable resistor circuit can be adjusted by the driver circuit to prevent malfunction of the first solid-state electronic device; and The resistance of the variable resistor circuit can be used to determine the health status of the gate oxide of the first solid-state electronic device.

21. The signal modulation circuit according to claim 20, wherein, The resistance of the variable resistor circuit can be adjusted by the driver circuit to affect the signal at the output, thereby preventing the first solid-state electronic device from being falsely activated when the first solid-state electronic device operates as a synchronous switch and is in the off state.

22. The signal modulation circuit according to claim 20, wherein, The resistance of the variable resistor circuit can be adjusted by the driver circuit to affect the signal at the output, thereby preventing malfunction of the first solid-state electronic device.

23. The signal modulation circuit according to claim 20, wherein, When the signal modulation circuit is operatively connected to or between the driver circuit and the first solid-state electronic device, the signal modulation circuit is operable to receive from the driver circuit: A first control signal is used to reduce the resistance of the variable resistor circuit by a predetermined amount; and A second control signal is used to increase the resistance of the variable resistor circuit by a predetermined amount.

24. The signal modulation circuit according to claim 20, wherein, The variable resistor circuit includes a rheostat that can be controlled by the driver circuit to adjust the resistance.

25. The signal modulation circuit according to claim 24, wherein, The rheostat includes a digital rheostat.

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