Three-dimensional chip and preparation method thereof, and electronic device

Abstract

The present application provides a three-dimensional chip and a preparation method thereof, and an electronic device. The three-dimensional chip includes a first functional layer and a second functional layer three-dimensionally connected to the first functional layer; wherein the first functional layer has M first extreme exposure areas; and the second functional layer has N second extreme exposure areas; wherein M and N are both integers greater than or equal to 2. Specifically, in the three-dimensional chip provided by the present application, the first functional layer has M first extreme exposure areas, and the second functional layer has N second extreme exposure areas. Since each extreme exposure area is formed by patterning a photolithography master, the three-dimensional chip provided by the present application is larger in size, and more functional units can be set. The first functional layer and the second functional layer are three-dimensionally connected together, and the interconnection height of the first functional layer and the second functional layer is very low, so that the data delay of the signal transmission channel is reduced, and the data transmission speed is greatly improved, which is conducive to improving product performance.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a three-dimensional chip and a preparation method thereof, and an electronic device. Background Art

[0002] As computing power requirements increase, CPUs (Central Processing Units), GPUs (Graphics Processing Units), and ASICs (Application Specific Integrated Circuits) are all facing the problem of a storage wall. For example, the data transmission bandwidth between the CPU and memory has become a bottleneck, affecting the improvement of overall processing capabilities.

[0003] Taking three-dimensional chips including logic chips and memory chips as an example, 3DIC (three-dimensional integrated circuit) technology connects logic chips and memory chips through three-dimensional bonding, thereby increasing storage capacity and storage bandwidth to a certain extent.

[0004] However, due to the limitation of Reticle (photolithography master) size, after the logic wafer and storage wafer are stacked and cut, the maximum size of the three-dimensional chip formed can only be the size of Reticle. This limits the storage bandwidth and storage capacity of the three-dimensional chip and affects the overall computing performance. Summary of the invention

[0005] The three-dimensional chip and its preparation method and electronic device provided in the present application can solve the problem that the three-dimensional chip is limited by the size of the reticle, which affects the product performance.

[0006] In order to solve the above technical problems, the first technical solution provided by the present application is: providing a three-dimensional chip, the three-dimensional chip comprising a first functional layer and a second functional layer three-dimensionally connected to the first functional layer;

[0007] Among them, the first functional layer has M first extreme exposure areas, each of which is formed by patterning a photolithography master; the second functional layer has N second extreme exposure areas, each of which is formed by patterning a photolithography master; wherein M and N are both integers greater than or equal to 2.

[0008] In one embodiment, the number of the first functional layer and the number of the second functional layer are both one.

[0009] In one embodiment, the number of the first functional layers is multiple, and the multiple first functional layers are stacked and three-dimensionally connected together;

[0010] And / or there are multiple second functional layers, and the multiple second functional layers are stacked and three-dimensionally connected together.

[0011] In one embodiment, a redistribution layer is further provided on the first functional layer and / or the second functional layer;

[0012] There are multiple first functional layers, and the first extreme exposure areas in two stacked and adjacent first functional layers are connected together in three dimensions via a redistribution layer;

[0013] And / or, there are a plurality of second functional layers, and the first limit exposure areas in two stacked and adjacent second functional layers are three-dimensionally connected via a redistribution layer;

[0014] And / or, the first extreme exposure region in the first functional layer and the second extreme exposure region in the second functional layer which are stacked and adjacent are connected together in three dimensions via a redistribution layer.

[0015] In one embodiment, the first limit exposure areas in the same first functional layer are interconnected by conductive wires;

[0016] The second limit exposure areas in the same second functional layer are interconnected by conductive wires.

[0017] In one embodiment, the M first limit exposure areas include a plurality of first functional areas and at least one first redundant area, and the first functional area and the first redundant area include the same functional unit;

[0018] The N second limit exposure areas include a plurality of second functional areas and at least one second redundant area, and the second functional areas and the second redundant areas include the same functional units.

[0019] In order to solve the above technical problems, the second technical solution provided in the present application is: to provide an electronic device, wherein the electronic device comprises the three-dimensional chip described in any one of the above items.

[0020] In one embodiment, the electronic device further includes a control circuit board and a conductive column connector, and the three-dimensional chip is electrically connected to the control circuit board via the conductive column connector.

[0021] In order to solve the above technical problems, the first technical solution provided by the present application is: to provide a method for preparing a three-dimensional chip, comprising:

[0022] providing a first semiconductor layer and a second semiconductor layer;

[0023] Using a photolithography master to pattern at least M first limit exposure regions on the first semiconductor layer, each of which is patterned by a photolithography master; and using a photolithography master to pattern at least N second limit exposure regions on the second semiconductor layer, each of which is patterned by a photolithography master; wherein M and N are both integers greater than or equal to 2;

[0024] The first semiconductor layer and the second semiconductor layer are three-dimensionally connected together.

[0025] In one embodiment, the preparation method further comprises:

[0026] Cutting the first semiconductor layer and the second semiconductor layer connected three-dimensionally to form a three-dimensional chip;

[0027] The three-dimensional chip formed after cutting includes a first functional layer and a second functional layer, the first functional layer has M first extreme exposure areas; the second functional layer has N second extreme exposure areas.

[0028] In one embodiment, the first semiconductor layer and the second semiconductor layer are three-dimensionally connected together to form a three-dimensional product, and the three-dimensional product is circular;

[0029] The step of cutting the first semiconductor layer and the second semiconductor layer connected three-dimensionally to form a three-dimensional chip comprises:

[0030] Determine an inscribed square area of ​​the circular three-dimensional product as an area to be cut;

[0031] The three-dimensional product is cut to obtain an inscribed square area of ​​the three-dimensional product as the three-dimensional chip.

[0032] The beneficial effects of the present application are different from those of the prior art. In the three-dimensional chip and its preparation method and electronic device provided by the present application, the three-dimensional chip includes a first functional layer and a second functional layer three-dimensionally connected to the first functional layer, and the first functional layer has M first extreme exposure areas, and the second functional layer has N second extreme exposure areas, wherein M and N are both integers greater than or equal to 2. Specifically, since each extreme exposure area is formed by patterning a photolithography master, the three-dimensional chip provided by the present application is larger in size, and more functional units can be set, and the first functional layer and the second functional layer are three-dimensionally connected together, the first functional layer and the second functional layer are directly connected, and the interconnection height is very low, so that the data delay of the signal transmission channel is reduced, and the data transmission speed is greatly improved, which is conducive to improving product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0034] Figure 1 It is a schematic diagram of the existing three-dimensional chip structure;

[0035] Figure 2 A schematic diagram of the structure of a three-dimensional chip provided in one embodiment of the present application;

[0036] Figure 3 A schematic diagram of the structure of a three-dimensional chip provided in another embodiment of the present application;

[0037] Figure 4 A schematic diagram of a process for preparing a three-dimensional chip provided in one embodiment of the present application;

[0038] Figure 5 A schematic diagram of a process for preparing a three-dimensional chip provided in another embodiment of the present application;

[0039] Figure 6 for Figure 5 A schematic flow chart of an embodiment of step S4;

[0040] Figure 7 for Figure 4 A schematic diagram of an intermediate product of an embodiment after step S1;

[0041] Figure 8 for Figure 4 A schematic diagram of an intermediate product of an embodiment after step S2;

[0042] Fig. 9 for Figure 4 A schematic diagram of an intermediate product of an embodiment after step S3;

[0043] Fig.10 for Figure 5 A schematic diagram of an intermediate product of an embodiment after step S4;

[0044] Fig.11 for Figure 5 A schematic diagram of an intermediate product of another embodiment after step S4;

[0045] Fig.12 A structural block diagram of an electronic device provided in one embodiment of the present application;

[0046] Fig.13 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0047] The terms "first", "second" and "third" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0048] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] See also Figure 1 , Figure 1 It is a schematic diagram of the existing three-dimensional chip structure. Specifically, Figure 1 The wafer-level three-dimensional advanced packaging technology (3DIC technology) is used to stack the logic chip 1 and the storage (DRMA) chip 2 to form a three-dimensional chip, thereby improving the storage capacity and storage bandwidth of the chip to a certain extent.

[0051] However, during the preparation process, due to the limitation of the size of the Reticle (photolithography master), after the logic wafer and the storage wafer are stacked, the maximum size of the three-dimensional chip formed after cutting can only be the size of the Reticle. This limits the storage bandwidth and storage capacity of the three-dimensional chip, affecting the overall computing performance.

[0052] To solve the above problems, the present application provides a three-dimensional chip that can avoid the limitation of Reticle (photolithography master) size and eliminate the need to cut the stacked logic wafers and storage wafers into small three-dimensional chips to avoid affecting the storage bandwidth and storage capacity of the three-dimensional chip, thereby avoiding affecting the overall computing performance of the product.

[0053] See also Figure 2 and Figure 3 , Figure 2 A schematic diagram of the structure of a three-dimensional chip provided in one embodiment of the present application; Figure 3 A schematic diagram of the structure of a three-dimensional chip provided in another embodiment of the present application.

[0054] The three-dimensional chip 100 provided in the present application includes a first functional layer 10 and a second functional layer 20 three-dimensionally connected to the first functional layer 10 .

[0055] Specifically, the first functional layer 10 and the second functional layer 20 are stacked and three-dimensionally connected through the 3D structure 30. The first functional layer 10 has M first limit exposure areas 11, each of which is formed by patterning a photolithography master; the second functional layer 20 has N second limit exposure areas 21, each of which is formed by patterning a photolithography master; wherein M and N are both integers greater than or equal to 2.

[0056] Specifically, each extreme exposure region on the first functional layer 10 and the second functional layer 20 is formed by patterning a photolithography master. Therefore, a first extreme exposure region 11 in the three-dimensional chip 100 provided by the present application and a second extreme exposure region 21 three-dimensionally connected to the first extreme exposure region 11 can be equivalent to a three-dimensional chip in the prior art. In the three-dimensional chip 100 provided by the present application, the first functional layer 10 has M first extreme exposure regions 11, and the second functional layer 20 has N second extreme exposure regions 21, and M and N are both integers greater than or equal to 2. Therefore, the size of the three-dimensional chip 100 provided by the present application is larger and more functional units can be set. In addition, the first functional layer 10 and the second functional layer 20 are three-dimensionally connected together, the first functional layer 10 and the second functional layer 20 are directly connected, and the interconnection height is very low, so that the data delay of the signal transmission channel is reduced, and the data transmission speed is greatly improved, which is conducive to improving the performance of the product.

[0057] The number of M and N may be the same or different. For example, when the number of the first extreme exposure areas 11 and the second extreme exposure areas 21 is the same, one first extreme exposure area 11 is three-dimensionally connected to the second extreme exposure area 21 in a one-to-one correspondence; for another example, when the number of the first extreme exposure areas 11 is greater than the number of the second extreme exposure areas 21, one first extreme exposure area 11 may be three-dimensionally connected to one or more second extreme exposure areas 21 through a redistribution layer; for another example, when the number of the first extreme exposure areas 11 is less than the number of the second extreme exposure areas 21, one second extreme exposure area 21 may be three-dimensionally connected to one or more first extreme exposure areas 11 through a redistribution layer. This is not limited here.

[0058] In some embodiments, the first functional layer 10 and the second functional layer 20 include but are not limited to a storage chip layer, a logic chip layer, a communication chip layer, a power management chip layer, etc., and the functional design of the functional layer is performed according to actual needs.

[0059] For ease of description, in the embodiment of the present application, the first functional layer 10 is taken as a storage chip layer, and the second functional layer 20 is taken as a logic chip layer as an example.

[0060] Specifically, when the first functional layer 10 is a storage chip layer, since each first extreme exposure area 11 includes at least one storage chip unit (the specific number is designed based on the storage capacity of the storage chip unit), the M first extreme exposure areas 11 in the first functional layer 10 can provide a larger storage capacity, thereby improving the storage bandwidth of the three-dimensional chip 100.

[0061] For example, taking the design storage capacity of a first extreme exposure area 11 as 8G, when the storage capacity of each memory chip unit is 1G, each first extreme exposure area 11 may include at most 8 memory chip units; when the storage capacity of each memory chip unit is 512MB, each first extreme exposure area 11 may include at most 16 memory chip units, and so on.

[0062] When the second functional layer 20 is a logic chip layer, the N second limit exposure regions 21 in the second functional layer 20 can provide computing logics of more standard cells (logic chip units), thereby improving the computing capability of the three-dimensional chip 100 .

[0063] Among them, a memory chip unit on the memory chip layer can be three-dimensionally connected with a logic chip unit on the logic chip layer; or multiple memory chip units on the memory chip layer can be three-dimensionally connected with a logic chip unit on the logic chip layer through a redistribution layer; or multiple logic chip units on the logic chip layer can be three-dimensionally connected with a memory chip unit on the memory chip layer through a redistribution layer. No limitation is made here.

[0064] In some embodiments, in order to avoid the failure of the functional units corresponding to some of the M first extreme exposure areas 11 in the first functional layer 10, or to avoid the failure of the functional units corresponding to some of the N second extreme exposure areas 21 in the second functional layer 20, which results in the three-dimensional chip being unable to be used normally, the present application sets the M first extreme exposure areas 11 to include multiple first functional areas and at least one first redundant area, and the first functional area and the first redundant area include the same functional units; the N second extreme exposure areas include multiple second functional areas and at least one second redundant area, and the second functional area and the second redundant area include the same functional units. In this way, the functional units in the first redundant area can replace the functional units in the failed first functional area to continue to execute the corresponding instructions, and the functional units in the second redundant area can replace the functional units in the failed second functional area to continue to execute the corresponding instructions, thereby improving the reliability of the three-dimensional chip.

[0065] For example, the first functional area and the first redundant area both include storage chip units. By setting the storage chip layer to include at least one first redundant area, when the storage chip unit corresponding to the first functional area fails, the storage chip unit corresponding to the first redundant area can replace the failed storage chip unit corresponding to the first functional area, thereby avoiding affecting the function of the entire three-dimensional chip.

[0066] For another example, the second functional area and the second redundant area both include logic chip units. By setting the logic chip layer to include at least one second redundant area, when the logic chip unit corresponding to the second functional area fails, the logic chip unit corresponding to the second redundant area can replace the failed logic chip unit corresponding to the second functional area, thereby avoiding affecting the function of the entire three-dimensional chip.

[0067] In one embodiment, a logic chip unit can three-dimensionally connect several storage chip units in the first functional area and at least one storage chip unit in the first redundant area, so that when the storage chip unit in the first functional area fails, the logic chip unit connected to it can call the storage chip unit in the first redundant area to take over and continue to perform read and write functions.

[0068] In one embodiment, if Figure 2As shown, the number of the first functional layer 10 and the number of the second functional layer 20 are both one. One first functional layer 10 is connected to one second functional layer 20 in three dimensions.

[0069] In another embodiment, see Figure 3 , the number of the first functional layers 10 is multiple, and the multiple first functional layers 10 are stacked and connected together in three dimensions. In this embodiment, the number of the second functional layers 20 can be one or more, and when the number of the second functional layers 20 is multiple, the multiple second functional layers 20 are stacked and connected together in three dimensions.

[0070] Specifically, the number of the first functional layers 10 is set to be multiple, and the multiple first functional layers 10 can provide more first limit exposure areas 11, thereby providing a larger storage capacity for the three-dimensional chip 100.

[0071] In another embodiment, please continue to see Figure 3 , the number of the second functional layers 20 is multiple, and the multiple second functional layers 20 are stacked and connected together in three dimensions. In this embodiment, the number of the first functional layers 10 can be one or more, and when the number of the first functional layers 10 is multiple, the multiple first functional layers 10 are stacked and connected together in three dimensions.

[0072] Specifically, the number of the second functional layers 20 is set to be multiple, and the multiple second functional layers 20 can provide more second limit exposure areas 21, and further can provide more standard unit (cell) computing logic for the three-dimensional chip 100, thereby improving the performance of the three-dimensional chip 100.

[0073] Among them, in traditional chip packaging, the I / O interface is often located at the edge of the chip, but in this application, due to the three-dimensional connection between the first functional layer 10 and the first functional layer 10, between the second functional layer 20 and the second functional layer 20, and between the first functional layer 10 and the second functional layer 20, the traditional I / O interface layout may no longer be applicable. Therefore, in one embodiment of the present application, a redistribution layer (RDL) is also provided on the first functional layer 10 and / or the second functional layer 20 (not shown). RDL technology can serve as a bridge between different functional layers to achieve high-speed signal transmission and power distribution from functional layer to functional layer.

[0074] In some embodiments, when the number of the first functional layers 10 is multiple, the first extreme exposure areas 11 in two stacked and adjacent first functional layers 10 are connected together through a redistribution layer and three-dimensional connection. For example, at least one of the two stacked and adjacent first functional layers 10 is provided with a redistribution layer on the surface close to each other, and the redistribution layer re-layouts the I / O interface of the first extreme exposure area 11 in the first functional layer 10 to a specific area, thereby facilitating the three-dimensional connection between the first extreme exposure areas 11 in the two adjacent first functional layers 10. Specifically, the first extreme exposure areas 11 in two stacked and adjacent first functional layers 10 are connected together through a redistribution layer and three-dimensional connection, thereby realizing data transmission between the first extreme exposure areas 11 in different first functional layers 10.

[0075] And / or, when the number of the second functional layers 20 is multiple, the second extreme exposure areas 21 in two stacked and adjacent second functional layers 20 are connected together through a redistribution layer and three-dimensional connection. For example, at least one of the two stacked and adjacent second functional layers 20 is provided with a redistribution layer on the surface close to the other, and the redistribution layer re-layouts the I / O interface of the second extreme exposure area 21 in the second functional layer 20 to a specific area, thereby facilitating the three-dimensional connection between the second extreme exposure areas 21 in the two adjacent second functional layers 20. Specifically, the second extreme exposure areas 21 in two stacked and adjacent second functional layers 20 are connected together through a redistribution layer and three-dimensional connection, thereby realizing data transmission between the second extreme exposure areas 21 in different second functional layers 20.

[0076] And / or, the first extreme exposure area 11 in the stacked and adjacent first functional layer 10 and the second extreme exposure area 21 in the second functional layer 20 are connected together through a redistribution layer and three-dimensional connection. For example, at least one of the adjacent first functional layer 10 and the second functional layer 20 is provided with a redistribution layer on the surface close to each other, and the redistribution layer re-layouts the I / O interface of the second extreme exposure area 21 in the second functional layer 20 to a specific area, or the redistribution layer re-layouts the I / O interface of the first extreme exposure area 11 in the first functional layer 10 to a specific area, thereby facilitating the first extreme exposure area 11 in the adjacent first functional layer 10 and the second extreme exposure area 21 in the second functional layer 20 to be connected together through three-dimensional connection. Specifically, the first extreme exposure area 11 in the adjacent first functional layer 10 and the second extreme exposure area 21 in the second functional layer 20 are connected through a redistribution layer and three-dimensional connection, thereby realizing data transmission between the first extreme exposure area 11 and the second extreme exposure area 21.

[0077] Among them, RDL interconnection technology can not only optimize I / O layout and increase packaging density, but also improve signal integrity, reduce parasitic effects, and enhance electrical performance. In addition, RDL also supports heterogeneous integration, that is, integrating different types of functional layers in one package and achieving efficient interconnection between them through RDL, thereby building more complex functional modules.

[0078] In some embodiments, the three-dimensional connection includes hybrid bonding and / or micro bump bonding.

[0079] For example, when there are multiple first functional layers 10, the first extreme exposure areas 11 in two adjacent first functional layers 10 are connected together by hybrid bonding; or the first extreme exposure areas 11 in two adjacent first functional layers 10 are connected together by micro-bump bonding; or the first extreme exposure areas 11 in some adjacent first functional layers 10 are connected together by hybrid bonding, and the first extreme exposure areas 11 in some adjacent first functional layers 10 are connected together by micro-bump bonding.

[0080] For another example, when the number of second functional layers 20 is multiple, the second extreme exposure areas 21 in two adjacent second functional layers 20 are connected together by hybrid bonding; or the second extreme exposure areas 21 in two adjacent second functional layers 20 are connected together by micro-bump bonding; or the second extreme exposure areas 21 in some adjacent second functional layers 20 are connected together by hybrid bonding, and the second extreme exposure areas 21 in some adjacent second functional layers 20 are connected together by micro-bump bonding.

[0081] For another example, the first extreme exposure area 11 in the adjacent first functional layer 10 and the second extreme exposure area 21 in the second functional layer 20 are connected together by hybrid bonding; or the first extreme exposure area 11 in the adjacent first functional layer 10 and the second extreme exposure area 21 in the second functional layer 20 are connected together by micro-bump bonding.

[0082] Among them, hybrid bonding is an advanced integrated circuit packaging technology. Its core feature is the use of direct copper-to-copper (Cu-Cu) connection to achieve high-density, high-performance chip-to-chip interconnection in a very small space. This enables the three-dimensional chip 100 to integrate more functions in a smaller size, improves the performance of the integrated circuit and reduces power consumption. In addition, this technology also supports finer interconnection spacing, which is critical for high-performance applications such as high-bandwidth memory.

[0083] Among them, micro-bump bonding is a very small three-dimensional structure used for electrical connection, usually with a diameter of several microns to tens of microns. They play a key role in the interconnection between the functional layer and the substrate, and between the functional layers.

[0084] Specifically, in the present application, the stacked and adjacent functional layers (the first functional layer 10, the second functional layer 20) are connected together by hybrid bonding and / or micro-bump bonding, so that the stacked and adjacent functional layers are directly connected, and the interconnection height is very low, thereby reducing the data delay of the signal transmission channel, greatly improving the data transmission speed, and increasing the storage bandwidth of the three-dimensional chip 100, which is beneficial to improving the performance of the product.

[0085] For further information, see Figure 2 or Figure 3 In the embodiment of the present application, the first extreme exposure regions 11 in the same first functional layer 10 are interconnected by conductive wires 40 to achieve data transmission between different first extreme exposure regions 11 in the same first functional layer 10. The second extreme exposure regions 21 in the same second functional layer 20 are interconnected by conductive wires 40 to achieve data transmission between different second extreme exposure regions 21 in the same second functional layer 20.

[0086] Specifically, the conductive wire 40 may be a metal connecting wire made on the functional layer. The material of the metal connecting wire may be one of copper, aluminum, silver and gold or an alloy thereof, which is not limited here and can be selected according to actual needs.

[0087] Specifically, in the three-dimensional chip 100 provided by the present application, the first functional layer 10 has M first extreme exposure areas 11, and the second functional layer 20 has N second extreme exposure areas 21. Each first extreme exposure area 11 and each second extreme exposure area 21 are formed by patterning a photolithography master, and M and N are both integers greater than or equal to 2. Therefore, the three-dimensional chip 100 provided by the present application is larger in size, and the M first extreme exposure areas 11 in the first functional layer 10 can provide a larger storage capacity, and the N second extreme exposure areas 21 in the second functional layer 20 can provide the computing logic of more standard units (cells), which can improve the computing power of the three-dimensional chip 100, and the first functional layer 10 and the second functional layer 20 are three-dimensionally connected together, the first functional layer 10 and the second functional layer 20 are directly connected, and the interconnection height is very low, so that the data delay of the signal transmission channel is reduced, the data transmission speed is greatly improved, and the storage bandwidth of the three-dimensional chip 100 is improved, which is beneficial to improve the performance of the product.

[0088] See also Figure 4-Figure 11 , Figure 4 A schematic diagram of a process for preparing a three-dimensional chip provided in one embodiment of the present application; Figure 5A schematic diagram of a process for preparing a three-dimensional chip provided in another embodiment of the present application; Figure 6 for Figure 5 A schematic flow chart of an embodiment of step S4; Figure 7 for Figure 4 A schematic diagram of an intermediate product of an embodiment after step S1; Figure 8 for Figure 4 A schematic diagram of an intermediate product of an embodiment after step S2; Fig. 9 for Figure 4 A schematic diagram of an intermediate product of an embodiment after step S3; Fig.10 for Figure 5 A schematic diagram of an intermediate product of an embodiment after step S4; Fig.11 for Figure 5 Schematic diagram of an intermediate product of another embodiment after step S4.

[0089] For details, see Figure 3 The present application also provides a method for preparing a three-dimensional chip 100, comprising:

[0090] Step S1: providing a first semiconductor layer 101 and a second semiconductor layer 102 .

[0091] For details, please see Figure 7 .

[0092] Specifically, the first semiconductor layer 101 and the second semiconductor layer 102 may be wafers or chips.

[0093] It should be noted that, in the embodiment of the present application, the sizes of the cuttable regions of the first semiconductor layer 101 and the second semiconductor layer 102 are both greater than or equal to the sizes of two photolithography masters (Reticles).

[0094] In some embodiments, the number of the first semiconductor layer 101 and the second semiconductor layer 102 may both be one; or the number of the first semiconductor layer 101 and the second semiconductor layer 102 may both be multiple; or the number of the first semiconductor layer 101 may be one; the number of the second semiconductor layer 102 may be multiple; or the number of the second semiconductor layer 102 may be one; the number of the first semiconductor layer 101 may be multiple. This is not limited here, and the present application takes the example that the number of the first semiconductor layer 101 and the second semiconductor layer 102 are both one as an example for description.

[0095] Step S2: Using a photolithography master to pattern at least M first extreme exposure areas 11 on the first semiconductor layer 101, each first extreme exposure area 11 is formed by patterning a photolithography master; and using a photolithography master to pattern at least N second extreme exposure areas 21 on the second semiconductor layer 102, each second extreme exposure area 21 is formed by patterning a photolithography master, wherein M and N are both integers greater than or equal to 2.

[0096] For details, please see Figure 8 . The number of M and N can be the same or different.

[0097] Specifically, patterning the at least M first limit exposure regions 11 on the first semiconductor layer 101 may be to use one photomask to sequentially form the at least M first limit exposure regions 11 on the first semiconductor layer 101; or may be to use X photomasks to simultaneously pattern the at least M first limit exposure regions 11 on the first semiconductor layer 101. Wherein, X is an integer, and X is greater than or equal to M.

[0098] The at least N second limit exposure regions 21 are patterned on the second semiconductor layer 102, which may be formed by sequentially forming the at least N second limit exposure regions 21 on the second semiconductor layer 102 using one photomask; or the at least N second limit exposure regions 21 are simultaneously patterned on the second semiconductor layer 102 using Y photomasks, where Y is an integer and is greater than or equal to N.

[0099] In one embodiment, step S2 also includes: the first extreme exposure areas 11 in the same first semiconductor layer 101 are interconnected by conductive wires 40 to achieve data transmission between different first extreme exposure areas 11 in the same first semiconductor layer 101; and the second extreme exposure areas 21 in the same second semiconductor layer 102 are interconnected by conductive wires 40 to achieve data transmission between different second extreme exposure areas 21 in the same second semiconductor layer 102.

[0100] Step S3: connecting the first semiconductor layer 101 and the second semiconductor layer 102 together in three dimensions.

[0101] For details, please see Fig. 9 .

[0102] The first semiconductor layer 101 and the second semiconductor layer 102 are three-dimensionally connected via the 3D structure 30 .

[0103] Specifically, when there are multiple first semiconductor layers 101, multiple first semiconductor layers 101 are stacked, and the first extreme exposure regions 11 in two adjacent first semiconductor layers 101 are three-dimensionally connected to achieve data transmission between the first extreme exposure regions 11 in different first semiconductor layers 101. When there are multiple second semiconductor layers 102, multiple second semiconductor layers 102 are stacked, and the second extreme exposure regions 21 in two adjacent second semiconductor layers 102 are three-dimensionally connected to achieve data transmission between the second extreme exposure regions 21 in different second semiconductor layers 102.

[0104] Furthermore, the stacked and adjacent first extreme exposure region 11 in the first semiconductor layer 101 and the second extreme exposure region 21 in the second semiconductor layer 102 are three-dimensionally connected together to achieve data transmission between the first extreme exposure region 11 and the second extreme exposure region 21 .

[0105] In some embodiments, a redistribution layer (RDL) (not shown) is further disposed on the first semiconductor layer 101 and / or the second semiconductor layer 102. Specifically, the RDL technology can serve as a bridge between different semiconductor layers to achieve high-speed signal transmission and power distribution from semiconductor layer to semiconductor layer.

[0106] Specifically, the redistribution layer is used to rearrange the I / O interface of the first extreme exposure area 11 in the first semiconductor layer 101 to a specific area, and to rearrange the I / O interface of the second extreme exposure area 21 in the second semiconductor layer 102 to a specific area, thereby facilitating the storage of three-dimensional connections between the first semiconductor layer 101 and the first semiconductor layer 101, the second semiconductor layer 102 and the second semiconductor layer 102, and the first semiconductor layer 101 and the second semiconductor layer 102, thereby realizing data transmission between different semiconductor layers.

[0107] In some embodiments, the three-dimensional connection includes hybrid bonding and / or micro bump bonding. Specifically, in the present application, the stacked and adjacent semiconductor layers (the first semiconductor layer 101, the second semiconductor layer 102) are connected together by hybrid bonding and / or micro bump bonding, so that the stacked and adjacent semiconductor layers are directly connected, and the interconnection height is very low, thereby reducing the data delay of the signal transmission channel, greatly improving the data transmission speed, and thus helping to improve the performance of the product.

[0108] Specifically, in the preparation method of the three-dimensional chip 100 provided in the present application, each first extreme exposure area 11 on the first semiconductor layer 101 and each second extreme exposure area 21 on the second semiconductor layer 102 are formed by patterning a photolithography master, and M and N are both integers greater than or equal to 2. Therefore, the three-dimensional chip 100 prepared by the present application is larger in size and can be provided with more functional units. The first semiconductor layer 101 and the second semiconductor layer 102 are three-dimensionally connected together, the first semiconductor layer 101 and the second semiconductor layer 102 are directly connected, and the interconnection height is very low, so that the data delay of the signal transmission channel is reduced, and the data transmission speed is greatly improved, which is beneficial to improving the performance of the product.

[0109] In one embodiment, see Figure 5 , the preparation method further comprises:

[0110] Step S4 : cutting the first semiconductor layer 101 and the second semiconductor layer 102 that are three-dimensionally connected together to form a three-dimensional chip 100 .

[0111] For details, see Fig.10 , the three-dimensionally connected first semiconductor layer 101 and the second semiconductor layer 102 can be cut to cut out a largest three-dimensional chip 100; or, see Fig.11 The three-dimensionally connected first semiconductor layer 101 and the second semiconductor layer 102 can be cut to obtain at least two three-dimensional chips 100. Fig. 9 3 are shown.

[0112] Among them, the three-dimensional chip 100 formed after cutting includes a first functional layer 10 and a second functional layer 20, the area of ​​the first semiconductor layer 101 corresponding to the three-dimensional chip 100 serves as the first functional layer 10 of the three-dimensional chip 100, and the first functional layer 10 has M first extreme exposure areas 11; the area of ​​the second semiconductor layer 102 corresponding to the three-dimensional chip 100 serves as the second functional layer 20 of the three-dimensional chip 100, and the second functional layer 20 has N second extreme exposure areas 21.

[0113] In one embodiment, the first semiconductor layer 101 and the second semiconductor layer 102 are three-dimensionally connected together to form a three-dimensional product, and the three-dimensional product is circular; see Figure 6 , step S4 specifically includes:

[0114] Step S41: determining an inscribed square area of ​​the circular three-dimensional product as the area to be cut.

[0115] Step S42 : cutting the three-dimensional product to obtain an inscribed square area of ​​the three-dimensional product as the three-dimensional chip 100 .

[0116] See Fig.10It can be understood that the inscribed square area of ​​the circular three-dimensional product is cut out as the three-dimensional chip 100, and the obtained three-dimensional chip 100 is the largest chip in the three-dimensional product. When the first functional layer 10 in the three-dimensional chip 100 is a storage chip layer and the second functional layer 20 is a logic chip layer, the three-dimensional chip 100 can provide a larger storage capacity and more standard cell computing logic, which can improve the computing power of the three-dimensional chip 100, and the first functional layer 10 and the second functional layer 20 are three-dimensionally connected together, the first functional layer 10 and the second functional layer 20 are directly connected, and the interconnection height is very low, so that the data delay of the signal transmission channel is reduced, the data transmission speed is greatly improved, and the storage bandwidth of the three-dimensional chip 100 is improved, which is conducive to improving the performance of the product.

[0117] Specifically, in the preparation method of the three-dimensional chip 100 provided in the present application, in the formed three-dimensional chip 100, the first functional layer 10 has M first extreme exposure areas 11, and the second functional layer 20 has N second extreme exposure areas 21, each first extreme exposure area 11 and each second extreme exposure area 21 are formed by patterning a photolithography master, and M and N are both integers greater than or equal to 2. Therefore, the three-dimensional chip 100 prepared by the present application is larger in size and can be provided with more functional units, and the first functional layer 10 and the second functional layer 20 are three-dimensionally connected together, the first functional layer 10 and the second functional layer 20 are directly connected, and the interconnection height is very low, so that the data delay of the signal transmission channel is reduced, and the data transmission speed is greatly improved, which is beneficial to improve the performance of the product.

[0118] See also Fig.12 , Fig.12 A structural block diagram of an electronic device provided in one embodiment of the present application.

[0119] The present application also provides an electronic device 1000, which includes the three-dimensional chip 100 provided by any of the above embodiments.

[0120] Specifically, the three-dimensional chip 100 can be set in a small or large electronic device 1000 as a storage device or a microprocessor device (CPU (Central Processing Unit, central processing unit), GPU (Graphics Processing Unit, graphics processor), ASIC (Application Specific Integrated Circuit)), etc., wherein the electronic device 1000 can be applied to intelligent manufacturing, information communication, chip semiconductors and other fields, and the embodiments of the present application are not specifically limited.

[0121] See also Fig.13 , Fig.13This is a structural schematic diagram of an electronic device provided in one embodiment of the present application. In one embodiment, the electronic device 1000 also includes a control circuit board 200 and a conductive column connector 300, and the three-dimensional chip 100 is electrically connected to the control circuit board 200 through the conductive column connector 300.

[0122] In some embodiments, the material of the conductive column connector 300 includes, but is not limited to, conductive materials such as copper, aluminum, silver, and gold. In addition, the present application sets the three-dimensional chip 100 and the control circuit board 200 to be connected through the conductive column connector 300. Compared with the traditional packaging technology, the interconnection height between the three-dimensional chip 100 and the control circuit board 200 is very low, thereby reducing the data delay of the signal transmission channel, greatly improving the data transmission speed, and thus helping to improve the performance of the product.

[0123] The above is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A three-dimensional chip, characterized in that: The three-dimensional chip is obtained by cutting a three-dimensional product, and the three-dimensional product is circular. The three-dimensional chip is an inscribed square area of ​​the three-dimensional product. The three-dimensional product includes a first semiconductor layer and a second semiconductor layer connected three-dimensionally. The three-dimensional chip includes a first functional layer and a second functional layer connected three-dimensionally to the first functional layer. The first functional layer has M first limit exposure regions, each of which is formed by patterning a photolithography master; the second functional layer has N second limit exposure regions, each of which is formed by patterning a photolithography master; wherein M and N are both integers greater than or equal to 2; Wherein, the first limit exposure areas in the same first functional layer are interconnected by conductive wires; The second limit exposure areas in the same second functional layer are interconnected by conductive wires; The M first limit exposure areas include a plurality of first functional areas and at least one first redundant area, and the first functional area and the first redundant area include the same functional unit; The N second limit exposure areas include a plurality of second functional areas and at least one second redundant area, and the second functional areas and the second redundant areas include the same functional units.

2. The three-dimensional chip according to claim 1, characterized in that: The number of the first functional layer and the number of the second functional layer are both one.

3. The three-dimensional chip according to claim 1, characterized in that: There are multiple first functional layers, and the multiple first functional layers are stacked and three-dimensionally connected together; And / or there are multiple second functional layers, and the multiple second functional layers are stacked and three-dimensionally connected together.

4. The three-dimensional chip according to claim 1, characterized in that: A redistribution layer is further provided on the first functional layer and / or the second functional layer; There are multiple first functional layers, and the first extreme exposure areas in two stacked and adjacent first functional layers are connected together in three dimensions via a redistribution layer; And / or, there are a plurality of second functional layers, and the first limit exposure areas in two stacked and adjacent second functional layers are three-dimensionally connected via a redistribution layer; And / or, the first extreme exposure region in the first functional layer and the second extreme exposure region in the second functional layer which are stacked and adjacent are connected together in three dimensions via a redistribution layer.

5. An electronic device, characterized in that: The electronic device comprises the three-dimensional chip described in any one of claims 1 to 4 above.

6. The electronic device according to claim 5, characterized in that: The electronic device further comprises a control circuit board and a conductive column connector, and the three-dimensional chip is electrically connected to the control circuit board via the conductive column connector.

7. A method for preparing a three-dimensional chip, characterized in that: include: providing a first semiconductor layer and a second semiconductor layer; At least M first limit exposure regions are patterned on the first semiconductor layer using a photolithography master, each of which is patterned by a photolithography master, wherein the M first limit exposure regions include a plurality of first functional regions and at least one first redundant region, and the first functional region and the first redundant region include the same functional unit; and at least N second limit exposure regions are patterned on the second semiconductor layer using a photolithography master, each of which is patterned by a photolithography master, wherein the N second limit exposure regions include a plurality of second functional regions and at least one second redundant region, and the second functional region and the second redundant region include the same functional unit; wherein M and N are both integers greater than or equal to 2; Connecting the first semiconductor layer and the second semiconductor layer three-dimensionally to form a three-dimensional product, wherein the three-dimensional product is circular; Cutting the first semiconductor layer and the second semiconductor layer connected three-dimensionally to form a three-dimensional chip; The three-dimensional chip formed after cutting includes a first functional layer and a second functional layer, the first functional layer has M first limit exposure areas; the second functional layer has N second limit exposure areas; The step of cutting the first semiconductor layer and the second semiconductor layer connected three-dimensionally to form a three-dimensional chip comprises: Determine an inscribed square area of ​​the circular three-dimensional product as an area to be cut; The three-dimensional product is cut to obtain an inscribed square area of ​​the three-dimensional product as the three-dimensional chip.

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