Three-dimensional gallium nitride-based CMOS inverter and preparation method thereof

Abstract

The present invention provides a three-dimensional gallium nitride-based CMOS inverter and a preparation method thereof, wherein the CMOS inverter comprises: a three-dimensional substrate, a plurality of devices arranged at intervals on the outer surface of the three-dimensional substrate, and an interconnection dielectric layer covering the devices and the exposed surface of the three-dimensional substrate; a plurality of interconnection metals are fixed inside and outside the interconnection dielectric layer; the devices comprise an NMOS device and a PMOS device arranged at intervals, an interconnection metal electrically connects the gate of the NMOS device with the gate of the PMOS device, and is led out of the interconnection dielectric layer; the source of the NMOS device is led out of the interconnection dielectric layer through an interconnection metal; the drain of the NMOS device is electrically connected to the drain of the PMOS device. The CMOS inverter in the present invention liberates the thermal limitation of the CMOS inverter, and by arranging a plurality of devices at intervals on the three-dimensional substrate, a CMOS inverter with high integration, high power density, high current density and support for higher frequencies is formed, so that the application range of the CMOS inverter is wider.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a three-dimensional gallium nitride-based CMOS inverter. Background Art

[0002] Gallium nitride is one of the most important semiconductors for power applications. It has a relatively large bandgap and breakdown electric field, and can achieve high voltage, high current and stable device operation. The CMOS inverter is an inverter with extremely low static power consumption, low dynamic power consumption, strong anti-interference ability, and no potential difference inside, which is not prone to drift and has strong stability. Gallium nitride-based CMOS inverters have the above advantages and are widely used. With the rapid development of the power electronics field, the requirements for electronic components have become more stringent. Researchers have continuously improved the integration of CMOS inverters to obtain gallium nitride-based CMOS inverters with lower power consumption. However, the integration of CMOS inverters is limited by the heat dissipation capacity of their substrates. With the increase in integration, the heat dissipation problem of CMOS inverters has become increasingly prominent. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a three-dimensional gallium nitride-based CMOS inverter, aiming to solve the problem that the gallium nitride CMOS inverter in the related art is limited by the heat dissipation capability and low integration.

[0004] To solve the above technical problems, the present invention is implemented as follows: a three-dimensional gallium nitride-based CMOS inverter, comprising: a three-dimensional substrate, a plurality of devices spaced apart on the outer surface of the three-dimensional substrate, and an interconnect dielectric layer covering the devices and the exposed surface of the three-dimensional substrate;

[0005] A plurality of interconnect metals are fixed inside and outside the interconnect dielectric layer;

[0006] The device includes an NMOS device and a PMOS device that are arranged at intervals, an interconnect metal electrically connects the gate of the NMOS device with the gate of the PMOS device and is led out of the interconnect dielectric layer; the source of the NMOS device is led out of the interconnect dielectric layer through the interconnect metal; and the drain of the NMOS device is electrically connected to the drain of the PMOS device.

[0007] Furthermore, the three-dimensional substrate is in the shape of a sphere, a polyhedron or a cylinder.

[0008] Furthermore, the three-dimensional substrate is a diamond or boron nitride substrate.

[0009] Furthermore, a substrate dielectric or an interconnect dielectric is filled between the NMOS device and the PMOS device to connect the NMOS device to the PMOS device, and the drain of the NMOS device and the drain of the PMOS device are formed by integral growth.

[0010] Further, the NMOS device includes a first dielectric layer, a first GaN buffer layer, a p-GaN channel layer, at least two n-GaN well layers, a first gate dielectric layer, an NMOS source, an NMOS drain and an NMOS gate;

[0011] The first dielectric layer is arranged on the surface of the three-dimensional substrate; the first GaN buffer layer is arranged on the surface of the first dielectric layer away from the three-dimensional substrate; the p-GaN channel layer is arranged on the surface of the first GaN buffer layer away from the first dielectric layer; the n-GaN well layer is arranged at intervals on the surface of the p-GaN channel layer away from the first GaN buffer layer; the first gate dielectric layer covers between the two n-GaN well layers and covers part of the n-GaN well layer; the NMOS source and the NMOS drain are respectively arranged on the surfaces of the two n-GaN well layers; the NMOS gate is arranged on the surface of the first gate dielectric layer.

[0012] Furthermore, the PMOS device includes a second dielectric layer, a second GaN buffer layer, an n-GaN channel layer, at least two p-GaN well layers, a second gate dielectric layer, a PMOS source, a PMOS drain and a PMOS gate; the second dielectric layer is arranged on the surface of the three-dimensional substrate; the second GaN buffer layer is arranged on the surface of the second dielectric layer away from the three-dimensional substrate; the n-GaN channel layer is arranged on the surface of the second GaN buffer layer away from the second dielectric layer; the p-GaN well layer is arranged on the surface of the n-GaN channel layer away from the second GaN buffer layer; the second gate dielectric layer covers between the two p-GaN well layers and covers part of the p-GaN well layer; the PMOS source and the PMOS drain are respectively arranged on the surfaces of the two p-GaN well layers; the PMOS gate is arranged on the surface of the second gate dielectric layer.

[0013] Furthermore, the first GaN buffer layer and the second GaN buffer layer use C as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 ;

[0014] The p-GaN channel layer uses Si or C as a dopant with a doping concentration of 1×10 18 cm -3~3×10 18 cm -3 The n-GaN channel layer uses Mg as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 ;

[0015] The n-GaN well layer uses Si as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 The p-GaN well layer uses Mg as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 .

[0016] Furthermore, the materials of the first dielectric layer and the second dielectric layer are AlN, SiO 2 or Si 3 N 4 In any one of the above, the thickness is 20 to 50 nm.

[0017] Furthermore, the material of the interconnect dielectric layer is AlN, SiO 2 or Si 3 N 4 Any one of the following, with a thickness of 1 to 5 μm.

[0018] The present invention also provides a method for preparing a three-dimensional gallium nitride-based CMOS inverter, comprising the steps of:

[0019] Preparing a three-dimensional substrate, sequentially forming a dielectric layer and a GaN buffer layer on the surface of the three-dimensional substrate, wherein the surface of the three-dimensional substrate has a plurality of device regions arranged at intervals;

[0020] Growing a p-GaN channel layer and an n-GaN channel layer at intervals on the GaN buffer layer;

[0021] Etching the p-GaN channel layer, the n-GaN channel layer, the GaN buffer layer and the dielectric layer in the non-device area on the surface of the three-dimensional substrate to expose the surface of the non-device area of ​​the three-dimensional substrate;

[0022] On each of the device regions, etching is performed along the contact between the p-GaN channel layer and the n-GaN channel layer until the surface of the three-dimensional substrate is exposed, so that the GaN buffer layer is separated to form a first GaN buffer layer located below the p-GaN channel layer and a second GaN buffer layer located below the n-GaN channel layer;

[0023] In each of the device regions, ion implantation is performed on the surface of the p-GaN channel layer to form a plurality of n-GaN well layers, and ion implantation is performed on the surface of the n-GaN channel layer to form a plurality of p-GaN well layers;

[0024] Depositing a gate dielectric layer on the surfaces of the p-GaN channel layer, the n-GaN well layer, the n-GaN channel layer, and the p-GaN well layer, etching a portion of the gate dielectric layer located on the surface of the n-GaN well layer to expose a portion of the surface of the n-GaN well layer, and etching a portion of the gate dielectric layer located on the surface of the p-GaN well layer to expose a portion of the surface of the p-GaN well layer;

[0025] Growing a source electrode on a portion of the exposed surface of the n-GaN well layer, growing a drain electrode on another portion of the exposed surface of the n-GaN well layer, and growing an NMOS gate on the gate dielectric layer on the surface of the p-GaN channel layer to obtain an NMOS device;

[0026] A source electrode is grown on a portion of the exposed surface of the p-GaN well layer, a drain electrode is grown on another portion of the exposed surface of the p-GaN well layer and is electrically connected to the drain electrode of the n-GaN well layer, and a PMOS gate electrode is grown on the gate dielectric layer on the surface of the n-GaN channel layer to obtain a PMOS device;

[0027] An interconnect dielectric layer is grown on the surface of the NMOS device, the PMOS device and the non-device area of ​​the three-dimensional substrate; holes are opened in the interconnect dielectric layer at the source of the PMOS device and the source of the NMOS device and interconnect metal is grown, so that the interconnect metal connects the source of the PMOS device and the source of the NMOS device; holes are opened in the interconnect dielectric layer on the surface of the PMOS gate and the NMOS gate and the interconnect metal is grown, so that the PMOS gate and the NMOS gate are respectively led out of the interconnect dielectric layer through the interconnect metal.

[0028] Compared with the prior art, the three-dimensional gallium nitride-based CMOS inverter and the preparation method thereof in the present invention have the following beneficial effects: first, a three-dimensional substrate is used to form an inverter with a highly integrated interconnected structure. The advantage is that the three-dimensional substrate has good heat dissipation compared to a planar substrate, which frees the thermal limitations of the CMOS inverter and can improve the integration level; second, by arranging a number of devices at intervals on the three-dimensional substrate, a CMOS inverter with high integration, high power density, high current density and support for higher frequencies is formed, which can be better used in power devices such as high voltage, high temperature and high power; third, the source, drain and gate of the device are interconnected by interconnecting metal, can be led out of the interconnecting dielectric layer and integrated into other circuits, the device can output large current and has rich application scenarios.

[0029] Furthermore, since the devices are spaced apart on the outer surface of the three-dimensional substrate, there is also a space between the NMOS device and the PMOS device, and the interconnecting dielectric layer has good thermal conductivity, which is more conducive to the heat dissipation of the devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is an equivalent circuit diagram of a CMOS inverter in an embodiment of the present invention;

[0031] Figure 2 is a schematic partial cross-sectional diagram after each process in step S100 in the embodiment of the present invention is completed;

[0032] Figure 3 is a schematic partial cross-sectional diagram after each process in steps S200 and S300 is completed in an embodiment of the present invention;

[0033] Figure 4 is a schematic partial cross-sectional diagram after each process in steps S400 and S500 is completed in an embodiment of the present invention;

[0034] Figure 5 is a schematic partial cross-sectional diagram after each process in step S600 in the embodiment of the present invention is completed;

[0035] Figure 6 It is a partial cross-sectional schematic diagram of a three-dimensional substrate in some embodiments of the present invention.

[0036] In the accompanying drawings, the reference numerals represent: 1. three-dimensional substrate; 2. NMOS device; 21. first dielectric layer; 22. first GaN buffer layer; 23. p-GaN channel layer; 24. n-GaN well layer; 25. first gate dielectric layer; 26. NMOS source; 27. NMOS drain; 28. NMOS gate; 3. PMOS device; 31. second dielectric layer; 32. second GaN buffer layer; 33. n-GaN channel layer; 34. p-GaN well layer; 35. second gate dielectric layer; 36. PMOS source; 37. PMOS drain; 38. PMOS gate; 4. interconnect dielectric layer; 5. interconnect metal; 6. substrate dielectric / interconnect dielectric. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] Example 1

[0039] like Figures 1 to 5As shown, in this embodiment, the three-dimensional gallium nitride-based CMOS inverter includes: a three-dimensional substrate 1, a plurality of devices arranged at intervals on the outer surface of the three-dimensional substrate 1, and an interconnection dielectric layer 4 covering the devices and the exposed surface of the three-dimensional substrate 1;

[0040] A plurality of interconnect metals 5 are fixed inside and outside the interconnect dielectric layer 4;

[0041] The device includes an NMOS device 2 and a PMOS device 3 arranged at intervals, an interconnect metal 5 electrically connects the gate of the NMOS device 2 and the gate of the PMOS device 3, and is led out to the outside of the interconnect dielectric layer 4; the source of the NMOS device 2 is led out to the outside of the interconnect dielectric layer 4 through an interconnect metal 5, and the source of the PMOS device 3 is led out to the outside of the interconnect dielectric layer 4 through an interconnect metal 5; the drain of the NMOS device 2 is electrically connected to the drain of the PMOS device 3.

[0042] The three-dimensional gallium nitride-based CMOS inverter provided in this embodiment uses a three-dimensional substrate 1 to form an inverter with an interconnected structure. The advantage is that the three-dimensional substrate 1 has better heat dissipation than a planar substrate, which frees the thermal limitation of the CMOS inverter and can improve the integration level. By arranging a number of devices at intervals on the three-dimensional substrate 1, a CMOS inverter with high integration, high power density, high current density and support for higher frequency is formed, which can be better used in power devices such as high voltage, high temperature and high power. The source, drain and gate of the device are interconnected by the interconnection metal 5, which can be led out of the interconnection dielectric layer 4 and integrated into other circuits. The device can output a large current and has rich application scenarios.

[0043] Furthermore, since the devices are spaced apart on the outer surface of the three-dimensional substrate 1 , there is also a space between the NMOS device 2 and the PMOS device 3 , and the interconnect dielectric layer 4 with good thermal conductivity is also beneficial to the heat dissipation of the devices.

[0044] It should be understood that a three-dimensional gallium nitride-based CMOS inverter has several devices. Since the devices are led out through the interconnection metal 5, each device can be connected to different circuits respectively, or connected to different positions in the same circuit. Specifically, the interconnection metal 5 can be a metal wire, and the interconnection metal 5 corresponding to the gate and source of each device is connected to the external pin of the circuit through the metal wire. The equivalent circuit diagram of the CMOS inverter in this embodiment is as follows: Figure 1 As shown, in the CMOS inverter structure, the source of NMOS device 2 is connected to V through the interconnect metal. SS The source of PMOS device 3 is connected to V through the interconnect metal. DD The gates of NMOS device 2 and PMOS device 3 are connected to V through an interconnect metal. OUT Pin.

[0045] Furthermore, the three-dimensional substrate 1 is in the shape of a sphere, a polyhedron or a cylinder.

[0046] The three-dimensional substrate 1 configured in this way is conducive to better heat dissipation of the device, thereby ensuring that the overall life of the device is improved. Figure 6 As shown, the three-dimensional substrate 1 can be a spherical substrate that is easy to prepare. Compared with a flat substrate, a spherical substrate increases the heat dissipation area of ​​the device, improves the reliability of the device in a high temperature environment, and improves the performance and life of the device. In addition, compared with a polyhedral or cylindrical three-dimensional substrate 1, a spherical three-dimensional substrate 1 is easy to prepare and has uniform heat dissipation.

[0047] Furthermore, the three-dimensional substrate 1 is a diamond or boron nitride substrate.

[0048] The common substrate materials for GaN-based CMOS inverters are sapphire, silicon or silicon carbide substrates, which have low thermal conductivity, greatly limiting the heat dissipation and high-power performance requirements of the device. Diamond and boron nitride are both heat dissipation materials with high thermal conductivity and low expansion coefficient. The use of high thermal conductivity diamond or boron nitride heat dissipation substrates can meet the heat dissipation requirements of CMOS inverters under high power and realize the high-power application of CMOS inverters.

[0049] Furthermore, if Figure 5 As shown, a substrate dielectric or an interconnect dielectric is filled between the NMOS device 2 and the PMOS device 3 to connect the NMOS device 2 and the PMOS device 3 , and the drain of the NMOS device 2 and the drain of the PMOS device 3 are grown integrally.

[0050] It should be understood that since there is a gap between the NMOS device 2 and the PMOS device 3 , the gap between the NMOS device 2 and the PMOS device 3 needs to be filled before preparing the drain of the NMOS device 2 and the drain of the PMOS device 3 .

[0051] After the gap between the NMOS device 2 and the PMOS device 3 is filled, a drain electrode can be grown on the device surface by photolithography and chemical vapor deposition, and the drain electrode covers the n-GaN well layer 24 of the NMOS device 2 and the p-GaN well layer 34 of the PMOS device 3. Specifically, in this embodiment, the drain electrode is grown at a position adjacent to the NMOS device 2 and the PMOS device 3. Such a configuration can simplify the structure of the CMOS inverter. The circuit of the CMOS inverter in the related art is complex and difficult to be applied to a highly integrated CMOS inverter.

[0052] After the gap between the NMOS device 2 and the PMOS device 3 is filled, drains can be grown on the n-GaN well layer 24 of the NMOS device 2 and the p-GaN well layer 34 of the PMOS device 3, respectively, and then an interconnect dielectric layer 4 is grown on the device surface, and the drain of the NMOS device 2 and the drain of the PMOS device 3 are connected through the interconnect metal 5 in the interconnect dielectric layer 4.

[0053] The substrate dielectric 6 or the interconnect dielectric 6 is filled between the NMOS device 2 and the PMOS device 3, wherein the substrate dielectric 6 is a dielectric of the same material as the three-dimensional substrate 1, grown from the surface of the three-dimensional substrate 1 and fills the gap between the NMOS device 2 and the PMOS device 3; the interconnect dielectric 6 is AlN, SiO 2 or Si 3 N 4 Any one of the materials can form an interconnect dielectric layer that supports the interconnect metal 5 and the drain.

[0054] Here is an example, Figures 1 to 5 As shown, a three-dimensional substrate 1 made of spherical diamond material with a diameter of 50 μm and an outer surface roughness of less than 0.3 nm is selected. A plurality of devices are arranged at intervals on the outer surface of the three-dimensional substrate 1, and the devices include NMOS devices 2 and PMOS devices 3 arranged at intervals.

[0055] The NMOS device 2 includes a first dielectric layer 21, a first GaN buffer layer 22, a p-GaN channel layer 23, two n-GaN well layers 24, a first gate dielectric layer 25, an NMOS source 26, an NMOS drain 27 and an NMOS gate 28;

[0056] The first dielectric layer 21 is arranged on the surface of the three-dimensional substrate 1; the first GaN buffer layer 22 is arranged on the surface of the first dielectric layer 21 away from the three-dimensional substrate 1; the p-GaN channel layer 23 is arranged on the surface of the first GaN buffer layer 22 away from the first dielectric layer 21; the n-GaN well layer 24 is arranged at intervals on the surface of the p-GaN channel layer 23 away from the first GaN buffer layer 22; the first gate dielectric layer 25 covers between the two n-GaN well layers 24 and covers part of the n-GaN well layer 24; the NMOS source 26 and the NMOS drain 27 are respectively arranged on the surfaces of the two n-GaN well layers 24; the NMOS gate 28 is arranged on the surface of the first gate dielectric layer 25.

[0057] The PMOS device 3 includes a second dielectric layer 31, a second GaN buffer layer 32, an n-GaN channel layer 33, a p-GaN well layer 34, a second gate dielectric layer 35, a PMOS source 36, a PMOS drain 37 and a PMOS gate 38; the second dielectric layer 31 is arranged on the surface of the three-dimensional substrate 1; the second GaN buffer layer 32 is arranged on the surface of the second dielectric layer 31 away from the three-dimensional substrate 1; the n-GaN channel layer 33 is arranged on the surface of the second GaN buffer layer 32 away from the second dielectric layer 31; the p-GaN well layer 34 is arranged at intervals on the surface of the n-GaN channel layer 33 away from the second GaN buffer layer 32; the second gate dielectric layer 35 covers between the two p-GaN well layers 34 and covers part of the p-GaN well layer 34; the PMOS source 36 and the PMOS drain 37 are respectively arranged on the surfaces of the two p-GaN well layers 34; the PMOS gate 38 is arranged on the surface of the second gate dielectric layer 35.

[0058] The first GaN buffer layer 22 and the second GaN buffer layer 32 use C as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 In this embodiment, the preferred doping concentration is 2×10 18 cm -3 .

[0059] The p-GaN channel layer 23 uses Si or C as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 In this embodiment, the preferred doping concentration is 2×10 18 cm -3 ; The n-GaN channel layer 33 uses Mg as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 In this embodiment, the preferred doping concentration is 2×10 18 cm -3 ;

[0060] The n-GaN well layer 24 uses Si as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 In this embodiment, the preferred doping concentration is 2×10 18 cm -3 ; The p-GaN well layer 34 uses Mg as a dopant with a doping concentration of 1×10 18 cm -3~3×10 18 cm -3 In this embodiment, the preferred doping concentration is 2×10 18 cm -3 .

[0061] The materials of the first dielectric layer 21, the second dielectric layer 31 and the interconnect dielectric layer 4 can be selected from AlN, SiO 2 or Si 3 N 4 In this embodiment, AlN material is selected, the thickness of the first dielectric layer 21 and the second dielectric layer 31 are both 20-50 nm, preferably 30 nm. The thickness of the interconnect dielectric layer 4 is 1-5 μm, preferably 2 μm.

[0062] Specifically, the first dielectric layer 21 is between the three-dimensional substrate 1 and the first GaN buffer layer 22, reducing the stress caused by the lattice mismatch and the different thermal expansion coefficients between the two, thereby improving the integrity of the first GaN buffer layer 22; the second dielectric layer 31 can reduce the stress between the three-dimensional substrate 1 and the second GaN buffer layer 32, AlN, SiO 2 or Si 3 N 4 Such materials have excellent thermal conductivity and strong thermal stability, which improves the heat dissipation capacity of the CMOS inverter.

[0063] Example 2

[0064] like Figures 2 to 6 As shown, this embodiment provides a method for preparing a three-dimensional gallium nitride-based CMOS inverter, comprising the steps of:

[0065] S100: Figure 2 and 6 As shown, a three-dimensional substrate 1 is prepared, a dielectric layer and a GaN buffer layer are sequentially formed on the surface of the three-dimensional substrate 1, and the surface of the three-dimensional substrate 1 has a plurality of device regions arranged at intervals;

[0066] S200: Figure 3 As shown, a p-GaN channel layer 23 and an n-GaN channel layer 33 are alternately grown on the GaN buffer layer;

[0067] Etching the p-GaN channel layer 23, the n-GaN channel layer 33, the GaN buffer layer and the dielectric layer in the non-device region on the surface of the three-dimensional substrate 1 to expose the surface of the non-device region of the three-dimensional substrate 1;

[0068] In each device region, etching is performed along the contact between the p-GaN channel layer 23 and the n-GaN channel layer 33 until the surface of the three-dimensional substrate 1 is exposed, so that the GaN buffer layer is separated to form a first GaN buffer layer 22 located below the p-GaN channel layer 23 and a second GaN buffer layer 32 located below the n-GaN channel layer 33;

[0069] S300: Figure 3 As shown, in each device region, ion implantation is performed on the surface of the p-GaN channel layer 23 to form a plurality of n-GaN well layers 24, and ion implantation is performed on the surface of the n-GaN channel layer 33 to form a plurality of p-GaN well layers 34;

[0070] S400: Figure 4 As shown, a gate dielectric layer is deposited on the surfaces of the p-GaN channel layer 23, the n-GaN well layer 24, the n-GaN channel layer 33 and the p-GaN well layer 34, a portion of the gate dielectric layer located on the surface of the n-GaN well layer 24 is etched to expose a portion of the surface of the n-GaN well layer 24, and a portion of the gate dielectric layer located on the surface of the p-GaN well layer 34 is etched to expose a portion of the surface of the p-GaN well layer 34;

[0071] S500: Figure 4 As shown, a source electrode is grown on a surface of a portion of the n-GaN well layer 24 exposed, a drain electrode is grown on a surface of another portion of the n-GaN well layer 24 exposed, and an NMOS gate 28 is grown on the gate dielectric layer on the surface of the p-GaN channel layer 23, thereby obtaining an NMOS device 2;

[0072] A source electrode is grown on a surface of a portion of the p-GaN well layer 34 that is exposed, a drain electrode is grown on another surface of the p-GaN well layer 34 that is exposed and is electrically connected to the drain electrode of the n-GaN well layer 24, and a PMOS gate electrode 38 is grown on the gate dielectric layer on the surface of the n-GaN channel layer 33, thereby obtaining a PMOS device 3;

[0073] S600: Figure 6 As shown, an interconnect dielectric layer 4 is grown on the surface of the NMOS device 2, the PMOS device 3 and the non-device area of ​​the three-dimensional substrate 1; holes are opened in the interconnect dielectric layer 4 at the source of the PMOS device 3 and the source of the NMOS device 2, and an interconnect metal 5 is grown, so that an interconnect metal 5 connects the source of the PMOS device 3 and the source of the NMOS device 2; holes are opened in the interconnect dielectric layer 4 on the surface of the PMOS gate 38 and the NMOS gate 28, and an interconnect metal 5 is grown, so that the PMOS gate 38 and the NMOS gate 28 are respectively led out of the interconnect dielectric layer 4 through an interconnect metal 5.

[0074] Specifically, Figure 2 As shown, step 100 includes:

[0075] S110: preparing spherical diamonds with a diameter of 50 to 60 μm by microwave plasma vapor deposition, performing three-dimensional dynamic friction polishing on the spherical diamonds to make the surface roughness of the spherical diamonds less than 0.3 nm, and performing ultrasonic cleaning on the spherical diamonds to remove surface impurities to obtain a three-dimensional substrate 1, wherein the surface of the three-dimensional substrate 1 has a plurality of device regions arranged at intervals;

[0076] S120: depositing a dielectric layer of 20 to 50 nm on the outer side of the three-dimensional substrate 1 by vacuum interconnected magnetron sputtering or atomic layer deposition, wherein the thickness of the dielectric layer is preferably 30 nm;

[0077] S130: A 10-40 μm GaN buffer layer is grown on the dielectric layer by hydride vapor phase epitaxy, molecular beam epitaxy or metal organic chemical vapor deposition. The thickness of the GaN buffer layer is preferably 20 μm. The GaN buffer layer uses C as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 ;

[0078] like Figure 3 As shown, step S200 specifically includes:

[0079] S210: blocking a portion of the device region by a photolithography process, growing a p-GaN channel layer 23 on the GaN buffer layer, and then blocking the p-GaN channel layer 23 by a photolithography process, and growing an n-GaN channel layer 33 on the GaN buffer layer and at a gap between the p-GaN channel layer 23;

[0080] Or, a partial area on each device area is blocked by a photolithography process, an n-GaN channel layer 33 is grown on the GaN buffer layer, and then the n-GaN channel layer 33 is blocked by a photolithography process, and an n-GaN channel layer 33 is grown on the GaN buffer layer at the interval between the p-GaN channel layer 23;

[0081] The p-GaN channel layer 23 has a thickness of 10 μm and uses Si or C as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 ; The thickness of the n-GaN channel layer 33 is 10 μm, and Mg is used as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 ;

[0082] It should be understood that the order of preparing the p-GaN channel layer 23 and the n-GaN channel layer 33 may be reversed.

[0083] S220: In each device region, a surface of the three-dimensional substrate 1 is exposed along the contact between the p-GaN channel layer 23 and the n-GaN channel layer 33 by a dry etching process, so that the GaN buffer layer is separated to form a first GaN buffer layer 22 located below the p-GaN channel layer 23 and a second GaN buffer layer 32 located below the n-GaN channel layer 33;

[0084] like Figure 3 As shown, step S300 specifically includes:

[0085] By ion implantation, Si is implanted into the p-GaN channel layer 23 to form two doping concentrations of 1×10 18 cm -3 ~3×10 18 cm -3 The n-GaN well layer 24 is formed by implanting Mg into the n-GaN channel layer 33 through an ion implantation process to form two doping concentrations of 1×10 18 cm -3 ~3×10 18 cm -3 The p-GaN well layer 34 is formed.

[0086] like Figure 4 As shown, step S400 specifically includes:

[0087] Depositing a gate dielectric layer on the surfaces of the p-GaN channel layer 23, the n-GaN well layer 24, the n-GaN channel layer 33 and the p-GaN well layer 34 by atomic layer deposition, followed by stripping and annealing;

[0088] After annealing, the gate dielectric layer at the opposite distal ends of the two adjacent n-GaN well layers 24 is etched to obtain a first gate dielectric layer 25, so that the first gate dielectric layer 25 covers the p-GaN channel layer 23 between the two adjacent n-GaN well layers 24 and the portion of the n-GaN well layer 24 adjacent to the p-GaN channel layer 23;

[0089] The gate dielectric layer at the opposite proximal portions of two adjacent p-GaN well layers 34 is etched to obtain a second gate dielectric layer 35 , so that the second gate dielectric layer 35 covers the n-GaN channel layer 33 between the two adjacent p-GaN well layers 34 and a portion of the p-GaN well layer 34 adjacent to the n-GaN channel layer 33 .

[0090] like Figure 4 As shown, step S500 specifically includes:

[0091] S510: after the photolithography process is blocked, a substrate dielectric or an interconnect dielectric is grown between the p-GaN channel layer 23 and the n-GaN channel layer 33 by microwave plasma chemical vapor deposition to fill the gap between the n-GaN channel layer 33 and the p-GaN channel layer 23;

[0092] S520: After the photolithography process blocks at least the first gate dielectric layer 25 and the second gate dielectric layer 35, a metal film Ti (25nm) / Au (75nm) or Ti (25nm) / Al (75nm) / Ni (25nm) / Au (75nm) is evaporated on the exposed surfaces of the n-GaN well layer 24, the p-GaN well layer 34, the p-GaN channel layer 23 and the n-GaN channel layer 33 by thermal evaporation, magnetron sputtering or electron beam evaporation. After the degumming process, an NMOS source 26 on the surface of one n-GaN well layer 24, a PMOS source 36 on the surface of one p-GaN well layer 34, an NMOS drain 27 on the surface of another n-GaN well layer 24, and a PMOS drain 37 on the surface of another p-GaN well layer 34 are obtained; at 650°C, N 2 Annealing in an ambient environment to form a better ohmic contact;

[0093] It should be understood that after the substrate dielectric and the interconnect dielectric fill the gap between the n-GaN channel layer 33 and the p-GaN channel layer 23, in S520 of the present embodiment, the NMOS drain 27 and the PMOS drain 37 are Ti (25nm) / Au (75nm) or Ti (25nm) / Al (75nm) / Ni (25nm) / Au (75nm) metal films grown integrally, which simplifies the preparation process of the NMOS drain 27 and the PMOS drain 37. In other embodiments, the NMOS drain 27 and the PMOS drain 37 can also be grown and connected multiple times.

[0094] S530: Deposit metal films Ti (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm) on the surfaces of the first gate dielectric layer 25 and the second gate dielectric layer 35 by thermal evaporation, magnetron sputtering or electron beam evaporation, and form NMOS gate 28 and PMOS gate 38 respectively after gold removal. 2 Annealing is performed under an ambient temperature to obtain better ohmic contact, thereby obtaining an NMOS device 2 and a PMOS device 3.

[0095] like Figure 5 As shown, S600 specifically includes:

[0096] S610: growing an interconnect dielectric layer 4 on the outer surface of the CMOS inverter by magnetron sputtering or pulsed laser deposition, and flattening the outer surface of the interconnect dielectric layer 4;

[0097] S620: Open holes by photolithography and ICP dry etching (SF6) to expose the NMOS source 26 and the PMOS source 36 and grow interconnection metals 5 respectively, so that the NMOS source 26 and the PMOS source 36 are led out of the interconnection dielectric layer 4 through an interconnection metal 5 respectively;

[0098] S630 : Open holes to expose the NMOS gate 28 and the PMOS gate 38 through photolithography and ICP dry etching (SF6) and grow interconnect metal 5 , so that the NMOS gate 28 and the PMOS gate 38 are connected through an interconnect metal 5 and led out of the interconnect dielectric layer 4 .

[0099] In addition, it should be understood that, firstly, those skilled in the art can select appropriate chemical vapor deposition methods to grow each layer, and select appropriate etching methods to expose the surface or openings of certain layers, including but not limited to the deposition methods of the devices and the interconnect dielectric layer 4 in the above-mentioned embodiments; the shape of the CMOS inverter, the material of the device, and the material of the interconnect dielectric layer 4 can also be replaced, as described in detail in Embodiment 1; the electrodes of the PMOS device 3 and the NMOS device 2 can be selected from suitable metal electrodes, as long as they can form good ohmic contacts;

[0100] Secondly, the above is only one embodiment. In other embodiments, the above steps are not limited in order, and some processes can be exchanged in order. In addition, the description of each aspect of the above embodiment has its own emphasis. For the part not described in detail in a certain part, please refer to the relevant description of other embodiments.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-dimensional gallium nitride-based CMOS inverter, characterized in that: include: A three-dimensional substrate, a plurality of devices spaced apart on an outer surface of the three-dimensional substrate, and an interconnect dielectric layer covering the devices and an exposed surface of the three-dimensional substrate; The three-dimensional substrate is in the shape of a sphere, a polyhedron or a cylinder, and the three-dimensional substrate is a diamond or boron nitride substrate; A plurality of interconnect metals are fixed inside and outside the interconnect dielectric layer; The device comprises an NMOS device and a PMOS device which are arranged at intervals, wherein an interconnect metal electrically connects a gate of the NMOS device with a gate of the PMOS device and is led out of the interconnect dielectric layer; a source of the NMOS device is led out of the interconnect dielectric layer through an interconnect metal; a source of the PMOS device is led out of the interconnect dielectric layer through an interconnect metal; a drain of the NMOS device is electrically connected to a drain of the PMOS device; The NMOS device comprises a first dielectric layer, a first GaN buffer layer, a p-GaN channel layer, at least two n-GaN well layers, a first gate dielectric layer, an NMOS source, an NMOS drain and an NMOS gate; The first dielectric layer is disposed on the surface of the three-dimensional substrate; the first GaN buffer layer is disposed on the surface of the first dielectric layer away from the three-dimensional substrate; The p-GaN channel layer is arranged on the surface of the first GaN buffer layer away from the first dielectric layer; the n-GaN well layer is arranged at intervals on the surface of the p-GaN channel layer away from the first GaN buffer layer; the first gate dielectric layer covers between the two n-GaN well layers and covers part of the n-GaN well layer; the NMOS source and the NMOS drain are respectively arranged on the surfaces of the two n-GaN well layers; and the NMOS gate is arranged on the surface of the first gate dielectric layer.

2. The inverter according to claim 1, characterized in that: A substrate dielectric or an interconnect dielectric is filled between the NMOS device and the PMOS device so that the NMOS device is connected to the PMOS device, and the drain of the NMOS device and the drain of the PMOS device are formed by integral growth.

3. The inverter according to claim 1, characterized in that: The PMOS device includes a second dielectric layer, a second GaN buffer layer, an n-GaN channel layer, at least two p-GaN well layers, a second gate dielectric layer, a PMOS source, a PMOS drain and a PMOS gate; the second dielectric layer is arranged on the surface of the three-dimensional substrate; the second GaN buffer layer is arranged on the surface of the second dielectric layer away from the three-dimensional substrate; the n-GaN channel layer is arranged on the surface of the second GaN buffer layer away from the second dielectric layer; the p-GaN well layer is arranged at intervals on the surface of the n-GaN channel layer away from the second GaN buffer layer; the second gate dielectric layer covers between the two p-GaN well layers and covers part of the p-GaN well layer; the PMOS source and the PMOS drain are respectively arranged on the surfaces of the two p-GaN well layers; the PMOS gate is arranged on the surface of the second gate dielectric layer.

4. The inverter according to claim 3, characterized in that: The first GaN buffer layer and the second GaN buffer layer use C as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 ; The p-GaN channel layer uses Si or C as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 The n-GaN channel layer uses Mg as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 ; The n-GaN well layer uses Si as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 The p-GaN well layer uses Mg as a dopant with a doping concentration of 1×10 18 cm -3 ~3×10 18 cm -3 .

5. The inverter according to claim 3, characterized in that: The material of the first dielectric layer and the second dielectric layer is any one of AlN, SiO2 or Si3N4, and the thickness of each layer is 20-50 nm.

6. The inverter according to claim 1, characterized in that: The interconnect dielectric layer is made of any one of AlN, SiO2 or Si3N4, and has a thickness of 1 to 5 μm.

7. A method for preparing a three-dimensional gallium nitride-based CMOS inverter, characterized in that: Includes steps: A three-dimensional substrate is prepared, a dielectric layer and a GaN buffer layer are sequentially formed on the surface of the three-dimensional substrate, and the surface of the three-dimensional substrate has a plurality of device regions arranged at intervals; the three-dimensional substrate is in the shape of a sphere, a polyhedron or a cylinder, and the three-dimensional substrate is a diamond or boron nitride substrate; Growing a p-GaN channel layer and an n-GaN channel layer at intervals on the GaN buffer layer; Etching the p-GaN channel layer, the n-GaN channel layer, the GaN buffer layer and the dielectric layer in the non-device area on the surface of the three-dimensional substrate to expose the surface of the non-device area of ​​the three-dimensional substrate; On each of the device regions, etching is performed along the contact between the p-GaN channel layer and the n-GaN channel layer until the surface of the three-dimensional substrate is exposed, so that the GaN buffer layer is separated to form a first GaN buffer layer located below the p-GaN channel layer and a second GaN buffer layer located below the n-GaN channel layer; In each of the device regions, ion implantation is performed on the surface of the p-GaN channel layer to form a plurality of n-GaN well layers, and ion implantation is performed on the surface of the n-GaN channel layer to form a plurality of p-GaN well layers; Depositing a gate dielectric layer on the surfaces of the p-GaN channel layer, the n-GaN well layer, the n-GaN channel layer, and the p-GaN well layer, etching a portion of the gate dielectric layer located on the surface of the n-GaN well layer to expose a portion of the surface of the n-GaN well layer, and etching a portion of the gate dielectric layer located on the surface of the p-GaN well layer to expose a portion of the surface of the p-GaN well layer; Growing a source electrode on a portion of the exposed surface of the n-GaN well layer, growing a drain electrode on another portion of the exposed surface of the n-GaN well layer, and growing an NMOS gate on the gate dielectric layer on the surface of the p-GaN channel layer to obtain an NMOS device; A source electrode is grown on a portion of the exposed surface of the p-GaN well layer, a drain electrode is grown on another portion of the exposed surface of the p-GaN well layer and is electrically connected to the drain electrode of the n-GaN well layer, and a PMOS gate electrode is grown on the gate dielectric layer on the surface of the n-GaN channel layer to obtain a PMOS device; An interconnect dielectric layer is grown on the surface of the NMOS device, the PMOS device and the non-device area of ​​the three-dimensional substrate; holes are opened in the interconnect dielectric layer at the source of the PMOS device and the source of the NMOS device and interconnect metal is grown, so that the interconnect metal connects the source of the PMOS device and the source of the NMOS device; holes are opened in the interconnect dielectric layer on the surface of the PMOS gate and the NMOS gate and the interconnect metal is grown, so that the PMOS gate and the NMOS gate are respectively led out of the interconnect dielectric layer through the interconnect metal.

Images