Pixel driving circuit, display panel and driving method thereof, and display device

Abstract

The application provides a pixel driving circuit, a display panel and a driving method thereof, and a display device. The pixel driving circuit comprises a data writing module, a driving module, a storage module, a light emitting element and an internal refresh module. The data writing module and the driving module have a first node therebetween, and the driving module and the light emitting element have a second node therebetween. The control end of the internal refresh module is electrically connected to an internal refresh control signal, and the first connection end is connected to the first node. When the data signal of a next frame is the same as the data signal of a current frame, the internal refresh control signal controls the internal refresh module to be turned on in the data writing stage of the current frame to store the data signal of the current frame, and controls the internal refresh module to be turned on in the data writing stage of the next frame to transmit the stored data signal to the first node. The data writing module remains closed in the next frame. The pixel driving circuit can reduce the power waste caused by high refresh rate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel driving circuit, a display panel and its driving method, and a display device. Background Technology

[0002] With the continuous development of display technology, the refresh rate specifications of display panels are also gradually improving. For high refresh rate display panels, the displayed content between adjacent frames is no longer differentiated, which can easily lead to repetition of displayed content between consecutive frames.

[0003] In traditional display driving modes, regardless of whether the data content of adjacent frames is the same, data needs to be rewritten at the beginning of a new frame. In many practical applications, including mobile phones, tablets, monitors, and televisions, at high refresh rates, the displayed content of adjacent frames remains globally or partially unchanged. Regardless of whether identical content exists, data signals are rewritten in each new frame, resulting in wasted power consumption. Summary of the Invention

[0004] This application provides a pixel driving circuit, a display panel and its driving method, and a display device, aiming to solve the problem of power consumption waste caused by the high refresh rate of the display panel in the prior art.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a pixel driving circuit. This pixel driving circuit includes:

[0006] The data writing module has its control terminal electrically coupled to the scan signal, its input terminal electrically coupled to the data signal, and its output terminal connected to the first node.

[0007] The drive module has a control terminal connected to the first node, the first terminal being electrically coupled to the first power signal, and a second terminal connected to the second node.

[0008] The storage module has one end connected to the first node and the other end connected to the second node.

[0009] The light-emitting element has a first electrode connected to a second node, and the second electrode electrically coupled to a second power supply signal.

[0010] An internal refresh module, the control terminal of which is electrically coupled to an internal refresh control signal, and the first connection terminal is connected to a first node;

[0011] When the data signal of the subsequent frame is the same as the data signal of the current frame, the internal refresh control signal controls the internal refresh module to start during the data writing phase of the current frame to store the data signal of the current frame; and controls the internal refresh module to start during the data writing phase of the subsequent frame to transmit the stored data signal to the first node; wherein, the data writing module remains closed in the subsequent frame.

[0012] In some embodiments, the internal refresh module includes a switching unit and a storage unit; the control terminal of the switching unit is electrically coupled to the internal refresh control signal, the first terminal is connected to the first node, and the second terminal is connected to the first pole of the storage unit; the second pole of the storage unit is connected to the ground terminal.

[0013] In some embodiments, the data writing module includes a first switching transistor, the control terminal of the first switching transistor is electrically coupled to a scan signal, the input terminal is electrically coupled to a data signal, and the output terminal is connected to a first node;

[0014] The driving module includes a driving transistor, the control terminal of which is connected to the first node and electrically coupled to the first power signal, and the second terminal is connected to the second node.

[0015] The storage module includes a bootstrap capacitor, with its first terminal connected to the first node and its second terminal connected to the second node.

[0016] The switching unit includes a second switching transistor, and the storage unit includes a storage capacitor. The control terminal of the second switching transistor is electrically coupled to an internal refresh control signal, the first terminal is connected to a first node, the second terminal is connected to the first electrode of the storage capacitor, and the second electrode of the storage capacitor is connected to a ground terminal.

[0017] In some embodiments, the pixel driving circuit further includes a reset module; a first connection terminal of the reset module is connected to a first node, and a second connection terminal is connected to a second node, for resetting the potential of the first node and the potential of the second node; and,

[0018] When the data signal of the subsequent frame is the same as the data signal of the current frame, the reset module resets the potential of the first node and the potential of the second node only during the reset phase of the current frame.

[0019] In some embodiments, the reset module includes a first reset transistor and a second reset transistor;

[0020] The control terminal of the first reset transistor is electrically coupled to the reset control signal, the first terminal is electrically coupled to the reference voltage signal, and the second terminal is connected to the first node, so as to reset the potential of the first node to the reference voltage under the control of the reset control signal.

[0021] The control terminal of the second reset transistor is electrically coupled to the reset control signal, the first terminal is electrically coupled to the second power supply signal, and the second terminal is connected to the second node, so as to reset the potential of the second node to the second power supply voltage under the control of the reset control signal.

[0022] To address the aforementioned technical problems, the second technical solution provided in this application is: to provide a display panel. The display panel includes:

[0023] Substrate;

[0024] A pixel driving layer is disposed on a substrate and includes multiple pixel driving circuits as described in the above technical solutions.

[0025] To address the aforementioned technical problems, the third technical solution provided in this application is: a driving method for a display panel. The display panel is the same as described in the above technical solutions, and the driving method includes:

[0026] Acquire the current frame signal and the next frame signal, and process them;

[0027] Determine whether the content of the next frame is the same as the content of the current frame;

[0028] In response to the fact that the content of the next frame is the same as the content of the current frame, the internal refresh control signal controls the internal refresh module to start during the data writing phase of the current frame, so that the internal refresh module stores the data signal of the current frame, starts during the data writing phase of the next frame, and transmits the stored data signal to the first node; the scan signal controls the data writing module to remain closed in the next frame.

[0029] In response to the fact that the content of the next frame is different from that of the current frame, the scanning signal controls the data writing module to start during the data writing phase of the next frame, so as to write the corresponding data signal to the first node.

[0030] In some implementations, the pixel driving circuit in the display panel further includes a reset module; the first end of the reset module is connected to the first node, and the second end is connected to the second node, for resetting the potential of the first node and the potential of the second node;

[0031] The driving method also includes:

[0032] In response to the fact that the content of the next frame is the same as the content of the current frame, the reset control signal controls the reset module to remain closed during the reset phase of the next frame and not perform a reset.

[0033] In response to the fact that the content of the next frame is different from that of the current frame, the reset control signal controls the reset module to start during the reset phase of the next frame in order to reset the potential of the first node and the potential of the second node.

[0034] In some implementations, the steps of acquiring and processing the current frame signal and the next frame signal include:

[0035] Obtain the data signal of the current frame and the data signal of the next frame;

[0036] Compare the data signal of the next frame with the data signal of the current frame line by line;

[0037] The steps to determine whether the content of the next frame is the same as the content of the current frame include: checking line by line whether the data signal of the next frame is the same as the data signal of the current frame.

[0038] To address the aforementioned technical problems, the fourth technical solution provided in this application is: to provide a display device. The display device includes:

[0039] The display panel is the same as the display panel described in the above technical solution;

[0040] The control module, coupled to the display panel, is used to execute the driving method described in the above technical solution to drive the display panel.

[0041] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a pixel driving circuit, a display panel and its driving method, and a display device. The pixel driving circuit includes a data writing module, a driving module, a storage module, a light-emitting element, and an internal refresh module. By adding an internal refresh module and electrically coupling its control terminal to an internal refresh control signal, and connecting its first connection terminal to a first node, a self-refresh function can be achieved when the data signal of the subsequent frame is the same as that of the current frame. This eliminates the need to rewrite the data signal through the data writing module in a new frame, thereby reducing driving power consumption and avoiding power waste. When the data signal of the subsequent frame is the same as the data signal of the current frame, during the data writing phase of the current frame, the internal refresh module is turned on by the internal refresh control signal to store the data signal of the current frame; and during the data writing phase of the subsequent frame, the internal refresh module is turned on by the internal refresh control signal to transmit the stored data signal to the first node, providing data signals to the driving module and the storage module. This realizes the self-refreshing driving mode of the sub-pixel driving circuit, and the data writing module remains closed in the subsequent frame, so there is no need to rewrite the data signal, thereby reducing the power consumption waste caused by high refresh rate and reducing the power consumption of the display panel. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application;

[0044] Figure 2 This is a schematic diagram of the pixel driving circuit provided in an embodiment of this application;

[0045] Figure 3 yes Figure 2 Timing diagram of the refresh drive corresponding to the mid-pixel drive circuit;

[0046] Figure 4 yes Figure 2 Another refresh drive timing diagram corresponding to the mid-pixel drive circuit;

[0047] Figure 5 This is a schematic diagram of the pixel driving circuit provided in another embodiment of this application;

[0048] Figure 6 yes Figure 5 Timing diagram of the refresh drive corresponding to the mid-pixel drive circuit;

[0049] Figure 7 yes Figure 5 Another refresh drive timing diagram corresponding to the mid-pixel drive circuit;

[0050] Figure 8 This is a flowchart illustrating a method for driving a display panel according to an embodiment of this application.

[0051] Figure 9 yes Figure 8 A flowchart illustrating one embodiment of step S1 is provided;

[0052] Figure 10 yes Figure 8 A flowchart illustrating another embodiment of step S1 is provided;

[0053] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0054] Figure label:

[0055] 100 - Display panel; 10 - Substrate; 20 - Pixel driving layer; 21 - Pixel driving circuit; 211 - Data writing module; 212 - Driving module; 213 - Storage module; 214 - Light-emitting element; 215 - Internal refresh module; 2151 - Switching unit; 2152 - Storage unit; 216 - Reset module; 2161 - First reset unit; 2162 - Second reset unit; 200 - Control module;

[0056] Q1 - First switching transistor; Q2 - Drive transistor; Q3 - First reset transistor; Q4 - Second reset transistor; Q5 - Second switching transistor; Cst - Bootstrap capacitor; Csr - Storage capacitor; P1 - First node; P2 - Second node; Gate - Scan signal; Data - Data signal; SW - Internal refresh control signal; Rst - Reset control signal; Vref - Reference voltage signal; ELVDD - First power supply signal; ELVSS - Second power supply signal; GND - Ground terminal; F(n) - Current frame; F(n+1) - Next frame; t0 - Reset stage; t1 - Data writing stage. Detailed Implementation

[0057] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0058] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0059] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0060] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0061] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0062] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0063] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application. In this embodiment, a display panel 100 is provided, which includes a substrate 10 and a pixel driving layer 20. The substrate 10 is used to support the pixel driving layer 20. The substrate 10 can be a glass substrate or a flexible substrate, depending on actual needs. For example, a flexible substrate can be used as the substrate 10 to achieve the foldable or rollable function of the display panel 100. The pixel driving layer 20 is disposed on one side of the substrate 10, specifically on one side surface of the substrate 10. The pixel driving layer 20 includes multiple pixel driving circuits 21 for displaying images. The multiple pixel driving circuits 21 can be arranged in a preset array to further improve the display effect. The specific structure and function of the pixel driving circuit 21 are described in the following embodiments; please refer to the detailed description below.

[0064] Please see Figure 2 , Figure 2This is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of this application. In this embodiment, a pixel driving circuit 21 is provided, which includes a data writing module 211, a driving module 212, a storage module 213, a light-emitting element 214, and an internal refresh module 215.

[0065] The data writing module 211 has its control terminal electrically coupled to the scan signal Gate, its input terminal electrically coupled to the data signal Data, and its output terminal connected to the first node P1. The data writing module 211 is used to control data writing so that the data signal Data is written to the first node P1.

[0066] The driving module 212 has its control terminal connected to the first node P1, its first terminal electrically coupled to the first power signal ELVDD, and its second terminal connected to the second node P2. The driving module 212 is used to generate a corresponding driving current according to the data signal Data, so as to drive the light-emitting element 214 to emit light.

[0067] The storage module 213 includes a first terminal and a second terminal. The first terminal is connected to a first node P1, and the second terminal is connected to a second node P2. The storage module 213 is used to store data signals and discharges during the light-emitting phase to maintain the voltage at the control terminal of the drive module 212.

[0068] The light-emitting element 214 has a first electrode connected to the second node P2 and a second electrode electrically coupled to the second power signal ELVSS; the light-emitting element 214 is used to emit light under the drive of the driving module 212.

[0069] The internal refresh module 215 has its control terminal electrically coupled to the internal refresh control signal SW, and its first connection terminal connected to the first node P1. The internal refresh module 215 is used to store the data signal Data in the current frame F(n) when the data signal Data in the subsequent frame F(n+1) is the same as the data signal Data in the current frame F(n), and output the stored data signal Data to the first node P1 in the subsequent frame F(n+1), thereby realizing the internal self-refresh driving mode of the sub-pixel driving circuit 21.

[0070] Specifically, when the data signal Data of the subsequent frame F(n+1) is the same as the data signal Data of the current frame F(n), the internal refresh control signal SW controls the internal refresh module 215 to start in the data writing stage t1 of the current frame F(n) to store the data signal Data of the current frame F(n); and controls the internal refresh module 215 to start in the data writing stage t1 of the subsequent frame F(n+1) to transmit the stored data signal Data to the first node P1; wherein, the data writing module 211 remains closed in the subsequent frame F(n+1).

[0071] It is understandable that when the data signal Data of the subsequent frame F(n+1) is detected to be the same as the data signal Data of the current frame F(n): during the data writing stage t1 of the current frame F(n), the scan signal Gate controls the data writing module 211 to turn on, so as to write the data signal Data to the first node P1 and the storage module 213; at the same time, the internal refresh control signal SW controls the internal refresh module 215 to turn on and store the data signal Data of the current frame F(n). During the subsequent frame F(n+1), the scan signal Gate and the data signal Data are not provided to the data writing module 211, and the data writing module 211 remains closed and does not perform data writing operations; during the data writing stage t1 of the subsequent frame F(n+1), the internal refresh control signal SW controls the internal refresh module 215 to turn on, the internal refresh control module 200 discharges, and transmits the stored data signal Data to the first node P1, so as to provide the data signal Data to the driving module 212 and the storage module 213, thereby realizing the self-refresh of the sub-pixel driving circuit 21.

[0072] In this embodiment, by setting an internal refresh module 215 in the sub-pixel driving circuit 21, when the data signal Data of the subsequent frame F(n+1) is the same as that of the current frame F(n), the internal refresh module 215 stores the data signal Data in the current frame F(n), and provides the data signal Data to the driving module 212 and the storage module 213 in the subsequent frame F(n+1). There is no need to rewrite the data. Therefore, when the display panel 100 displays the same content in the subsequent frame F(n+1), there is no need to refresh the sub-pixel driving circuit 21, thereby avoiding the waste of power consumption and reducing the power consumption of the display panel 100.

[0073] Specifically, the internal refresh module 215 includes a switching unit 2151 and a storage unit 2152. The control terminal of the switching unit 2151 is electrically coupled to the internal refresh control signal SW, the first terminal is connected to the first stage, the second terminal is connected to the first pole of the storage unit 2152, and the second pole of the storage unit 2152 is connected to the ground terminal GND.

[0074] When the data signal Data of the subsequent frame F(n+1) is detected to be the same as the data signal Data of the current frame F(n): During the data writing stage t1 of the current frame F(n), the internal refresh control signal SW controls the switch unit 2151 to turn on, and the storage unit 2152 stores the data signal Data of the current frame F(n). During the data writing stage t1 of the subsequent frame F(n+1), the internal refresh control signal SW controls the switch unit 2151 to turn on, the storage unit 2152 discharges, and the stored data signal Data is transmitted to the first node P1 through the switch unit 2151 to provide the data signal Data to the driving module 212 and the storage module 213, thereby realizing the self-refresh of the sub-pixel driving circuit 21.

[0075] In this embodiment, the internal structures of the data writing module 211, the driving module 212, the storage module 213, the light-emitting element 214, and the internal refresh module 215 are as follows:

[0076] The data writing module 211 includes a first switching transistor Q1. The control terminal of the first switching transistor Q1 is electrically coupled to the scan signal Gate, the input terminal is electrically coupled to the data signal Data, and the output terminal is connected to the first node P1.

[0077] The driving module 212 includes a driving transistor Q2. The control terminal of the driving transistor Q2 is connected to the first node P1. The first terminal is electrically coupled to the first power signal ELVDD. The second terminal is connected to the second node P2.

[0078] The storage module 213 includes a bootstrap capacitor Cst, the first terminal of which is connected to the first node P1 and the second terminal of which is connected to the second node P2.

[0079] The light-emitting element 214 includes a current-driven light-emitting device, such as a light-emitting diode (LED), a sub-millimeter light-emitting diode (Mini-LED), a micro-light-emitting diode (Micro-LED), or an organic light-emitting diode (OLED). In this embodiment, the light-emitting element 214 is a Mini-LED; in other embodiments, the light-emitting element 214 may be other types of light-emitting devices. The light-emitting element 214 includes a first electrode and a second electrode. The first electrode is connected to a second node P2, and the second electrode is electrically coupled to a second power supply signal ELVSS. The first electrode may be an anode, and the second electrode may be a cathode; in other embodiments, the first electrode may be a cathode, and the second electrode may be an anode.

[0080] In the internal refresh unit, the switching unit 2151 includes a second switching transistor Q5, and the storage unit 2152 includes a storage capacitor Csr; the control terminal of the second switching transistor Q5 is electrically coupled to the internal refresh control signal SW, the first terminal is connected to the first node P1, the second terminal is connected to the first terminal of the storage capacitor Csr, and the second terminal of the storage capacitor Csr is connected to the ground terminal GND.

[0081] The transistors and driving transistor Q2 described above can be N-type transistors or P-type transistors; they can be silicon-based transistors, such as amorphous silicon (a-Si) transistors, hydrogenated amorphous silicon (a-Si:H) transistors, low-temperature polycrystalline silicon (LTPS) transistors, or low-temperature polycrystalline oxide (LTPO) transistors. In this embodiment, N-type transistors are used as an example for illustration.

[0082] In this embodiment, the refresh driving method of the sub-pixel driving circuit 21 is as follows:

[0083] Please see Figure 2 and Figure 3 , Figure 3 yes Figure 2 The timing diagram for the refresh drive corresponding to the mid-pixel drive circuit. When the data signal Data of the subsequent frame F(n+1) is detected to be the same as the data signal Data of the current frame F(n):

[0084] In the current frame F(n), during the data writing phase t1, the scan signal Gate is high, the first switching transistor Q1 is turned on, and the data signal Data is transmitted to the first node P1 through the first switching transistor Q1. The bootstrap capacitor Cst is charged, and the potential of the control terminal of the driving transistor Q2 rises to the data voltage to realize the data writing operation and refresh the screen. At the same time, during the data writing phase t1, the internal refresh control signal SW is also high, the second switching transistor Q5 is turned on, and the data signal Data charges the storage capacitor Csr through the second switching transistor Q5 to store the data signal Data.

[0085] In the subsequent frame F(n+1), during the data writing phase t1, the scan signal Gate is low, the first switching transistor Q1 is off, and no data writing or screen refresh occurs. During the data writing phase t1, the internal refresh control signal SW is high, the second switching transistor Q5 is on, the storage capacitor Csr discharges, and the discharge is sent to the first node P1 through the second switching transistor Q5 to provide a gate voltage to the control terminal of the driving transistor Q2, so that the light-emitting element 214 maintains the same brightness as the current frame F(n) and displays the same image.

[0086] Please see Figure 2 and Figure 4 , Figure 4 yes Figure 2 Another refresh driving timing diagram corresponding to the pixel driving circuit. When the data signal Data of the subsequent frame F(n+1) is detected to be different from the data signal Data of the current frame F(n), the pixel driving circuit 21 performs normal refresh display, while the internal refresh module 215 remains off, does not store the data signal Data to save power, and does not perform self-refresh operation, as follows:

[0087] In the current frame F(n), during the data writing phase t1, the scan signal Gate is high, the first switching transistor Q1 is turned on, and the data signal Data is transmitted to the first node P1 through the first switching transistor Q1. The bootstrap capacitor Cst is charged, raising the potential of the control terminal of the driving transistor Q2 to the data voltage to realize the data writing operation and refresh the screen. In this frame, the internal refresh control signal SW is always low, keeping the second switching transistor Q5 off during the current frame F(n), and the storage capacitor Csr does not charge or discharge, saving power consumption.

[0088] In the subsequent frame F(n+1), during the data writing phase t1, the scan signal Gate is high, the first switching transistor Q1 is turned on, and the new data signal Data is transmitted to the first node P1 through the first switching transistor Q1. The bootstrap capacitor Cst is charged, and the potential of the control terminal of the driving transistor Q2 changes to the new data voltage, thereby realizing the data rewriting operation and refreshing the screen to display the new image. In this frame, the internal refresh control signal SW is always low, so that the second switching transistor Q5 remains off during the current frame F(n), and the storage capacitor Csr does not charge or discharge, saving power consumption.

[0089] Please see Figure 5 , Figure 5 This is a schematic diagram of the pixel driving circuit provided in another embodiment of this application. In this embodiment, another pixel driving circuit 21 is provided. Unlike the previous embodiment, the pixel driving circuit 21 in this embodiment also includes a reset module 216. The control terminal of the reset module 216 is electrically coupled to the reset control signal Rst, the first connection terminal is connected to the first node P1, and the second connection terminal is connected to the second node P2, for resetting the potential of the first node P1 and the potential of the second node P2.

[0090] In this embodiment, to ensure the accuracy, consistency, absence of ghosting, and good signal quality of image display, the sub-pixel driving circuit 21 performs a reset operation through the reset module 216 at the initial stage of each frame. Specifically, during the reset stage t0, the reset control signal Rst controls the reset module 216 to turn on, resetting the potentials of the first node P1 and the second node P2 so that the potentials of the first node P1 and the second node P2 become the initial state voltages.

[0091] Furthermore, when the data signal Data of the subsequent frame F(n+1) is the same as the data signal Data of the current frame F(n), the reset module 216 only resets the potential of the first node P1 and the potential of the second node P2 during the reset phase t0 of the current frame F(n). It can be understood that when the data signal Data of the subsequent frame F(n+1) is the same as the data signal Data of the current frame F(n), that is, the brightness of the subsequent frame F(n+1) is the same as that of the previous frame, there are no problems such as ghosting. Therefore, the subsequent frame F(n+1) does not need to be reset to reduce power consumption.

[0092] Specifically, the internal structure of the reset module 216 is as follows:

[0093] The reset module 216 includes a first reset unit 2161 and a second reset unit 2162.

[0094] The first reset unit 2161 includes a first reset transistor Q3. The control terminal of the first reset transistor Q3 is electrically coupled to a reset control signal Rst, the first terminal is electrically coupled to a reference voltage signal Vref, and the second terminal is connected to the first node P1, so as to reset the potential of the first node P1 to the reference voltage under the control of the reset control signal Rst.

[0095] The second reset unit 2162 includes a second reset transistor Q4. The control terminal of the second reset transistor Q4 is electrically coupled to the reset control signal Rst, the first terminal is electrically coupled to the second power supply signal ELVSS, and the second terminal is connected to the second node P2, so as to reset the potential of the second node P2 to the second power supply voltage under the control of the reset control signal Rst.

[0096] Similarly, the first reset transistor Q3 and the second reset transistor Q4 are of the same or similar type as the transistors in the modules described above. Please refer to the relevant descriptions above for details.

[0097] In this embodiment, each frame includes a reset phase t0, a data writing phase t1, and a light emission phase arranged in chronological order; the reset phase t0 occurs at the beginning of each frame. The specific reset method of the sub-pixel driving circuit 21 is as follows:

[0098] Please refer to the figure. Figure 5 and Figure 6, Figure 6 yes Figure 5 The timing diagram for the refresh drive corresponding to the mid-pixel drive circuit. When the data signal Data of the subsequent frame F(n+1) is detected to be the same as the data signal Data of the current frame F(n):

[0099] In the current frame F(n), during the reset phase t0, the reset control signal Rst is high, the first reset transistor Q3 and the second reset transistor Q4 are turned on, the reference voltage signal Vref is transmitted to the first node P1 through the first reset transistor Q3, the control terminal potential of the driving transistor Q2 changes to the reference voltage signal Vref, and the driving transistor Q2 is turned off; at the same time, the second power supply signal ELVSS is transmitted to the second node P2 through the second reset transistor Q4, so that the potential of the first electrode of the light-emitting element 214 is the same as the potential of the second electrode, the light-emitting element 214 is not turned on, thereby completing the reset operation.

[0100] In the subsequent frame F(n+1), during the reset phase t0, the reset control signal Rst remains low, the first reset transistor Q3 and the second reset transistor Q4 are turned off, the potentials of the first node P1 and the second node P2 remain at their original states, and the light-emitting element 214 maintains its original brightness to continue displaying the original image. In the subsequent frame F(n+1), no reset operation is performed, thereby reducing power consumption.

[0101] Please see Figure 5 and Figure 7 , Figure 7 yes Figure 5 Another refresh drive timing diagram corresponding to the mid-pixel drive circuit. When the data signal Data of the subsequent frame F(n+1) is detected to be different from the data signal Data of the current frame F(n):

[0102] In the current frame F(n), during the reset phase t0, the reset control signal Rst is high, the first reset transistor Q3 and the second reset transistor Q4 are turned on, the reference voltage signal Vref is transmitted to the first node P1 through the first reset transistor Q3, the control terminal potential of the driving transistor Q2 changes to the reference voltage signal Vref, and the driving transistor Q2 is turned off; at the same time, the second power supply signal ELVSS is transmitted to the second node P2 through the second reset transistor Q4, so that the potential of the first electrode of the light-emitting element 214 is the same as the potential of the second electrode, the light-emitting element 214 is not turned on, thereby completing the reset operation.

[0103] In the later frame F(n+1), during the reset phase t0, the reset control signal Rst goes high, and the first reset transistor Q3 and the second reset transistor Q4 are turned on to perform a reset operation on the first node P1 and the second node P2 again, in preparation for image refresh.

[0104] In this embodiment, the capacity of the storage capacitor Csr can be adjusted so that when the data signals Data are the same for several consecutive frames, the second switching transistor Q5 only needs to be turned on in the current frame F(n) to charge the storage capacitor Csr. In the subsequent frames, the pixel driving circuit 21 does not need to be reset and the data signals Data need to be rewritten. The storage capacitor Csr is discharged so that the driving transistor Q2 generates a corresponding driving current, so that the light-emitting element 214 maintains the same brightness as the previous frame, which can further reduce the power consumption of the display panel 100.

[0105] Please see Figure 8 , Figure 8 This is a flowchart illustrating a driving method for a display panel according to an embodiment of this application. In this embodiment, a driving method for a display panel 100 is provided, which is used to drive the display panel 100 involved in the above embodiments. The driving method includes:

[0106] S1: Obtain the current frame F(n) signal and the next frame signal, and process them;

[0107] S2: Determine whether the content of the next frame is the same as the content of the current frame F(n);

[0108] S3: In response to the fact that the content of the next frame is the same as the content of the current frame F(n), the internal refresh control signal SW controls the internal refresh module 215 to be turned on during the data writing phase t1 of the current frame F(n), so that the internal refresh module 215 stores the data signal Data of the current frame F(n), turns on during the data writing phase t1 of the next frame, and transmits the stored data signal Data to the first node P1; the scan signal Gate controls the data writing module 211 to remain off in the next frame;

[0109] S4: In response to the fact that the content of the next frame is different from the content of the current frame F(n), the scanning signal Gate controls the data writing module 211 to start in the data writing stage t1 of the next frame, so as to write the corresponding data signal Data to the first node P1.

[0110] Please see Figure 9 , Figure 9 yes Figure 8 A flowchart illustrating one embodiment of step S1 is provided. In this embodiment, step S1 specifically includes:

[0111] S11: Obtain the data signal Data of the current frame F(n) and the data signal Data of the next frame;

[0112] S12: Compare the data signal Data of the next frame with the current data signal Data one by one.

[0113] Specifically, the number of data signals Data in each frame is the same as and corresponds one-to-one with the number of pixel driving circuits 21 on the display panel 100. During comparison, the data signals Data of the next frame are compared one-to-one with the data signals Data of the current frame F(n). If each data signal Data of the next frame is the same as the corresponding data signal Data of the current frame F(n), it is determined that the content of the next frame is the same as the content of the current frame F(n). Then, step S3 is executed. Each pixel driving circuit 21 activates its internal refresh module 215 to store the current data signal Data in the current frame F(n), and activates its internal refresh module 215 in the next frame to provide the stored data signal Data to the driving module 212 and the storage module 213, thus achieving self-refresh without rewriting the data signal Data, thereby reducing the power consumption of the display panel 100. For the specific driving process, please refer to [link to relevant documentation]. Figure 2 and Figure 3 The corresponding text description above will not be repeated here.

[0114] If the subsequent frame contains a data signal Data that is different from the current frame F(n), it is determined that the content of the subsequent frame is different from the content of the current frame F(n). Then, step S4 is executed, and the pixel driving circuit 21 also performs a data writing operation in the subsequent frame to refresh the display screen. During this driving process, the internal refresh module 215 of the pixel driving circuit 21 remains closed, and does not store or self-refresh the data signal Data, thereby reducing the power consumption of the display panel 100. For the corresponding driving process, please refer to [link to relevant documentation]. Figure 2 and Figure 4 The corresponding text description above will not be repeated here.

[0115] In another embodiment, the sub-pixel driving circuit 21 further includes a reset module 216, which performs a reset operation during the frame start phase and before the data writing phase t1 during screen refresh. Correspondingly, the driving method of the display panel 100 further includes:

[0116] S31: In response to the fact that the content of the next frame is the same as the content of the current frame F(n), the reset control signal Rst controls the reset module 216 to remain closed during the reset phase t0 of the next frame and not to perform a reset.

[0117] S32: In response to the fact that the content of the next frame is different from the content of the current frame F(n), the reset control signal Rst controls the reset module 216 to be turned on in the reset phase t0 of the next frame, so as to reset the potential of the first node P1 and the potential of the second node P2.

[0118] In each frame, the reset phase t0 is located at the frame start phase and before the data write phase t1. If the content of the subsequent frame is the same as the content of the current frame F(n), then no reset operation is performed in the subsequent frame to reduce power consumption. If the content of the subsequent frame is different from the content of the current frame F(n), then a reset operation is still performed in the subsequent frame. For a detailed description of the reset process, please refer to [link to relevant documentation]. Figure 5-7 The corresponding text descriptions mentioned above will not be repeated here.

[0119] Please see Figure 10 , Figure 10 yes Figure 8 A flowchart illustrating another embodiment of step S1 is provided. In this embodiment, step S1 specifically includes:

[0120] S11: Obtain the data signal Data of the current frame F(n) and the data signal Data of the next frame;

[0121] S12': Compare the data signal Data of the next frame with the data signal Data of the current frame F(n) line by line.

[0122] When the content of the next frame is not completely the same as the content of the current frame F(n), but only partially the same, the display panel 100 can refresh only the areas with different content, and not refresh the areas with the same content. The pixel driving circuit 21 located in the area is driven by the self-refresh method described above, without rewriting the data, thereby further reducing the power consumption of the display panel 100.

[0123] Correspondingly, step S2 specifically includes: judging line by line whether the data signal Data of the next frame is the same as the data signal Data of the current frame F(n).

[0124] Specifically, the data signal Data of the next frame is compared line by line with the data signal Data of the current frame F(n). If the data signal Data of the i-th row of the next frame is the same as the data signal Data of the i-th row of the current frame F(n), then the pixel driving circuit 21 of the i-th row will not be refreshed in the next frame, and its driving process is the same as... Figure 3 or Figure 6 The process is the same; please refer to the above description for details. If the k-th row data signal Data of the next frame is different from the k-th row data signal Data of the current frame F(n), then in the next frame, the k-th row pixel driving circuit 21 will still be refreshed, and its driving process is the same as... Figure 4 or Figure 7 The same applies; please refer to the above description for details. Here, i and k are positive integers, and not greater than the number of rows in pixel driving circuit 21.

[0125] In this embodiment, by comparing the data signals Data of the preceding and following frames F(n+1) line by line, when the content of the following frame is partially the same as the content of the current frame F(n) in the line arrangement direction, the pixel driving circuit 21 in the partially the same area does not perform reset and refresh, only the pixel driving circuit 21 in the area with different content performs reset and refresh operation, so as to optimize power consumption and further reduce the power consumption of the display panel 100.

[0126] Please see Figure 11 , Figure 11 This is a display device provided in one embodiment of the present application. In this embodiment, a display device is provided, which includes a display panel 100 and a control module 200.

[0127] The display panel 100 is the same as the display panel 100 mentioned in the above embodiments, and has the same structure and function as the display panel 100 mentioned in the above embodiments, and can achieve the same technical effect. For details, please refer to the above detailed description.

[0128] The control module 200 is coupled to the display panel 100 and is used to drive the display panel 100. The driving method is the driving method described in the above embodiments, which has the same technical effect as the driving method described in the above embodiments. For details, please refer to the above description.

[0129] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A pixel driving circuit, comprising: The data writing module has its control terminal electrically coupled to the scan signal, its input terminal electrically coupled to the data signal, and its output terminal connected to the first node. The drive module has a control terminal connected to the first node, a first terminal electrically coupled to a first power signal, and a second terminal connected to the second node. The storage module has a first end connected to the first node and a second end connected to the second node; The light-emitting element has a first electrode connected to the second node and a second electrode electrically coupled to a second power supply signal. The pixel driving circuit is characterized in that it further includes an internal refresh module, wherein the control terminal of the internal refresh module is electrically coupled to an internal refresh control signal, and the first connection terminal is connected to the first node. When the data signal of the subsequent frame is the same as the data signal of the current frame, the internal refresh control signal controls the internal refresh module to start during the data writing phase of the current frame to store the data signal of the current frame; and controls the internal refresh module to start during the data writing phase of the subsequent frame to transmit the stored data signal to the first node; wherein, the data writing module remains closed in the subsequent frame.

2. The pixel driving circuit according to claim 1, characterized in that, The internal refresh module includes a switching unit and a storage unit; the control terminal of the switching unit is electrically coupled to the internal refresh control signal, the first terminal is connected to the first node, and the second terminal is connected to the first pole of the storage unit; the second pole of the storage unit is connected to the ground terminal.

3. The pixel driving circuit according to claim 2, characterized in that, The data writing module includes a first switching transistor, the control terminal of which is electrically coupled to the scan signal, the input terminal of which is electrically coupled to the data signal, and the output terminal of which is connected to the first node. The driving module includes a driving transistor. The control terminal of the driving transistor is connected to the first node, the first terminal is electrically coupled to the first power signal, and the second terminal is connected to the second node. The storage module includes a bootstrap capacitor, with its first terminal connected to the first node and its second terminal connected to the second node. The switching unit includes a second switching transistor, and the storage unit includes a storage capacitor; the control terminal of the second switching transistor is electrically coupled to the internal refresh control signal, the first terminal is connected to the first node, the second terminal is connected to the first electrode of the storage capacitor, and the second electrode of the storage capacitor is connected to the ground terminal.

4. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit further includes a reset module; the first connection terminal of the reset module is connected to the first node, and the second connection terminal is connected to the second node, for resetting the potential of the first node and the potential of the second node; and... When the data signal of the subsequent frame is the same as the data signal of the current frame, the reset module resets the potential of the first node and the potential of the second node only during the reset phase of the current frame.

5. The pixel driving circuit according to claim 4, characterized in that, The reset module includes a first reset transistor and a second reset transistor; The control terminal of the first reset transistor is electrically coupled to a reset control signal, the first terminal is electrically coupled to a reference voltage signal, and the second terminal is connected to the first node, so as to reset the potential of the first node to the reference voltage under the control of the reset control signal; The control terminal of the second reset transistor is electrically coupled to the reset control signal, the first terminal is electrically coupled to the second power supply signal, and the second terminal is connected to the second node, so as to reset the potential of the second node to the second power supply voltage under the control of the reset control signal.

6. A display panel, characterized in that, include: Substrate; A pixel driving layer is disposed on the substrate and includes a plurality of pixel driving circuits as described in any one of claims 1-5.

7. A driving method for a display panel, characterized in that, The display panel is the display panel as described in claim 6, and the driving method includes: Acquire the current frame signal and the next frame signal, and process them; Determine whether the content of the next frame is the same as the content of the current frame; In response to the fact that the content of the next frame is the same as the content of the current frame, the internal refresh control signal controls the internal refresh module to be turned on during the data writing phase of the current frame, so that the internal refresh module stores the data signal of the current frame, turns on during the data writing phase of the next frame, and transmits the stored data signal to the first node; the scan signal controls the data writing module to remain off in the next frame. In response to the fact that the content of the next frame is different from the content of the current frame, the scanning signal controls the data writing module to start during the data writing phase of the next frame, so as to write the corresponding data signal into the first node.

8. The driving method according to claim 7, characterized in that, The pixel driving circuit in the display panel also includes a reset module; the first end of the reset module is connected to the first node, and the second end is connected to the second node, for resetting the potential of the first node and the potential of the second node; The driving method further includes: In response to the fact that the content of the next frame is the same as the content of the current frame, the reset control signal controls the reset module to remain closed during the reset phase of the next frame and not to perform a reset. In response to the fact that the content of the next frame is different from the content of the current frame, the reset control signal controls the reset module to start during the reset phase of the next frame in order to reset the potential of the first node and the potential of the second node.

9. The driving method according to claim 7, characterized in that, The steps of acquiring the current frame signal and the next frame signal and processing them include: Obtain the data signal of the current frame and the data signal of the next frame; The data signal of the next frame is compared with the data signal of the current frame line by line; The step of determining whether the content of the next frame is the same as the content of the current frame includes: determining line by line whether the data signal of the next frame is the same as the data signal of the current frame.

10. A display device, characterized in that, include: The display panel is the display panel as described in claim 6; A control module, coupled to the display panel, is used to execute the driving method as described in any one of claims 7-9 to drive the display panel.

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