A double-pulse data calculation device and method

Abstract

The present invention discloses a dual-pulse data operation device and method. The device includes: a storage module including at least one storage array composed of a plurality of storage cells, wherein the storage cells include at least a strobe port, a data port, and a control port; a dual-pulse generation module electrically connected to the storage module, the dual-pulse generation module is used to generate a data input pulse signal and a state switching pulse signal, and apply the data input pulse signal and the state switching pulse signal to the data port and the control port of the storage cell, respectively; an enable control module electrically connected to the storage module, and is used to output an enable signal to the strobe port to select a specified storage cell; a data reading module electrically connected to the storage module, the data reading module is used to read data from the storage cell; and a global control module electrically connected to the dual-pulse generation module, the enable control module, and the data reading module. The present invention achieves higher accuracy than read-in-memory calculation.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a double-pulse data operation device and method. Background Art

[0002] Pulse-based in-memory computing is one of the means to achieve analog in-memory computing. Pulse-based in-memory computing is implemented by a pulse-based storage computing array, which takes multiple pulse signals as input, can complete data writing functions, has storage functions, can achieve data accumulation functions, has data reading functions, etc. The pulse-based in-memory computing architecture includes a data writing module, a pulse input module, a storage array, a data accumulation module, and a data reading module. Among them, the data writing module can write weight data into the storage unit of the storage array; the pulse input module converts the input data into a single pulse signal of multiple branches; the storage array is composed of storage units, which are used to store weights and express the weights as the resistance value or conductance value of the memory. Under the action of multiple single pulse signals, the relationship between the resistance, voltage or current of the memory is used to complete the product operation, and the operation result is expressed as the current value or voltage value of the memory; then the data accumulation module completes the accumulation operation in the current domain or charge domain according to the result of the product operation; the data reading module reads the calculated data to complete the in-memory computing. During the implementation of pulsed in-memory computing, the nonlinearity of the storage unit will reduce the accuracy of the calculation results, and the analog-to-digital converter in the data reading module will occupy a large area, thereby reducing the area efficiency of the in-memory computing. At the same time, the in-memory computing efficiency of a single pulse applied to the storage unit is low, the calculation speed of completing the in-memory calculation is slow, and the computing power consumption is also high. Therefore, it is necessary to propose an in-memory computing method with high accuracy, small circuit area, fast computing speed, and low computing power consumption. Summary of the Invention

[0003] The embodiment of the present invention provides a dual-pulse data operation device and method, which is used to at least solve the problems of slow calculation speed, high calculation power consumption, low calculation result accuracy and large circuit area in the implementation process of in-memory calculation in the prior art.

[0004] According to a first aspect of the present invention, a dual-pulse data operation device is provided, comprising:

[0005] A storage module, comprising at least one storage array consisting of a plurality of storage units, wherein the storage units at least include a strobe port, a data port, and a control port;

[0006] a dual-pulse generating module electrically connected to the storage module, the dual-pulse generating module being used to generate a data input pulse signal and a state switching pulse signal, and applying the data input pulse signal and the state switching pulse signal to the data port and the control port of the storage unit, respectively, for controlling the data writing function and the state switching speed of the storage unit, respectively;

[0007] An enable control module, electrically connected to the storage module, configured to output an enable signal to the strobe port to select a designated storage unit;

[0008] a data reading module, electrically connected to the storage module, and configured to read data from the storage unit;

[0009] The global control module is electrically connected to the dual pulse generation module, the enable control module, and the data reading module. The global control module controls the port signal of the storage unit through the dual pulse generation module, the enable control module, and the data reading module to achieve complete data calculation.

[0010] According to some embodiments of the present invention, the data reading module is a sense amplifier.

[0011] According to some embodiments of the present invention, the data port includes a first data port and a second data port.

[0012] According to some embodiments of the present invention, the storage unit is composed of a storage device and a transistor, and the storage device is composed of an upper plate, an insulating layer, a free layer, a barrier layer, a fixed layer, an insulating layer and a lower plate stacked in sequence, the first data port is electrically connected to the drain of the transistor, the second data port is electrically connected to the free layer, the selection port is electrically connected to the gate of the transistor, and the control port is electrically connected to the upper plate.

[0013] A double-pulse data calculation method according to a second aspect of the present invention includes:

[0014] Outputting an enable signal to the strobe port of the storage unit to select the specified storage unit;

[0015] Modulating a data input pulse signal and a state switching pulse signal, and applying the data input pulse signal and the state switching pulse signal to a data port and a control port of the storage unit respectively;

[0016] The data of the storage unit is read to obtain the result of the double-pulse data operation.

[0017] According to some embodiments of the present invention, the modulating data input pulse signal and the state switching pulse signal includes:

[0018] Modulating the amplitude and pulse width of the data input pulse signal and the state switching pulse signal based on a preset operation logic;

[0019] The application sequence of the data input pulse signal and the state switching pulse signal is adjusted for different ports.

[0020] According to some embodiments of the present invention, the data input pulse signal and the state switching pulse signal are non-reciprocal.

[0021] According to an embodiment of the present invention, a global control module is used to control a dual-pulse generating module, an enabling control module, and a data reading module to realize complete data operations on a memory. By more compactly applying a dual-pulse signal to the dual-pulse data operation device, a variety of operations can be completed within an operation device or a combination of multiple operation devices, and the operation results can be stored in the operation device. The circuit area of ​​the operation device is smaller, and the accuracy of the in-memory calculation operation is higher. At the same time, under the action of the dual-pulse signal, the in-memory calculation speed is faster and the calculation energy consumption is lower.

[0022] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Various other advantages and benefits will become apparent to those skilled in the art by reading the detailed description of the embodiments below. The accompanying drawings are only for the purpose of illustrating preferred embodiments and are not to be considered as limiting the present invention. In the accompanying drawings:

[0024] Figure 1 2 is a schematic structural diagram of a dual-pulse data operation device according to an embodiment of the first aspect of the present invention;

[0025] Figure 2 is a connection diagram of a storage unit port in an embodiment of the first aspect of the present invention;

[0026] Figure 3 It is a flow chart of the double-pulse data calculation method in the embodiment of the second aspect of the present invention. DETAILED DESCRIPTION

[0027] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0028] A first embodiment of the present invention provides a dual-pulse data operation device, comprising:

[0029] The storage module includes at least one storage array composed of a plurality of storage cells, wherein the storage cells include at least a strobe port, a data port, and a control port. It is understandable that the number of the three types of ports of the storage cells is not specifically limited here. The strobe port is used to apply an enable signal to select a specified storage cell in the storage array according to an external address instruction. Only the storage cell selected by the enable signal can implement a write function or a read function. The data port is used to transmit a data signal to the specified storage cell and implement functions such as writing data, reading data, refreshing data, or performing logical calculations on it. The control port is used to change the properties of the storage cell other than the storage state.

[0030] A dual-pulse generation module is electrically connected to the memory module. The dual-pulse generation module is used to generate a data input pulse signal and a state switching pulse signal, and apply the data input pulse signal and the state switching pulse signal to the data port and the control port of the memory unit, respectively, to control the data writing function and state switching speed of the memory unit, respectively. The switching speed refers to the speed at which the data stored in the memory changes from 1 to 0 or from 0 to 1. The storage state of the memory unit is changed or maintained by controlling the dual-pulse signal.

[0031] The enabling control module is electrically connected to the storage module and is used to output an enabling signal to the strobe port to select a designated storage unit. It is understandable that only one storage unit is selected here, that is, one storage unit is called.

[0032] A data reading module is electrically connected to the storage module, and the data reading module is used to read the data in the storage unit.

[0033] The global control module is electrically connected to the dual pulse generation module, the enable control module, and the data reading module. The global control module controls the port signal of the storage unit through the dual pulse generation module, the enable control module, and the data reading module to achieve complete data calculation.

[0034] According to an embodiment of the present invention, a global control module is used to control a dual-pulse generating module, an enabling control module, and a data reading module to realize complete data operations on a memory. The dual-pulse data operation can complete logical operations such as "NAND", "NOR", and "majority gate" in a single memory cell only by inputting a dual-pulse signal from the memory cell. By more compactly applying the dual-pulse signal to the dual-pulse data operation device, multiple operations can be completed in a single operation device or a combination of multiple operation devices, and the operation results can be stored in the operation device. The circuit area of ​​the operation device is smaller, the linearity of the in-memory calculation operation is higher, and the accuracy of the output result is better.

[0035] Based on the above embodiment, various modified embodiments are further proposed. It should be noted that, in order to simplify the description, only the differences from the above embodiment are described in each modified embodiment.

[0036] According to some embodiments of the present invention, the data port includes a first data port and a second data port.

[0037] According to some embodiments of the present invention, a control path is added for implementing the logic calculation function of the storage unit by applying a pulse signal to a control port; then, a controlled variable is added by applying the pulse signal to the control port, and a plurality of logic operations are implemented by combining it with the original pulse signal applied to the data port.

[0038] According to some embodiments of the present invention, the data reading module is a sense amplifier. The sense amplifier compares the stored data of the memory cell with a decision threshold in the form of voltage or current, and outputs the comparison result. It is understandable that the decision threshold can be defined as a comparison benchmark during the memory reading process. By comparing the read voltage or read current of the memory cell with the decision threshold, the current or voltage above the decision threshold or below the decision threshold can be distinguished into two states, and the data stored in the memory can be distinguished based on these two states. The method for generating the decision threshold includes generating a reference voltage or current based on a reference memory cell; or generating a reference voltage or reference current by a reference module, and the generated voltage or current signal is equivalent to the decision threshold. When selecting the calculation result, from the output port of the sense amplifier, according to the required logic selection, a selection is made from the positive output terminal and the negative output terminal of the sense amplifier to obtain the voltage signal of the calculation result.

[0039] According to some embodiments of the present invention, referring to Table 1, the data operation method based on the dual pulse signal input, when implementing the OR-N logic or the AND-N logic, its logic signal can be divided into: (1) the resistance state of the memory, denoted as R, wherein the resistance state during reset is denoted as R1, and the resistance state after the operation is denoted as R2; (2) the amplitude of the data write pulse is denoted as B; (3) the time of the state switching pulse is denoted as C.

[0040] Assuming that the time required for reset is T1, the time required for logical operation is T2, and the time required for reading is T3, the total time required to complete an in-memory calculation is T=T1+T2+T3. At this time, in the data writing stage, the data writing pulse and the state switching pulse act synchronously on the port of the storage unit.

[0041] When implementing the OR-NOT logic, R=1 represents that the memory state is high-impedance state, and R=0 represents that the memory state is low-impedance state; B=1 represents that the data write pulse amplitude is large, and B=0 represents that the data write pulse amplitude is small; C=1 represents that the action time of the state switching pulse is T1+T2, and C=0 represents that the action time of the state switching pulse is T1. When C=1, the data write pulse and the state switching pulse act together in the logic operation stage. When C=0, there is only a data write pulse in the logic operation stage, and no state switching pulse.

[0042] According to the logic to be completed, the reset signal is determined to be 1, and the global control module controls the dual-pulse generation module and the enable control module. The enable control module controls the enable signal to be high, enabling the data writing function of the storage unit; the dual-pulse generation module outputs a state switching pulse and keeps the amplitude of the state switching pulse at a high level to speed up the state switching speed of the storage unit; the dual-pulse generation module outputs a data writing pulse and controls the amplitude of the data writing pulse to be positive. The voltage of the first data port is greater than the voltage of the second data port, generating a current from the free layer to the fixed layer. The current will change the direction of the magnetic field of the free layer to be opposite to that of the fixed layer, corresponding to a high-resistance state, and write data 1.

[0043] To implement the NOR logic, the enable control module controls the enable signal to a high level, enabling the memory cell's in-memory calculation function. The dual pulse signal is determined based on the logic input. First, the amplitude of the data write pulse is negative, and the voltage at the first data port is greater than the voltage at the second data port, generating a current from the fixed layer to the free layer, corresponding to writing data 0. The memory's initial state is 1. Only when the amplitude of the data write pulse is small and the state switching pulse lasts for T1, the write current is too short or too small to change the memory's storage state to 0. For B = 0 and C = 0, R2 = 1 is output; otherwise, R2 = 0 is output, completing the NOR logic operation.

[0044] R1 B C R2 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0

[0045] Table 1: Truth table for implementing OR / NOT logic

[0046] According to some embodiments of the present invention, referring to Table 2, after completing the NOR logic operation, the result of the logic operation is stored in the memory, and the global control module controls the dual-pulse generation module, the enable control module, and the data reading module. The enable control module controls the enable signal to a high level, enabling the data reading function of the storage unit; the dual-pulse generation module controls the amplitude of the state switching pulse to a low level, reducing the state switching speed of the storage unit and reducing the probability of read disturbance in the memory during the data reading phase. Simultaneously, the storage unit is connected to the sense amplifier to read the data from the memory. The positive output of the sense amplifier is the result of the NOR logic operation, and the negative output of the sense amplifier is the result of the OR logic operation.

[0047] The data operation method based on the double pulse signal input and the non-logical logic can be divided into:

[0048] (1) The resistance state of the memory, denoted as R, where the resistance state during reset is denoted as R1 and the resistance state after in-memory calculation is denoted as R2; (2) The amplitude of the data write pulse is denoted as B; (3) The duration of the state switching pulse is denoted as C.

[0049] Assuming that the time required for a reset is T1, the time required for a logical operation is T2, and the time required for a read is T3, the total time required to complete an in-memory calculation is T = T1 + T2 + T3. During the data write phase, the data write pulse and the state switching pulse are synchronously applied to the port of the memory cell.

[0050] When implementing NAND logic, R = 1 represents a high-impedance state for the memory, while R = 0 represents a low-impedance state for the memory. B = 1 represents a low-amplitude data write pulse, while B = 0 represents a high-amplitude data write pulse. C = 1 represents a state-switching pulse duration of T1, while C = 0 represents a state-switching pulse duration of T1 + T2. When C = 0, the data write pulse and the state-switching pulse are applied synchronously to the memory cell port during the logic operation phase. When C = 1, only the data write pulse is applied during the logic operation phase, with no state-switching pulse.

[0051] According to the logic to be completed, the reset signal is determined to be 0, and the global control module controls the dual-pulse generation module and the enable control module. The enable control module controls the enable signal to be high, enabling the data writing function of the storage unit; the dual-pulse generation module outputs a state switching pulse and keeps the amplitude of the state switching pulse at a high level to speed up the state switching speed of the storage unit; the dual-pulse generation module outputs a data writing pulse and controls the amplitude of the data writing pulse to be negative. The voltage of the first data port is less than the voltage of the second data port, generating a current from the fixed layer to the free layer. The current will change the direction of the magnetic field of the free layer to the same as that of the fixed layer, corresponding to a low resistance state, and write data 0.

[0052] To implement the NAND logic, the enable control module sets the enable signal to a high level, enabling the memory cell's in-memory calculation function. The dual pulse signal is determined based on the logic input. First, the amplitude of the data write pulse is positive, and the voltage at the first data port is greater than the voltage at the second data port, generating a current from the free layer to the fixed layer, corresponding to writing data 1. The memory's initial state is 0. Only when the amplitude of the data write pulse is small and the state switching pulse lasts for T1, the write current is too short or too small to change the memory's storage state to 1. For B = 1 and C = 1, R2 = 0 is output; otherwise, R2 = 1 is output, completing the NAND logic operation.

[0053] R1 B C R2 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0

[0054] Table 2: Truth table for implementing AND-NOT logic

[0055] According to some embodiments of the present invention, after completing a "NAND" logic operation, the result of the logic operation is stored in a memory. The global control module controls the dual-pulse generation module, the enable control module, and the data reading module. The enable control module controls the enable signal to a high level, enabling the data reading function of the memory cell. The dual-pulse generation module controls the amplitude of the state switching pulse to a low level, reducing the state switching speed of the memory cell and reducing the probability of read disturbance in the memory during the data reading phase. Simultaneously, the memory cell is connected to a sense amplifier to read the data from the memory. The positive output of the sense amplifier is the result of the "NAND" logic operation, and the negative output of the sense amplifier is the result of the "AND" logic operation.

[0056] The data operation method based on pulse control realizes the "majority gate" logic, and its logic signal can be divided into (1) the resistance state of the memory, denoted as R, wherein the resistance state during reset is denoted as R1, and the resistance state after the logic operation is denoted as R2; (2) the amplitude of the data write pulse, wherein the amplitude of the data write pulse is determined by the logic signal B and the logic signal C. When realizing the "majority gate" logic, the logic signal A is used as the reset signal, and the reset signal A is stored in the memory in the form of a resistor, R=1 represents that the memory state is a high resistance state, and R=0 represents that the memory state is a low resistance state; A=1 represents that the initial state of the memory is a high resistance state, and A=0 represents that the initial state of the memory is a low resistance state; the amplitude of the data write pulse can be obtained according to the combination of the logic signal B and the logic signal C, wherein when B=1 and C=0 or B=0 and C=1, the amplitude of the data write pulse is 0; when B=0 and C=0, the amplitude of the data write pulse is negative; when B=1 and C=1, the amplitude of the data write pulse is positive. At this time, during the data writing and logic operation phase, the data writing pulse and the state switching pulse act together.According to the logic to be completed, the reset signal is determined to be A, the global control module controls the dual pulse generation module and the enable control module, the enable control module controls the enable signal to be high level, and enables the data writing function of the storage unit; the dual pulse generation module outputs a state switching pulse, and keeps the amplitude of the state switching pulse at a high level to speed up the state switching speed of the storage unit; the dual pulse generation module outputs a data writing pulse, if A=0, the amplitude of the data writing pulse is controlled to be negative, the voltage of the first data port is less than the voltage of the second data port, and a current is generated from the fixed layer to the free layer. The current will change the direction of the magnetic field of the free layer to the same as that of the fixed layer, corresponding to a low resistance state, and write data 0; if A=1, the amplitude of the data writing pulse is controlled to be positive, the voltage of the first data port is greater than the voltage of the second data port, and a current is generated from the free layer to the fixed layer. The current will change the direction of the magnetic field of the free layer to the opposite direction of the fixed layer, corresponding to a high resistance state, and write data 1; when implementing the majority gate logic, the enable control module controls the enable signal to be high level to enable the in-memory calculation function of the storage unit; according to the logic signal, the Double pulse signal, when realizing "majority gate" logic, the action time of state switching pulse is T1+T2, the amplitude of data writing pulse is controlled by logic signal B and logic signal C, when B=0, C=0, the amplitude of corresponding data writing pulse is negative, the current direction is from bottom to top, it will generate current from fixed layer to free layer, the current will change the direction of magnetic field of free layer to the same as that of fixed layer, corresponding to low resistance state, writing data 0, at this time, no matter reset data is 1 or 0, the resistance state of memory after logic operation is 0, that is, R2=0; when B= When B=1 and C=0 or B=0 and C=1, the amplitude of the data write pulse is 0, and the memory state does not change. At this time, the memory resistance state after the logical operation is the reset memory resistance state, R2=A. When B=1 and C=1, the amplitude of the data write pulse is positive, and the voltage of the first data port is greater than the voltage of the second data port, generating a current from the free layer to the fixed layer. This current changes the direction of the magnetic field in the free layer to the opposite direction of the fixed layer, corresponding to the high resistance state, writing data 1, and the resistance state of the memory after the logical operation is 1, that is, R2=1. According to the truth table, this operation implements majority gate logic.

[0057] R1 A B C R2 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1

[0058] Table 3: Truth table for implementing majority gate logic

[0059] After the majority gate logic operation is completed, the result is stored in memory. The global control module controls the dual-pulse generation module, the enable control module, and the data read module. The enable control module sets the enable signal to a high level, enabling the data read function of the memory cell. The dual-pulse generation module controls the amplitude of the state switching pulse to a low level, reducing the state switching speed of the memory cell and the probability of read disturb during the data read phase. Simultaneously, the memory cell is connected to the sense amplifier to read the memory data. The positive output of the sense amplifier is the result of the majority gate logic operation.

[0060] According to some embodiments of the present invention, the memory cell is composed of a memory device and a transistor. The memory device can be a memory that stores data in the form of resistance or conductance, and data can be read based on the difference between the resistance or conductance values. The memory device is non-volatile. Even when the external power supply is turned off, the memory can still retain the stored data. Figure 2 The memory device is composed of an upper plate, an insulating layer, a free layer, a barrier layer, a fixed layer, an insulating layer and a lower plate stacked in sequence, the first data port is electrically connected to the drain of the transistor, the second data port is electrically connected to the free layer, the selection port is electrically connected to the gate of the transistor, and the control port is electrically connected to the upper plate.

[0061] According to some embodiments of the present invention, when the enable signal of the control port is at a high level, the enable signal is applied to the selection port of the memory cell to select the specified memory cell in the memory array. Only the memory cell selected by the enable signal can implement the write function or the read function. Applying a double pulse signal to the first data port and the second data port of the memory cell will generate a write current, which will change the direction of the free layer magnetic field of the memory device. When the directions of the free layer and the fixed layer magnetic fields are consistent, the resistance of the memory device is low, corresponding to a low resistance state. When the directions of the free layer and the fixed layer magnetic fields are opposite, the resistance of the memory device is high, corresponding to a high resistance state. The data write pulse acts on the first data port and the second data port on the port of the storage unit, which will generate write currents of different sizes and directions. The write current switches the memory state. When the amplitude of the data write pulse is positive, the voltage of the first data port is greater than the voltage of the second data port, generating a current from the free layer to the fixed layer. When the current is large enough and the action time is long enough, the current will change the direction of the free layer magnetic field to the opposite of the fixed layer, corresponding to a high resistance state, and write data 1; when the amplitude of the data write pulse is negative, the voltage of the first data port is greater than the voltage of the second data port, generating a current from the fixed layer to the free layer. When the current is large enough and the action time is long enough, the current will change the direction of the free layer magnetic field to the same as that of the fixed layer, corresponding to a low resistance state, and write data 0.

[0062] When the signal applied to the control port is high, i.e., a pulse signal is applied, an electric field is generated between the upper and lower plates of the memory device. Under the action of this electric field, the state switching speed of the memory cell becomes faster, requiring only a smaller current and a shorter activation time to complete the data writing. When the signal applied to the control port is low, a larger current and a longer write time are required to complete the write operation.

[0063] During a write operation, the enable signal at the control port is high. This signal is applied to the memory cell's select port, selecting the memory cell in the memory array and enabling data writes. Applying a pulse signal to the control port accelerates the state switching of the memory cell. Pulse signals are applied to the first and second data ports, generating a write current in the memory cell that changes its storage state, enabling data writes.

[0064] During a read operation, the enable signal on the control port is high, enabling the memory cell to read data. The signal on the control port remains low, slowing the memory cell's state switching. The first and second data ports receive read signals, generating different currents or voltages when the memory's resistance states differ, allowing for data to be read.

[0065] According to some embodiments of the present invention, in the logic operation stage, the global control module controls the dual pulse generation module and the enable control module, the enable control module controls the enable signal to be high, selects the storage unit, and enables the logic operation function of the storage unit. At the same time, according to the required logic operation and the logic signal, the dual pulse signal is output, the action timing of the dual pulse signal is determined, and the dual pulse signal is used as input to act on the port of the storage unit. The dual pulse signal acts on the port of the storage unit. According to the action of different dual pulse signals, the state of the memory may switch. The dual pulse signal will affect the storage state of the memory and store the logic operation result in the memory.

[0066] According to some embodiments of the present invention, the dual pulse generation module can modulate the amplitude and pulse width of the dual pulse signal based on the input signal and the required logic, the amplitude being the voltage amplitude and current amplitude of the pulse signal, and can select the order of applying the two pulse signals for the port to which the pulse signal is applied. The solution of this embodiment can ensure that the selected storage unit is kept in the selected state throughout the entire process of implementing the data operation operation. It can also be possible to further combine the enable signal with the data signal and the control signal by applying an additional control signal to the enable port. By introducing an additional pulse signal applied to the control port, the degree of freedom of the in-memory calculation is increased, a controlled variable is added, and a variety of logical operation functions can be completed while retaining the storage unit selection function, realizing more operation functions.

[0067] The second embodiment of the present invention proposes a double-pulse data operation method, referring to Figure 3 ,include:

[0068] Output an enable signal to the select port of the storage unit to select the specified storage unit.

[0069] A data input pulse signal and a state switching pulse signal are modulated, and the data input pulse signal and the state switching pulse signal are applied to a data port and a control port of the storage unit respectively.

[0070] The data of the storage unit is read to obtain the result of the double-pulse data operation.

[0071] According to some embodiments of the present invention, the modulating data input pulse signal and the state switching pulse signal includes:

[0072] Modulating the amplitude and pulse width of the data input pulse signal and the state switching pulse signal based on a preset operation logic;

[0073] The application sequence of the data input pulse signal and the state switching pulse signal is adjusted for different ports.

[0074] According to some embodiments of the present invention, the data input pulse signal and the state switching pulse signal are non-reciprocal.

[0075] According to some embodiments of the present invention, before outputting the enable signal to the strobe port of the storage unit, the method further includes: determining a reset signal based on the desired logical operation. The port signal of the storage unit is controlled based on the reset signal, and the data write function is implemented by controlling the port signal of the storage unit to write reset data. It is understood that the reset signal type can be single-bit data or multi-bit data.

[0076] It should be noted that, in the description of this specification, well-known methods, structures and technologies are not shown in detail so as not to obscure the understanding of this specification.

Claims

1. A dual-pulse data computing device, characterized in that: include: A storage module, comprising at least one storage array consisting of a plurality of storage units, wherein the storage units at least include a strobe port, a data port, and a control port; a dual-pulse generating module electrically connected to the storage module, the dual-pulse generating module being used to generate a data input pulse signal and a state switching pulse signal, and applying the data input pulse signal and the state switching pulse signal to the data port and the control port of the storage unit, respectively; the state switching pulse signal being used to control the data writing function and state switching speed of the storage unit; An enable control module, electrically connected to the storage module, configured to output an enable signal to the strobe port to select a designated storage unit; a data reading module, electrically connected to the storage module, and configured to read data from the storage unit; a global control module electrically connected to the dual-pulse generation module, the enable control module, and the data reading module, wherein the global control module controls the port signals of the storage unit through the dual-pulse generation module, the enable control module, and the data reading module to achieve complete data operation; The data port includes a first data port and a second data port; when the voltage of the first data port is greater than the voltage of the second data port, a current is generated from the free layer to the fixed layer, and the current changes the direction of the magnetic field of the free layer to be opposite to that of the fixed layer, corresponding to a high resistance state, and writing data 1; when the voltage of the first data port is less than the voltage of the second data port, a current is generated from the fixed layer to the free layer, and the current changes the direction of the magnetic field of the free layer to be the same as that of the fixed layer, corresponding to a low resistance state, and writing data 0; The storage unit is composed of a storage device and a transistor. The storage device is composed of an upper plate, an insulating layer, a free layer, a barrier layer, a fixed layer, an insulating layer and a lower plate stacked in sequence. The first data port is electrically connected to the drain of the transistor, the second data port is electrically connected to the free layer, the selection port is electrically connected to the gate of the transistor, and the control port is electrically connected to the upper plate.

2. The double-pulse data operation device according to claim 1, wherein: The data reading module is a sensitive amplifier.

3. A double-pulse data calculation method, characterized in that: The device according to any one of claims 1 to 2 comprises: Outputting an enable signal to the strobe port of the storage unit to select the specified storage unit; Modulating a data input pulse signal and a state switching pulse signal, and applying the data input pulse signal and the state switching pulse signal to a data port and a control port of the storage unit respectively; The data of the storage unit is read to obtain the result of the double-pulse data operation.

4. The method according to claim 3, wherein The modulated data input pulse signal and the state switching pulse signal include: The amplitude, pulse width, application sequence and delay between pulse signals of the data input pulse signal and the state switching pulse signal are modulated based on a preset operation logic.

5. The method according to claim 4, wherein Effects of the data input pulse signal and the state switching pulse signal are non-reciprocal.

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