Display substrate, display panel and display device

Abstract

A display substrate, a display panel and a display device are provided. The display substrate comprises: a pixel circuit unit (DP) disposed on a substrate (100), the pixel circuit unit (DP) comprising a plurality of pixel circuit groups (DX), each pixel circuit group (DX) comprising a pixel circuit (DE) and a spacing area (W); a light emitting device (L) disposed on the substrate (100), the pixel circuit (DE) being electrically connected with the light emitting device (L); and a constant signal line (HL) disposed on the substrate (100); wherein the pixel circuit (DE) and the spacing area (W) are arranged alternately; the spacing area (W) comprises a first spacing area (W1) and a second spacing area (W2), the first spacing area (W1) and the second spacing area (W2) are arranged alternately; the data line (DL) is located in the first spacing area (W1), two adjacent pixel circuits (DE) in the second direction (X) share the same data line (DL), the constant signal line (HL) is located in the second spacing area (W2), different constant signal lines (HL) are located in different second spacing areas (W2), and the pixel circuits (DE) in the pixel circuit unit (DP) share the constant signal line (HL).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate, a display panel, and a display device. Background Technology

[0002] Ultra-high resolution display technology can improve the display effect of a screen and can be applied to a variety of special displays, such as 3D display.

[0003] In 3D displays, existing display units are divided into multiple viewpoints, each displaying object information from a different angle. Combined with microlenses, this achieves 3D display. The more viewpoints, the better the 3D display effect. However, a higher number of viewpoints equates to higher resolution, which limits the linewidth of signal lines, leading to increased signal line resistance and consequently, increased display power consumption. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a display substrate, a display panel, and a display device.

[0005] According to a first aspect of this disclosure, a display substrate is provided, comprising:

[0006] Substrate;

[0007] Pixel circuit units disposed on the substrate, the pixel circuit units comprising a plurality of pixel circuit groups arranged along the first direction, at least one of the pixel circuit groups comprising a plurality of pixel circuits and a plurality of spacing regions;

[0008] A plurality of light-emitting devices are disposed on the substrate and electrically connected to the plurality of pixel circuits, wherein at least one pixel circuit is electrically connected to at least one light-emitting device, different pixel circuits are electrically connected to different light-emitting devices, the light-emitting devices electrically connected to pixel circuits in the same pixel circuit group are of the same color, and the light-emitting devices electrically connected to pixel circuits in different pixel circuit groups are of different colors; and...

[0009] Multiple data lines and multiple constant signal lines are disposed on the substrate and electrically connected to the multiple pixel circuits, and the multiple data lines and the multiple constant signal lines all extend along a first direction;

[0010] In this configuration, the plurality of pixel circuits and the plurality of spacing regions in the same pixel circuit group are arranged alternately in a second direction, which intersects with the first direction.

[0011] The plurality of intervals includes a plurality of first intervals and a plurality of second intervals, the plurality of first intervals and the plurality of second intervals being alternately arranged along the second direction; and,

[0012] The multiple data lines are located in the multiple first interval regions, and different data lines are located in different first interval regions. Two adjacent pixel circuits in the second direction share the same data line. The multiple constant signal lines are located in the multiple second interval regions, and different constant signal lines are located in different second interval regions. Multiple pixel circuits in the pixel circuit unit share the multiple constant signal lines.

[0013] According to embodiments of this disclosure, the plurality of constant signal lines include at least one first power line and a plurality of reference signal lines, wherein the spacing between the at least one reference signal line and the first power line adjacent to it is approximately the same as the spacing between two adjacent data lines.

[0014] According to an embodiment of this disclosure, the spacing between two adjacent first power lines is approximately the same as the spacing between two adjacent data lines.

[0015] According to an embodiment of this disclosure, the spacing between two adjacent constant signal lines is greater than the spacing between two adjacent data lines.

[0016] According to embodiments of this disclosure, the plurality of constant signal lines include at least one first power supply line and a plurality of reference signal lines, wherein at least one of the reference signal lines is located between two adjacent first power supply lines.

[0017] According to embodiments of this disclosure, the plurality of constant signal lines include at least one first power supply line and a plurality of reference signal lines, wherein the plurality of reference signal lines are located on the same side of the at least one first power supply line.

[0018] According to embodiments of this disclosure, the plurality of reference signal lines includes at least one first reference signal line and at least one second reference signal line;

[0019] The plurality of light-emitting devices are arranged in an array along the first direction and the second direction, wherein the light-emitting devices arranged along the second direction are of the same color, and the light-emitting devices arranged along the first direction are of different colors.

[0020] The plurality of light-emitting devices arranged along the second direction include a plurality of light-emitting device groups arranged along the second direction, at least one light-emitting device group includes a plurality of light-emitting devices, the light-emitting devices in different light-emitting device groups are different, at least one light-emitting device group is used to display at least one parallax map group, and different light-emitting device groups are used to display different parallax map groups;

[0021] The spacing between at least one of the first reference signal lines and the adjacent second reference signal line is greater than the size of the light-emitting device group in the second direction.

[0022] According to embodiments of this disclosure, at least one of the plurality of pixel circuits in the pixel circuit group is electrically connected to the light-emitting devices in the plurality of light-emitting device groups.

[0023] According to an embodiment of this disclosure, the first reference signal line is electrically connected to the first electrode of the plurality of light-emitting devices;

[0024] The display substrate includes a plurality of pixel circuit units, wherein the first reference signal lines in two adjacent pixel circuit units are isolated and disconnected, and the second reference signal lines in two adjacent pixel circuit units are connected.

[0025] According to an embodiment of this disclosure, the plurality of second interval regions include a plurality of first sub-regions arranged along the second direction and at least one second sub-region, the plurality of constant signal lines are located in the plurality of first sub-regions, and a filling structure is provided in the at least one second sub-region, the thickness of the filling structure being approximately the same as the thickness of the constant signal lines.

[0026] According to an embodiment of the present disclosure, the display substrate further includes a first pixel defining layer disposed on the substrate and a second pixel defining layer disposed on the side of the first pixel defining layer away from the substrate.

[0027] The first pixel defining layer includes a first pixel opening extending along the first direction and a plurality of first defining portions located on both sides of the first pixel opening in the second direction; the second pixel defining layer includes a second pixel opening extending along the second direction and a plurality of second defining portions located on both sides of the second pixel opening in the first direction; in the thickness direction of the display substrate, the first pixel opening and the second pixel opening at least partially overlap to define a third pixel opening, and the light-emitting portion of at least one of the light-emitting devices is located in the third pixel opening;

[0028] The orthographic projection of at least one of the constant signal lines on the substrate at least partially overlaps with the orthographic projection of at least one of the first defining portions on the substrate.

[0029] According to embodiments of the present disclosure, the orthographic projection of at least one of the constant signal lines on the substrate lies within the orthographic projection of at least one of the first defining portions on the substrate.

[0030] According to embodiments of this disclosure, the display substrate further includes:

[0031] A first conductive layer, a first insulating layer, and a second conductive layer are sequentially disposed along a direction away from the substrate, wherein the second conductive layer is located on the side of the first pixel defining layer closer to the substrate.

[0032] Wherein, at least one of the pixel circuits includes an input transistor, and the plurality of data lines are located in the second conductive layer;

[0033] At least one of the data lines is electrically connected to the input transistors of two adjacent pixel circuits in the second direction through a first via penetrating the first insulating layer;

[0034] The orthographic projection of the first via on the substrate is located within the orthographic projection of at least one of the first defining portions on the substrate.

[0035] According to embodiments of the present disclosure, at least one of the pixel circuits further includes a light-emitting control transistor;

[0036] The plurality of constant signal lines include a first power line, which is located in the second conductive layer;

[0037] The first conductive layer includes a first power lead;

[0038] The first power line is electrically connected to the first power lead through a second via penetrating the first insulating layer, and the light-emitting control transistors of the plurality of pixel circuits arranged along the second direction are electrically connected to the same first power lead.

[0039] The orthographic projection of the second via on the substrate is located within the orthographic projection of at least one of the first defining portions on the substrate.

[0040] According to embodiments of this disclosure, the plurality of constant signal lines further include a plurality of reference signal lines, the plurality of reference signal lines including a first reference signal line located in the second conductive layer, and at least one of the pixel circuits further includes a first reset transistor;

[0041] The first conductive layer includes a first reference signal line lead;

[0042] The first reference signal line is electrically connected to the first reference signal line lead through a third via penetrating the first insulating layer, and the first reset transistors of the plurality of pixel circuits arranged along the second direction are electrically connected to the same first reference signal line lead.

[0043] The orthographic projection of at least one of the first defining portions and at least one of the second defining portions onto the substrate defines a first pattern, and the orthographic projection of the third via onto the substrate lies within the first pattern.

[0044] According to embodiments of this disclosure, the plurality of reference signal lines further include a second reference signal line located in the second conductive layer, and at least one of the pixel circuits further includes a second reset transistor;

[0045] The first conductive layer includes a second reference signal line lead;

[0046] The second reference signal line is electrically connected to the second reference signal line lead through a fourth via penetrating the first insulating layer, and the second reset transistors of the plurality of pixel circuits arranged along the second direction are electrically connected to the same second reference signal line lead;

[0047] The orthographic projection of the fourth via on the substrate is located within the orthographic projection of at least one of the second limiting portions on the substrate.

[0048] According to an embodiment of this disclosure, a plurality of first vias and a plurality of fourth vias are provided on the first insulating layer, wherein the orthographic projection of at least one fourth via in the second direction overlaps with the orthographic projection of the plurality of first vias in the second direction.

[0049] According to an embodiment of the present disclosure, the display substrate further includes a first electrode layer disposed on the side of the second pixel defining layer opposite to the substrate, and at least one light-emitting device includes a first electrode disposed in the first electrode layer;

[0050] The first electrode of at least one of the light-emitting devices includes a first edge and a second edge disposed opposite to each other in the second direction, wherein the orthographic projection of one of the first edge and the second edge on the substrate at least partially overlaps with the orthographic projection of at least one of the data lines on the substrate, and the orthographic projection of the other edge on the substrate at least partially overlaps with the orthographic projection of at least one of the constant signal lines on the substrate.

[0051] According to a second aspect of this disclosure, a display panel is provided, comprising the display substrate described above.

[0052] According to a third aspect of this disclosure, a display device is provided, comprising the display panel described above. Attached Figure Description

[0053] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0054] Figure 1 A schematic plan view of a display substrate according to an embodiment of the present disclosure is shown;

[0055] Figure 2AOne of the plan views of a pixel circuit unit according to an embodiment of the present disclosure is illustrated schematically;

[0056] Figure 2B A schematic plan view of a light-emitting device according to an embodiment of the present disclosure is shown;

[0057] Figure 3 A second plan view of a pixel circuit unit according to an embodiment of the present disclosure is shown schematically;

[0058] Figure 4 A third plan view of a pixel circuit unit according to an embodiment of the present disclosure is shown schematically;

[0059] Figure 5 An equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure is shown schematically;

[0060] Figure 6 This schematically illustrates a stacking diagram of the various film layers of a display substrate according to an embodiment of the present disclosure;

[0061] Figures 7 to 21 A schematic plan view of each film layer of a pixel circuit according to an embodiment of the present disclosure is shown.

[0062] Figure 22 A schematic plan view of the third pixel opening according to an embodiment of the present disclosure is shown;

[0063] Figure 23 A schematic diagram of a display panel according to an embodiment of the present disclosure is shown. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0065] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0066] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0067] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0068] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0069] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0070] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0071] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0072] In one example, a display substrate is provided that can be used in 3D displays. This example display substrate includes a plurality of pixel units arranged in an array along a first direction and a second direction on a substrate. Each pixel unit includes multiple groups of sub-pixels, and each group of sub-pixels includes multiple sub-pixels arranged along the second direction. Sub-pixels in the same group have the same color, while sub-pixels in different groups have different colors. The multiple groups of sub-pixels in the same pixel unit are arranged along the first direction.

[0073] For example, a pixel unit consists of three rows of subpixels, with each row of subpixels forming a group. The first row of subpixels consists of red subpixels, the second row consists of green subpixels, and the third row consists of blue subpixels.

[0074] In a set of sub-pixels, each sub-pixel is a viewpoint, and each viewpoint can load a disparity map. Different viewpoints load different disparity maps, and with the help of microlenses, 3D display can be achieved. The more viewpoints there are, the more disparity maps can be loaded, and the better the 3D display effect. Correspondingly, the more viewpoints there are, the more sub-pixels there are, and the space on the display substrate for laying signal lines will decrease accordingly. This will limit the linewidth of the signal lines, resulting in increased resistance of the signal lines.

[0075] In view of the above, embodiments of this disclosure provide a display substrate applicable to 3D displays, comprising: a substrate; pixel circuit units disposed on the substrate, the pixel circuit units including a plurality of pixel circuit groups arranged along a first direction, at least one pixel circuit group including a plurality of pixel circuits and a plurality of spacing regions; a plurality of light-emitting devices disposed on the substrate and electrically connected to the plurality of pixel circuits, at least one pixel circuit being electrically connected to at least one light-emitting device, different pixel circuits being electrically connected to different light-emitting devices, the light-emitting devices electrically connected to pixel circuits in the same pixel circuit group having the same color, and the light-emitting devices electrically connected to pixel circuits in different pixel circuit groups having different colors; and a plurality of light-emitting devices disposed on the substrate and electrically connected to the plurality of pixel circuits. Multiple data lines and multiple constant signal lines extend along a first direction; wherein, multiple pixel circuits and multiple spacing regions in the same pixel circuit group are alternately arranged in a second direction, the second direction intersecting the first direction; the multiple spacing regions include multiple first spacing regions and multiple second spacing regions, which are alternately arranged along the second direction; and multiple data lines are located in multiple first spacing regions, different data lines are located in different first spacing regions, two adjacent pixel circuits in the second direction share the same data line, multiple constant signal lines are located in multiple second spacing regions, different constant signal lines are located in different second spacing regions, and multiple pixel circuits in a pixel circuit unit share multiple constant signal lines.

[0076] In embodiments of this disclosure, within a pixel circuit unit, the spacing between adjacent pixel circuits is divided into alternately arranged first and second spacing regions. The first spacing region is used for data lines, and adjacent pixel circuits share the same data line within the first spacing region. This frees up more space on the display substrate for the placement of constant signal lines. Specifically, all or part of the second spacing regions in multiple spacing regions can be used for placing constant signal lines, thereby increasing the number of constant signal lines and reducing their resistance. Furthermore, in embodiments of this disclosure, different constant signal lines are located in different second spacing regions, and multiple pixel circuits in the pixel circuit unit share multiple constant signal lines. This allows only one constant signal line to be placed in each second spacing region, making the linewidth of the constant signal line unrestricted by other parallel signal lines, thus enabling more flexible linewidth design. For example, the linewidth of the constant signal line can be increased to further reduce its resistance, and the linewidth of the constant signal line can be made close to that of the data line. This helps to ensure that the step differences in different spacing regions are approximately the same. For display substrates where the light-emitting material is formed by printing, this structure is beneficial for printing uniformity.

[0077] The following is combined with Figures 1 to 22 The display substrate of the present disclosure will be described in detail.

[0078] Embodiments of this disclosure provide a display substrate, Figure 1 A schematic plan view of a display substrate according to an embodiment of the present disclosure is shown.

[0079] Reference Figure 1 The display substrate of the embodiments of this disclosure includes a display area AA and a peripheral area NA located at least on one side of the display area AA. The display area AA can have various shapes. For example, the display area AA can be configured in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle, an ellipse, etc., including curved edges, and a semicircle, a semi-ellipse, etc., including both straight and curved edges. In the embodiments of this disclosure, the display area AA is configured as a region having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof.

[0080] The peripheral area NA may be disposed on at least one side of the display area AA. In embodiments of this disclosure, the peripheral area NA may surround the outer periphery of the display area AA. In embodiments of this disclosure, the peripheral area NA may include a longitudinal portion extending in a first direction Y and a lateral portion extending in a second direction X.

[0081] The display substrate may further include a gate driving circuit 11 and a driving chip 12 located within the peripheral region NA. For example, the gate driving circuit 11 may be located on at least one side of the display region AA. Figure 1 In the illustrated embodiment, the gate driving circuit 11 is located on the left and right sides of the display area AA, respectively. It should be noted that the left and right sides can refer to the left and right sides of the display substrate (screen) as viewed by the human eye during display. For example, the driving chip 12 can be located on at least one side of the display area AA. Figure 1 In the illustrated embodiment, the driver chip 12 is located below the display area AA. It should be noted that "below" can refer to the lower side of the display substrate (screen) as viewed by the human eye during display.

[0082] The gate driving circuit 11 can be implemented by a shift register, and the gate driving circuit 11 can provide scan signals to each gate line (not shown in the figure) on the display substrate. The driving chip 12 can provide data signals to each data signal line dataL on the display substrate.

[0083] It should be noted that, although Figure 1 The diagram shows that the gate driving circuit 11 is located on the left and right sides of the display area AA, and the driving chip 12 is located on the lower side of the display area AA. However, the embodiments of this disclosure are not limited to this, and the gate driving circuit 11 and the driving chip 12 can be located at any suitable position in the peripheral area NA.

[0084] For example, the gate driving circuit 11 can employ GOA (Gate Driver on Array) technology. In GOA technology, the gate driving circuit 11 is directly disposed on the array substrate, replacing an external chip. The driving chip 12 can be folded onto the back side of the display substrate using a structure such as a flip-chip film.

[0085] Each GOA unit acts as a first-level shift register, with each level connected to a gate line. By sequentially outputting scan signals from each shift register, line-by-line scanning of the pixel units is achieved. In some embodiments, each shift register can also be connected to multiple gate lines. This adapts to the trend towards higher resolution and narrower bezels in display substrates.

[0086] Figure 2A One of the plan views of a pixel circuit unit according to an embodiment of the present disclosure is shown schematically.

[0087] The display substrate of the embodiments of this disclosure can be applied to 3D displays, in conjunction with reference to... Figure 1 and Figure 2AThe display substrate further includes a substrate 100 and pixel circuit units DP disposed on the substrate 100. Each pixel circuit unit DP includes a plurality of pixel circuit groups DX arranged along a first direction Y. At least one pixel circuit group DX includes a plurality of pixel circuits DE and a plurality of spacing regions W. It should be noted that, in the embodiments of this disclosure, the display substrate may include a plurality of pixel circuit units DP, which may be arranged in an array along the first direction Y and the second direction X. The structures of the plurality of pixel circuit units DP are generally the same. Therefore, in the embodiments of this disclosure, unless otherwise specified, a single pixel circuit unit DP is used as an example for description. For example, the first direction Y may be... Figure 1 The vertical direction in the middle, the second direction X can be Figure 1 The horizontal direction in the equation means that the first direction Y and the second direction X are perpendicular to each other.

[0088] Figure 2B A schematic plan view of a light-emitting device according to an embodiment of the present disclosure is shown.

[0089] Combined with reference Figures 1 to 2B In the embodiments of this disclosure, the display substrate further includes a plurality of light-emitting devices L disposed on the substrate 100 and electrically connected to a plurality of pixel circuits DE. At least one pixel circuit DE is electrically connected to at least one light-emitting device L. Different pixel circuits DE are electrically connected to different light-emitting devices L. The light-emitting devices L electrically connected to the pixel circuits DE in the same pixel circuit group DX have the same color. The light-emitting devices L electrically connected to the pixel circuits DE in different pixel circuit groups DX have different colors.

[0090] For example, a pixel circuit unit DP includes three rows of pixel circuits DE, each row of pixel circuits DE is a pixel circuit group DX, the first row of pixel circuits DE can be electrically connected to a light-emitting device Lr for emitting red light, the second row of pixel circuits DE can be electrically connected to a light-emitting device Lg for emitting green light, and the third row of pixel circuits DE can be electrically connected to a light-emitting device Lb for emitting blue light.

[0091] In the embodiments of this disclosure, the display substrate includes a plurality of pixel units P, at least one pixel unit P includes a plurality of sub-pixels PX, the plurality of sub-pixels PX includes a plurality of sub-pixel groups arranged along a first direction Y, the plurality of sub-pixels PX in the same sub-pixel group are arranged along a second direction X, and the plurality of sub-pixels PX in the same sub-pixel group have the same color, while the sub-pixels PX in different sub-pixel groups have different colors.

[0092] For example, a pixel unit P includes three rows of subpixels PX, each row of subpixels PX is a pixel group, the first row of subpixels PX can be described as red subpixels Pr, the second row of subpixels PX can be described as green subpixels Pg, and the third row of subpixels PX can be described as blue subpixels Pb.

[0093] Each sub-pixel PX may include a pixel circuit DE and a light-emitting device L electrically connected to the pixel circuit DE. For example, a red sub-pixel Pr may include a first light-emitting device L and a first pixel circuit DE electrically connected to the first light-emitting device L, and the first light-emitting device L may emit red light; a green sub-pixel Pg may include a second light-emitting device L and a second pixel circuit DE electrically connected to the second light-emitting device L, and the second light-emitting device L may emit green light; a blue sub-pixel Pb may include a third light-emitting device L and a third pixel circuit DE electrically connected to the third light-emitting device L, and the third light-emitting device L may emit blue light.

[0094] In a sub-pixel group, a sub-pixel PX is a viewpoint. Each viewpoint can load a disparity map. Different viewpoints load different disparity maps. With the help of microlenses, 3D display can be achieved.

[0095] For example, a subpixel group may include 11 subpixel groups PX, that is, 11 viewpoints, each viewpoint loading a disparity map, thereby enabling the loading of 11 disparity maps, which can achieve better 3D display effects.

[0096] In the embodiments of this disclosure, from the perspective of the display driving signal, each pixel unit P constitutes one repeating unit. However, in the design and wiring, a pixel circuit unit DP is considered as a repeating unit, and a pixel circuit unit DP may include the pixel circuits DE of multiple pixel units P. For example, a pixel unit P may include three sub-pixel groups, each sub-pixel group including 11 sub-pixels PX, that is, a pixel unit P includes 11 pixel circuits DE in the second direction X; while a pixel circuit unit DP includes three pixel circuit groups DX, each pixel circuit group DX including 24 pixel circuits DE, that is, a pixel circuit unit DP may include 24 pixel circuits DE in the second direction X.

[0097] The display substrate of this embodiment further includes multiple data lines DL and multiple constant signal lines HL disposed on the substrate 100 and electrically connected to multiple pixel circuits DE, wherein the multiple data lines DL and multiple constant signal lines HL extend along the first direction Y.

[0098] In embodiments of this disclosure, a constant signal line HL can refer to a signal line whose signal remains constant during display. For example, a constant signal line HL may include a first power supply line VDDL for providing a high-level voltage signal and reference signal lines for resetting (e.g., a first reference signal line Vinil and a second reference signal line VrefL).

[0099] In embodiments of this disclosure, multiple pixel circuits DE and multiple spacing regions W in the same pixel circuit group DX are arranged alternately in the second direction X.

[0100] Reference Figure 2A In a pixel circuit group DX, a spacing area W is provided between every two adjacent pixel circuits DE. Multiple spacing areas W are used to lay signal lines extending along the first direction Y on the display substrate, such as the data line DL and constant signal line HL mentioned above.

[0101] Multiple interval regions W include multiple first interval regions W1 and multiple second interval regions W2, which are arranged alternately along a second direction X. Multiple data lines DL are located in multiple first interval regions W1, with different data lines DL located in different first interval regions W1. Two adjacent pixel circuits DE in the second direction X share the same data line DL. Multiple constant signal lines HL are located in multiple second interval regions W2, with different constant signal lines HL located in different second interval regions W2. Multiple pixel circuits DE in a pixel circuit unit DP share multiple constant signal lines HL.

[0102] In the embodiments of this disclosure, in a pixel circuit unit DP, the interval W between adjacent pixel circuits DE is divided into alternately arranged first interval W1 and second interval W2. The first interval W1 is used to set up data lines DL. Two adjacent pixel circuits DE share the same data line DL in the first interval W1. In this way, more space can be freed up on the display substrate for the laying of constant signal lines HL. Specifically, all or part of the second interval W2 in the multiple interval W can be used to lay out constant signal lines HL, thereby increasing the number of constant signal lines HL and reducing the resistance on the constant signal lines HL. At the same time, in the embodiments of this disclosure, different constant signal lines HL are located in different second interval W2, and multiple pixel circuits DE in the pixel circuit unit DP share multiple constant signal lines HL. In this way, only one constant signal line HL can be laid out in each second interval W2, so that the linewidth of the constant signal line HL is not limited by other signal lines parallel to it, thus making the linewidth design of the constant signal line HL more flexible. For example, the linewidth of the constant signal line HL can be increased to further reduce its resistance. At the same time, the linewidth of the constant signal line HL can be made close to that of the data line DL. This is beneficial to making the step differences in different intervals W approximately the same. For display substrates where light-emitting materials are formed by printing, this structure is beneficial to the uniformity of printing.

[0103] In summary, the embodiments of this disclosure provide a display substrate applicable to 3D displays. This display substrate can set more viewpoints in a single pixel unit P to achieve a better 3D display effect. In addition, compared with traditional display substrates for 3D displays, this display substrate increases the number of constant signal lines HL and also increases the linewidth design space of the constant signal lines HL. This can further reduce the resistance on the constant signal lines HL, alleviate voltage drop and other problems, and also improve the uniformity of the printed light-emitting material, thus enhancing the display effect.

[0104] The following is combined with Figures 1 to 22 The display substrate of the present disclosure embodiment will be further described.

[0105] In some specific embodiments, a plurality of signal lines are provided on the display substrate. The plurality of signal lines include scan lines (such as gate lines and light emission control lines) extending along the second direction X, and also include a plurality of data lines DL and a plurality of constant signal lines HL extending along the first direction Y. For example, the plurality of constant signal lines HL may include a plurality of first power supply lines VDDL for providing high-level voltage signals and a plurality of reference signal lines (such as a first reference signal line Vinil and a second reference signal line VrefL) for resetting.

[0106] Reference Figure 2AThe spacing between at least one reference signal line and its adjacent first power line VDDL is approximately the same as the spacing between two adjacent data lines DL. For example, two adjacent data lines DL are positioned on opposite sides of a pixel circuit DE, and correspondingly, at least one reference signal line and its adjacent first power line VDDL are also positioned on opposite sides of a pixel circuit DE.

[0107] The first power line VDDL adjacent to the reference signal line can refer to a line where there are no other first power lines VDDL between them. The spacing between the reference signal line and the first power line VDDL can refer to the average spacing between them in the second direction X, and the spacing between two adjacent data lines DL can refer to the average size between them in the second direction X.

[0108] In some specific embodiments, the spacing between two adjacent first power lines VDDL is approximately the same as the spacing between two adjacent data lines DL. Here, two adjacent first power lines VDDL can refer to two data lines with no other first power lines VDDL between them. The spacing between two adjacent first power lines VDDL can refer to the average dimension between them in the second direction X.

[0109] For example, in multiple constant signal lines HL, the spacing between each pair is the same, and this spacing is the same as the spacing between two adjacent data lines DL. This allows the multiple constant signal lines HL and data lines DL to be set at equal intervals, enabling the multiple constant signal lines HL to be arranged closely together. This allows for the placement of as many constant signal lines HL as possible on the display substrate, thereby significantly reducing the resistance on the constant signal lines HL. For example, referring to reference... Figure 2A and Figure 2B A pixel circuit unit DP comprises 24 columns and 3 rows of pixel circuits DE. Each row of pixel circuits DE forms a pixel circuit group DX. The first row of pixel circuits DE is connected to a light-emitting device Lr for emitting red light, the second row of pixel circuits DE is connected to a light-emitting device Lg for emitting green light, and the third row of pixel circuits DE is connected to a light-emitting device Lb for emitting blue light. A constant signal line HL is provided in each second interval area of ​​this pixel circuit unit DP. For example, 10 first power lines VDDL, 1 first reference signal line ViniL, and 1 second reference signal line VrefL are provided. Each first power line VDDL provides an electrical signal to 2.4 columns of pixel circuits DE. As the number of first power lines VDDL increases, the resistance on the first power line VDDL decreases, and the corresponding voltage drop (IR Drop) also decreases.

[0110] Alternatively, the line widths of the constant signal line HL and the data line DL can be made approximately the same. This allows the routing layout on the left and right sides of multiple pixel circuits DE to be basically consistent, thereby ensuring a greater degree of consistency in the printing environment.

[0111] Optionally, the two columns of pixel circuits DE (or two adjacent groups of pixel circuits DE) on both sides of the first interval W1 can share one or more data lines DL in the first interval W1. For clarity, unless otherwise specified, the following explanation uses the example of setting one data line DL in the first interval W1. In other words, two adjacent groups of pixel circuits DE share one data line DL in the first interval W1.

[0112] Optionally, two gate lines can be set for a row of pixel circuits DE. One line is used to control the on or off of the input transistors of the odd-numbered column pixel circuits DE, and the other line is used to control the on or off of the input transistors of the even-numbered column pixel circuits DE, thereby realizing that one data line DL is time-division multiplexed by two pixel circuits DE.

[0113] Figure 3 A second plan view of a pixel circuit unit according to an embodiment of the present disclosure is shown schematically.

[0114] Reference Figure 3 In some other embodiments, the spacing between two adjacent constant signal lines HL is greater than the spacing between two adjacent data lines DL. Compared to the above embodiments, the increased spacing between constant signal lines HL allows multiple constant signal lines HL to be arranged in a relatively loose manner, thus reducing the space occupied by the constant signal lines HL and freeing up space for other components, thereby increasing design flexibility.

[0115] In some specific embodiments, the multiple constant signal lines HL include at least one first power line VDDL and multiple reference signal lines (e.g., a first reference signal line Vinil and a second reference signal line VrefL), with at least one reference signal line located between two adjacent first power lines VDDL. Exemplarily, one reference signal line can be provided between every two adjacent first power lines VDDL. This allows for a greater number of first power lines VDDL (compared to the reference signal lines) on the display substrate, thereby minimizing the resistance on the first power lines VDDL and improving the voltage drop across them.

[0116] In some specific embodiments, multiple constant signal lines HL can be arranged at equal intervals, thereby making the multiple constant signal lines HL uniformly arranged on the display substrate.

[0117] For example, refer to Figure 3A pixel circuit unit DP includes 24 columns and 3 rows of pixel circuits DE. Each row of pixel circuits DE is a pixel circuit group DX. The first row of pixel circuits DE is connected to a light-emitting device Lr for emitting red light, the second row of pixel circuits DE is connected to a light-emitting device Lg for emitting green light, and the third row of pixel circuits DE is connected to a light-emitting device Lb for emitting blue light. A constant signal line HL is provided in a portion of the second interval area within this pixel circuit unit DP. For example, two first power lines VDDL, one first reference signal line ViniL, and one second reference signal line VrefL are provided. Each first power line VDDL provides an electrical signal to 12 columns of pixel circuits DE. Compared to the previous embodiment, the constant signal lines HL in this embodiment can be arranged in a more sparse manner, thereby freeing up more space for other devices.

[0118] Figure 4 A third plan view of a pixel circuit unit according to an embodiment of the present disclosure is shown schematically.

[0119] Reference Figure 4 In other specific embodiments, the multiple constant signal lines HL include at least one first power line VDDL and multiple reference signal lines (e.g., a first reference signal line Vinil and a second reference signal line VrefL), with the multiple reference signal lines located on the same side of the at least one first power line VDDL.

[0120] For example, the first reference signal line ViniL can be located between the second reference signal line VrefL and the first power line VDDL. In other words, the second reference signal line VrefL and the first power line VDDL can be positioned at opposite ends of the pixel circuit unit DP. This facilitates the connection between the second reference signal line VrefL and the first power line VDDL of two adjacent pixel circuit units DP in the second direction X. As for the first reference signal line ViniL, the first reference signal line ViniL in two adjacent pixel circuit units DP in the second direction X is provided with an insulating gap. Thus, the first reference signal line ViniL can be positioned in the middle of the pixel circuit unit DP.

[0121] For example, refer to Figure 4A pixel circuit unit DP includes 24 columns and 3 rows of pixel circuits DE. Each row of pixel circuits DE is a pixel circuit group DX. The first row of pixel circuits DE is connected to a light-emitting device Lr for emitting red light, the second row of pixel circuits DE is connected to a light-emitting device Lg for emitting green light, and the third row of pixel circuits DE is connected to a light-emitting device Lb for emitting blue light. A constant signal line HL is provided in a portion of the second interval area within this pixel circuit unit DP. For example, one first power line VDDL, one first reference signal line ViniL, and one second reference signal line VrefL are provided. Each first power line VDDL provides an electrical signal to the 24 columns of pixel circuits DE. Compared to the previous embodiment, this embodiment has the fewest constant signal lines HL, thereby maximizing the space available for other devices.

[0122] Combined with reference Figures 2A to 4 In some specific embodiments, the multiple reference signal lines include at least one first reference signal line ViniL and at least one second reference signal line VrefL. Multiple light-emitting devices L are arranged in an array along a first direction Y and a second direction X. The light-emitting devices L arranged along the second direction X have the same color, while the light-emitting devices L arranged along the first direction Y have different colors.

[0123] Reference Figure 2B For example, multiple light-emitting devices L electrically connected to a pixel circuit unit DP include 24 columns and 3 rows of light-emitting devices L. The 24 columns and 3 rows of light-emitting devices L include a light-emitting device Lr for emitting red light, a light-emitting device Lg for emitting green light, and a light-emitting device Lb for emitting blue light, wherein the light-emitting device Lr for emitting red light is located in the first row, the light-emitting device Lg for emitting green light is located in the second row, and the light-emitting device Lb for emitting blue light is located in the third row.

[0124] The plurality of light-emitting devices L arranged along the second direction include a plurality of light-emitting device groups LX arranged along the second direction. At least one light-emitting device group LX includes a plurality of light-emitting devices L. The light-emitting devices L in different light-emitting device groups LX are different. At least one light-emitting device group LX is used to display at least one parallax map group. Different light-emitting device groups LX are used to display different parallax map groups.

[0125] In the embodiments of this disclosure, each light-emitting device L can display one disparity map. For example, a disparity map group includes 11 disparity maps, and a light-emitting device group LX can include 11 light-emitting devices L. Each light-emitting device L is used as a viewpoint to display one of the disparity maps. In other words, the light-emitting devices L in a light-emitting device group LX are also the light-emitting devices L of all sub-pixels PX in a sub-pixel group as described above. For example, a sub-pixel group includes 11 sub-pixels PX, and the 11 light-emitting devices L of the 11 sub-pixels PX constitute a light-emitting device group LX.

[0126] In embodiments of this disclosure, the spacing between at least one first reference signal line ViniL and its adjacent second reference signal line VrefL is greater than the size of the light-emitting device group LX in the second direction X.

[0127] For example, in conjunction with reference Figures 2A to 4 There are 12 columns of pixel circuits DE between the first reference signal line ViniL and the adjacent second reference signal line VrefL. A light-emitting device group LX covers 11 columns of pixel circuits DE in the second direction X. Thus, the first reference signal line ViniL and the adjacent second reference signal line VrefL are arranged in two light-emitting device groups LX, so that the corresponding pixel circuits DE can provide the corresponding electrical signals for the light emission of the light-emitting device L in at least two light-emitting device groups LX.

[0128] In some specific embodiments, at least one pixel circuit group DX contains multiple pixel circuits DE that are electrically connected to multiple light-emitting device groups LX containing light-emitting devices L. For example, a pixel circuit group DX includes 24 columns of pixel circuits DE, and a light-emitting device group LX includes 11 light-emitting devices L. The 24 columns of pixel circuits DE in a pixel circuit group DX are electrically connected to the 11 light-emitting devices L in the first two light-emitting device groups LX and the first two light-emitting devices L in the third light-emitting device group LX (a total of 24 light-emitting devices L).

[0129] Optionally, multiple pixel circuits DE in a pixel circuit unit DP can share the first reference signal line Vinil and the second reference signal line VrefL by reference signal line leads (e.g., the first reference signal line lead VinilS and the second reference signal line lead VrefS) extending along the second direction X.

[0130] In some specific embodiments, the first reference signal line ViniL is electrically connected to the first pole of a plurality of light-emitting devices L, and the display substrate includes a plurality of pixel circuit units DP. The first reference signal lines ViniL in two adjacent pixel circuit units DP are isolated and disconnected, and the second reference signal lines VrefL in two adjacent pixel circuit units DP are connected.

[0131] Optionally, the first power line VDDL in two adjacent pixel circuit units DP are connected. For example, the first power line VDDL and the first power line VDDL located in multiple pixel circuit units DP can be connected by the second reference signal line lead VrefS extending along the second direction X and the first power line lead VDDS.

[0132] Combined with reference Figure 3 and Figure 4In some specific embodiments, the plurality of second interval regions W2 include a plurality of first sub-regions W21 and a plurality of second sub-regions W22 arranged along the second direction X, a plurality of constant signal lines HL are located in the plurality of first sub-regions W21, and at least one second sub-region W22 is provided with a filling structure, the thickness of the filling structure being approximately the same as the thickness of the constant signal line HL.

[0133] In the embodiments of this disclosure, the width of the second sub-region W22 and the first sub-region W21 can be the same. The difference between the second sub-region W22 and the first sub-region W21 is that no constant signal line HL is provided in the second sub-region W22. The position in the second sub-region W22 corresponding to the constant signal line HL can be filled by a pixel defining layer to maintain the consistency of the film layer height in the first sub-region W21 and the second sub-region W22.

[0134] Reference Figure 3 In a pixel circuit unit DP, multiple second sub-regions W22 are provided between two adjacent first sub-regions W21.

[0135] In the embodiments of this disclosure, the number of first sub-regions W21 and second sub-regions W22 can be set according to actual needs. For example, when the voltage drop on the first power line VDDL is more sensitive, more first power lines VDDL can be set, thereby increasing the number of first sub-regions W21 and decreasing the number of second sub-regions W22. Correspondingly, when the voltage drop on the first power line VDDL is less sensitive, fewer first power lines VDDL can be set, thereby decreasing the number of first sub-regions W21 and increasing the number of second sub-regions W22.

[0136] Figure 5 An equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure is shown schematically.

[0137] Reference Figure 5 The pixel circuit DE may include an input transistor T1, a first reset transistor T2, a second reset transistor T3, a light-emitting control transistor T4, a driving transistor T5, and a storage capacitor Cst. This pixel circuit DE can be referred to as a 5T1C structure.

[0138] It should be noted that the embodiments of this disclosure use a 5T1C structure as an example to describe the pixel circuit DE of the embodiments of this disclosure. It should also be noted that while the embodiments of this disclosure use a 5T1C structure as an example to describe the pixel circuit DE of the embodiments of this disclosure, this does not constitute a limitation on the embodiments of this disclosure. The pixel circuit DE of the embodiments of this disclosure can also adopt other structures, such as 7T1C, etc., which will not be listed here.

[0139] It should also be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the following text, one of the first and second terminals of the transistor can refer to the source terminal, and the other to the drain terminal. Since the source and drain terminals of the thin-film transistor used here are symmetrical, they can be interchanged.

[0140] In the embodiments of this disclosure, the first terminal of the input transistor T1 is electrically connected to the data line DL, the second terminal of the input transistor T1 is electrically connected to the gate of the driving transistor T5, and the gate of the input transistor T1 is electrically connected to the first scan line GL1.

[0141] The first terminal of the driving transistor T5 is electrically connected to the second terminal of the light-emitting control transistor T4. The second terminal of the driving transistor T5 is electrically connected to the first terminal of the light-emitting device L. The gate of the driving transistor T5 is also electrically connected to the first plate of the storage capacitor Cst. The second terminal of the light-emitting device L is electrically connected to the second power line VSSL. The second plate of the storage capacitor Cst is connected between the second terminal of the driving transistor T5 and the light-emitting device L.

[0142] The first terminal of the first reset transistor T2 is electrically connected to the first reference signal line ViniL, the second terminal of the first reset transistor T2 is electrically connected to the second terminal of the driving transistor T5, and the gate of the first reset transistor T2 is electrically connected to the second scan line GL2.

[0143] The first terminal of the second reset transistor T3 is electrically connected to the second reference signal line VrefL, the second terminal of the second reset transistor T3 is electrically connected to the gate of the driving transistor T5, and the gate of the second reset transistor T3 is electrically connected to the third scan line GL3.

[0144] The first terminal of the light-emitting control transistor T4 is electrically connected to the first power supply line VDDL, the second terminal of the light-emitting control transistor T4 is electrically connected to the first terminal of the driving transistor T5, and the gate of the light-emitting control transistor T4 is electrically connected to the light-emitting control line EML.

[0145] Figure 6 This schematically illustrates a stacking diagram of the various film layers of a display substrate according to an embodiment of the present disclosure. Figures 7 to 21 A schematic plan view of each film layer of a pixel circuit according to an embodiment of the present disclosure is shown, wherein, Figure 7 A schematic plan view of a semiconductor layer according to an embodiment of the present disclosure is shown. Figure 8 A schematic plan view of the first gate layer according to an embodiment of the present disclosure is shown. Figure 9 A schematic plan view of the semiconductor layer, the first gate insulating layer, and the first gate layer according to an embodiment of the present disclosure is shown. Figure 10 A schematic plan view of the first conductive layer according to an embodiment of the present disclosure is shown. Figure 11 A schematic plan view of the semiconductor layer, the first gate insulating layer, the first gate layer, the interlayer dielectric layer, the first conductive layer, and the first insulating layer according to the present disclosure is shown. Figure 12 A schematic plan view of the second gate layer according to an embodiment of the present disclosure is shown. Figure 13 The diagram schematically illustrates a plan view of a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first conductive layer, and a first insulating layer according to an embodiment of the present disclosure. Figure 14 A schematic plan view of the second conductive layer according to an embodiment of the present disclosure is shown. Figure 15 The diagram schematically illustrates a plan view of a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer according to an embodiment of the present disclosure. Figure 16 A schematic plan view of a first pixel-defining layer according to an embodiment of the present disclosure is shown. Figure 17 The diagram schematically illustrates a plan view of a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a first pixel defining layer according to an embodiment of the present disclosure. Figure 18 A schematic plan view of the first electrode layer according to an embodiment of the present disclosure is shown. Figure 19 The diagram schematically illustrates a plan view of a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a first pixel defining layer, and a first electrode layer according to an embodiment of the present disclosure. Figure 20 A schematic plan view of a second pixel-defining layer according to an embodiment of the present disclosure is shown. Figure 19 The diagram schematically illustrates a plan view of a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a first pixel defining layer, a first electrode layer, and a second pixel defining layer according to an embodiment of the present disclosure.

[0146] It should be noted that in some of the accompanying drawings, the vias located in the insulating film layer are mainly shown schematically, and the insulating material of the insulating film layer itself is not shown. In this way, the location of the vias located in the insulating film layer can be highlighted.

[0147] The following is combined with Figures 6 to 21 The planar structure of the pixel circuit DE, data lines, and constant signal lines according to embodiments of this disclosure will be described.

[0148] It should be noted that, for ease of explanation, unless otherwise specified, the following description will use a pixel circuit DE and the signal lines electrically connected to the pixel circuit DE and their related structures (such as vias) as examples.

[0149] In some specific embodiments, the display substrate includes a semiconductor layer ACT, a first gate insulating layer GI1, a first gate layer GT1, a second gate insulating layer GI2, a second gate layer GT2, an interlayer dielectric layer ILD, a first conductive layer SD1, a first insulating layer J1, a second conductive layer SD2, a second insulating layer J2, and a first electrode layer N, which are disposed on the substrate 100 and sequentially disposed in a direction away from the substrate 100.

[0150] For example, the conductive film layer in the above-mentioned film layer can be made of metallic materials, such as silver, copper, aluminum, molybdenum, etc., or alloys of the above-mentioned metals, such as aluminum-niobium alloys, molybdenum-niobium alloys, etc., or it can be a multilayer metal, such as Mo / Cu / Mo, etc., or it can be a stacked structure formed by metal and transparent conductive materials, such as ITO / Ag / ITO, etc.

[0151] The semiconductor layer ACT can include materials such as amorphous silicon, polycrystalline silicon, or oxide semiconductors, and includes, for example, a channel, a first electrode connection, and a second electrode connection. The channel may be undoped or have a different doping type than the first and second electrode connections, and therefore possesses semiconductor characteristics. The first and second electrode connections are located on opposite sides of the channel and are doped with impurities, thus possessing conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0152] In embodiments of this disclosure, the input transistor T1 includes a first active portion A1 located in the semiconductor layer ACT, the first reset transistor T2 includes a second active portion A2 located in the semiconductor layer ACT, the second reset transistor T3 includes a third active portion A3 located in the semiconductor layer ACT, the light-emitting control transistor T4 includes a fourth active portion A4 located in the semiconductor layer ACT, and the driving transistor T5 includes a fifth active portion A5 located in the semiconductor layer ACT.

[0153] In embodiments of this disclosure, the input transistor T1 further includes a first gate G1 located in the first gate layer GT1, the first reset transistor T2 further includes a second gate G2 located in the first gate layer GT1, the second reset transistor T3 further includes a third gate G3 located in the first gate layer GT1, the light-emitting control transistor T4 further includes a fourth gate G4 located in the first gate layer GT1, and the driving transistor T5 further includes a fifth gate G5 located in the first gate layer GT1.

[0154] In embodiments of this disclosure, the first active portion A1 includes a first electrode connection portion A11, a second electrode connection portion A12, and a channel portion A13 located between the first electrode connection portion A11 and the second electrode connection portion A12. The channel portion A13 of the first active portion A1 is disposed opposite to the first gate G1. The first electrode connection portion A11, the channel portion A13, and the second electrode connection portion A12 of the first active portion A1 are arranged along a first direction Y.

[0155] In embodiments of this disclosure, the second active portion A2 includes a first electrode connection portion A21, a second electrode connection portion A22, and a channel portion A23 located between the first electrode connection portion A21 and the second electrode connection portion A22. The channel portion A23 of the second active portion A2 is disposed opposite to the second gate G2. The first electrode connection portion A21, the channel portion A23, and the second electrode connection portion A22 of the first active portion A1 are arranged along a first direction Y.

[0156] In embodiments of this disclosure, the third active portion A3 includes a first electrode connection portion A31, a second electrode connection portion A32, and a channel portion A33 located between the first electrode connection portion A31 and the second electrode connection portion A32. The channel portion A33 of the third active portion A3 is disposed opposite to the third gate G3. The first electrode connection portion A31, the channel portion A33, and the second electrode connection portion A32 of the third active portion A3 are arranged along a first direction Y.

[0157] In embodiments of this disclosure, the fourth active portion A4 includes a first electrode connection portion A41, a second electrode connection portion A42, and a channel portion A43 located between the first electrode connection portion A41 and the second electrode connection portion A42. The channel portion A43 of the fourth active portion A4 is disposed opposite to the fourth gate G4. The first electrode connection portion A41, the channel portion A43, and the second electrode connection portion A42 of the fourth active portion A4 are arranged along a first direction Y.

[0158] In embodiments of this disclosure, the fifth active portion A5 includes a first electrode connection portion A51, a second electrode connection portion A52, and a channel portion A53 located between the first electrode connection portion A51 and the second electrode connection portion A52. The channel portion A53 of the fifth active portion A5 is disposed opposite to the fifth gate G5. The first electrode connection portion A51, the channel portion A53, and the second electrode connection portion A52 of the fifth active portion A5 are arranged along a first direction Y.

[0159] In some specific embodiments, the second active portion A2, the fifth active portion A5, and the fourth active portion A4 are arranged sequentially in the first direction Y. The second pole connecting portion A32 of the third active portion A3 and the first pole connecting portion A21 of the second active portion A2 at least partially overlap in the orthographic projection in the second direction X.

[0160] In some specific embodiments, the second pole connection portion A12 of the first active portion A1 and the first pole connection portion A41 of the fourth active portion A4 at least partially overlap in the orthographic projection in the second direction X.

[0161] In the embodiments of this disclosure, the first electrode of the storage capacitor Cst can be disposed in the semiconductor layer ACT, and the second electrode of the input transistor T1 can be formed by doping in the semiconductor layer ACT, and the second electrode of the input transistor T1 and the first electrode of the storage capacitor Cst are formed into an integral structure.

[0162] Optionally, the first plate of the storage capacitor Cst is electrically connected to the fifth gate G5 of the driving transistor T5 through the first transition portion Z1 located in the first conductive layer SD1.

[0163] In some specific embodiments, the second electrode of the storage capacitor Cst is located in the second gate layer GT2. A groove C1 is provided on the second electrode of the storage capacitor Cst, which exposes the first electrode of the storage capacitor Cst. The groove C1 and the orthographic projection of the first transition portion Z1 on the substrate 100 at least partially overlap. Thus, the first transition portion Z1 can be electrically connected to the first electrode of the storage capacitor Cst through the groove C1.

[0164] In some specific embodiments, the display substrate further includes a first pixel defining layer PDL1 and a second pixel defining layer PDL2 sequentially disposed along a direction away from the substrate 100. The first pixel defining layer PDL1 is located on the side of the first electrode layer N away from the substrate 100. The first pixel defining layer PDL1 includes a first pixel opening D11 extending along a first direction Y and a plurality of first defining portions D12 located on both sides of the first pixel opening D11 in a second direction X. The second pixel defining layer PDL2 includes a second pixel opening D21 extending along a second direction X and a plurality of second defining portions D22 located on both sides of the second pixel opening D21 in the first direction Y. In the thickness direction of the display substrate, the first pixel opening D11 and the second pixel opening D21 at least partially overlap to define a third pixel opening D3, and the light-emitting portion of at least one light-emitting device L is located in the third pixel opening D3. The orthographic projection of at least one constant signal line HL on the substrate 100 at least partially overlaps with the orthographic projection of at least one first defining portion D12 on the substrate 100.

[0165] The third pixel opening D3 can be the effective light-emitting area of ​​the light-emitting device L. For example, in an OLED display panel, the light-emitting device L of the pixel circuit DE can include a first electrode, a light-emitting layer, and a second electrode stacked together. The third pixel opening D3 can be the area corresponding to the portion of the light-emitting layer sandwiched between the first electrode and the second electrode.

[0166] For example, the first defining portion D12 in the first pixel defining layer PDL1 extends along the first direction Y, thereby defining the first pixel opening D11 extending along the first direction Y. The second defining portion D22 in the second pixel defining layer PDL2 extends along the second direction X, thereby defining the second pixel opening D21 extending along the second direction X. The first pixel opening D11 and the second pixel opening D21 intersect, that is, in the thickness direction of the display substrate, the two partially overlap, and the area defined by the edge of the overlapping portion is the third pixel opening D3.

[0167] This structure allows luminescent materials of the same color to flow along the second direction X during the printing process, while being blocked by the second limiting portion D22 in the first direction Y. After curing, a light-emitting layer is formed for each light-emitting device L. Between two adjacent light-emitting devices L along the second direction X, a groove or a blocking dam can be formed on the first pixel defining layer PDL to allow the cured luminescent material to be misaligned at that location, thereby separating the light-emitting layers of multiple adjacent light-emitting devices L along the second direction X from each other.

[0168] At least one light-emitting device L includes a first electrode N1 located in a first electrode layer N, which is situated between a first pixel defining layer PDL and a second insulating layer J2. The at least one light-emitting device L also includes a second electrode located in a second electrode layer (not shown). One of the first electrode N1 and the second electrode can be an anode, and the other can be a cathode. For example, the second electrode is a cathode and is electrically connected to the aforementioned second power line VSSL to provide a low-level voltage signal. A first defining portion D12 separates the first electrode layer N from the light-emitting layer, and a first pixel opening D11 exposes the first electrode N1, allowing the light-emitting layer located in the first pixel opening D11 to contact the first electrode N1, thereby emitting light under the drive of the electrical signals provided by the first electrode N1 and the second electrode.

[0169] Optionally, the distance between two adjacent first limiting portions D12 in the second direction X is less than the distance between two adjacent first constant signal lines HL in the second direction X.

[0170] In some specific embodiments, the orthographic projection of at least one constant signal line HL on the substrate 100 lies within the orthographic projection of at least one first defining portion D12 on the substrate 100. This ensures that the constant signal line HL maintains a certain distance from the first pixel opening D11, thereby preventing issues such as step differences caused by the constant signal line HL from affecting the uniformity of the first pixel opening D11.

[0171] In some specific embodiments, the second pixel opening D21 extends along the second direction X and spans multiple pixel circuits DE. At the edge of the second pixel opening D21, two adjacent second limiting portions D22 are connected by a third limiting portion D23 extending along the first direction Y, thereby forming a closed pattern of the second pixel opening D21.

[0172] In some specific embodiments, the first power line VDDL, the data line DL, and the reference signal line are disposed in the same layer and made of the same material. For example, the first power line VDDL, the data line DL, and the reference signal line are all located in the second conductive layer SD2, so that the signal line layout on both sides of each pixel circuit DE is consistent, which is beneficial to the uniformity of the printed light-emitting material.

[0173] In some specific embodiments, the display substrate includes: a first conductive layer SD1, a first insulating layer J1, and a second conductive layer SD2 sequentially disposed along a direction away from the substrate 100, wherein the second conductive layer SD2 is located on the side of the first pixel defining layer PDL near the substrate 100. At least one pixel circuit DE includes an input transistor T1, and multiple data lines DL are located in the second conductive layer SD2. At least one data line DL is electrically connected to the input transistor T1 of two adjacent pixel circuits DE in the second direction X through a first via V1 penetrating the first insulating layer J1. The orthographic projection of the first via V1 onto the substrate 100 lies within the orthographic projection of at least one first defining portion D12 onto the substrate 100.

[0174] It should be noted that, in this document, the term "via" should be understood as a structure used for electrically connecting components located in at least two different conductive film layers. For example, a via in an insulating film layer exposes at least a portion of a component in a conductive film layer below the insulating film layer. When a conductive film layer is formed above the insulating film layer, a conductive structure (e.g., a conductive plug) is formed in the via in the insulating film layer. The via (including the conductive plug) in the insulating film layer can electrically connect the component in the conductive film layer above the insulating film layer to the component in the conductive film layer below the insulating film layer. Furthermore, the form of the term "via" can include various forms, including but not limited to, through holes, grooves, openings, etc.

[0175] In embodiments of this disclosure, a spacer layer is disposed between the first conductive layer SD1 and the semiconductor layer ACT. The spacer layer may include one or more of the first gate G1 insulating layer GI1, the second gate G2 insulating layer GI2, and the interlayer dielectric layer ILD. The first insulating layer J1 and the second insulating layer J2 may be single films or composite films. For example, the first insulating layer J1 may be a composite film composed of multiple films such as the first passivation layer PVX1 and the first planarization layer PLN1, and the second insulating layer J2 may be a composite film composed of multiple films such as the second passivation layer PVX2 and the second planarization layer PLN2. The first terminal of the input transistor T1 may be electrically connected to the first terminal connection portion A1 of the input transistor T1 through a fifth via V5 penetrating the spacer layer. The orthogonal projections of the first via V1 and the fifth via V5 on the substrate 100 are arranged along the second direction X.

[0176] In the two pixel circuits DE arranged along the second direction X, the first electrode of the input transistor T1 is formed as a single structure. The orthographic projection of the fifth via V5 located in the two pixel circuits DE onto the substrate 100 is located on the left and right sides of the orthographic projection of the first via V1 onto the substrate 100.

[0177] In some specific embodiments, a plurality of first scan lines GL1 are provided on the display substrate, and the plurality of first scan lines GL1 include a first gate line GL11 and a second gate line GL12. In two adjacent pixel circuits DE along the second direction X, the first gate G1 of the input transistor T1 of one of them is electrically connected to the first gate line GL11, and the first gate G1 of the input transistor T1 of the other is electrically connected to the second gate line GL12, thereby realizing time-division multiplexing of the same data line DL.

[0178] In the embodiments of this disclosure, the first gate line GL11 and the second gate line GL12 are arranged along the first direction Y. The first gate line GL11 and the second gate line GL12 are both located in the first conductive layer SD1. They are electrically connected to the first gate G1 of the input transistor T1 located in the first gate layer GT1 through the sixth via V6 that penetrates the spacer layer.

[0179] In some specific embodiments, the orthographic projection of the sixth via V6 on the substrate 100 and the orthographic projection of the channel portion A13 of the input transistor T1 on the substrate 100 are aligned along the second direction X.

[0180] In some specific embodiments, the first gates G1 of the input transistors T1 of two adjacent pixel circuits DE in the second direction X are spaced apart by their orthogonal projections in the second direction X.

[0181] In some specific embodiments, at least one pixel circuit DE further includes a light-emitting control transistor T4. Multiple constant signal lines HL include a first power line VDDL, which is located in the second conductive layer SD2. The first conductive layer SD1 includes a first power lead VDDS. The first power line VDDL is electrically connected to the first power lead VDDS through a second via V2 penetrating the first insulating layer J1. The light-emitting control transistors T4 of the multiple pixel circuits DE arranged along the second direction X are electrically connected to the same first power lead VDDS. The orthographic projection of the second via V2 on the substrate 100 lies within the orthographic projection of at least one first limiting portion D12 on the substrate 100.

[0182] In some specific embodiments, the first electrode of the light-emitting control transistor T4 is located in the first conductive layer SD1, and the first electrode of the light-emitting control transistor T4 is formed as an integral structure with the first power supply lead VDDS. The first electrode of the light-emitting control transistor T4 is electrically connected to the first electrode connection portion A41 of the light-emitting control transistor T4 through the seventh via V7 penetrating the spacer layer.

[0183] In some specific embodiments, the orthographic projection of the seventh via V7 on the substrate 100 and the orthographic projection of the second via V2 on the substrate 100 are aligned along the second direction X.

[0184] In some specific embodiments, the light emission control line EML is located in the first conductive layer SD1, and the light emission control line EML is electrically connected to the fourth gate G4 of the light emission control transistor T4 through the eighth via V8 that penetrates the spacer layer.

[0185] In some specific embodiments, the orthographic projection of the eighth via V8 on the substrate 100 and the orthographic projection of the second via V2 on the substrate 100 are aligned along the first direction Y.

[0186] In embodiments of this disclosure, the first conductive layer SD1 includes multiple first power leads VDDS, which are arranged along a first direction Y. Each first power lead VDDL can be electrically connected to the multiple first power leads VDDS, thereby providing electrical signals to the multi-row, multi-column pixel circuit DE.

[0187] Optionally, a second via V2 can be provided at the intersection of each first power line VDDL and the first power lead VDDS, so that the first power line VDDL and the first power lead VDDS are electrically connected through the second via V2.

[0188] In some specific embodiments, the multiple constant signal lines HL also include multiple reference signal lines, including a first reference signal line ViniL located in the second conductive layer SD2. At least one pixel circuit DE also includes a first reset transistor T2. The first conductive layer SD1 includes a lead for the first reference signal line ViniL. The first reference signal line ViniL is electrically connected to the lead through a third via V3 penetrating the first insulating layer J1. The first reset transistors T2 of the multiple pixel circuits DE arranged along the second direction X are electrically connected to the same lead for the first reference signal line ViniL. The orthographic projection of the overlapping portion of at least one first defining portion D12 and at least one second defining portion D22 onto the substrate 100 defines a first pattern, and the orthographic projection of the third via V3 onto the substrate 100 lies within the first pattern.

[0189] Optionally, the first electrode of the driving transistor T5 is located in the first conductive layer SD1, and the first electrode of the driving transistor T5 and the second transition portion Z2 in the first conductive layer SD1 are formed as an integral structure. The second electrode connection portion A2 of the driving transistor T5 is electrically connected to the first electrode of the driving transistor T5 through the ninth via V9 penetrating the spacer layer, and the second transition portion Z2 is electrically connected to the fourth transition portion Z4 in the second conductive layer SD2 through the tenth via V10 penetrating the first insulating layer J1. The fourth transition portion Z4 is electrically connected to the first electrode N1 of the pixel circuit DE through the eleventh via V11 penetrating the second insulating layer J2. The tenth via V10 and the eleventh via V11 are arranged along the first direction Y.

[0190] The orthographic projection of the third via V3 on the substrate 100 and the orthographic projection of the fourth adapter Z4 on the substrate 100 at least partially overlap in the second direction X.

[0191] The first reference signal line, ViniL, is electrically connected to the first terminal connection A21 of the first reset transistor T2 through the twelfth via V12 that penetrates the spacer layer. The third via V3 and the twelfth via V12 are arranged along the second direction X.

[0192] In some specific embodiments, the second scan line GL2 is electrically connected to the second gate G2 of the first reset transistor T2 through the thirteenth via V13 that penetrates the spacer layer. The orthogonal projection of the thirteenth via V13 on the substrate 100 is located between the orthogonal projection of the twelfth via V12 on the substrate 100 and the orthogonal projection of the ninth via V9 on the substrate 100.

[0193] In some specific embodiments, the first transition portion Z1 is electrically connected to the first plate of the storage capacitor and the fifth gate G5 of the driving transistor T5 through the fourteenth via V14 penetrating the spacer layer. The orthographic projection of the fourteenth via V14 on the substrate 100 is located between the orthographic projection of the tenth via V10 on the substrate 100 and the orthographic projection of the eighth via V8 on the substrate 100.

[0194] Optionally, the first conductive layer SD1 includes multiple first reference signal lines (ViniL leads) arranged along a first direction Y. Each first reference signal line (ViniL) can be electrically connected to the multiple first reference signal lines (ViniL leads) to provide electrical signals to the multi-row, multi-column pixel circuit DE.

[0195] Optionally, a third via V3 is provided at the intersection of each first reference signal line Vinil and each first reference signal line Vinil lead, so that the first reference signal line Vinil is electrically connected to the first reference signal line Vinil lead.

[0196] In some specific embodiments, the plurality of reference signal lines further include a second reference signal line VrefL, which is located in the second conductive layer SD2. At least one pixel circuit DE also includes a second reset transistor T3. The first conductive layer SD1 includes a lead for the second reference signal line VrefL. The second reference signal line VrefL is electrically connected to the lead for the second reference signal line VrefL through a fourth via V4 penetrating the first insulating layer J1. The second reset transistors T3 of the plurality of pixel circuits DE arranged along the second direction X are electrically connected to the same lead for the second reference signal line VrefL. The orthographic projection of the fourth via V4 on the substrate 100 lies within the orthographic projection of at least one second limiting portion D22 on the substrate 100.

[0197] Optionally, the second reference signal line VrefL lead is electrically connected to the first terminal connection portion A31 of the second reset transistor T3 through the fifteenth via V15 penetrating the spacer layer, and the orthographic projection of the fourth via V4 on the substrate 100 at least partially overlaps with the orthographic projection of the fifteenth via V15 on the substrate 100.

[0198] In some specific embodiments, the third scan line GL3 is electrically connected to the third gate G3 of the second reset transistor T3 through the sixteenth via V16 that penetrates the spacer layer. The orthogonal projection of the sixteenth via V16 on the substrate 100 is located between the orthogonal projection of the fifteenth via V15 on the substrate 100 and the orthogonal projection of the twelfth via V12 on the substrate 100.

[0199] Optionally, the first conductive layer SD1 includes multiple second reference signal lines VrefL leads, which are arranged along a first direction Y. Each second reference signal line VrefL can be electrically connected to the multiple second reference signal lines VrefL leads, thereby providing electrical signals to the multi-row, multi-column pixel circuit DE.

[0200] Optionally, a fourth via is provided at the intersection of each second reference signal line VrefL with each second reference signal line VrefL lead, so that the second reference signal line VrefL is electrically connected to the second reference signal line VrefL lead.

[0201] In some specific embodiments, a plurality of first vias V1 and a plurality of fourth vias V4 are provided on the first insulating layer J1, and at least one fourth via V4 overlaps with the orthographic projection of the plurality of first vias V1 in the second direction X.

[0202] In some specific embodiments, the display substrate further includes a first electrode layer N disposed on the side of the second pixel defining layer PDL2 facing away from the substrate 100, and at least one light-emitting device L includes a first electrode N1 disposed in the first electrode layer N. The first electrode N1 of at least one light-emitting device L includes a first edge N11 and a second edge N12 disposed opposite to each other in the second direction X. The orthographic projection of one of the first edge N11 and the second edge N12 on the substrate 100 at least partially overlaps with the orthographic projection of at least one data line DL on the substrate 100, and the orthographic projection of the other edge N11 on the substrate 100 at least partially overlaps with the orthographic projection of at least one constant signal line HL on the substrate 100.

[0203] For example, the first edge N11 can be the left edge of the first electrode N1, and the second edge N12 can be the right edge of the first electrode N1. In two adjacent light-emitting devices L along the second direction X, the first edge N11 of the first electrode N1 of the left light-emitting device L overlaps with the data line DL, and the second edge N12 overlaps with the constant signal line HL. The first edge N11 of the first electrode N1 of the right light-emitting device L overlaps with the constant signal line HL, and the second edge N12 overlaps with the data line DL.

[0204] Optionally, the first electrode N1 further includes two edges (e.g., upper and lower edges) disposed opposite each other along the first direction Y, wherein the upper edge at least partially overlaps with the first reference signal line Vinil lead, and the lower edge is located below the first electrode of the input transistor T1 and covers the second scan line of the next row pixel circuit DE.

[0205] Figure 22 A schematic plan view of the third pixel opening according to an embodiment of the present disclosure is shown.

[0206] Combined with reference Figure 2A and Figure 22 In the embodiments of this disclosure, the first spacing regions W1 and W2 in the pixel circuit unit DP are alternately arranged; that is, a data line DL and a constant signal line HL are respectively arranged on both sides of each group of pixel circuits DE. In this example, the routing layout and via layout on both sides of the third pixel opening D3 of multiple sub-pixels are basically the same, ensuring the consistency of the printing environment to the greatest extent. It should be noted that in Figure 22 The image only shows the edge of the second defining part D22 in the second pixel defining layer PDL. The area enclosed by this edge is the second pixel opening D21.

[0207] At least some embodiments of this disclosure also provide a display panel, Figure 23 A schematic diagram of a display panel according to an embodiment of the present disclosure is shown, with reference to... Figure 23 The display panel includes the display substrate as described above, having a display area AA and a peripheral area NA, as well as related structures therein. For example, the display panel can be a liquid crystal display panel or an OLED display panel.

[0208] It should be understood that the display device according to the embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be found in the above description and will not be repeated here.

[0209] At least some embodiments of this disclosure also provide a display device, which may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0210] It should be understood that the display device according to the embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be found in the above description and will not be repeated here.

[0211] While some embodiments of the overall technical concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, include: Substrate; Pixel circuit units disposed on the substrate, the pixel circuit units comprising a plurality of pixel circuit groups arranged along a first direction, at least one of the pixel circuit groups comprising a plurality of pixel circuits and a plurality of spacing regions; Multiple light-emitting devices disposed on the substrate and electrically connected to the multiple pixel circuits, wherein at least one pixel circuit is electrically connected to at least one light-emitting device, different pixel circuits are electrically connected to different light-emitting devices, the light-emitting devices electrically connected to the pixel circuits in the same pixel circuit group are of the same color, and the light-emitting devices electrically connected to the pixel circuits in different pixel circuit groups are of different colors. as well as, Multiple data lines and multiple constant signal lines are disposed on the substrate and electrically connected to the multiple pixel circuits, and the multiple data lines and the multiple constant signal lines all extend along a first direction; In this configuration, the plurality of pixel circuits and the plurality of spacing regions in the same pixel circuit group are arranged alternately in a second direction, which intersects with the first direction. The plurality of intervals includes a plurality of first intervals and a plurality of second intervals, the plurality of first intervals and the plurality of second intervals being arranged alternately along the second direction; as well as, The multiple data lines are located in the multiple first interval regions, and different data lines are located in different first interval regions. Two adjacent pixel circuits in the second direction share the same data line. The multiple constant signal lines are located in the multiple second interval regions, and different constant signal lines are located in different second interval regions. Multiple pixel circuits in the pixel circuit unit share the multiple constant signal lines. The plurality of second interval regions include a plurality of first sub-regions and at least one second sub-region arranged along the second direction. The plurality of constant signal lines are located in the plurality of first sub-regions. The at least one second sub-region is provided with a filling structure, the thickness of which is approximately the same as the thickness of the constant signal lines.

2. The display substrate according to claim 1, wherein, The plurality of constant signal lines include at least one first power line and a plurality of reference signal lines, wherein the spacing between the at least one reference signal line and the first power line adjacent to it is approximately the same as the spacing between two adjacent data lines.

3. The display substrate according to claim 2, wherein, The spacing between two adjacent first power lines is approximately the same as the spacing between two adjacent data lines.

4. The display substrate according to claim 1, wherein, The spacing between two adjacent constant signal lines is greater than the spacing between two adjacent data lines.

5. The display substrate according to claim 4, wherein, The plurality of constant signal lines include at least one first power supply line and a plurality of reference signal lines, wherein at least one of the reference signal lines is located between two adjacent first power supply lines.

6. The display substrate according to claim 4, wherein, The plurality of constant signal lines include at least one first power line and a plurality of reference signal lines, wherein the plurality of reference signal lines are located on the same side of the at least one first power line.

7. The display substrate according to any one of claims 2 to 3, 5 to 6, wherein, The plurality of reference signal lines includes at least one first reference signal line and at least one second reference signal line; The plurality of light-emitting devices are arranged in an array along the first direction and the second direction, wherein the light-emitting devices arranged along the second direction are of the same color, and the light-emitting devices arranged along the first direction are of different colors. The plurality of light-emitting devices arranged along the second direction include a plurality of light-emitting device groups arranged along the second direction, at least one light-emitting device group includes a plurality of light-emitting devices, the light-emitting devices in different light-emitting device groups are different, at least one light-emitting device group is used to display at least one parallax map group, and different light-emitting device groups are used to display different parallax map groups; The spacing between at least one of the first reference signal lines and the adjacent second reference signal line is greater than the size of the light-emitting device group in the second direction.

8. The display substrate according to claim 7, wherein, At least one of the pixel circuits in the pixel circuit group is electrically connected to the light-emitting devices in the multiple light-emitting device groups.

9. The display substrate according to claim 7, wherein, The first reference signal line is electrically connected to the first electrode of the plurality of light-emitting devices; The display substrate includes a plurality of pixel circuit units, wherein the first reference signal lines in two adjacent pixel circuit units are isolated and disconnected, and the second reference signal lines in two adjacent pixel circuit units are connected.

10. The display substrate according to claim 1, wherein, The display substrate further includes a first pixel defining layer disposed on the substrate and a second pixel defining layer disposed on the side of the first pixel defining layer away from the substrate. The first pixel defining layer includes a first pixel opening extending along the first direction and a plurality of first defining portions located on both sides of the first pixel opening in the second direction; the second pixel defining layer includes a second pixel opening extending along the second direction and a plurality of second defining portions located on both sides of the second pixel opening in the first direction. In the thickness direction of the display substrate, the first pixel opening and the second pixel opening at least partially overlap to define a third pixel opening, and the light-emitting portion of at least one of the light-emitting devices is located in the third pixel opening; The orthographic projection of at least one of the constant signal lines on the substrate at least partially overlaps with the orthographic projection of at least one of the first defining portions on the substrate.

11. The display substrate according to claim 10, wherein, At least one of the constant signal lines has its orthogonal projection on the substrate located within the orthogonal projection of at least one of the first defining portions on the substrate.

12. The display substrate according to claim 10, wherein, The display substrate further includes: A first conductive layer, a first insulating layer, and a second conductive layer are sequentially disposed along a direction away from the substrate, wherein the second conductive layer is located on the side of the first pixel defining layer closer to the substrate. Wherein, at least one of the pixel circuits includes an input transistor, and the plurality of data lines are located in the second conductive layer; At least one of the data lines is electrically connected to the input transistors of two adjacent pixel circuits in the second direction through a first via penetrating the first insulating layer; The orthographic projection of the first via on the substrate is located within the orthographic projection of at least one of the first defining portions on the substrate.

13. The display substrate according to claim 12, wherein, At least one of the pixel circuits further includes a light-emitting control transistor; The plurality of constant signal lines include a first power line, which is located in the second conductive layer; The first conductive layer includes a first power lead; The first power line is electrically connected to the first power lead through a second via penetrating the first insulating layer, and the light-emitting control transistors of the plurality of pixel circuits arranged along the second direction are electrically connected to the same first power lead. The orthographic projection of the second via on the substrate is located within the orthographic projection of at least one of the first defining portions on the substrate.

14. The display substrate according to claim 12, wherein, The plurality of constant signal lines also include a plurality of reference signal lines, the plurality of reference signal lines including a first reference signal line located in the second conductive layer, and at least one of the pixel circuits also includes a first reset transistor; The first conductive layer includes a first reference signal line lead; The first reference signal line is electrically connected to the first reference signal line lead through a third via penetrating the first insulating layer, and the first reset transistors of the plurality of pixel circuits arranged along the second direction are electrically connected to the same first reference signal line lead. The orthographic projection of at least one of the first defining portions and at least one of the second defining portions onto the substrate defines a first pattern, and the orthographic projection of the third via onto the substrate lies within the first pattern.

15. The display substrate according to claim 14, wherein, The plurality of the reference signal lines also include a second reference signal line located in the second conductive layer, and at least one of the pixel circuits also includes a second reset transistor; The first conductive layer includes a second reference signal line lead; The second reference signal line is electrically connected to the second reference signal line lead through a fourth via penetrating the first insulating layer, and the second reset transistors of the plurality of pixel circuits arranged along the second direction are electrically connected to the same second reference signal line lead; The orthographic projection of the fourth via on the substrate is located within the orthographic projection of at least one of the second limiting portions on the substrate.

16. The display substrate according to claim 15, wherein, The first insulating layer is provided with a plurality of first vias and a plurality of fourth vias, wherein the orthographic projection of at least one fourth via in the second direction overlaps with the orthographic projection of the plurality of first vias in the second direction.

17. The display substrate according to claim 10, wherein, The display substrate further includes a first electrode layer disposed on the side of the second pixel defining layer opposite to the substrate, and at least one light-emitting device includes a first electrode disposed in the first electrode layer; The first electrode of at least one of the light-emitting devices includes a first edge and a second edge disposed opposite to each other in the second direction, wherein the orthographic projection of one of the first edge and the second edge on the substrate at least partially overlaps with the orthographic projection of at least one of the data lines on the substrate, and the orthographic projection of the other edge on the substrate at least partially overlaps with the orthographic projection of at least one of the constant signal lines on the substrate.

18. A display panel, wherein, Includes the display substrate as described in any one of claims 1 to 17.

19. A display device, wherein, Includes the display panel as described in claim 18.

Images