Display pixel including light emitting diode for display screen

Abstract

This specification relates to a display pixel (12 i,j ), which includes a light-emitting diode (LED), a driving circuit (40) for the light-emitting diode, and first, second, third, and fourth conductive pads (36). The light-emitting diode is powered by a first voltage (Vcc) received between the first and second conductive pads. The driving circuit controls the light-emitting diode based on first and second binary signals (Com i , Data j ). The first signal (Com i ) is received between the third and second conductive pads and alternates between a second voltage (Vdd) lower than the first voltage and a third voltage (Gnd) lower than the second voltage. The second signal (Data j ) is received between the fourth and second conductive pads and alternates between the second voltage (Vdd) and the third voltage (Gnd). The display pixel includes a circuit (60) for providing a power supply voltage (Vdd) to the driving circuit based on the first and second signals.

Description

[0001] This patent application claims priority from French patent application FR 21 / 13487, which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates generally to display pixels including light emitting diodes for use in display screens. Background Art

[0003] A pixel of an image corresponds to a unit element of an image displayed by a display screen. For the display of a color image, the display screen usually comprises at least three components, also referred to as display sub-pixels, for the display of each pixel of the image, each component emitting light radiation substantially in a single color (e.g. red, green and blue). The superposition of the radiation emitted by the three display sub-pixels provides the observer with a colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by these three display sub-pixels for the display of a pixel of the image is referred to as a display pixel of the display screen. Each display sub-pixel may comprise a light source, in particular a light emitting diode.

[0004] The display pixels may be distributed in an array, with each display pixel located at the intersection of a row (or line) and a column of the array. Typically, each row of display pixels is selected sequentially, and the display pixels of the selected row are programmed to display the desired image pixels.

[0005] An active array is a screen drive architecture that enables all rows of pixels to be kept active for the entire duration of the image, as opposed to an array known as a passive array, where each row is active only for a time T = Tframe / N (where Tframe is the duration of the image and N is the number of rows of the screen). This enables the brightness of the display to be increased. In addition, low voltage or current levels can be transmitted to the array control lines, which enables larger data streams to be displayed.

[0006] In the context of screens based on light-emitting diodes of dimensions in the micrometer range formed on electronic circuits, the dimensions of the light-emitting diode circuits are generally smaller than the dimensions of the image pixels due to the high intrinsic luminosity of the light-emitting diodes. One of the solutions used is therefore to deposit these unit light-emitting diodes on a support (also called a flat plate) containing the driving electronics. Another solution consists in using display pixels comprising a light-emitting diode and a circuit for controlling the light-emitting diode. These are subsequently referred to as smart pixels. This makes it possible, in particular, to simplify the formation of the active array, since the control electronics of the light-emitting diodes of the display pixels are largely embedded in the display pixels. Document WO 2018 / 185433 describes an example of a smart pixel.

[0007] For smart pixels, the number of conductive pads of the smart pixel for electrically connecting the smart pixel to the support imposes an imposition on the size of the smart pixel, in particular due to the minimum size of these pads and the minimum space provided between these pads. In order to limit the number of conductive pads, it is known to deliver a single supply voltage to the display pixel and each display pixel internally generates one or more reduced supply voltages, in particular for biasing of components of the control electronics.

[0008] The static power consumption of a display pixel corresponds to the electrical power consumed by the display pixel when the display pixel is not emitting light. It may be formed by leakage currents of components of the display pixel control circuit, or by currents necessary for the internal operation of the display pixel control circuit. In the context of smart pixels, a large part of the static power consumption originates from generating the supply voltage inside the smart pixel.

[0009] It is conceivable to provide an additional conductive pad on each smart pixel to provide a reduced supply voltage to the smart pixel so that it is not generated within the smart pixel. However, this will result in an increase in the size of the smart pixel, which is undesirable.

[0010] There is a trend to increase the number of display pixels of a display screen. Then the static power consumption of the display pixels becomes a key factor. In fact, for a so-called 4K display screen having a resolution of 2,160×3,840 display pixels, the static power consumption of the display screen may be greater than 150W.

[0011] The static power consumption of the display needs to be reduced. Summary of the invention

[0012] An object of an embodiment is to provide a display screen including light emitting diodes, which overcomes all or part of the disadvantages of existing display screens including light emitting diodes.

[0013] Another object of an embodiment is to have display pixels with dimensions less than 200 μm, which limits the number of interconnections between the display pixels and the display pixel support.

[0014] An embodiment provides a display pixel for a display screen, comprising at least one light emitting diode (LED), a circuit for driving the light emitting diode, and first, second, third and fourth conductive pads, wherein the light emitting diode is powered by a first voltage received between the first conductive pad and the second conductive pad, and the driver circuit is configured to control the light emitting diode according to first and second binary signals, the first binary signal being received between the third conductive pad and the second conductive pad, the first binary signal alternating between a second voltage lower than the first voltage and a third voltage lower than the second voltage, the second binary signal being received between the fourth conductive pad and the second conductive pad, the second binary signal alternating between the second voltage and the third voltage, the display pixel also comprising a circuit for delivering a power supply voltage, the power supply voltage being equal to within 10% of the second voltage, for powering the driver circuit based on the first and second binary signals.

[0015] This advantageously enables a reduced supply voltage to be generated within the display pixels while reducing quiescent power consumption of the display pixels, because the reduced supply voltage is not generated from the first supply voltage of the light emitting diodes within each display pixel.

[0016] According to one embodiment, the circuit for delivering the power supply voltage comprises a first switch coupling the third conductive pad to a node delivering the power supply voltage, and a second switch coupling the fourth conductive pad to the node. Therefore, the structure of the power supply voltage delivery circuit is simple.

[0017] According to one embodiment, the circuit for delivering the power supply voltage comprises: a first circuit for controlling the first switch, the first circuit being configured to control the first switch to be turned on when the first binary signal is at the second voltage, and to control the first switch to be turned off when the first binary signal is at the third voltage; and a second circuit for controlling the second switch, the second circuit being configured to control the second switch to be turned off when the second binary signal is at the third voltage. Therefore, as long as the first binary signal is at the second voltage, the power supply voltage of the driver circuit is preferentially obtained from the first binary signal.

[0018] According to one embodiment, the second circuit for controlling the second switch is configured to control the second switch to be turned on when the second binary signal is at the second voltage and the first binary signal is at the third voltage, and to control the second switch to be turned off when the first binary signal is at the second voltage. Therefore, the power supply voltage of the driver circuit is obtained from the second binary signal only when the first binary signal is at the third voltage or the second voltage.

[0019] According to one embodiment, the first switch is a first MOS transistor and the second switch is a second MOS transistor.This enables the supply voltage delivery circuit to be easily formed in an integrated manner.

[0020] According to one embodiment, the gate of the first MOS transistor is connected to the third conductive pad and the gate of the second MOS transistor is connected to the fourth conductive pad. Control of the first and second MOS transistors is directly performed by the first and second binary signals, which simplifies the circuit for delivering the supply voltage.

[0021] According to one embodiment, the circuit for delivering the supply voltage comprises a capacitor having a first plate connected to the node and a second plate coupled to the second conductive pad. This enables delivery of a substantially constant supply voltage to be ensured even when both the first and second binary signals are at the third voltage.

[0022] According to one embodiment, the circuit for delivering the supply voltage does not comprise a capacitor having a plate connected to the node. Thus, the supply voltage delivery circuit has a particularly simple structure.

[0023] According to one embodiment, the driver circuit is configured to determine a digital signal from the value of the second binary signal received during each first pulse of the first binary signal at the second voltage, and to control the light emitting diode based on the digital signal. The first binary signal is advantageously used to clock the driver circuit to obtain the value of the second binary signal.

[0024] According to one embodiment, the driver circuit is configured to determine a digital signal from the value of the second binary signal received during each first pulse of the first binary signal at the third voltage, and to control the light emitting diode based on the digital signal. The first pulse of the binary signal at the third voltage enables clocking of the driver circuit for acquiring the value of the second binary signal, which advantageously enables the first binary signal at the second voltage to be delivered between the first pulses.

[0025] According to one embodiment, the driver circuit is configured to determine a digital signal from the value of the second binary signal received immediately after each first pulse of the first binary signal at the third voltage, and to control the light emitting diode based on the digital signal. This enables the second binary signal to be delivered at the second voltage during the first pulse.

[0026] According to one embodiment, the driver circuit is configured to control the light emitting diode by pulse width modulation based on the digital signal. This enables the light emitting diode to be controlled at its optimal operating point.

[0027] According to one embodiment, the display pixel only includes the first, second, third and fourth conductive pads, which advantageously reduces the number of conductive pads of the display pixel.

[0028] According to one embodiment, the driver circuit is configured to switch the light emitting diode on or off at a rate of second pulses of the first binary signal at the second voltage or at the third voltage. The first binary signal is advantageously used for clocking the driver circuit for controlling the light emitting diode.

[0029] An embodiment also provides a display screen comprising an array of display pixels such as previously defined, the display screen also comprising a circuit for, for each display pixel, delivering the first voltage between the first conductive pad and the second conductive pad, delivering the first binary signal between the third conductive pad and the second conductive pad, and delivering the second binary signal on the fourth conductive pad.

[0030] Embodiments also provide a method of controlling a display screen, the display screen comprising an array of display pixels such as previously defined, the method comprising: for each display pixel, delivering the first voltage between the first conductive pad and the second conductive pad, delivering the first binary signal between the third conductive pad and the second conductive pad, and delivering the second binary signal on the fourth conductive pad. Thus, a reduced number of signals / voltages will be delivered to each display pixel for control and power of the display pixel.

[0031] According to one embodiment, the method comprises delivering the first binary signal and the second binary signal such that in operation, the ratio of the average duration of at least one of the first binary signal and the second binary signal being at the second voltage to the sum of the average duration of the first binary signal and the second binary signal being at the third voltage and the average duration of at least one of the first binary signal and the second binary signal being at the second voltage is greater than 75%. This advantageously enables a stable supply voltage to be provided internally to the display pixels.

[0032] According to one embodiment, the method comprises delivering the first binary signal and the second binary signal such that at any time in operation at least one of the first binary signal and the second binary signal is at the second voltage. This advantageously enables a stable supply voltage to be delivered internally to the display pixels for each display pixel without the need for capacitors within the display pixels.

[0033] According to one embodiment, the method comprises delivering, for each display pixel, a first pulse of the first binary signal at the second voltage, and a driver circuit of the display pixel is configured to determine a digital signal from the value of the second binary signal received during each first pulse of the first binary signal at the second voltage, and to control the light emitting diode based on the digital signal. The driver circuit for controlling the light emitting diode is advantageously clocked using the first binary signal.

[0034] According to one embodiment, the method comprises: for each display pixel, delivering a first pulse of the first binary signal at the third voltage, and the driver circuit of the display pixel is configured to determine a digital signal from the value of the second binary signal received during each first pulse of the first binary signal at the third voltage, and to control the light emitting diode based on the digital signal. The first pulse of the binary signal at the third voltage enables clocking of the driver circuit for acquiring the value of the second binary signal, which advantageously enables delivering the first binary signal at the second voltage between each first pulse.

[0035] According to one embodiment, the method comprises delivering, for each display pixel, a first pulse of the first binary signal at the third voltage, and the driver circuit is configured to determine a digital signal from the value of the second binary signal received immediately after each first pulse of the first binary signal at the third voltage, and to control the light emitting diode based on the digital signal. This enables the second binary signal to be delivered at the second voltage during the first pulse. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above features and advantages as well as other features and advantages will be described in detail in the remainder of this disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0037] Figure 1 An example of a display screen is shown partially and schematically;

[0038] Figure 2 is a very simplified cross-sectional diagram showing an example of a pixel;

[0039] Figure 3 yes Figure 2 A bottom view of a display pixel;

[0040] Figure 4 Show Figure 2 An example of a block diagram showing pixels;

[0041] Figure 5 Show Figure 1 A block diagram of a display pixel of a display screen according to an embodiment of the present invention;

[0042] Figure 6 Shown for Figure 5 A block diagram of one embodiment of a circuit for delivering a reduced voltage to a display pixel;

[0043] Figure 7 Shown for Figure 5 A block diagram of another embodiment of a circuit for delivering a reduced voltage to a display pixel;

[0044] Figure 8 An embodiment of a method for operating a display screen is shown. Figure 5 An example of a timing diagram of a signal of a display pixel;

[0045] Fig. 9 Another embodiment of the method for operating a display screen is shown. Figure 5 An example of a timing diagram of a signal of a display pixel;

[0046] Fig.10 Another embodiment of the method for operating a display screen is shown. Figure 5 A timing diagram of a signal of a display pixel;

[0047] Fig.11 Show Figure 4 or Figure 5 An electrical diagram of one embodiment of a current source for a display pixel; and

[0048] Fig.12 Show Figure 4 or Figure 5 Electrical diagram of another embodiment of a current source for a display pixel. DETAILED DESCRIPTION

[0049] Similar features are referred to by similar reference numerals in the various drawings. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be arranged with the same structure, size, and material properties. For clarity, only the steps and elements for understanding the embodiments described herein are shown and described in detail.

[0050] In the following description, when referring to terms such as "front", "back", "top", "bottom", "left", "right" and the like that define absolute positions, or terms such as "above", "below", "upper", "lower" and the like that define relative positions, or terms such as "horizontal", "vertical" and the like that define directions, unless otherwise specified, it refers to the orientation of the drawing or the display screen in the normal usage position.

[0051] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0052] Furthermore, a signal that alternates between a first constant state (e.g., a low state labeled "0") and a second constant state (e.g., a high state labeled "1") is referred to as a "binary signal". The high and low states of different binary signals of the same electronic circuit may be different. In practice, a binary signal may correspond to a voltage that may not be completely constant in either the high or low state.

[0053] Furthermore, in the following description, the source and drain of an insulated gate field effect transistor or MOS transistor are referred to as “power supply terminals” of the MOS transistor.

[0054] Furthermore, unless otherwise stated, when referring to the voltage at a conductive pad, the difference between the potential at the conductive pad and a reference potential (eg, ground taken to be equal to 0 V) ​​is considered.

[0055] Furthermore, the terms "insulating" and "conductive" are considered herein to mean "electrically insulating" and "conductive", respectively.

[0056] Unless otherwise indicated, the expressions "approximately", "about", "substantially" and "approximately" mean within 10%, preferably within 5%.

[0057] Figure 1 A known example of a display screen 10 is shown partially and schematically. The display screen 10 comprises display pixels 12 arranged, for example, in M ​​rows and N columns. i,j , M is an integer varying from 1 to 8000, N is an integer varying from 1 to 16000, i is an integer varying from 1 to M, and j is an integer varying from 1 to M. As an example, in Figure 1 In this example, M and N are equal to 6. Each display pixel has 12 i,j Via electrode 14 i is coupled to a source of low reference potential Gnd (eg ground) and via electrode 16 j is coupled to a source of high reference potential Vcc. As an example, electrode 14 iShown as Figure 1 The rows are aligned, and the electrodes 16 j Shown as Figure 1 The columns in the display are aligned, and the opposite layout is also possible. The power supply voltage of the display corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd, and is marked as Vcc like the high reference potential. The power supply voltage Vcc depends in particular on the arrangement of the light-emitting diodes and the technology for manufacturing the light-emitting diodes. As an example, the power supply voltage Vcc can be about 4V to 5V.

[0058] For each row, the display pixels 12 in the row i,j Coupled to row electrode 18 i For each column, the display pixels in that column are 12 i,j Coupled to column electrode 20 j Display screen 10 includes selection circuit 22 coupled to row electrodes 18 i And suitable for each row electrode 18 i Delivery selection and timing signals Com i Display screen 10 includes data delivery circuit 24 coupled to column electrodes 20 j And it is suitable for each column electrode 20 j Data signal j The selection circuit 22 and the control circuit 24 are controlled by a circuit 26 comprising, for example, a microprocessor.

[0059] Figure 2 Display Pixel 12 i,j A very simplified cross-sectional view of a known example of Figure 3 Display Pixel 12 i,j Bottom view of each display pixel 12 i,j The control circuit 30 includes a display circuit 32 covered thereon. The display circuit 32 includes at least one light emitting diode LED, preferably at least three light emitting diodes LED. The display pixel includes a lower surface 34 and an upper surface 35 opposite to the lower surface 34, and the surfaces 34 and 35 are preferably flat and parallel. The control circuit 30 also includes a conductive pad 36 ( Figure 2). The control circuit 30 may correspond to an integrated circuit comprising electronic components, in particular insulated gate field effect transistors (also called MOS transistors) or thin film transistors (also called TFTs). Preferably, the display circuit 32 comprises only light emitting diodes LED and conductive elements of these light emitting diodes LED, and the control circuit 30 comprises all the electronic components required to control the light emitting diodes LED of the display circuit 32. As a variant, the display circuit 32 may comprise other electronic components in addition to the light emitting diodes LED. The light emitting diodes LED may be 2D light emitting diodes, also called planar light emitting diodes, comprising a stack of planar layers, or may be 3D light emitting diodes, each comprising a three-dimensional semiconductor element covered with an active area. Figure 2 In FIG. 1 , the light emitting diodes LED are shown as being connected to a common anode. However, it may be desirable to arrange the light emitting diodes LED according to another configuration. As an example, the light emitting diodes LED may be connected to a common cathode, or may be connected independently of each other.

[0060] According to one embodiment, the display pixel 12 i,j Three display sub-pixels are included that emit light of first, second and third wavelengths. According to one embodiment, the first wavelength corresponds to blue light and is in the range from 430nm to 490nm. According to one embodiment, the second wavelength corresponds to green light and is in the range from 510nm to 570nm. According to one embodiment, the third wavelength corresponds to red light and is in the range from 600nm to 720nm.

[0061] Each conductive pad 36 is intended to be connected to Figure 2 The electrode 14 schematically shown in i , 16 j , 18 i , 20 j The first conductive pad 36 is coupled to a source of a low reference potential Gnd. The second conductive pad is coupled to a source of a high reference potential Vcc. The third conductive pad 36 is coupled to the row electrode 18. i , and receives the selection and timing signals Com i The fourth conductive pad 36 is coupled to the column electrode 20 j , and receive data signal Data j In particular, by displaying pixel 12 i,j design rules and by displaying the pixel 12 i,j The method of assembly in display screen 10 implements the size of conductive pads 36 and the layout of conductive pads 36 on surface 34 .

[0062] Figure 4 The display pixel 12 of the display screen 10 is shown i,j An example of a block diagram of Figure 4, the supply voltage used to power the electronic components of the block is indicated above each block.

[0063] According to one example, the display pixel 12 i,j comprising at least three light emitting diodes, Figure 4 A single light emitting diode LED is shown in FIG. Each light emitting diode LED is coupled in series with a controllable current source CS, for example, comprising a MOS transistor. In this example, for each light emitting diode LED, the anode of the light emitting diode LED is coupled, for example, to a conductive pad 36 receiving a high reference potential Vcc, and the cathode of the light emitting diode LED is coupled, for example, to one terminal of the controllable current source CS, and the other terminal of the controllable current source CS is coupled to a conductive pad 36 receiving a low reference potential Gnd.

[0064] Display Pixel 12 i,j A circuit 40 for driving the controllable current source CS is also included. The driver circuit 40 may in particular include electronic components such as MOS transistors. It may be desirable to use a low supply voltage of less than 4 V (e.g., about 1 V or 1.8 V) to power the electronic components of the driver circuit 40, which corresponds, for example, to a voltage that may be applied between the power supply terminals of a MOS transistor. To this end, the display pixel 12 i,j A circuit 42 (Vdd generation) is included for delivering a reduced supply voltage Vdd based on the supply voltage Vcc, in particular for the power supply of the driver circuit 40. The circuit 42 comprises, for example, a voltage divider.

[0065] According to one embodiment, in each display pixel 12 i,j The detection and timing signal Com received at one of the conductive pads 36 i It is a binary signal that alternates between a low state "0" and a high state "1", the low state corresponds to a low reference potential Gnd, and the high state "1" corresponds to a low voltage, which is substantially equal to the reduced power supply voltage Vdd. j It is a binary signal that alternates between a low state "0" corresponding to a low reference potential Gnd and a high state "1" corresponding to a low voltage, substantially equal to the reduced supply voltage Vdd.

[0066] The driver circuit 40 includes a circuit 44 (Clk & Data separation) coupled to receive the data signal Data j The conductive pad 36 and based on the data signal Data j The driver circuit 40 includes a circuit 46 (mode select) that receives the signals Clk and Data and is coupled to receive the selection and timing signal Com iThe circuit 50 is configured to deliver the signals Clk and Data to the storage circuit 48 (color data register) or to deliver the PWM signal to the circuit 50 (LED driver) for controlling the controllable current source CS associated with each light emitting diode LED. The storage circuit 48 is configured to store the color signals R, G, B representing the image pixel to be displayed. The circuit 50 is suitable for controlling the controllable current source CS coupled to the light emitting diode LED using the signals I_red, I_green and I_blue obtained from the R, G, B color signals and according to the signal PWM.

[0067] As described below, in order to limit the i,j The number of conductive pads 36, the data signal Data j Each display pixel is allowed to pass 12 i,j The clock signal and the R, G, B color signals representing the desired light intensity of the radiation of the first, second and third wavelengths are determined. According to another embodiment, the selection and timing signal Com i Obtain the clock signal Clk.

[0068] Display Pixel 12 i,j The static power consumption of the display screen 10 is largely due to the electronic components other than the MOS transistors of the driver circuit 40, in particular the circuit 42 for delivering the reduced supply voltage Vdd. i,j The static power consumption of the display pixels may become a critical factor. In fact, for a so-called 4K display screen 10 having a resolution of 2,160×3,840 display pixels, the static power consumption of the display screen 10 may be greater than 150W.

[0069] It can be imagined that except Figure 3 In addition to those shown, each display pixel 12 i,j Additional conductive pads 36 are provided on the display pixel 12 to i,j Supplying an additional high reference potential Vdd causes the display pixel 12 to i,j However, the additional conductive pad 36 is added without increasing the display pixel 12. i,j A lateral dimension of 1000 m is not possible and would be undesirable.

[0070] According to an embodiment of the present invention, from the signal Com i and data signal Data j The reduced voltage Vdd is generated. Thus, the total number of conductive pads 36 is not modified. In addition, no more i,jThe Vcc inside the display is used to generate a reduced power supply voltage Vdd, which reduces the static power consumption of the display. i,j The horizontal dimensions may not be modified.

[0071] Figure 5 The display pixel 12 is shown i,j A block diagram of an embodiment of the invention. Figure 5 Display pixels 12 i,j With Figure 4 The display pixel 12 is shown i,j The same structure, except that the circuit 42 for delivering the reduced supply voltage Vdd is replaced by a circuit 60 for delivering the reduced supply voltage Vdd, which receives the selection and timing signal Com i and data signal Data j .

[0072] Figure 6 Shown for delivery Figure 5 Display pixels 12 i,j FIG. 6 is a block diagram of an embodiment of a circuit 60 for reducing a power supply voltage Vdd. The circuit 60 includes a first switch T1 and a second switch T2. The first switch T1 receives a selection and timing signal Com i The conductive pad 36 is coupled to the node Q delivering the reduced power supply voltage Vdd, and the second switch T2 receives the data signal Data j The conductive pad 36 of the switch 60 is coupled to the node Q. The circuit 60 includes a circuit 64 for delivering a signal GT1 for controlling the switch T1, and a circuit 66 for delivering the signal GT1 for controlling the switch T1. The circuit 60 includes a capacitor C having a plate coupled (preferably connected) to the node Q, and a second plate coupled to the conductive pad 36 receiving the low reference signal Gnd. The node Q corresponds to the output of the circuit 60 for delivering the reduced voltage Vdd.

[0073] When the selection and timing signal Com i When the switch T1 is in state "1" (i.e. at voltage Vdd), the switch T1 is turned on and when the selection and timing signal Com i When the switch T1 is in state "0" (e.g., equal to 0V), the switch T1 is off. When the switch T1 is on, the capacitor C is charged by the voltage Vdd via the switch T1. i When the data signal Data is in state “0”, the switch T1 is turned off, preventing the capacitor C from being discharged by the switch T1. j When the switch T2 is in state "1" (ie, at voltage Vdd), the switch T2 can be turned on, and when the data signal Data jWhen the switch T2 is in state "0" (e.g., equal to 0V), the switch T2 is turned off. When the switch T2 is turned on, the capacitor C is charged by the voltage Vdd via the switch T2. j In state "0", the switch T2 is turned off, preventing the capacitor C from being discharged by the switch T2.

[0074] Each switch T1, T2 may correspond to a MOS transistor, for example an N-channel MOS transistor having its source coupled (preferably connected) to the node Q. Then, the signal GT1 corresponds to a voltage for controlling the gate of the transistor T1, while the signal GT2 corresponds to a voltage for controlling the gate of the transistor T2.

[0075] exist Figure 6 In the embodiment shown, the circuit 64 includes an input terminal receiving a signal Com i The circuit 64 replicates at its output the signal Com received as input i The circuit 66 includes an AND logic gate, a first input terminal of which receives a data signal Data j , the second input terminal receives the selection and timing signal Com i The inverted signal of GT2 is transmitted to its output terminal. i When in state "1" (ie at voltage Vdd), transistor T1 is turned on and transistor T2 is turned off. Then capacitor C is charged by voltage Vdd via switch T1. i is in state "0" (e.g., equal to 0V) and the data signal Data j When in state "1" (ie, at voltage Vdd), transistor T1 is turned off and transistor T2 is turned on. Then capacitor C is charged by voltage Vdd via switch T2. i is in state "0" (e.g., equal to 0V) and the data signal Data j In the state "0" (eg equal to 0V), the transistor T1 is turned off and the transistor T2 is turned off. Then the capacitor C is not discharged via the transistor T1 and the transistor T2.

[0076] Therefore, as long as the selection and timing signal Com i Or data signal Data j In the case where one of the capacitors C is in state "1", the capacitor C is charged to a reduced voltage Vdd. This enables the use of a capacitor C with a reduced capacitance, for example, in the range from 10 fF to 10 pF.

[0077] Figure 7 Shown for delivery Figure 5 Display pixels 12i,j FIG. 6 is a block diagram of another embodiment of a circuit 60 for reducing the supply voltage Vdd. Figure 7 The circuit 60 shown includes Figure 6 All elements of the circuit 60 are shown, except that the circuit 64 corresponds to a conductive trace connecting the gate of transistor T1 to the drain of transistor T1, transistor T1 being thus assembled as a diode, and the circuit 66 corresponds to a conductive trace connecting the gate of transistor T2 to the drain of transistor T2, transistor T2 being thus assembled as a diode. Figure 7 The embodiment is advantageously Figure 6 The embodiment is more responsive.

[0078] According to another embodiment, circuit 64 is absent and switch T1 is coupled (preferably connected) with its anode to receive selection and timing signal Com i The switch T2 corresponds to a diode having a conductive pad 36 and a cathode coupled (preferably connected) to the node Q. According to another embodiment, the circuit 66 does not exist, and the switch T2 corresponds to a diode having an anode coupled (preferably connected) to the receiving data signal Data j The diode has a conductive pad 36 and a cathode coupled (preferably connected) to the node Q.

[0079] Figure 8 An embodiment of a method for displaying an image on a display screen 10 is shown by a Figure 5 The display pixel 12 of the structure shown i,j Timing diagram of the received signal.

[0080] The potentials Vcc and Gnd are substantially constant. The image pixels of the new image to be displayed are displayed successively from the row numbered 1 to the row numbered M. The call frame duration T is the duration separating two consecutive selections of the same row of the display screen 10. The timing diagram of Com1 and Data1 will be described in detail for the row numbered 1, knowing that the signal Com1 is always the same despite the time offset. i Similar to the timing diagram of signal Com1. 1,j (where j changes from 1 to N) The display of the new image pixel includes a first phase P1, followed by a second phase P2. During phase P1, the data signal Data j Transmitted to each display pixel 12 in row number 1 1,j , Figure 8 During the second phase P2, according to the data signal Data j Determine the R, G, B color signals to control each display pixel 12 1,j of light emitting diodes.

[0081] During the first phase P1, the selection and timing signal Com1 is set to state "1". Each display pixel 12 of the row numbered 1 1,j The circuit 46 detects that the signal Com1 is set to the state "1" for a long duration, thereby enabling the display pixel 12 of the row to be selected. 1,j , while the display pixels of other rows are not selected. During the first phase P1, the data signal Data j Transmitted to the column electrode 20 j For each display pixel 12 1,j , circuit 44 is based on the data signal Data j The pulses of the clock signal Clk and the data Data are determined. As an example, the data signal Data j Each pulse of may have a first duration or a second duration longer than the first duration. The signal Clk may correspond to a pulse sequence of the same duration, whose rising edge coincides with the rising edge of the pulse of the data signal Dataj within a possible constant offset range. The data Data may correspond to the rising edge of the pulse of the signal Dataj. j The pulse of the signal Data has a first duration and is in the state "0" and j The circuit 46 selected by the signal Com1 in state "1" delivers data Data at the rate of the clock signal Clk, which data Data is stored in the circuit 50 in the form of R, G, B digital signals (whose individual bits are provided by the successive values ​​of the signal Data). The end of the first period P1 of one row corresponds to the beginning of the first period P1 of the next row.

[0082] According to one embodiment, the display pixel 12 1,j The light emitting diodes are controlled by pulse width modulation or PWM control. To this end, during the second phase P2, the selection and timing signal Com1 represents the switching of each display pixel 12 of the row numbered 1. 1,jThe circuit 46 transmits a repetition of a pulse series in state "1" (PWM signal) to the circuit 50 to time the operation of the circuit 50 for controlling the light emitting diode LED by pulse width modulation. The number of pulses in the series corresponds to the number of bits of each R, G and B digital signal. As an example, when the current source CS corresponds to a MOS transistor, the transistor is turned on or off at the rate of the PWM pulses according to the value "0" or "1" of each bit of the R, G or B color signal, and the transistor remains turned on or off, starting from the most significant bit, until the next pulse of the signal Com1. The duration between two consecutive pulses of the signal Com1 is divided by 2 each time, so that the total duration of the conduction of the light emitting diode depends on the value of the R, G or B color signal. The pulse series of the signal Com1 is repeated until the next first phase P1 of the row numbered 1, at Figure 8 A single repetition is shown as an example in FIG.

[0083] Fig. 9 Another embodiment of the method for displaying an image on the display screen 10 is shown by Figure 5 The display pixel 12 of the structure shown i,j Timing diagram of the received signal.

[0084] Fig. 9 The signals Vcc, Gnd and Data of the embodiment shown are j The timing diagram can be compared with Figure 8 Same as shown. Fig. 9 The signal Com of the embodiment shown i (i changes from 1 to M) corresponds to Figure 8 The signal Com of the embodiment shown i complementarity, that is, Figure 8 The signal Com of the embodiment shown i When in state "0" Fig. 9 The signal Com of the embodiment shown i (i changes from 1 to M) is in state "1", and Figure 8 The signal Com of the embodiment shown i When in state "1" Fig. 9 The signal Com of the embodiment shown i To this end, pixel 12 i,j is configured to detect when the signal Com i Phase P1 when the signal Com is in state "0" for a long time, and during phase P2 the signal Com is in state "0" i The pulses perform pulse width modulation or PWM control.

[0085] About Figure 8 Compared to the described embodiment, the signal Comi In About Fig. 9 In the described embodiment it is most often in the "1" state. This advantageously enables more frequent recharging of the capacitor C of the circuit 60 to deliver the reduced voltage Vdd and thus further reduces the capacitance of the capacitor C.

[0086] Generally, according to one embodiment, the signal Com i and signalData j The average duration of at least one of the reduced voltage Vdd and the signal Com i and signalData j Average duration of low reference potential Gnd and signal Com i and the second signal Data j The ratio of the sum of average durations of at least one of the voltages Vdd is greater than 75%, preferably greater than 85%, and more preferably greater than 95%.

[0087] According to another embodiment, the selection circuit 22, the control circuit 24, and the circuit 26 are configured so that for each display pixel 12 i,j , by displaying pixel 12 i,j Receive selection and timing signal Com i and data signal Data j There is always one in state "1", ie at voltage Vdd. Therefore, in this embodiment, the capacitor C of the circuit 60 for delivering the reduced voltage Vdd may not be present.

[0088] Fig.10 Another embodiment of the method for displaying an image on the display screen 10 is shown by Figure 5 The display pixel 12 of the structure shown i,j Timing diagram of the received signal.

[0089] exist Fig.10 FIG. 1 shows a timing diagram of the signals Com1, Com2, Com3, and Data1 in the rows numbered 1, 2, and 3 and the column numbered 1. It should be noted that although the other signals Com i The timing diagram of the signal Vcc, Gnd (not shown) and Fig.10 The signal Com of the embodiment shown i The timing diagram can be compared with Fig. 9 Same as those shown. Fig. 9 The data signal Data in the embodiment shown j The timing diagram and Figure 8The same as those shown, except that each phase P1 comprises two consecutive phases P1.1 and P1.2. During phase P1.1, when, for the selected row numbered i, Com i When one of the data signals (i changes from 1 to N) is in the state of "0" for a long time, each data signal Data j (j changes from 1 to N) remains in state "1". During phase P1.2 after phase P1, the data signal Data j is transmitted to the column electrode 20 j and the display pixel 12 of the row numbered i i,j Get.

[0090] This embodiment is particularly suitable for the case where there is no capacitor C for delivering the reduced voltage Vdd circuit 60. In fact, at any time, for each display pixel 12 i,j , by displaying pixel 12 i,j Received signal Com i and data signal Data j At least one of is in state "1", so that node Q permanently delivers voltage Vdd even if capacitor C is not present.

[0091] In the above-mentioned embodiment, the display pixel 12 i,j The LED is controlled by pulse width modulation. i,j The control of the light emitting diode LED may differ from control by pulse width modulation. According to one embodiment, the control of the light emitting diode LED is current level control.

[0092] Fig.11 An embodiment of a current source CS is shown, wherein the current source CS includes N basic controllable current sources CS1 to CSN, where N is an integer greater than or equal to 2. Preferably, N is equal to the number of bits of the R, G or B digital color signal. j (j changes from 1 to N) are assembled in parallel between nodes A1 and A2. When the light emitting diodes LED are assembled with a common anode, such as Figure 4 or Figure 5 As shown, for each color, node A1 is coupled (preferably connected) to the cathode of the light emitting diode LED corresponding to the color under consideration, and node A2 is coupled (preferably connected) to the conductive pad 36 coupled to the source of the low reference potential Gnd. When the light emitting diode LED is assembled with a common cathode, node A1 is coupled (preferably connected) to the conductive pad 36 coupled to the source of the high reference potential Vcc, and for each color, node A2 is coupled (preferably connected) to the anode of the light emitting diode LED corresponding to the color under consideration.

[0093] Each basic current source CS j The circuit 50 uses the control signal C j Activate or deactivate. As an example, the control signal C j It is a binary signal corresponding to the j-bit of the R, G or B digital color signal. j When the basic current source CS is in the first state (eg, low state), j Close, and when the signal C j When the current source CS is in the second state (eg, high state), j is activated.

[0094] The activated current source CS j The greater the number of the conducting common light emitting diodes, the higher the intensity of the current ICS. According to one embodiment, the current source CS is capable of providing a current ICS having an intensity of one of a plurality of constant levels and whose level depends on the number of conducting common light emitting diodes. j The currents provided may be the same or different. According to one embodiment, each basic current source CS j The current source CS is then adapted to provide a current having a strength ICS, which may be adjusted according to the control signal C j Take any value k*I, where k varies from 0 to 2M-1.

[0095] According to one embodiment, the control of the light emitting diode LED is an analog control.

[0096] Fig.12 An embodiment of a current source CS is shown, wherein the current source comprises a MOS transistor T assembled in series with a resistor Rs between nodes A1 and A2, the nodes A1 and A2 being as described above with respect to Fig.11 The current source CS also includes a digital-to-analog converter DAC receiving an R, G or B digital color signal, and an operational amplifier having an inverting input terminal (-) coupled (preferably connected) to a midpoint between the resistor Rs and the MOS transistor, and a non-inverting input terminal (+) receiving an analog signal delivered by the digital-to-analog converter DAC. The transistor T is made more or less conductive according to the R, G or B digital color signal transmitted to the digital-to-analog converter DAC.

[0097] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, PWM modulation may be used in display pixels 12 i,j The control circuit 30 is internally generated, avoiding the use of the signal Com iTo generate it. Other embodiments may also use linear drive of the light emitting diodes LED instead of PWM modulation. Other embodiments may also use other electro-optical components, such as organic light emitting diodes.

[0098] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. Figure 5 In the second embodiment described in , it may be advantageous to use a SOI type (Silicon On Insulator) structure to facilitate the management of negative voltages.

Claims

1. A display pixel (12) for a display screen (10) i,j ), comprising at least one light emitting diode (LED), a driver circuit (40) for driving the light emitting diode, and a first conductive pad, a second conductive pad, a third conductive pad and a fourth conductive pad (36), the light emitting diode being powered by a first voltage (Vcc) received between the first conductive pad and the second conductive pad, the driver circuit being configured to generate a first binary signal and a second binary signal (Com i 、Data j ) to control the light emitting diode, the first binary signal (Com i ) is received between the third conductive pad and the second conductive pad, the first binary signal alternates between a second voltage (Vdd) lower than the first voltage and a third voltage (Gnd) lower than the second voltage, and the second binary signal (Data j ) is received between the fourth conductive pad and the second conductive pad, the second binary signal alternates between the second voltage (Vdd) and the third voltage (Gnd), the display pixel also includes a circuit (60) for delivering a power supply voltage (Vdd), the power supply voltage (Vdd) being equal to within 10% of the second voltage, for powering the driver circuit based on the first binary signal and the second binary signal.

2. The display pixel according to claim 1, wherein: The circuit (60) for delivering the power supply voltage (Vdd) includes a first switch (T1) coupling the third conductive pad (36) and a node (Q) delivering the power supply voltage (Vdd), and a second switch (T2) coupling the fourth conductive pad (36) and the node (Q).

3. The display pixel according to claim 2, wherein: The circuit (60) for delivering the power supply voltage (Vdd) comprises: a first circuit (64) for controlling the first switch (T1), the first circuit being configured to i ) is at the second voltage (Vdd), and controls the first switch to be turned on, and when the first binary signal (Com i ) is at the third voltage, controlling the first switch to be disconnected; and a second circuit (66) for controlling the second switch (T2), the second circuit being configured to j ) is at the third voltage, controlling the second switch to be disconnected.

4. The display pixel according to claim 3, wherein: The second circuit (66) for controlling the second switch (T2) is configured to j ) is at the second voltage (Vdd) and the first binary signal (Com i ) is at the third voltage (Gnd), controls the second switch to be turned on, and when the first binary signal (Com i ) is at the second voltage (Vdd) and controls the second switch to be disconnected.

5. The display pixel according to any one of claims 2 to 4, wherein: The first switch (T1) is a first MOS transistor, and wherein the second switch (T2) is a second MOS transistor.

6. A display pixel according to claim 5 when appended to claim 2, wherein: The gate of the first MOS transistor is connected to the third conductive pad (36), and wherein the gate of the second MOS transistor is connected to the fourth conductive pad (36).

7. The display pixel according to any one of claims 2 to 4, wherein: The circuit (60) for delivering the supply voltage (Vdd) includes a capacitor (C) having a first plate connected to the node (Q) and a second plate coupled to the second conductive pad (36).

8. The display pixel according to any one of claims 2 to 4, wherein: The circuit (60) for delivering the supply voltage (Vdd) does not include a capacitor (C) having a plate connected to the node (Q).

9. The display pixel according to claim 8, wherein: The driver circuit (40) is configured to generate a first binary signal (Com i ) received during each first pulse of the second binary signal (Data j ) values ​​to determine a digital signal (R, G, B), and control the light emitting diode (LED) based on the digital signal.

10. The display pixel according to claim 8, wherein: The driver circuit (40) is configured to generate a first binary signal (Com i ) received during each first pulse of the second binary signal (Data j ) values ​​to determine a digital signal (R, G, B), and control the light emitting diode (LED) based on the digital signal.

11. The display pixel according to claim 8, wherein: The driver circuit (40) is configured to generate a first binary signal (Com i ) after each first pulse received by the second binary signal (Data j ) values ​​to determine a digital signal (R, G, B), and control the light emitting diode (LED) based on the digital signal.

12. The display pixel according to any one of claims 9 to 11, wherein: The driver circuit (40) is configured to control the light emitting diode (LED) by pulse width modulation based on the digital signal (R, G, B).

13. The display pixel of claim 12, comprising only the first conductive pad, the second conductive pad, the third conductive pad and the fourth conductive pad (36).

14. The display pixel according to claim 13, wherein: The driver circuit (40) is configured to receive the first binary signal (Com i )'s second pulse rate to turn on or off the light emitting diode (LED).

15. A display screen (10) comprising a display pixel (12) according to any one of claims 1 to 14 i,j ), the display screen further comprising a circuit (22, 24) for: for each display pixel, delivering the first voltage (Vcc) between the first conductive pad and the second conductive pad, and delivering the first binary signal (Com) between the third conductive pad and the second conductive pad. i ), and delivering the second binary signal (Data) on the fourth conductive pad j ).

16. A method for controlling a display screen (10), the display screen comprising a display pixel (12) according to any one of claims 1 to 14 i,j ), the method comprising: For each display pixel (12 i,j ), delivering the first voltage (Vcc) between the first conductive pad and the second conductive pad, and delivering the first binary signal (Com i ), and delivering the second binary signal (Data) on the fourth conductive pad j ).

17. The method according to claim 16, comprising: Delivering the first binary signal (Com i ) and the second binary signal (Data j ), so that in operation, the first binary signal (Com i ) and the second binary signal (Data j ) is at the second voltage (Vdd), and the average duration of the first binary signal (Com i ) and the second binary signal (Data j ) is at the third voltage (Gnd) and the average duration of the first binary signal (Com i ) and the second binary signal (Data j ) is at the second voltage (Vdd) has a ratio greater than 75%.

18. The method according to claim 17, comprising: Delivering the first binary signal (Com i ) and the second binary signal (Data j ), so that at any time during operation, the first binary signal (Com i ) and the second binary signal (Data j ) is at least one of the second voltage (Vdd).

19. A method according to any one of claims 16 to 18, comprising: For each display pixel (12 i,j ), delivering the first binary signal (Com i ), and wherein the driver circuit (40) of the display pixel is configured to generate a first pulse of the first binary signal (Com i ) received during each of the first pulses of the second binary signal (Data j ) values ​​to determine a digital signal (R, G, B), and control the light emitting diode (LED) based on the digital signal.

20. The method according to any one of claims 16 to 18, comprising: For each display pixel (12 i,j ), delivering the first binary signal (Com i ), and wherein the driver circuit (40) of the display pixel is configured to generate a first pulse of the first binary signal (Com i ) received during each of the first pulses of the second binary signal (Data j ) values ​​to determine a digital signal (R, G, B), and control the light emitting diode (LED) based on the digital signal.

21. A method according to any one of claims 16 to 18, comprising: For each display pixel (12 i,j ), delivering the first binary signal (Com i ), and wherein the driver circuit (40) is configured to generate a first pulse of the first binary signal (Com i ) after each of the first pulses received by the second binary signal (Data j ) values ​​to determine a digital signal (R, G, B), and control the light emitting diode (LED) based on the digital signal.

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