Super junction MOSFET with optimized reverse recovery characteristics and manufacturing method thereof

Abstract

The present invention discloses a super junction MOSFET with optimized reverse recovery characteristics and a manufacturing method thereof. The super junction MOSFET includes a gate trench, a body trench, a substrate, a drift region and a source region of a first doping type, and a well region, a contact region and a column region of a second doping type. A gate structure composed of a gate dielectric and a gate conductor is formed in the gate trench, and a body structure composed of a body dielectric and a body conductor is formed in the body trench. By arranging a body structure in the device, in the reverse conduction state, freewheeling is achieved by means of the current paths on both sides of the body structure, thereby avoiding the body diode of the contact area from being turned on, greatly reducing the reverse recovery charge, and thus optimizing the reverse recovery characteristics of the super junction MOSFET. The present invention also discloses a manufacturing method of the device structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a super junction MOSFET with optimized reverse recovery characteristics and a manufacturing method thereof. Background Art

[0002] Superjunction Metal Oxide Semiconductor Field Effect Transistor (SJ MOSFET) is a widely used power semiconductor device. This structure adopts a voltage-resistant layer structure with alternating N-columns and P-columns, which can achieve a higher breakdown voltage while maintaining a smaller on-resistance, thereby greatly reducing the conduction loss of the device and significantly improving the constraint relationship between the breakdown voltage and on-resistance of the traditional power MOSFET. The traditional trench gate superjunction MOSFET device structure is as follows: Figure 4 shown.

[0003] However, in practical applications, the main disadvantage of superjunction MOSFET devices is that the reverse recovery characteristics of the device are poor, which is specifically manifested in a large reverse recovery charge and a harder reverse recovery curve. The former is because the body diode is turned on during reverse conduction, and a large number of minority carriers are stored in the drift region. The latter is because the lateral PN junction area of ​​the superjunction structure is large, and the lateral depletion rate of the N column / P column is fast, which can easily cause current and voltage overshoot, thereby affecting application reliability. The mainstream solution to improve the reverse recovery characteristics of superjunction MOSFET is to add a buffer layer at the bottom of the N column and P column, and use the slower depletion rate of the buffer layer to obtain a softer reverse recovery characteristic curve. However, the introduction of the buffer layer will further increase the reverse recovery charge and on-resistance. Summary of the invention

[0004] Technical purpose: In view of the shortcomings of trench gate super junction MOSFET in the prior art, the present invention discloses a super junction MOSFET with optimized reverse recovery characteristics and a manufacturing method thereof. Compared with the traditional trench gate super junction MOSFET, the super junction MOSFET provided by the present invention can achieve better reverse recovery characteristics.

[0005] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] A super junction MOSFET with optimized reverse recovery characteristics, comprising:

[0007] Drain;

[0008] A substrate, located on the drain;

[0009] A drift region located on the substrate;

[0010] A column region, located on the substrate and adjacent to the drift region, including a first column region and a second column region located on both sides of the drift region;

[0011] A well region, located above the drift region and the pillar region;

[0012] A source region, located in the well region, including a gate structure source region and a body structure source region, wherein the gate structure source region includes a first gate structure source region and a second gate structure source region; and the body structure source region includes a first body structure source region and a second body structure source region;

[0013] A contact region, located in the well region and adjacent to the source region;

[0014] A gate trench, which penetrates the well region and the gate structure source region and extends into the contact region, wherein the first gate structure source region and the second gate structure source region are respectively located on two sides of the gate trench;

[0015] A body trench, which penetrates the well region and the body structure source region and extends into the contact region, wherein the first body structure source region and the second body structure source region are respectively located on two sides of the body trench;

[0016] A gate dielectric, located on the sidewall and bottom of the gate trench;

[0017] A gate conductor, located in the gate trench and surrounded by the gate dielectric on three sides;

[0018] A body dielectric, located on the sidewalls and bottom of the body trench;

[0019] A body conductor, located in the body trench and surrounded on three sides by the body dielectric;

[0020] An isolation dielectric is located above the well region and completely covers the gate conductor;

[0021] The source electrode is located on both sides and on the isolation medium and is in full contact with the body conductor.

[0022] A method for manufacturing a super junction MOSFET with optimized reverse recovery characteristics, used for manufacturing the above-mentioned super junction MOSFET with optimized reverse recovery characteristics, comprises the following steps:

[0023] Step 1, forming a first conductivity type drift region on a substrate;

[0024] Step 2, etching a portion of the first conductive type drift region to form a drift region;

[0025] Step 3, forming pillar regions on both sides of the drift region, the pillar regions including a first pillar region and a second pillar region;

[0026] Step 4, forming a well region on the drift region and the pillar region;

[0027] Step 5, forming a source region and a contact region in the well region, etching to form a gate trench and a body trench penetrating the well region and extending into the drift region; the source region includes a gate structure source region and a body structure source region, the gate structure source region includes a first gate structure source region and a second gate structure source region, the body structure source region includes a first body structure source region and a second body structure source region, the first gate structure source region and the second gate structure source region are located on both sides of the gate trench, and the first body structure source region and the second body structure source region are located on both sides of the body trench; the contact region is adjacent to the source region and is located between the gate trench and the body trench;

[0028] Step 6, forming a gate dielectric on the sidewall and bottom of the gate trench, and forming a gate conductor in the gate trench and wrapped on three sides by the gate dielectric, forming a body dielectric on the sidewall and bottom of the body trench, and forming a body conductor in the body trench and wrapped on three sides by the body dielectric;

[0029] Step 7: forming an isolation dielectric on the gate conductor, forming a source on both sides and on the isolation dielectric, and forming a drain at the bottom of the substrate 2.

[0030] Beneficial effects: The super junction MOSFET with optimized reverse recovery characteristics proposed by the present invention forms a gate trench and a body trench in the cell, the gate trench is used to form a gate structure, the body trench is used to form a body structure, and the body conductor is electrically connected to the source metal. In the reverse conduction state, freewheeling is achieved through the current path on both sides of the body trench, avoiding the opening of the body diode, thereby greatly reducing the reverse recovery charge of the device, weakening the current and voltage overshoot, and obtaining a better reverse recovery characteristic. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of a super junction MOSFET with optimized reverse recovery characteristics according to Example 1;

[0032] Figure 2 A schematic diagram of a super junction MOSFET with optimized reverse recovery characteristics according to Example 2;

[0033] Figure 3 A schematic diagram of a super junction MOSFET with optimized reverse recovery characteristics according to Example 3;

[0034] Figure 4 Schematic diagram of a conventional trench gate superjunction MOSFET;

[0035] Figure 5~Figure 11 A schematic diagram of the preparation process of a super junction MOSFET with optimized reverse recovery characteristics of Example 1;

[0036] Explanation of the accompanying drawings: 1. drain; 2. substrate; 3. drift region; 4-1. first column region; 4-2. second column region; 5. gate trench; 6. body trench; 7. well region; 8-1. first gate structure source region; 8-2. second gate structure source region; 9-1. first body structure source region; 9-2. second body structure source region; 10. contact region; 11-1. gate dielectric; 11-2. body dielectric; 12-1. gate conductor; 12-2. body conductor; 13. isolation dielectric layer; 14. source; 15. shielding region. DETAILED DESCRIPTION

[0037] The present invention is further explained and illustrated below in conjunction with the accompanying drawings and embodiments.

[0038] The embodiments are only used to illustrate the present invention and do not limit the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present invention.

[0039] In addition, in the description of the present invention, it should be noted that the terms "central", "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. Example 1

[0040] As attached Figure 1 As shown, a super junction MOSFET with optimized reverse recovery characteristics comprises:

[0041] Drain 1; substrate 2 located on drain 1; drift region 3 located on substrate 2, the depth of drift region 3 ranges from 5µm to 100µm, and the doping concentration is 1e16cm -3 ~ 9e17cm -3 ;

[0042] The column region is located on the substrate 2 and adjacent to the drift region 3. The column region includes a first column region 4-1 and a second column region 4-2. The depth of the first column region 4-1 and the second column region 4-2 ranges from 5µm to 100µm, and the doping concentration is 1e16cm -3 ~ 5e17cm -3 ; In this embodiment, the drift region 3 is flush with the bottom of the first column region 4-1 and the second column region 4-2, that is, the drift region 3 has the same depth as the first column region 4-1 and the second column region 4-2;

[0043] The well region 7 is located above the drift region 3 and the pillar region. The depth of the well region 7 ranges from 0.5µm to 4.0µm, and the doping concentration is 5e15cm -3 ~ 5e17cm -3 ;

[0044] The source region is located in the well region 7, and the source region includes a gate structure source region and a body structure source region. The gate structure source region includes a first gate structure source region 8-1 and a second gate structure source region 8-2. The body structure source region includes a first body structure source region 9-1 and a second body structure source region 9-2. The depth of the source region ranges from 0.1µm to 0.3µm, and the doping concentration is 1e19cm -3 ~ 5e20cm -3 ;

[0045] The contact region 10 is located in the well region 7. The depth of the contact region 10 ranges from 0.1µm to 0.3µm, and the doping concentration is 5e18cm -3 ~ 5e20cm -3 ;

[0046] A gate trench 5 penetrates the well region 7 and extends into the drift region 3, the first gate structure source region 8-1 and the second gate structure source region 8-2 are located on both sides of the gate trench 5, the depth of the gate trench 5 ranges from 1.0µm to 10.0µm, the depth of the gate trench 5 is greater than the depth of the well region 7, the difference between the two is not less than 0.2µm, and the spacing between the gate trench 5 and the adjacent column region is 0.3µm to 5.0µm;

[0047] A body trench 6 penetrates the well region 7 and extends into the drift region 3, a first body structure source region 9-1 and a second body structure source region 9-2 are located on both sides of the body trench 6, a depth of the body trench 6 ranges from 1.0µm to 10.0µm, a depth of the body trench 6 is greater than a depth of the well region 7, a difference between the depth of the body trench 6 and the well region 7 is not less than 0.2µm, and a spacing between the body trench 6 and an adjacent column region is from 0.3µm to 5.0µm; a contact region 10 is located between the gate trench 5 and the body trench 6;

[0048] A gate dielectric 11-1 located on the sidewall and bottom of the gate trench 5, wherein the thickness of the gate dielectric 11-1 is in the range of 40nm to 300nm; a gate conductor 12-1 located in the gate trench 5;

[0049] A body dielectric 11-2 located on the sidewall and bottom of the body trench 6, wherein the thickness of the body dielectric 11-2 is in the range of 10nm to 80nm; a body conductor 12-2 located in the body trench 6;

[0050] An isolation dielectric 13 is located above the well region 7, the isolation dielectric 13 completely covers the gate conductor 12-1, and the isolation dielectric 13 covers part of the gate structure source region, and does not exceed the boundaries of the first gate structure source region 8-1 and the second gate structure source region 8-2; a source electrode 14 is located on both sides and above the isolation dielectric 13.

[0051] In the present invention, the doping type of the substrate, drift region and source region is a first type, and the doping type of the column region, well region and contact region is a second type. The first type can be N type or P type, and correspondingly, the second conductive type can be P type or N type.

[0052] As attached Figure 5 To Attachment Fig.11 As shown, a method for manufacturing a super junction MOSFET with optimized reverse recovery characteristics of the present invention comprises the following steps:

[0053] Step 1: forming a first conductivity type drift region on the substrate 2; Figure 5 As shown, a drift region 3 is formed on the substrate 2 by epitaxial growth. The depth of the drift region 3 ranges from 5µm to 100µm, and the doping concentration is 1e16cm -3 ~ 9e17cm -3 ; The semiconductor material used in the device, that is, the material of the first conductive type substrate can be Si, SiC and other materials.

[0054] Step 2, etching part of the first conductive type drift region to form a drift region 3; Figure 6 As shown, a portion of the first conductive type drift region is removed by an etching process to form a drift region 3;

[0055] Step 3, forming a first column region 4-1 and a second column region 4-2 on both sides of the drift region 3; Figure 7 As shown, the first column region 4-1 and the second column region 4-2 are formed by an epitaxial backfilling process. The first column region 4-1 and the second column region 4-2 are adjacent to the drift region 3, and the depth range is 5µm ~ 100µm, and the doping concentration is 1e16cm -3 ~ 5e17cm -3 After the epitaxial backfilling process, a CMP (Chemical Mechanical Polishing) process may be added to level the surface of the semiconductor material. In this embodiment, when etching a portion of the first conductive type drift region to form the drift region in step 2, the etching is complete, that is, the column region formed in step 3 has the same depth as the drift region 3, and the column region is flush with the bottom of the drift region 3.

[0056] Step 4, forming a well region 7 on the drift region 3, the first column region 4-1 and the second column region 4-2; Figure 8As shown, a well region 7 is formed on the drift region 3, the first column region 4-1 and the second column region 4-2 by an epitaxial process. The depth of the well region 7 ranges from 0.5µm to 4.0µm, and the doping concentration is 5e15cm -3 ~ 5e17cm -3 ;

[0057] Step 5: forming a source region and a contact region 10 in the well region 7, and etching to form a gate trench 5 and a body trench 6 penetrating the well region 7 and extending into the drift region 3; Fig. 9 As shown, a source region and a contact region 10 are formed in the well region 7 by diffusion and annealing processes. The depth of the source region ranges from 0.1µm to 0.3µm, and the doping concentration is 1e19cm -3 ~ 5e20cm -3 The depth of the contact region 10 ranges from 0.1µm to 0.3µm, and the doping concentration is 5e18cm -3 ~ 5e20cm -3 The depths of the source region and the contact region may be the same or different; the upper surfaces of the well region 7, the source region and the contact region are flush; a gate trench 5 and a body trench 6 are formed by an etching process, the depths of the gate trench 5 and the body trench 6 are the same, both ranging from 1.0µm to 10.0µm, the depths of the gate trench 5 and the body trench 6 are greater than the depth of the well region 7, and the difference between the two is not less than 0.2µm, the spacing between the gate trench 5 and the adjacent column region is 0.3µm to 5.0µm, and the spacing between the body trench 6 and the adjacent column region is 0.3µm to 10.0µm. 5.0µm, the adjacent column region here refers to the adjacent first column region 4-1 or the second column region 4-2; the source region includes a gate structure source region and a body structure source region, the gate structure source region includes a first gate structure source region 8-1 and a second gate structure source region 8-2, the body structure source region includes a first body structure source region 9-1 and a second body structure source region 9-2, the first gate structure source region 8-1 and the second gate structure source region 8-2 are located on both sides of the gate trench 5, the first body structure source region 9-1 and the second body structure source region 9-2 are located on both sides of the body trench 6; the contact region 10 is adjacent to the source region and is located between the gate trench 5 and the body trench 6; the gate trench and the body trench are in the device depth direction, that is, vertical Figure 1 The paper orientation shown can be continuous or discontinuous.

[0058] Step 6: forming a gate dielectric 11-1 on the sidewall and bottom of the gate trench 5, and forming a gate conductor 12-1 on three sides of the gate trench 5; forming a body dielectric 11-2 on the sidewall and bottom of the body trench 6; and forming a body conductor 12-2 on three sides of the body trench 6; Fig.10As shown, a gate dielectric 11-1 and a gate conductor 12-1 are formed in the gate trench 5 by LPCVD (Low Pressure Chemical Vapor Deposition) process and an etching process, and a body dielectric 11-2 and a body conductor 12-2 are formed in the body trench 6, and the surfaces of the gate conductor 12-1 and the body conductor 12-2 are flattened by a CMP process; the materials of the gate dielectric 11-1 and the body dielectric 11-2 can be silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire or hafnium oxide; the materials of the gate conductor 12-1 and the body conductor 12-2 can be metal or doped polysilicon;

[0059] Step 7: forming an isolation dielectric 13 on the gate conductor 12-1, forming a source 14 on both sides and on the isolation dielectric 13, and forming a drain 1 at the bottom of the substrate 2; Fig.11 As shown, an isolation dielectric 13 is deposited on the surface of the device prepared in step 6, and the isolation dielectric 13 completely covers the gate conductor 12-1. A source metal is deposited on both sides and on the isolation dielectric 13 to form a source ohmic contact. A drain metal is deposited on the bottom layer of the substrate 2 to form a drain ohmic contact. A source 14 is formed on the surface of the source ohmic contact, and a drain 1 is formed on the surface of the drain ohmic contact.

[0060] In step 7, source metal can be formed by sputtering or evaporation stripping process to ensure that the source metal is in full contact with the source region, the contact region and the body conductor, that is, the source 14 is in full contact with the contact region 10, the source 14 is in full contact with the gate structure source region and the body structure source region in the source region, and the source 14 is in full contact with the body conductor 12-2.

[0061] In this embodiment, the electrode materials of the source and drain are one or more combinations of metals such as Ti, Al, Ni, Pt, etc.; the isolation dielectric layer can be silicon dioxide, or nitride, or a composite of silicon dioxide and nitride. Example 2

[0062] As attached Figure 2 As shown, the present embodiment is a super junction MOSFET with optimized reverse recovery characteristics, which is different from the embodiment 1 in that: the depth of the first column region 4-1 and the second column region 4-2 is less than the depth of the drift region 3, the difference between the two ranges from 0.5µm to 15.0µm, and the bottom surfaces of the first column region 4-1 and the second column region 4-2 are flush. The present embodiment reserves the area of ​​the drift region 3 below the first column region 4-1 and the second column region 4-2, which can improve the softness of the reverse recovery characteristics and further improve the reverse recovery characteristics of the device.

[0063] The method for manufacturing a super junction MOSFET with optimized reverse recovery characteristics in this embodiment is different from that in Embodiment 1 in that:

[0064] When etching part of the first conductive type drift region to form the drift region in step 2, the etching is incomplete, that is, the depth of the column region formed in step 3 is smaller than the depth of the drift region 3 , and the bottom of the column region is higher than the bottom of the drift region 3 . Example 3

[0065] As attached Figure 3 As shown, a super junction MOSFET with optimized reverse recovery characteristics of this embodiment is different from that of embodiment 1 in that: a shielding region 15 is formed at the bottom of the gate trench 5, the conductivity type of the shielding region 15 is the same as the conductivity type of the well region 7, the depth of the shielding region 15 ranges from 0.2µm to 1.0µm, and the doping concentration is 5e17cm -3 ~ 3e19cm -3 The setting of the shielding area 15 can more effectively protect the gate dielectric 11 - 1 and improve the reliability of the device.

[0066] The method for manufacturing a super junction MOSFET with optimized reverse recovery characteristics in this embodiment is different from that in Embodiment 1 in that:

[0067] In step 5, after forming the gate trench 5 and the body trench 6, a shielding region 15 is formed at the bottom of the gate trench 5 by ion implantation, with a doping concentration of 5e17cm -3 ~ 3e19cm -3 .

[0068] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A super junction MOSFET with optimized reverse recovery characteristics, characterized in that: include: Drain; A substrate, located on the drain; a drift region located on the substrate; A column region, located on the substrate and adjacent to the drift region, including a first column region and a second column region located on both sides of the drift region; A well region, located above the drift region and the pillar region; A source region, located in the well region, including a gate structure source region and a body structure source region, wherein the gate structure source region includes a first gate structure source region and a second gate structure source region; and the body structure source region includes a first body structure source region and a second body structure source region; a contact region located in the well region and adjacent to the source region; the doping types of the substrate, drift region and source region are of a first type, the doping types of the pillar region, well region and contact region are of a second type, the first type is N-type or P-type, and the second type is P-type or N-type; A gate trench, which penetrates the well region and the gate structure source region and extends into the contact region, wherein the first gate structure source region and the second gate structure source region are respectively located on two sides of the gate trench; A body trench, which penetrates the well region and the body structure source region and extends into the contact region, wherein the first body structure source region and the second body structure source region are respectively located on both sides of the body trench; the gate trench and the body trench are respectively located in adjacent drift regions separated by the first column region, and the gate structure source region is connected to the body structure source region through the contact region; A gate dielectric, located on the sidewall and bottom of the gate trench; A gate conductor, located in the gate trench and surrounded by the gate dielectric on three sides; A body dielectric, located on the sidewalls and bottom of the body trench; A body conductor, located in the body trench and surrounded on three sides by the body dielectric; An isolation dielectric is located above the well region and completely covers the gate conductor; The source electrode is located on both sides and on the isolation medium and is in full contact with the body conductor.

2. A super junction MOSFET with optimized reverse recovery characteristics according to claim 1, characterized in that: When the depth of the column region is less than or equal to the depth of the drift region, and the depth of the column region is less than the depth of the drift region, the difference between the two ranges from 0.5µm to 15.0µm.

3. The super junction MOSFET with optimized reverse recovery characteristics according to claim 1, characterized in that: A shielding region is provided at the bottom of the gate trench. The conductivity type of the shielding region is the same as that of the well region. The depth of the shielding region ranges from 0.2µm to 1.0µm.

4. The super junction MOSFET with optimized reverse recovery characteristics according to claim 1, characterized in that: The depths of the first gate structure source region, the second gate structure source region, the first body structure source region, and the second body structure source region are 0.1µm to 0.3µm, and the doping concentration is 1e19cm -3 ~ 5e20cm -3 .

5. The super junction MOSFET with optimized reverse recovery characteristics according to claim 1, characterized in that: The gate trench and the body trench have the same depth, ranging from 1.0µm to 10.0µm, the depths of the gate trench and the body trench are greater than the depth of the well region, and the difference between the two is not less than 0.2µm, the spacing between the gate trench and the adjacent column region is 0.3µm to 5.0µm, and the spacing between the body trench and the adjacent column region is 0.3µm to 5.0µm.

6. The super junction MOSFET with optimized reverse recovery characteristics according to claim 1, characterized in that: The thickness of the body dielectric ranges from 10nm to 80nm, and the thickness of the gate dielectric ranges from 40nm to 300nm.

7. A method for manufacturing a super junction MOSFET with optimized reverse recovery characteristics, used to manufacture a super junction MOSFET with optimized reverse recovery characteristics as claimed in any one of claims 1 to 6, characterized in that: The following steps are involved: Step 1, forming a first conductivity type drift region on a substrate; Step 2, etching a portion of the first conductive type drift region to form a drift region; Step 3, forming pillar regions on both sides of the drift region, the pillar regions including a first pillar region and a second pillar region; Step 4, forming a well region on the drift region and the pillar region; Step 5, forming a source region and a contact region in the well region, etching to form a gate trench and a body trench penetrating the well region and extending into the drift region; the source region includes a gate structure source region and a body structure source region, the gate structure source region includes a first gate structure source region and a second gate structure source region, the body structure source region includes a first body structure source region and a second body structure source region, the first gate structure source region and the second gate structure source region are located on both sides of the gate trench, and the first body structure source region and the second body structure source region are located on both sides of the body trench; the contact region is adjacent to the source region and is located between the gate trench and the body trench; Step 6, forming a gate dielectric on the sidewall and bottom of the gate trench, and forming a gate conductor in the gate trench and wrapped on three sides by the gate dielectric, forming a body dielectric on the sidewall and bottom of the body trench, and forming a body conductor in the body trench and wrapped on three sides by the body dielectric; Step 7: forming an isolation dielectric on the gate conductor, forming a source on both sides and on the isolation dielectric, and forming a drain at the bottom of the substrate.

8. The method for manufacturing a super junction MOSFET with optimized reverse recovery characteristics according to claim 7, characterized in that: When etching part of the first conductive type drift region to form the drift region in step 2, the etching is complete or incomplete, so that the depth of the column region formed in step 3 is less than or equal to the depth of the drift region.

9. The method for manufacturing a super junction MOSFET with optimized reverse recovery characteristics according to claim 7, characterized in that: In step 5, after forming the gate trench and the body trench, a shielding region is formed at the bottom of the gate trench by ion implantation.

10. The method for manufacturing a super junction MOSFET with optimized reverse recovery characteristics according to claim 7, characterized in that: Step 3 and step 6 also include: flattening the device surface by a CMP process.

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