Data processing method, measurement circuit and electronic device

Abstract

The present application provides a data processing method, a measurement circuit and an electronic device, which can realize reasonable processing of ADC sampling data. The method includes: obtaining sampling data collected by an analog-to-digital converter, and obtaining the current state of the electronic device; based on the correspondence between the state of the electronic device and the compression method, processing the sampling data according to the compression method corresponding to the current state of the electronic device.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to a data processing method, a measuring circuit and an electronic equipment. Background Art

[0002] Analog to Digital Converter (ADC) is a device used to convert continuous analog signals into discrete digital signals. For example, analog signals such as the voltage of an electronic device can be converted into a multi-bit digital signal through an ADC.

[0003] When using ADC to measure the circuit of electronic equipment in real time, a large amount of data storage and external transmission will be involved. For example, taking a 16-bit ADC with a sampling rate of 100KHz as an example, the storage space M required for the sampled data generated per second is 100K*2Byte, that is, 200Kbyte. However, the storage space in the electronic equipment is limited and cannot meet the storage requirements of the ADC sampled data.

[0004] Therefore, there is a lack of a storage solution suitable for ADC sampling data. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a data processing method and electronic device, which can realize reasonable processing of ADC sampling data.

[0006] In a first aspect, the present application provides a data processing method applied to an electronic device, the electronic device including an analog-to-digital converter, the data processing method including: obtaining sampled data collected by the analog-to-digital converter, and obtaining a current state of the electronic device; based on a correspondence between the state of the electronic device and a compression method, processing the sampled data according to a compression method corresponding to the current state of the electronic device.

[0007] Through the correspondence between the state of the electronic device and the compression method, a suitable compression method that matches the current state of the electronic device can be selected to perform flexibly and variably compress the sampled data. Then, when the compressed sampled data is transmitted and stored, the storage space can be reduced while taking into account the flexibility of data compression, thereby achieving the rationality of the sampled data processing process.

[0008] Exemplarily, the current state of the electronic device may be represented by a current state value. The current state value may be represented by binary, for example, four state values ​​of "00", "01", "10", and "11" represent four states of the electronic device.

[0009] Illustratively, different compression methods may compress the sampled data to different degrees.

[0010] Exemplarily, the data processing method may be used in a measuring circuit of an electronic device, and the measuring circuit may be integrated in a measuring chip.

[0011] Exemplarily, the sampled data may be a digital quantity obtained by performing analog-to-digital conversion on a voltage signal acquired by an analog-to-digital converter. The voltage signal may be a voltage signal of a module to be detected in an electronic device, such as a display drive signal voltage, a camera power supply voltage, or a CPU power supply voltage. The signal acquired by the analog-to-digital converter may be a high-speed measurement signal.

[0012] Exemplarily, the correspondence between the state of the electronic device and the compression method may include a correspondence between a preset state value and a control parameter of a preset data processing scheme, or a correspondence between a preset state value and a preset data processing scheme.

[0013] According to the first aspect, the sampled data is processed according to the compression method corresponding to the current state of the electronic device, including: determining that the current state of the electronic device is a first state, and compressing the sampled data in a first compression method; determining that the current state of the electronic device is a second state, and compressing the sampled data in a second compression method.

[0014] In this way, different compression methods can be selected to compress the sampled data according to different states of the electronic device, thereby improving the flexibility of compression.

[0015] Exemplarily, the first state pair includes the first preset state value below, and the first compression method includes the first preset data compression method below

[0016] Exemplarily, the second state includes the second preset state value described below, and the second compression method includes the second preset data processing method described below.

[0017] Exemplarily, the first state includes a state in which the electronic device runs at least one application or task, such as an active state.

[0018] Exemplarily, the second state includes a standby state of the electronic device.

[0019] According to the first aspect, or any implementation of the first aspect above, the sampled data is processed according to the compression method corresponding to the current state of the electronic device, and also includes: determining that the current state of the electronic device is a third state, and outputting the sampled data.

[0020] In this way, when the electronic device is in the third state, the sampled data may not be compressed, so that whether to compress or not and different compression schemes may be selected according to the state of the electronic device, thereby further improving the flexibility of compression.

[0021] Exemplarily, the third state may be an abnormal state or an experimental test state of the electronic device. The abnormal state may refer to a state in which a device related to the sampled data is abnormal. The experimental test state may refer to a state of preliminary testing and verification of the electronic device before it leaves the factory.

[0022] In this way, in abnormal conditions, laboratory test conditions, and other conditions where power consumption is not a concern and storage space does not need to be saved, it is possible to choose not to compress the sampled data, thereby improving the flexibility of sampled data processing and meeting the needs of electronic equipment for using sampled data in different conditions.

[0023] According to the first aspect, or any implementation of the first aspect above, the first compression method includes a lossless compression method.

[0024] In this way, since lossless compression can compress the sampled data into compressed data with a smaller number of bits without losing the sampling accuracy of the sampled data, when the measurement circuit stores the compressed data, compared with the solution of storing the sampled data, it can save the storage space of the measurement circuit and reduce the storage pressure of the measurement circuit. Optionally, in the case where the sampled data needs to be sent to a target memory outside the measurement circuit for storage, the solution of storing the compressed data in the target memory can reduce the storage pressure of the target memory.

[0025] Exemplarily, the first state corresponding to the first compression mode includes a state in which the electronic device runs at least one application or task, such as an active state. In this way, since the electronic device needs to save storage space of the measurement circuit when running an application or task, lossless compression of sampling can meet the storage requirements of the electronic device when running an application or task while ensuring the accuracy requirements of the electronic device for the sampled data.

[0026] According to the first aspect, or any implementation method of the first aspect above, determining that the current state of the electronic device is the first state, and compressing the sampled data in a first compression manner, includes: determining that the current state of the electronic device is the first state, and the sampled data is the first sampled data, for the i-th sampled data after the first sampled data, calculating the difference between the i-th sampled data and the i-1-th sampled data, where i is greater than or equal to 1; compressing the difference between the i-th sampled data and the i-1-th sampled data according to the maximum bit position, where the maximum bit position is less than the bit position of the first sampled data.

[0027] In this way, since the change of the analog signal is continuous, the signal change between adjacent sampling points is often small. Therefore, the difference between the sampling data corresponding to the signal change (analog quantity) between adjacent sampling points (digital quantity converted from analog quantity) is also small. Therefore, by storing the difference, storage space can be further saved while ensuring lossless compression accuracy.

[0028] Exemplarily, the first sampled data is the first sampled data collected after the compression circuit receives and determines the current state of the electronic device and determines the compression method based on the current state.

[0029] Exemplarily, the compression circuit may output the first sample data, that is, the first sample data is not compressed.

[0030] Exemplarily, the compression circuit may represent the difference between the i-th sample data and the i-1-th sample data as a fixed-bit compressed data, where the fixed-bit number (compression bit number) is less than or equal to the maximum bit. For example, if the maximum bit is 7 bits, the difference between the i-th sample data and the i-1-th sample data may be represented as a 7-bit compressed data.

[0031] Exemplarily, the maximum bit is the number of bits of the difference calculated using a lossless compression algorithm.

[0032] Exemplarily, when the compression circuit receives the first sampling data (first sampling data), it can output the first sampling data; when receiving the second sampling data, it calculates the difference between the second sampling data and the first sampling data, and represents the difference as a 7-bit compressed data; when receiving the third sampling data, it calculates the difference between the third sampling data and the second sampling data, and represents the difference as a 7-bit compressed data; and so on,…

[0033] According to the first aspect, or any implementation of the first aspect above, after compressing the difference between the i-th sampling data and the i-1-th sampling data according to the maximum bit, the method further includes:

[0034] When it is determined that the number of compressed sampling data exceeds the preset number, the next sampling data is used as the first sampling data to repeat the calculation for the i-th sampling data after the first sampling data, the difference between the i-th sampling data and the i-1-th sampling data is calculated, and the difference between the i-th sampling data and the i-1-th sampling data is compressed according to the maximum bit.

[0035] In this way, the sampled data can be stored and read in blocks, and when reading the sampled data, it is not necessary to read all the sampled data, which improves the flexibility of data reading and ensures the flexibility of data editing. Optionally, it can also reduce the occurrence of the situation where subsequent data are all wrong due to an error in one data, thereby reducing the error rate of data reading.

[0036] Exemplarily, the preset number may be the size of a data block, for example, represented as N, where N is an integer greater than or equal to 2.

[0037] Exemplarily, when the compression module receives the first sampling data (first sampling data), it can output the first sampling data; when the second sampling data is received, the difference between the second sampling data and the first sampling data is calculated, and the difference is represented as a 7-bit compressed data; when the third sampling data is received, the difference between the third sampling data and the second sampling data is calculated, and the difference is represented as a 7-bit compressed data; ...; when the Nth sampling data is received, the difference between the Nth sampling data and the N-1th sampling data is calculated, and the difference is represented as a 7-bit compressed data; and, the received N+1th sampling data is used as the first sampling data, and the N+1th sampling data is output; when the N+2th sampling data is received, the difference between the N+2th sampling data and the N+1th sampling data is calculated, and the difference is represented as a 7-bit compressed data; ...; and so on.

[0038] According to the first aspect, or any implementation of the first aspect above, the second compression method includes a lossy compression method.

[0039] In this way, since lossy compression can further compress the sampled data into compressed data with a smaller number of bits based on lossless compression, the storage pressure on the measurement circuit is further reduced, and the storage pressure on the electronic device can also be further reduced.

[0040] Exemplarily, the second state corresponding to the second compression mode includes a standby state. In this way, although lossy compression may cause a risk of loss of measurement accuracy, that is, a portion of the measurement accuracy may be lost, since the measured voltage does not fluctuate much when the electronic device is in the standby state, the electronic device does not have high requirements for the measurement accuracy of the measured voltage at this time, and the storage space can be further saved while meeting the accuracy requirements of the electronic device for the test voltage (i.e., sampling data).

[0041] According to the first aspect, or any implementation method of the first aspect above, determining that the current state of the electronic device is the second state, and compressing the sampled data in a second compression method, includes: determining that the current state of the electronic device is the second state, and the sampled data is the first sampled data, for the i-th sampled data after the first sampled data, calculating the difference between the i-th sampled data and the i-1-th sampled data, where i is an integer greater than or equal to 1 and less than a preset number; compressing the difference between the i-th sampled data and the i-1-th sampled data according to a preset bit position, where the preset bit position is less than the maximum bit position.

[0042] In this way, since the preset bit is smaller than the maximum bit, compared with lossless compression, the number of bits of compressed data can be further shortened, thereby further reducing the storage pressure on the measurement circuit and the storage pressure on the electronic device.

[0043] Exemplarily, the preset bit position is the number of compression bits corresponding to the lossy compression.

[0044] Exemplarily, at least one bit at the end of the difference between the i-th sample data and the (i-1)-th sample data may be discarded, so that the number of bits of the compressed data obtained by discarding is equal to the preset bit.

[0045] Exemplarily, the compression circuit may represent the difference between the i-th sample data and the i-1-th sample data as a compressed data with a fixed number of bits, where the fixed number of bits is equal to the preset bit number. For example, if the maximum bit number is 7 bits and the fixed number of bits is 5 bits, the difference between the i-th sample data and the i-1-th sample data may be represented as a compressed data with 5 bits.

[0046] Exemplarily, when the compression module receives the first sampling data (first sampling data), it can output the first sampling data; when the second sampling data is received, it calculates the difference between the second sampling data and the first sampling data, and represents the difference as a 5-bit compressed data; when the third sampling data is received, it calculates the difference between the third sampling data and the second sampling data, and represents the difference as a 5-bit compressed data; and so on,…

[0047] According to the first aspect, or any implementation of the first aspect above, after compressing the difference between the i-th sampling data and the i-1-th sampling data according to the preset bit position, the method further includes:

[0048] When it is determined that the number of compressed sampling data exceeds the preset number, the next sampling data is used as the first sampling data and the steps of calculating the difference between the i-th sampling data and the i-1-th sampling data for the i-th sampling data after the first sampling data are repeated; and compressing the difference between the i-th sampling data and the i-1-th sampling data according to the preset bit position are performed.

[0049] In this way, the sampled data can be stored and read in blocks, and when reading the sampled data, it is not necessary to read all the sampled data, which improves the flexibility of data reading and ensures the flexibility of data editing. Optionally, it can also reduce the occurrence of the situation where subsequent data are all wrong due to an error in one data, thereby reducing the error rate of data reading.

[0050] Exemplarily, the preset number may be the size of a data block, for example, represented as N, where N is an integer greater than or equal to 2.

[0051] Exemplarily, when the compression module receives the first sampling data (first sampling data), it can output the first sampling data; when the second sampling data is received, the difference between the second sampling data and the first sampling data is calculated, and the difference is represented as a 5-bit compressed data; when the third sampling data is received, the difference between the third sampling data and the second sampling data is calculated, and the difference is represented as a 5-bit compressed data; ...; when the Nth sampling data is received, the difference between the Nth sampling data and the N-1th sampling data is calculated, and the difference is represented as a 5-bit compressed data; and, the received N+1th sampling data is used as the first sampling data, and the N+1th sampling data is output; when the N+2th sampling data is received, the difference between the N+2th sampling data and the N+1th sampling data is calculated, and the difference is represented as a 5-bit compressed data; ...; and so on.

[0052] According to the first aspect, or any implementation of the first aspect above, the maximum bit Lmax satisfies:

[0053]

[0054] in, represents a round-up function, f is the signal frequency of the analog signal corresponding to the sampled data, A is the maximum amplitude of the analog signal, k is the sampling rate of the analog-to-digital converter, Vref is the reference voltage of the analog-to-digital converter, and P is the number of bits of the analog-to-digital converter.

[0055] Thus, since 2πfA / k can represent the maximum change of the analog signal between adjacent sampling points, Vref / 2 PThe analog value of the analog signal that can be represented by one bit of the digital signal can be represented. Therefore, it is possible to accurately calculate how many bits can be used to represent the difference.

[0056] According to the first aspect, or any implementation of the first aspect above, the first state includes multiple first sub-states, the first compression mode includes multiple first compression sub-modes, and the multiple first sub-states correspond one-to-one to the multiple first compression sub-modes; determining that the current state of the electronic device is the first state, and compressing the sampled data in the first compression mode, includes: determining that the current state of the electronic device is the target first sub-mode, and compressing the sampled data in the first compression sub-mode corresponding to the target first sub-mode, wherein the target first sub-mode is one of the multiple first sub-states.

[0057] Different degrees of lossless compression can be applied to electronic devices according to their different state levels in the same state, which further improves the compression flexibility and meets the compression requirements of electronic devices at different state levels.

[0058] Exemplarily, the electronic device has different numbers of applications or tasks running in different first sub-states. For example, different first sub-states may correspond to different activity levels of the active state.

[0059] Exemplarily, different first compression sub-modes may correspond to different compression bit numbers, and the compression bit numbers are all greater than or equal to the maximum bit. For example, the compression bit numbers corresponding to different first compression sub-modes may be 7 bits, 8 bits, or 9 bits.

[0060] According to the first aspect, or any implementation of the first aspect above, the second state includes multiple second sub-states, the second compression mode includes multiple second compression sub-modes, and the multiple second sub-states correspond one-to-one to the multiple second compression sub-modes; determining that the current state of the electronic device is the second state, and compressing the sampled data in the second compression mode, includes: determining that the current state of the electronic device is the target second sub-mode, and compressing the sampled data in the second compression sub-mode corresponding to the target second sub-mode, wherein the target second sub-mode is one of the multiple second sub-states.

[0061] Different degrees of lossless compression can be applied to electronic devices according to their different state levels in the same state, which further improves the compression flexibility and meets the compression requirements of electronic devices at different state levels.

[0062] Exemplarily, the electronic device has different standby degrees in different second sub-states. For example, different second sub-states may correspond to different standby levels of the standby state.

[0063] Exemplarily, different second compression sub-modes may correspond to different compression bit numbers, and the compression bit numbers are all less than the maximum bit. For example, the compression bit numbers corresponding to different second compression sub-modes may be 6 bits, 5 bits, or 4 bits.

[0064] In a second aspect, an embodiment of the present application provides a measurement circuit, which is arranged in an electronic device, and the measurement circuit includes an analog-to-digital converter, a control circuit and a compression circuit; the control circuit is used to obtain the current state of the electronic device, and based on the correspondence between the state of the electronic device and the compression method, sends a control signal to the compression circuit; the compression circuit is used to process the sampled data collected by the analog-to-digital converter according to the control signal according to a preset compression method, wherein the preset compression method is a compression method corresponding to the current state of the electronic device.

[0065] Exemplarily, the control signal is used to control the compression circuit to process and compress the sampled data according to the compression method corresponding to the current state.

[0066] Exemplarily, the control signal may include control parameters of the compression method corresponding to the current state, such as whether to compress, the size of the data block, or one or more of the compression bits.

[0067] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0068] According to the second aspect, the current state of the electronic device is the first state, and the compression circuit is used to compress the sampled data in a first compression mode; the current state of the electronic device is the second state, and the compression circuit is used to compress the sampled data in a second compression mode.

[0069] According to the second aspect, or any implementation of the second aspect, the current state of the electronic device is the third state, and the compression circuit is further used to: directly output the sampled data.

[0070] According to the second aspect, or any implementation of the second aspect, the first compression method includes a lossless compression method.

[0071] According to the second aspect, or any implementation method of the second aspect above, the current state of the electronic device is the first state, and the compression circuit is used to: when the sampling data is the first sampling data, for the i-th sampling data after the first sampling data, calculate the difference between the i-th sampling data and the i-1-th sampling data, where i is greater than or equal to 1; and compress the difference between the i-th sampling data and the i-1-th sampling data according to the maximum bit position, and the maximum bit position is less than the bit position of the first sampling data.

[0072] According to the second aspect, or any implementation of the second aspect above, the compression circuit is also used to: when it is determined that the number of compressed sampling data exceeds a preset number, use the next sampling data as the first sampling data to repeat the calculation for the i-th sampling data after the first sampling data, calculate the difference between the i-th sampling data and the i-1-th sampling data, and compress the difference between the i-th sampling data and the i-1-th sampling data according to the maximum bit.

[0073] According to the second aspect, or any implementation of the second aspect, the second compression method includes a lossy compression method.

[0074] According to the second aspect, or any implementation of the second aspect above, the compression circuit is used to: determine that the current state of the electronic device is the second state, and the sampling data is the first sampling data, and for the i-th sampling data after the first sampling data, calculate the difference between the i-th sampling data and the i-1-th sampling data, where i is greater than or equal to 1; compress the difference between the i-th sampling data and the i-1-th sampling data according to a preset bit position, wherein the preset bit position is less than the maximum bit position, and the maximum bit position is less than the bit position of the first sampling data.

[0075] According to the second aspect, or any implementation of the second aspect above, the compression circuit is further used to: when it is determined that the number of compressed sampling data exceeds a preset number, use the next sampling data as the first sampling data to repeat the steps of calculating the difference between the i-th sampling data and the i-1-th sampling data for the i-th sampling data after the first sampling data; and compress the difference between the i-th sampling data and the i-1-th sampling data according to a preset bit position.

[0076] According to the second aspect, or any implementation of the second aspect above, the maximum bit Lmax satisfies:

[0077]

[0078] in, represents a round-up function, f is the signal frequency of the analog signal corresponding to the sampled data, A is the maximum amplitude of the analog signal, k is the sampling rate of the analog-to-digital converter, Vref is the reference voltage of the analog-to-digital converter, and P is the number of bits of the analog-to-digital converter.

[0079] According to the second aspect, or any implementation of the second aspect above, the first state includes multiple first sub-states, the first compression mode includes multiple first compression sub-modes, and the multiple first sub-states correspond one-to-one to the multiple first compression sub-modes; the current state of the electronic device is the target first sub-mode, and the compression circuit is used to: compress the sampled data in the first compression sub-mode corresponding to the target first sub-mode, wherein the target first sub-mode is one of the multiple first sub-states.

[0080] According to the second aspect, or any implementation of the second aspect above, the second state includes multiple second sub-states, the second compression mode includes multiple second compression sub-modes, and the multiple second sub-states correspond one-to-one to the multiple second compression sub-modes; the current state of the electronic device is the target second sub-mode, and the compression circuit is used to: compress the sampled data in the second compression sub-mode corresponding to the target second sub-mode, wherein the target second sub-mode is one of the multiple second sub-states.

[0081] In a third aspect, the present application provides an electronic device comprising: one or more processors; one or more memories; the one or more memories storing one or more programs, which, when executed by the one or more processors, enable the electronic device to execute instructions of the method in the first aspect or any possible implementation of the first aspect.

[0082] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0083] In a fourth aspect, the present application provides a computer-readable medium for storing a computer program, wherein the computer program includes instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0084] The fourth aspect and any implementation of the fourth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0085] In a fifth aspect, the present application provides a chip, the chip comprising a processing circuit and a transceiver pin, wherein the transceiver pin and the processing circuit communicate with each other through an internal connection path, and the processing circuit executes the method in the first aspect or any possible implementation of the first aspect to control the receiving pin to receive a signal and control the sending pin to send a signal.

[0086] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0087] In a sixth aspect, the present application provides a computer program comprising instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0088] The sixth aspect and any implementation of the sixth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the sixth aspect and any implementation of the sixth aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Figure 1 A schematic diagram of an exemplary analog signal provided in an embodiment of the present application;

[0090] Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application

[0091] Figure 3 A circuit diagram of an electronic device provided in an embodiment of the present application;

[0092] Figure 4 A schematic diagram of a circuit structure of a measurement circuit provided in an embodiment of the present application;

[0093] Figure 5a A schematic diagram of the circuit structure of another measurement circuit provided in an embodiment of the present application;

[0094] Figure 5b A schematic diagram of the circuit structure of another measurement circuit provided in an embodiment of the present application;

[0095] Figure 6a A flowchart of an exemplary data processing method provided in an embodiment of the present application;

[0096] Figure 6bA flowchart of another exemplary data processing method provided in an embodiment of the present application;

[0097] Figure 7 A schematic diagram of a processing flow of a compression circuit provided in an embodiment of the present application;

[0098] Figure 8 A schematic diagram of an exemplary data block provided in an embodiment of the present application;

[0099] Fig. 9 A schematic diagram showing an exemplary data to be stored provided by an embodiment of the present application;

[0100] Fig.10 A logical diagram of an exemplary data processing provided by an embodiment of the present application is shown;

[0101] Fig.11 A schematic diagram showing another exemplary data block provided in an embodiment of the present application is shown;

[0102] Figure 12a-12b Another exemplary logic diagram of data processing provided by an embodiment of the present application is shown;

[0103] Fig.13 A schematic diagram showing another exemplary data block provided in an embodiment of the present application is shown;

[0104] Fig.14 A logical schematic diagram of another exemplary data processing provided by an embodiment of the present application is shown;

[0105] Fig.15 A flowchart of a data processing method provided in an embodiment of the present application;

[0106] Fig.16 A schematic diagram of an exemplary lossy compression process provided in an embodiment of the present application;

[0107] Fig.17 A schematic block diagram of a device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0108] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0109] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0110] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0111] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0112] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0113] In electronic devices such as mobile phones, it is often necessary to use ADC to measure the performance parameters of the electronic devices. For example, in order to ensure the normal use of the electronic device, the electronic device can detect the performance parameters of the electronic device through ADC, so that the abnormality of the electronic device can be detected in time when the sampled data is abnormal. For another example, the electronic device can calculate the sampled data to obtain the data required by the electronic device.

[0114] During the ADC measurement process, it can sample the analog signal multiple times, and convert the sampled analog quantity into a digital quantity (sampled data in the embodiment of the present application) for storage or transmission. The large amount of sampled data generated by the ADC often involves storage and transmission problems, which puts storage pressure on electronic devices. Therefore, how to provide a storage solution suitable for ADC sampled data has become a technical problem that needs to be solved urgently.

[0115] To facilitate understanding, before introducing the technical solutions of the embodiments of the present application, the technical terms involved are explained first.

[0116] (1)Analog signal. Figure 1 Schematic diagram of an exemplary analog signal provided in an embodiment of the present application. Figure 1 As shown, the ADC can sample the continuous analog signal 101. Specifically, the ADC can sample the analog signal 101 multiple times according to the sampling frequency. Figure 1 A sampling point 1011 ( Figure 1 The black dots in the figure, such as the first sampling point 1011a or the second sampling point 1011b, correspond to one sampling, and an amplitude (analog quantity) of an analog signal can be sampled at each sampling point 1011. For example, taking the sampling data as a voltage signal, the voltage value Va (the amplitude of the voltage signal at the first sampling point 1011a) is sampled at the first sampling point 1011a, and the voltage value Vb (the amplitude of the voltage signal at the first sampling point 1011a) is sampled at the second sampling point 1011b.

[0117] (2) Sampled data, i.e., a digital quantity obtained by ADC converting the analog quantity of an analog signal into a digital quantity. Specifically, a sampled data may be a binary string consisting of "0" and / or "1", for example, Figure 1 As shown in the figure, a sample value can be a 14-bit binary string. The signal amplitude (analog value) of a sampling point can be converted into a sample data (digital value). For example, continue to refer to Figure 1 For the first sampling point 1011a, the voltage value Va of the first sampling point 1011a can be converted into the sampling data "11111110101110". For the second sampling point 1011b, the voltage value Vb of the second sampling point 1011b can be converted into the sampling data "00000010111010". It should be noted that the data values ​​of the sampling data obtained by converting different voltage values ​​are different, and the data values ​​of the sampling data obtained by converting the same voltage value are the same.

[0118] (3) ADC bit number, that is, the number of bits of the digital signal converted by the ADC. Figure 1 For example, the ADC bit number is 14. In the embodiment of the present application, the symbol P is used to represent the ADC bit number.

[0119] (4) The sampling rate of the ADC, that is, the number of times the ADC samples in one second. For example, if the sampling rate of the ADC is 100K, it means that the ADC performs 100K samplings in one second. In the embodiment of the present application, the symbol k is used to represent the sampling rate of the ADC.

[0120] (5) The signal frequency of the analog signal, that is, the frequency of the analog signal, which is equal to the inverse of the period of the analog signal. Figure 1 , if the period of the analog signal is T, then the signal frequency of the analog signal is 1 / T. In the embodiment of the present application, the symbol f is used to represent the signal frequency of the analog signal.

[0121] (6) The maximum amplitude of the analog signal, that is, the difference between the amplitude of the analog signal and the zero value of the analog signal. Figure 1 , the maximum amplitude of the analog signal is A. In the embodiment of the present application, the symbol A is used to represent the maximum amplitude of the analog signal.

[0122] (7) Reference voltage, i.e., the maximum input voltage that can be successfully converted into an accurate digital representation. Specifically, the reference voltage is greater than or equal to the maximum value of the analog signal. In the embodiment of the present application, the reference voltage is represented by the symbol Vref.

[0123] After the preliminary explanation of the above technical terms, the embodiments of the present application will be described next.

[0124] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 2 As shown, an embodiment of the present application provides an electronic device, and the electronic device provided in the embodiment of the present application may include but is not limited to mobile phones, tablet computers, laptop computers, ultra-mobile personal computers (Ultra-Mobile Personal Computer, UMPC), personal digital assistants (Personal Digital Assistant, PDA), point of sales (Point Of Sales, POS) machines, intercoms, car computers, televisions, smart wearable devices (such as smart watches or smart bracelets, etc.), smart home devices (such as Bluetooth speakers, etc.), driving recorders, security equipment, etc. Electronic devices, the embodiment of the present application does not specifically limit the specific types of the above electronic devices. For the convenience of explanation, the following description is taken as an example of an electronic device being a mobile phone.

[0125] in, Figure 2 (1) is a schematic diagram of the front structure of the electronic device. Figure 2 (2) is a schematic diagram of the back structure of the electronic device. Figure 2 As shown, the electronic device 100 includes a display module 10 , a back cover (also called a battery cover) 20 and a middle frame 30 .

[0126] The display module 10 includes a cover plate and a display screen which are stacked. The cover plate, for example, protects the display screen. The display screen includes, for example, a liquid crystal display (LCD), an organic light emitting diode (OLED) display screen, and an LED display screen, among which the LED display screen includes, for example, a Micro-LED display screen, a Mini-LED display screen, and the like. The embodiment of the present application does not limit the type of the display screen.

[0127] The material of the back cover 20 may include, for example, opaque materials such as plastic, plain leather, and glass fiber; or may include translucent materials such as glass. The material of the back cover 20 is not limited in the embodiment of the present application.

[0128] The middle frame 30 includes an annular appearance member 31 and a support member (not shown) located inside the annular appearance member 31 and between the display module 10 and the back cover 20 .

[0129] The display module 10, the back cover (also called the battery cover) 20 and the annular appearance member 31 surround a housing cavity, in which a battery, a printed circuit board (PCB) 40 and a functional device 50 are arranged ( Figure 2 (not shown in the figure), the functional device 50 includes a first functional component and a second functional component. The first functional component can be arranged on PCB 40 and electrically connected to PCB 40; the second functional component is not arranged on the PCB, but is electrically connected to PCB 40. The first functional component may include devices such as a processor, a power supply module (such as a power management chip and / or a charging management module, etc.), a display drive circuit and a measurement circuit, and the second functional component may include devices such as a flash and a camera 55. The various devices are electrically connected through PCB 40 to achieve signal transmission and interaction. The support member can support part of the structure in the accommodating cavity.

[0130] The processor may include one or more processing units, for example, the processor may include a baseband processor, an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0131] A memory may be provided in the processor for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. The memory may store instructions or data that the processor has just used or circulated. If the processor needs to use the instruction or data again, it may be directly called from the memory. Repeated access is avoided, the waiting time of the processor is reduced, and the efficiency of the system is improved. In an embodiment of the present application, the memory may store compressed data that needs to be stored and is sent by the measurement circuit.

[0132] In some embodiments, the processor may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, a serial peripheral interface (SPI), an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0133] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor may include multiple groups of I2C buses. The processor can be coupled to a flash, a camera 55, etc. through different I2C bus interfaces. In an embodiment of the present application, the processor can be coupled to a measurement circuit through the I2C interface, so that the processor and the measurement circuit communicate through the I2C bus interface to realize the detection function of the electronic device 100.

[0134] The charging management module is used to receive charging input from a charger. The charger can be a wireless charger or a wired charger. While the charging management module charges the battery, it can also power the electronic device through the power management module.

[0135] The power management module is used to connect the battery, the charging management module and the processor. The power management module receives input from the battery and / or the charging management module to power the processor, the display screen, the camera 55, etc. In some other embodiments, the power management module can also be set in the processor. In some other embodiments, the power management module and the charging management module can also be set in the same device. The display drive circuit is used to drive the display screen to display pictures or videos, etc.

[0136] The camera 55 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then transmits the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device may include one or more cameras. The flash is used to provide a fill light function for the camera 55.

[0137] It is to be understood that the above content only schematically illustrates some components included in the mobile phone 100. The actual mobile phone 100 may have more or fewer components than the above content, or some components may be combined, or some components may be separated, or the components may be arranged differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0138] It should be noted that Figure 2 In the embodiment, the mobile phone 100 is in a rectangular flat plate shape. In other optional embodiments, the shape of the electronic device can also be a square flat plate shape, a circular flat plate shape, an elliptical flat plate shape, etc. Of course, the electronic device can also be a foldable electronic device, etc.

[0139] Figure 3 A circuit diagram of an electronic device provided in an embodiment of the present application, such as Figure 3 As shown, the display driving circuit 52 is connected to the processor 51 and the display screen 53 respectively, and is used to drive the display screen 53 under the control of the processor 51. Specifically, the display driving circuit 52 can send a display driving signal to the display screen 53 to drive the display screen 53 to display an image or video.

[0140] The power supply module 54 is connected to the processor 51 and the camera 40, etc., respectively, and is used to supply power to the power modules such as the processor 51 and the camera 55. For example, the power supply module 54 may include but is not limited to a processor power supply circuit 541 and a camera power supply circuit 542, so as to supply power to the processor 51 through the processor power supply circuit 541, and to supply power to the camera 55 through the camera power supply circuit 542. Exemplarily, the processor power supply circuit 541 and the camera power supply circuit may be powered by the same power supply, or by different power supplies, which is not limited in this application. Among them, the number of power supplies may be one or more, which is not limited in this application.

[0141] The measuring circuit 56 is used to measure the performance parameters of the electronic device and the components of the electronic device. The performance parameters may be parameters such as voltage, current, temperature, pressure, etc. For example, the measuring circuit 56 may be a measuring chip or other structure with a measuring function. Specifically, the measuring circuit 56 may detect the performance parameters of the module to be detected in the electronic device. The module to be detected may be any circuit, functional module or device in the electronic device that needs to perform performance parameter detection, such as Figure 3 , Figure 3 The dotted arrows in the figure are used to represent the test relationship of the measurement circuit 56. Accordingly, the modules to be tested may be the display driving circuit 52, the processor power supply circuit 541, the camera power supply circuit 542, etc.

[0142] It should be noted that the module to be detected can be selected according to specific measurement requirements and measurement scenarios, and there is no specific limitation on this. Also, it should be noted that in the embodiment of the present application, one measurement circuit 56 can be used to detect multiple modules to be detected, or multiple measurement circuits 56 can be used to detect different modules to be detected, and there is no specific limitation on this.

[0143] In one embodiment, taking voltage measurement as an example, Figure 4 The circuit structure diagram of a measurement circuit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the measurement circuit 56 may include a test resistor R, an ADC 561, a data cache unit 562, a bus 563, a first transmission interface 564, a data storage unit 565, and a second transmission interface 566. Exemplarily, the above circuit composition structure may be integrated into a measurement chip.

[0144] A test resistor R is connected to the module to be detected (such as being connected to the inside or outside of the device to be tested). In one example, in the measurement scenario of the display drive signal (which may be a voltage signal) of the display driver circuit 52, the test resistor R can be connected in series between the display driver circuit 52 and the display screen 53. That is to say, one end of the test resistor R is connected to the display driver circuit 52, and the other end of the test resistor R is connected to the display screen 53. In this example, the display drive signal output by the display driver circuit 52 is transmitted to the display screen 53 through the test resistor R. When the display drive signal voltage changes, the voltage difference across the test resistor R will change due to the ohmic characteristics of the test resistor R. Accordingly, the measurement of the display drive signal can be achieved by measuring the voltage difference across the test resistor R. In another example, in the test scenario of the processor power supply voltage (i.e., the voltage supplied by the processor 51 to the processor), the test resistor R can be arranged on the power supply link of the processor power supply circuit 541. Exemplarily, for one or more power supplies of the processor power supply circuit 541, if multiple branches are separated from the main road to power the processor 51, the test resistor R can be set on the main road of the one or more power supplies to measure the processor power supply voltage output by the processor power supply circuit 541. In this example, when the processor power supply voltage changes, the voltage difference across the test resistor R will change due to the ohmic characteristics of the test resistor R. Accordingly, the measurement of the processor power supply voltage can be achieved by measuring the voltage difference across the test resistor R. In another example, in the test scenario of the camera power supply voltage (i.e., the voltage for powering the camera 55), the test resistor R can be set on the power supply link of the camera power supply circuit 542. Exemplarily, for one or more power supplies of the camera power supply circuit 542, if multiple branches are separated from the main road to power the camera 55, the test resistor R can be set on the main road of the one or more power supplies to measure the camera power supply voltage output by the camera power supply circuit 542. In this example, when the camera power supply voltage changes, the voltage difference across the test resistor R will change due to the ohmic characteristics of the test resistor R. Accordingly, the camera power supply voltage can be measured by measuring the voltage difference across the test resistor R.

[0145] ADC 561 includes a positive input terminal Vin+ and a negative input terminal Vin-, wherein the positive input terminal Vin+ is connected to one end of the test resistor, and the negative input terminal Vin- is connected to the other end of the test resistor, so that the voltage difference across the test resistor R can be collected through ADC561, and the collected voltage difference is converted into analog-to-digital to obtain P-bit sampling data Out[0:P-1].

[0146] Specifically, ADC561 can be an analog-to-digital conversion chip or other devices or functional modules with analog-to-digital conversion functions, and there is no specific limitation on this. For example, ADC561 can convert the input differential pressure data into sampled data Out[0:P-1] by sampling-holding-quantization-encoding. Wherein, P is a positive integer greater than or equal to 2, for example, it can be 14 bits, etc. It should be noted that P can also be set to other values ​​such as 8 bits, 10 bits, 18 bits, etc. according to the conversion accuracy of the ADC and the data accuracy requirements, and there is no specific limitation on this.

[0147] The data cache unit 562 is used to cache the sampled data Out[0:P-1] output by ADC561. Exemplarily, the data cache unit 562 may include one or more first-in-first-out (FIFO) buffers. It should be noted that the data cache unit 562 may also be other devices capable of data caching, without limitation. In an embodiment of the present application, when the sampling rate of the ADC is inconsistent with the transmission rate of the sampled data, the data cache unit 562 may temporarily cache the sampled data before transmitting or storing it, to avoid data processing problems caused by the inconsistency between the sampling rate and the storage rate.

[0148] Bus 563 is used to transmit the sampled data output by the data cache unit 562. For example, bus 563 can be an I2C bus or an SPI bus. For example, a suitable bus can be selected according to the transmission rate, such as selecting an SPI bus when the transmission rate is faster, and selecting an I2C bus when the transmission rate is slower. It should be noted that a bus using other transmission protocols can also be selected according to actual transmission requirements and specific transmission scenarios, and this application does not limit this.

[0149] The first transmission interface 564 can be connected to a first memory (not shown in the figure) located outside the measurement circuit 56. For example, the first memory can be a memory of the processor 51, or an internal memory of an electronic device (such as a storage area of ​​a double data rate synchronous dynamic random access memory (DDR) of a mobile phone), an external memory of an electronic device, and other memories. Specifically, when the sampled data needs to be transmitted in real time, the sampled data can be transmitted to the first memory in real time through the first transmission interface 564. It should be noted that the number of first memories in the embodiment of the present application can be one or more, the first memory can be implemented as a memory chip, and each first memory can include one or more storage areas.

[0150] In other optional embodiments of the present application, the first transmission interface 564 can also be connected to other devices, such as a processor or a detection device. When the first transmission interface 564 is connected to the processor, the detection module 56 transmits the detected data to the processor through the first transmission interface 564, and the signal is processed by the processor to determine whether the data meets the preset requirements. When the first transmission interface 564 is connected to the detection device (the detection device is a device that needs to detect the module to be detected inside the electronic device before the electronic device leaves the factory), the detection module 56 transmits the detected data to the detection device through the first transmission interface 564 to determine whether the data meets the preset requirements.

[0151] The data storage unit 565 is used to store the received sampled data and, after the data output condition is met, batch output the stored multiple sampled data. Exemplarily, the data storage unit 565 may include a static random access memory (SRAM). It should be noted that the data storage unit 565 may also be implemented as other memories capable of data storage, and there is no specific limitation on its type.

[0152] Furthermore, the data output condition may be a condition that the sampled data must satisfy before it can be output. Next, the data output condition will be described through a number of examples.

[0153] In one example, the data output condition may include condition 1, that is, the data storage unit 565 is full, that is, the remaining storage space of the data storage unit 565 is less than the preset storage space, such as the remaining storage space of the storage unit 565 is zero. In other words, when the data storage unit 565 is not full, the data storage unit 565 stores the received sampled data and does not output the data at this time. When the data storage unit 565 is full, the data storage unit 565 collectively outputs the stored sampled data.

[0154] In another example, the data output condition may include condition 2, that is, the amount of sampled data stored in the data storage unit 565 reaches a preset quantity threshold (the preset quantity threshold can be set according to the actual scenario and specific needs, and its specific value is not limited). In other words, when the data storage amount of the data storage unit 565 does not reach the preset data threshold, the data storage unit 565 stores the received sampled data and does not output the data at this time. When the data storage amount of the data storage unit 565 reaches the preset data threshold, the data storage unit 565 collectively outputs the stored sampled data.

[0155] In another example, the data output condition may include condition 3, that is, a preset time has passed since the last data transmission (that is, data transmission is performed periodically, and the preset time is the time of a data storage cycle, which can be set according to the actual scenario and specific needs, and there is no restriction on its specific value). That is to say, in each data storage cycle, the data storage unit 565 stores the received sampled data, and no data output is performed at this time. At the end of each data storage cycle, the data storage unit 565 outputs the stored sampled data collectively. In other words, the sampled data stored within the preset time is collectively output according to the preset time interval. For example, the data storage unit 565 can output the sampled data stored within 1s every 1s (the preset time interval is 1s).

[0156] In another example, the data output condition may include condition 4, i.e., receiving a data transmission command sent by the processor 51. The data transmission command is used to control the data storage unit 565 to output the stored data. Exemplarily, a digital logic processing module is also provided in the measurement circuit, which can analyze the sampled data. If the sampled data is found to be abnormal (for example, the sampled data exceeds the normal value range of the preset data), an abnormal prompt message can be sent to the processor 51. After the processor 51 determines that the sampled data is abnormal in response to the abnormal prompt message, it can send a data transmission instruction to the data storage unit 565. In response to the data transmission instruction, the data storage unit 565 sends the stored data to the processor 51 through the second transmission interface 566.

[0157] It should be noted that in the embodiment of the present application, the data output condition set by the data storage unit 565 may include one or more of the conditions 1 to 4 shown in the above example. It should be noted that the data output condition can also be set to other conditions according to the actual data transmission scenario and data transmission requirements, and there is no specific limitation on this.

[0158] The second transmission interface 566 can be connected to a second memory (not shown) outside the measurement circuit 56, wherein the second memory can be a memory of the processor 51, an internal memory of an electronic device, or an external memory of an electronic device. Specifically, when it is necessary to transfer the sampled data in batches, the sampled data can be transferred in batches to the second memory through the second transmission interface 566. It should be noted that the second memory is similar to the first memory, and the relevant description of the first memory in the above part of the embodiment of the present application can be referred to, which will not be repeated here. The first memory and the second memory can be the same memory, or can be different memories, without specific limitation.

[0159] In other optional embodiments of the present application, the second transmission interface 566 may also be connected to other devices, such as a processor, etc. When the second transmission interface 566 is connected to the processor, the measurement circuit 56 transmits the data stored in the data storage unit 565 to the processor through the second transmission interface 566, and the processor processes the signal to determine whether the data meets the preset requirements.

[0160] In an embodiment of the present application, in a data transmission scenario, when real-time transmission is required, after the ADC 561 acquires the sampled data and caches the sampled data using the data cache unit 562, the data cache unit 562 can output the sampled data to the first transmission interface 564 through the bus 563, so as to transmit the sampled data to the processor 51 in real time through the first transmission interface 564. In another data transmission scenario, in order to reduce the power consumption of the processor 51, after the ADC 561 acquires the sampled data and caches the sampled data using the data cache unit 562, the data cache unit 562 can send the sampled data to the data storage unit 565 through the bus 563. The data storage unit 565 can output the sampled data to the second transmission interface 566 when it is determined that the data output condition is met (for example, the data storage unit 565 is full), so as to transmit the sampled data to the processor 51 in batches through the second transmission interface 566. In this data transmission scenario, the processor 51 can be awakened at intervals for data processing, and the processor 51 does not need to work continuously, thereby reducing the power consumption of the processor 51.

[0161] However, when using the above Figure 4 When the circuit structure shown is used to measure performance parameters such as voltage, the inventors have found that ADC involves the storage and external transmission of a large amount of data. If the sampled data is not compressed, N pieces of sampled data (if the data length of each piece of sampled data is 14 bits) require at least N*14 bits of memory space, which will cause great storage pressure on the electronic device. For example, if the sampling rate of the ADC is 100K (thousands) and the number of bits is 14 bits (bits), the storage space M required for the samples generated by the ADC per second reaches 200K*Byte, and the data storage unit in the measurement circuit cannot provide enough storage space for it, thereby causing storage pressure on the measurement circuit and / or.

[0162] Therefore, how to store ADC sampling data has become a technical problem that needs to be solved urgently.

[0163] Based on this, the embodiment of the present application provides a data processing method and a measurement circuit, which are suitable for the storage scenario of ADC sampling data, and illustratively, are suitable for the storage scenario of voltage sampling data. In the embodiment of the present application, whether to compress and the appropriate degree of compression can be flexibly selected according to the system state of the electronic device, while reducing the storage pressure of the electronic device, taking into account the flexibility of data storage, and realizing the reasonable storage of ADC sampling data.

[0164] The following describes the measurement circuit provided in the embodiments of the present application and the data processing method based on the measurement circuit.

[0165] Figure 5a FIG5 is a schematic diagram of the circuit structure of another measurement circuit provided in an embodiment of the present application. Figure 4 The difference is that the measurement circuit 56 further includes a data processing unit 567 , and the data processing unit 567 can be arranged between the ADC 561 and the data buffer unit 562 .

[0166] The data processing unit 567 includes a control circuit 5671 and a compression circuit 5672. The compression circuit 5672 is located between the ADC 561 and the data buffer unit 562, and the control circuit 5671 and the compression circuit 5672 are in communication connection.

[0167] To reduce the number of interfaces, in some embodiments, see Figure 5b ,and Figure 5a The difference is that the measurement circuit 56 only includes the first transmission interface 564, and the data storage unit 565 is connected to the first transmission interface 564. When the sampled data needs to be transmitted in real time, the sampled data can be transmitted to the external device in real time through the first transmission interface 564; when the sampled data is transmitted in batches, the sampled data can be first stored in the data storage unit 565, and then transmitted to the external device through the first transmission interface 564, that is, the real-time transmission of the sampled data and the batch transmission of the sampled data can be realized through one first transmission interface 564, reducing the number of interfaces.

[0168] The control circuit 5671 is used to select a suitable data processing scheme according to the system state of the electronic device (such as a mobile phone), wherein the system state may be the operating state of the electronic device system (hereinafter referred to as the state of the electronic device).

[0169] Exemplarily, the system state may include at least one of the following states: an active state, a standby state, an abnormal state, and a laboratory test state. Among them, the active state may refer to an operating state in which the system is processing more tasks, such as an operating state of an electronic device when it is running at least one application at the same time. The standby state may refer to an operating state in which the system has no tasks being processed, or has fewer tasks being processed. The abnormal state may be a state in which the electronic device confirms that a device related to the sampled data has an abnormality (or failure), wherein the abnormality (or failure) of the device related to the sampled data may be an abnormality (or failure) of the measurement circuit 56; or an abnormality (or failure) of the module to be detected. The laboratory test state refers to the state of preliminary test verification of the electronic device before it leaves the factory.

[0170] In one example, for the active state and the standby state, it can be a comprehensive decision made by the processor 51 and notified to the control circuit 5671. For example, the processor 51 can determine whether the electronic device is in the active state or the standby state according to the number of tasks running. Alternatively, if the active state can be divided into multiple levels, the processor 51 can also determine the specific level of the active state. For example, when the number of running tasks is 2, the processor 51 determines it as the first level active state; when the number of running tasks is 3, the processor 51 determines it as the second level active state. Similarly, if the standby state can also be divided into multiple levels, the processor 51 can also determine the specific level of the standby state. It should be noted that the processor 51 can also determine the system state based on other operating parameters of the system, such as system energy consumption, and there is no specific restriction on this. It should also be noted that the number of levels of the active state and the number of levels of the standby state can be set according to the specific situation and actual scenario, and there is no specific restriction on this.

[0171] In another example, for the laboratory test state, it may be that in the laboratory test phase, the processor 51 may determine that the system state is the laboratory test state according to the configuration parameters in the processor 51 by the operator.

[0172] In another example, when the processor 51 determines that the device related to the sampled data is abnormal (or faulty), it can confirm that the electronic device is in an abnormal state. For example, when the processor 51 determines that the measurement circuit 56 (such as a measurement chip) is abnormal (or faulty), it can confirm that the electronic device is in an abnormal state. For another example, when it is determined that the module to be detected in the electronic device is abnormal (or faulty), it can confirm that the electronic device is in an abnormal state.

[0173] It should be noted that the four states of active state, standby state, abnormal state, and laboratory test state are merely examples of the present application and do not constitute a limitation of the present application. Those skilled in the art can define different system states according to actual conditions and then select different data processing schemes (i.e., compression methods).

[0174] The control circuit 5671 may pre-store a correspondence between the state of the electronic device and the compression method, that is, different states of the electronic device correspond to different compression methods.

[0175] The system state of the electronic device may be represented by a preset state value. For example, the preset state value may be a binary value. For example, if the number of bits of the binary value is Q, then at most 2 Q different system states. Wherein, Q is an integer greater than or equal to 1. For example, if the number of bits of the binary value is 2, it can include 4 preset state values ​​of "00", "01", "10", and "11". The 4 preset state values ​​of "00", "01", "10", and "11" can represent four system states of the electronic device. For example, "01" corresponds to the standby state, "10" corresponds to the active state, "00" corresponds to the abnormal state, and "11" corresponds to the laboratory test state. Optionally, different numerical values ​​can also be used to represent different levels of activity of the same system state of the electronic device. For example, "10" is used to represent the first-level active state, and "11" is used to represent the second-level active state. The compression method may include, for example, a method of not compressing the sampled data, a method of lossless compression of the sampled data, and a method of lossy compression of the sampled data. The compression method can be characterized by the control parameters of the preset data processing scheme. Among them, the control parameters of the preset data processing scheme can be the parameters of the control circuit 5671 controlling the compression circuit 5672 to compress the sampled data, that is, the compression circuit 5672 does not compress or compresses the sampled data based on the control parameter and the degree of compression. Exemplarily, the control parameter may include one or more of a compression state value, a size of a data block, and a compression bit. In some embodiments, the control parameter may also include an alignment state value for characterizing whether byte alignment is required. The compression state value may be used to characterize whether compression is required, or may indicate whether compression is required and the degree of compression. The size of a data block may be the number of sampled data in a data block. The compression bit may be the data length (or number of bits) after the sampled data is compressed.

[0176] It should be noted that the types of control parameters in different preset data processing schemes may be the same or different. For example, the control parameters of the preset data processing scheme that does not perform data compression may not include the number of compressed bits. For another example, the control parameters of the preset data processing scheme for lossy compression may not include the alignment state value. And, it should also be noted that the control parameters in different preset data processing schemes are at least partially different. For example, the control parameters of the preset data processing scheme for lossy compression and the control parameters of the preset data processing scheme for lossless compression have the same data block size, but different compression bits. In other words, the correspondence between the state of the electronic device pre-stored in the control circuit 5671 and the compression method can be the correspondence between the preset state value and the control parameter of the preset data processing scheme, that is, a preset state value can correspond to the control parameter of a preset data processing scheme. Among them, a preset state value corresponds to a preset data processing scheme, and a preset data processing scheme corresponds to a control parameter.

[0177] Exemplarily, the correspondence may include: a one-to-one correspondence between a plurality of preset state values ​​and a plurality of control parameters of preset data processing schemes. Figure 6a The following is a flow chart of an exemplary data processing method provided in the embodiment of the present application. Figure 6a As shown, a corresponding relationship 601 (i.e., a one-to-one corresponding relationship) may be stored in the control circuit 5671. Specifically, in the corresponding relationship 601, the preset state value 1 (also referred to as the first preset state value) may correspond to the control parameter 1 (i.e., the control parameter of the preset data processing scheme 1), the preset state value 2 (also referred to as the second preset state value) may correspond to the control parameter 2 (i.e., the control parameter of the preset data processing scheme 2), the preset state value 3 (also referred to as the third preset state value) may correspond to the control parameter 3 (i.e., the control parameter of the preset data processing scheme 3), and the preset state value 4 may correspond to the control parameter 4 (i.e., the control parameter of the preset data processing scheme 4).

[0178] In another exemplary embodiment, the correspondence may include a many-to-one correspondence between at least two preset state values ​​and a control parameter of a preset data processing solution. Figure 6b A flowchart of another exemplary data processing method provided in an embodiment of the present application. Figure 6b As shown, a corresponding relationship 602 (i.e., a many-to-one corresponding relationship) may be stored in the control circuit 5671. Specifically, in the corresponding relationship 601, the preset state value 1 and the preset state value 2 may correspond to the control parameter 1 (i.e., the control parameter of the preset data processing scheme 1) at the same time, and the preset state value 3 and the preset state value 4 may correspond to the control parameter 2 (i.e., the control parameter of the preset data processing scheme 2) at the same time.

[0179] Optionally, the correspondence between the state of the electronic device and the compression method pre-stored in the control circuit 5671 may also be a correspondence between a preset state value and a preset data processing scheme. It should be noted that this correspondence is similar to the correspondence between the preset state value and the control parameter, and reference may be made to the relevant description of the above-mentioned part of the embodiment of the present application, which will not be described in detail.

[0180] The control circuit 5671 can be communicatively connected with the processor 51 and the compression circuit 5672 respectively. Specifically, the processor 51 can determine the current system state of the electronic device (referred to as the current state of the electronic device for short), and send the current state value (such as "10") used to characterize the current system state to the control circuit 5671. After receiving the current state value sent by the processor 51, the control circuit 5671 can determine the control parameters of the target data processing scheme corresponding to the current state value (hereinafter referred to as the target control parameters for simplicity of description) based on the correspondence between the preset state value and the control parameters of the preset data processing scheme (or the correspondence between the preset state value and the preset data processing scheme). Then, the target control parameters are sent to the compression circuit 5672. For example, continue to refer to Figure 6a , if the current state value is the preset state value 2, then after receiving the current state value, the control circuit 5671 can determine that the control parameter 2 corresponding to the preset state value 2 is the target control parameter based on the corresponding relationship 601 (correspondingly, the preset data processing scheme 2 is the target data processing scheme). Then the control parameter 2 is sent to the compression circuit 5672, so that the compression circuit 5672 can process the sampled data according to the preset data processing scheme 2 to obtain the data to be stored, which can be uncompressed data or compressed data. When the data to be stored is compressed data, the compressed data can be the corresponding data after lossless compression or the data after lossy compression, wherein the specific introduction of the corresponding data after lossless compression and the data after lossy compression can be found below and will not be repeated here.

[0181] The compression circuit 5672 can process the sampled data according to the target data processing scheme to obtain the data to be stored. In the embodiment of the present application, one sampled data can correspond to one data to be stored. Specifically, the compression circuit 5672 can be connected to the data cache unit 562 for communication, and the processed data to be stored is sent to the data cache unit 562 for caching. Then it is sent to the data storage unit 565 for storage, and when one or more of the conditions 1-condition 4 in the above content are met, it is output through the second transmission interface 566; or, it is directly output through the first transmission interface 564.

[0182] For example, Figure 7A schematic diagram of a processing flow of a compression circuit provided in an embodiment of the present application. Figure 7 As shown, after 3N sample data E1 to E3N are input into the compression processing unit 5672, the compression circuit 5672 can process them into three data blocks F1 to F3. Each data block can be composed of N data to be stored. For example, Figure 8 A schematic diagram of an exemplary data block provided in an embodiment of the present application. Figure 8 As shown, data block F1 may include data to be stored F11 (data to be stored obtained by processing the first sample data E1) to data to be stored F1N (data to be stored obtained by processing the Nth sample data EN). Data block F2 may include data to be stored FN+1 (data to be stored obtained by processing the N+1th sample data EN+1) to data to be stored F2N (data to be stored obtained by processing the 2Nth sample data 1). Data block F3 may include data to be stored F2N+1 (data to be stored obtained by processing the 2N+1th sample data E2N+1) to data to be stored F3N (data to be stored obtained by processing the 3Nth sample data E3N). It should be noted that if block division is not performed, when processing a certain sample data in the middle, all the previous sample data need to be read. In the embodiment of the present application, by block division processing, that is, by merging the data to be stored into data blocks for transmission and storage, only the sample data of the current data block can be read, which reduces the processing difficulty and reduces the probability of data processing abnormality. It should be noted that, depending on actual needs and specific scenarios, block processing may not be performed, and there is no restriction on this.

[0183] After a preliminary introduction to the control circuit 5671 and the compression circuit 5672 involved in the embodiment of the present application, the embodiment of the present application first describes the preset data processing scheme in conjunction with the accompanying drawings.

[0184] The preset data processing scheme 1 is a data processing scheme that does not compress the sampled data. In other words, the original value of the sampled data can be used as a data processing method for the data to be stored. For example, Fig. 9 A schematic diagram of an exemplary data block provided by an embodiment of the present application is shown. In which, x represents the uncompressed original value, and 0 is the padded value. Fig. 9As shown, the first data block F1a may include N data to be stored F11a to F1Na, and the second data block F2a may include N data to be stored F21a to F2Na, ... Each data block has the same data structure. Specifically, each data to be stored may include the original value of 14 bits of sampled data. Among them, the 2 bits of 0 in each data to be stored are used to byte-align the data to be stored, so that the data to be stored after byte alignment is 2 bytes, which is convenient for processing the data to be stored. It should be noted that, in order to save storage space, the data to be stored may not be byte-aligned, and there is no restriction on this. It should also be noted that in the data processing scheme where the sampled data is not compressed, the sampled data can be directly output instead of being output in the form of data blocks.

[0185] For example, Fig.10 FIG. 1 shows a logic diagram of an exemplary data processing provided by an embodiment of the present application. Fig.10 As shown, after receiving the sampled data 1001 sent by ADC561, the compression circuit 5672 can execute process ① under the control of the control circuit 5671, that is, the sampled data is not compressed, and the data to be stored including the sampled data is generated and then output. It should be noted that in this data processing scheme, taking the ADC bit number of 14 bits and each data block including N data to be stored as an example, a data block requires N*16 bits (each sampled data is byte padded with 2 bits) of storage space.

[0186] Exemplarily, the compression circuit 5672 may be in a bypass state and not perform compression processing on the sampled data.

[0187] The preset data processing scheme 2 is a data scheme for losslessly compressing the sampled data, that is, a compression scheme that does not affect the accuracy of the sampled data. The data to be stored can be restored to compressed data by decompression in a subsequent process.

[0188] In an embodiment of the present application, the inventor provides a block-based differential information compression scheme, that is, a compression scheme that uses the difference between sampled data and reference sampled data as the data to be stored. The reference sampled data may be the previous sampled data of the sampled data, the first sampled data of the data block, or a preset reference value.

[0189] For the difference in lossless compression, its maximum bit position may be related to the signal frequency f of the analog signal, the maximum amplitude A of the analog signal, the sampling rate k of ADC51, the reference voltage of ADC51, and the number of ADC bits.

[0190] Specifically, the maximum bit position can satisfy the following formula (1):

[0191]

[0192] Among them, Lmax represents the maximum bit, that is, the maximum length of the difference calculated using the lossless compression algorithm. Function represents rounding up. f represents the signal frequency of the analog signal. A represents the maximum amplitude of the analog signal. k represents the sampling rate of ADC51. Vref represents the reference voltage of ADC51. P represents the number of bits of ADC51.

[0193] Taking f as 100Hz, A as 1.2V, and k as 100Ksps as an example, the maximum change of the measured voltage in one second, that is, the first signal change SR = 2π*100Hz*1.2V = 754V / s (volts / second), that is, the maximum change of the measured voltage in 1S is 754V. Correspondingly, the maximum change of the measured voltage between adjacent sampling points of ADC51 is 754 / 100K = 0.0075V, that is, the maximum change of the measured voltage between adjacent sampling points does not exceed 0.0075V. And, the minimum resolution of ADC51 can be 1.2V / 2 14 =0.000073V, that is, one bit of the ADC digital signal can represent 0.000073V. Then Lmax is equal to the rounded value of log0.0075V / 0.000073V, that is, Lmax is equal to 7, that is, a 7-bit binary string is required to represent the difference calculated by the lossless compression algorithm.

[0194] For example, Fig.11 FIG. 2 shows another exemplary data block provided in an embodiment of the present application. Wherein, d represents the compressed value after compression. Fig.11 As shown, the first data block F1b may include N data to be stored F11b to F1Nb, and the second data block F2b may include N data to be stored F21b to F2Nb, ... Taking the first data block F1b as an example, the first data to be stored F11b in the first data block F1b may include the 14-bit original value of the first sampled data. Except for the first data to be stored F11b, the remaining data to be stored may be a compressed value of 7 bits (i.e., Lmax calculated according to formula (1) above), for example, Fig.11 The data to be stored F21b and F22b in the data block may be a 7-bit data. It should be noted that each data block has the same data structure, and the specific data structures of other data blocks can refer to the above description of the first data block F1b, which will not be repeated here.

[0195] In one embodiment, for a single data block, the difference between the i-th sampled data and the i-1-th sampled data in the data block can be used as the i-th data to be stored, where i is any integer greater than or equal to 2 and less than or equal to N. The first sampled data in the data block can be directly used as the first data to be stored in the data block.

[0196] Figure 12a-12b FIG. 2 shows another exemplary logic diagram of data processing provided by an embodiment of the present application. Fig.12a As shown, after receiving the first sampled data 1201 of the data block sent by ADC561, the compression circuit 5672 can execute process ① under the control of the control circuit 5671, and the compression circuit 5672 does not compress the first sampled data 1201, generates the data to be stored including the first sampled data and then outputs it. And the compression circuit 5672 executes process ②, and stores the first sampled data 1201 as the cache value T in the cache area of ​​the compression circuit 5672.

[0197] And, if Figure 12b As shown, after receiving the second sampled data 1202 of the data block sent by ADC561, the compression circuit 5672 can execute process ① under the control of the control circuit 5671, and the compression circuit 5672 obtains the cache value T (i.e., the first sampled data 1201) from the cache area. Then, the compression circuit 5672 continues to execute process ②, calculates the difference 1203 between the second sampled data 1202 and the first sampled data 1201, and outputs the difference 1203 as the second data to be stored. In addition, the compression circuit 5672 also executes process ③, stores the second sampled data 1202 as the cache value T in the cache area of ​​the compression circuit 5672, so as to determine the third data to be stored according to the difference between the third sampled data and the second sampled data in the subsequent process.

[0198] Similarly, for subsequent sampled data of a single data block, the difference between the sampled data and T in the cache (the previous sampled data cached in the last calculation process) can be calculated and used as the data to be stored. In addition, the sampled data is stored in the cache area as a cache value to perform the calculation of the next data to be stored.

[0199] It should be noted that in this data processing solution, taking the ADC bit number as 14 bits, each data block including N data to be stored, and Lmax as 7 as an example, a data block requires (7N+7) bits of storage space. Compared with 16N bits of uncompressed storage, the storage capacity is reduced by (9N-7) bits, reducing the storage pressure of electronic devices.

[0200] Also, it should be noted that in this data processing method, since the analog signal is continuous, the voltage change between adjacent sampling points is often small. Therefore, the difference calculated using the voltage change between adjacent sampling points is also small, thereby further saving storage space while ensuring lossless compression accuracy.

[0201] It should be noted that when performing lossless compression, the bit position can select the maximum bit position Lmax. Of course, the bit position that is smaller than the bit position of the original data and larger than the maximum bit position can also be selected. In this way, the compression accuracy can also be guaranteed.

[0202] In another embodiment, for a single data block, the difference between the i-th sampled data and the first sampled data can be used as the i-th data to be stored, wherein the first sampled data in the data block can be directly used as the first data to be stored in the data block.

[0203] In this storage mode, the maximum bit position Lmax of the i-th sample data satisfies the following formula (2):

[0204]

[0205] In another embodiment, for a single data block, the i-th sampled data and the preset reference value can be used as the i-th data to be stored. The first sampled data in the data block can be directly used as the first data to be stored in the data block. Exemplarily, the reference value can be a digital value of the voltage average value over a period of time, or can be an empirical value, or can be other values, which are not specifically limited.

[0206] The preset data processing scheme 3 is a data scheme for lossy compression of the sampled data, that is, a compression scheme that can appropriately reduce the data accuracy in order to further reduce the bit. Exemplarily, the data length (corresponding bit) of the lossy compressed data to be stored is less than the data length (corresponding bit) of the lossless compressed data to be stored.

[0207] In an embodiment of the present application, after obtaining the difference calculated by the lossless compression scheme, one or more data at the end of the difference can be discarded to obtain the data to be stored. For example, if the difference calculated by the lossless compression is 7 bits, the last 2 bits are discarded to obtain 5 bits of data to be stored. Fig.13 A schematic diagram of another exemplary data block provided in an embodiment of the present application is shown. Fig.13 and Fig.11The difference is that, except for the first data to be stored (such as the data F11c and F21c to be stored), the remaining data to be stored can be the compressed value of 5 bits (such as other data to be stored in data blocks F1c and F2c), for example, Fig.13 The data to be stored F21c and F22c may be 5-bit data.

[0208] For example, Fig.14 A logical schematic diagram of another exemplary data processing provided in an embodiment of the present application is shown. Fig.14 The difference from FIG. 12 is that the compression circuit 5672 further executes process ④, discarding the last two bits of the difference 1203 to obtain the data 1204 to be stored.

[0209] It should be noted that in this data processing solution, taking the ADC bit number as 14 bits, each data block including N data to be stored, and Lmax as 7 as an example, a data block requires (5N+9) bits of storage space. Compared with 16N bits of uncompressed storage, the storage capacity is reduced by (11N-9) bits, reducing the storage pressure of electronic devices.

[0210] Optionally, for a single data block, one or more data at the end of the i-th sampled data are discarded to obtain a first data to be processed. One or more data at the end of a preset reference value are discarded to obtain a second data to be processed. The first data to be processed and the second data to be processed are used as the i-th data to be stored.

[0211] After introducing the above preset data processing solutions, the application scenarios corresponding to each preset data processing solution are described next.

[0212] In an exemplary scenario, when the mobile phone system does not need to save storage space or requires uncompressed sampled data, such as in the early test and verification process before the electronic device leaves the factory, when the tester does not pay attention to the storage pressure of the electronic device, the compression circuit 5672 can adopt the above-mentioned preset data processing scheme 1 and does not compress the sampled data. Also, when the power consumption of the processor 51 is not concerned, the sampled data can be transmitted in real time through the first transmission interface 564.

[0213] In another exemplary scenario, when a device related to the sampled data is abnormal (or fails), in order to quickly analyze the sampled data, the compression circuit 5672 can adopt the above-mentioned preset data processing scheme 1 and not compress the sampled data. Also, when the power consumption of the processor 51 is not a concern, the sampled data can be transmitted to the processor 51 in real time through the first transmission interface 564, so that the processor 51 can analyze the problem of the sampled data.

[0214] In another exemplary scenario, when the user is using the mobile phone to play games, watch videos, take photos and other tasks, the mobile phone system is in the active state. If space needs to be saved, the compression circuit 5672 can use the above-mentioned preset data processing scheme 2 to losslessly compress the sampled data under the control of the control circuit 5671, so that the length of the compressed data to be stored can be equal to Lmax. Therefore, when the mobile phone is in the active state, the storage space can be saved while ensuring the measurement accuracy of the measured voltage.

[0215] In another embodiment, when the electronic device is in standby mode, in order to further save storage space, the compression circuit 5672 can, under the control of the control circuit 5671, use the above-mentioned preset data processing scheme 3 to perform lossy compression on the sampled data, so that the length of the compressed data to be stored can be less than Lmax. It should be noted that, although lossy compression has the risk of loss of measurement accuracy, that is, part of the measurement accuracy may be lost, but because the electronic device does not fluctuate much when it is in standby mode, the electronic device does not have high requirements for the measurement accuracy of the measured voltage, and can further save storage space while meeting the accuracy requirements of the electronic device for the test voltage (i.e., the sampled data).

[0216] After introducing the application scenarios corresponding to the preset data processing solutions, the data processing method provided in the embodiments of the present application will be described below.

[0217] Fig.15 A flow chart of a data processing method provided in an embodiment of the present application. Fig.15 As shown, the data processing method may include:

[0218] S1501, ADC starts measuring and obtains a plurality of sampling data.

[0219] For example, the ADC can measure the voltage of the module to be detected to obtain a plurality of sampling data in a digital signal format. For example, if the ADC bit number is 14 bits, the data length of one sampling data is 14 bits.

[0220] It should be noted that before S1501, one of the multiple compression modes of the compression circuit 5672 can be set in advance as the default compression mode, that is, when the ADC starts measuring and obtains multiple sampled data, the compression circuit 5672 can process the sampled data in the default compression mode. Among them, the default compression mode can be one of no compression, lossy compression and lossless compression. In the subsequent steps, the compression mode of the compression circuit 5672 can be changed according to the control of the control circuit 5671, that is, the default compression mode is changed to the compression mode corresponding to the current state of the electronic device. Exemplarily, the default compression mode is no compression, and the compression mode corresponding to the current state of the electronic device is lossless compression, then the compression mode of the compression circuit 5672 is changed from no compression to lossless compression.

[0221] S1502, the control circuit sends control parameters according to the system status.

[0222] Exemplarily, the processor can comprehensively determine the current system state of the electronic device, and send the current state value used to characterize the current system state to the control circuit to notify the control circuit of the current system state of the electronic device. After the control circuit receives the current state value, it can determine the target control parameter corresponding to the current state value based on the correspondence between the preset state value and the control parameter, and send the target control parameter to the compression circuit. Among them, the corresponding relationship and control parameters can refer to the relevant description of the above part of the embodiment of the present application, which will not be repeated here.

[0223] S1503, the compression circuit selects a processing scheme according to the control parameters. If no compression is selected, S1504a can be executed. If the number of compressed bits is greater than or equal to the maximum bit Lmax, S1504b can be executed. If the number of compressed bits is less than the maximum bit Lmax, S1504c can be executed.

[0224] Exemplarily, if the compression circuit determines that the compression state value in the target control parameter is the first state value representing non-compression, it may be determined to execute the non-compression data processing solution, that is, S1504a may continue to be executed.

[0225] In another exemplary embodiment, if the compression circuit determines that the number of compressed bits in the target control parameter is greater than or equal to the maximum bit Lmax, then a data processing scheme for performing lossless compression can be determined, that is, S1504a can be continued. For lossless compression, please refer to the relevant description of the preset data processing scheme 2 in the embodiment of the present application, and no further details will be given for this.

[0226] Optionally, when the active state of the system can be divided into multiple levels, different levels of active states can correspond to different numbers of compressed bits. Among them, when the level of the active state is proportional to the number of its tasks, the higher the level of the active state, the lower the number of compressed bits, but the number of compressed bits of the active state of each level is greater than or equal to the maximum bit Lmax. For example, for the first level active state, the second level active state, and the third level active state, the number of compressed bits in the corresponding control parameters can be 9 bits, 8 bits, and 7 bits, respectively.

[0227] In another exemplary embodiment, if the compression circuit determines that the number of compressed bits in the target control parameter is less than the maximum bit Lmax, it can determine to perform a data processing scheme for lossy compression, that is, it can continue to execute S1504a. Among them, lossless compression can refer to the relevant description of the preset data processing scheme 3 in the embodiment of the present application, and no specific details are given for this.

[0228] Optionally, when the standby state of the system can be divided into multiple levels, different levels of standby states can correspond to different numbers of compressed bits. Among them, when the level of the standby state is inversely proportional to the number of its tasks, the higher the level of the standby state, the lower the number of compressed bits, but the number of compressed bits of each level of the standby state is less than the maximum bit Lmax. For example, for the first level standby state, the second level standby state, and the third level standby state, the number of compressed bits in the corresponding control parameters can be 6 bits (discarding 1 bit of data), 5 bits (discarding 2 bits of data), and 4 bits (discarding 3 bits of data), respectively.

[0229] In some embodiments, the default state of the compression circuit can be configured to not perform data compression. That is, before receiving the control parameter, the compression circuit can process the sampled data according to the preset data processing scheme 1. And after receiving the target state parameter, the sampled data is processed according to the data processing scheme corresponding to the target state parameter.

[0230] S1504a: The compression circuit does not compress the sampled data.

[0231] For example, the compression circuit can be in a bypass state, outputting the sampled data as the data to be stored, or byte-aligning the sampled data and outputting the byte-aligned sampled data as the data to be stored. It should be noted that the specific method of not compressing can refer to the above part of the embodiment of the present application in combination with Fig. 9 and Fig.10 The relevant description of the preset data processing scheme 1 is not elaborated in detail.

[0232] For example, after acquiring the current sampled data, the compression circuit can determine whether the data volume of the current data block reaches a preset quantity threshold (i.e., the size of the database). If the preset quantity threshold is not reached, the current sampled data is merged with the existing sampled data of the current data block. If the preset quantity threshold is reached, the compression circuit sends the current data block to the target memory, and uses the current sampled data as the first data to be stored in the next data block. The preset quantity threshold N can be set according to the actual scenario and specific situation, and no specific limitation is made to this.

[0233] S1504b, the compression circuit performs lossless compression on the sampled data.

[0234] In some embodiments, Fig.16 A schematic diagram of an exemplary lossy compression process provided in an embodiment of the present application is shown in FIG. Fig.16 As shown, S1504b may include the following steps:

[0235] S1601, the compression circuit receives current sampling data.

[0236] S1602, the compression circuit determines whether the current sampled data is the first data of the current data block. If the determination result is yes, execute S1603a. If the determination result is no, execute S1603b.

[0237] Exemplarily, the compression circuit can determine whether the current sampled data is the first data of the data block according to the sequence number of the current sampled data and the size N of the data block. In one example, if the sequence number of the current sampled data is r*N+1, the current sampled data is the first data of the r-1th data block. Wherein, r is an integer greater than or equal to 0. For example, if the size of the data block is 100, the current sampled data with sequence numbers 1, 101, and 201 are the first data of the first data block, the first data of the second data block, and the first data of the third data block, respectively.

[0238] S1603a, if the current sampled data is the first data, the compression circuit uses the current sampled data as the cache value T. Then the current sampled data is used as the data to be stored, and S1605 is continued.

[0239] S1603b, if the current sampled data is not the first data, the compression circuit calculates the difference d between the current sampled data and the cache value T. Exemplarily, the data length of the difference d can be adjusted to the number of compressed bits, and then the difference d after the length adjustment is used as the data to be stored. Then jump to execute S1604 and S1605.

[0240] S1604: Use the current sampled data to update the cache value T. That is, update the cache value T in the cache area to the current sampled data.

[0241] S1605, the compression circuit writes into the byte merging area and merges bytes, so as to merge the data to be stored with the existing data of the current data block in the byte merging area, and then jumps to execute S1606.

[0242] It should be noted that the merged data block can be Fig.11 As shown, no further elaboration is given.

[0243] S1606, the compression circuit writes the data byte by byte into the target memory.

[0244] Exemplarily, after the current data block is fully written, the compression circuit may write the data block into the target memory.

[0245] It should be noted that the specific implementation of lossless compression can refer to the above-mentioned part of the embodiment of this application combined with Fig.11 , Figure 12a-12b The description of the preset data processing scheme 2 is not elaborated in detail.

[0246] After introducing S1504b through S1601 to S1606, S1504c will be described next.

[0247] S1504c, the compression circuit performs lossy compression on the sampled data. Exemplarily, the difference from S1504b is that after obtaining the difference d, one or more bits at the end of the difference d can be discarded, so that the data length of the difference d after the data is discarded is equal to the number of compressed bits. For example, taking the difference d length as 7 bits, if the number of compressed bits is 6 bits, one bit at the end of the difference d is discarded, so that the data length of the difference d (data to be stored) after the data is discarded is equal to 6 bits.

[0248] It should be noted that the specific implementation of lossy compression can refer to the above-mentioned part of the embodiment of this application combined with Fig.11 , Figure 12a-12b The description of the preset data processing scheme 2 is not elaborated in detail.

[0249] S1505, the compression circuit outputs the data to be stored, so as to write the data to be stored (such as a data block formed by a plurality of data to be stored) into the target memory.

[0250] The target memory may be a storage module where the data to be stored (or sampled data) is stored, and the target memory may be a memory of the processor 51, an internal memory of an electronic device, an external memory of an electronic device, etc., without limitation.

[0251] Exemplarily, in S1505, the compression circuit may store the data to be stored (e.g., a data block formed by a plurality of data to be stored) in a storage area of ​​the target memory. Exemplarily, the data to be stored (e.g., a data block formed by a plurality of data to be stored) may be stored in a storage area of ​​a DDR chip of the mobile phone.

[0252] It is understandable that, in order to realize the above functions, the electronic device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.

[0253] In one example, Fig.17 A schematic block diagram of a device 600 according to an embodiment of the present application is shown. The device 600 may include: a processor 601 and a transceiver / transceiver pin 602 , and optionally, a memory 603 .

[0254] The components of the device 600 are coupled together via a bus 604, wherein the bus 604 includes a power bus, a control bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, all buses are referred to as bus 604 in the figure.

[0255] Optionally, the memory 603 may be used for the instructions in the aforementioned method embodiment. The processor 601 may be used to execute the instructions in the memory 603, and control the receiving pin to receive a signal, and control the sending pin to send a signal.

[0256] The apparatus 600 may be the electronic device or a chip of the electronic device in the above method embodiment.

[0257] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0258] The steps performed by the electronic device 100 in the data processing method provided in the above embodiment of the present application may also be performed by a chip system included in the electronic device 100, wherein the chip system may include a processor and a Bluetooth chip. The chip system may be coupled to a memory so that the chip system calls a computer program stored in the memory when it is running to implement the steps performed by the above electronic device 100. The processor in the chip system may be an application processor or a processor other than an application processor.

[0259] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing method, characterized in that, applied to an electronic device, the electronic device includes an analog-to-digital converter, and includes: Obtain the sampling data collected by the analog-to-digital converter, and obtain the current state of the electronic device; Based on the correspondence between the state of the electronic device and the compression method, process the sampling data according to the compression method corresponding to the current state of the electronic device; Wherein, processing the sampling data according to the compression method corresponding to the current state of the electronic device includes: Determine that the current state of the electronic device is the first state, and compress the sampling data in a first compression method, the first state includes the state where the electronic device runs at least one application or task, and the first compression method includes a lossless compression method; Determine that the current state of the electronic device is the second state, and compress the sampling data in a second compression method, the second state includes the standby state of the electronic device, and the second compression method includes a lossy compression method.

2. The data processing method according to claim 1, characterized in that, Processing the sampling data according to the compression method corresponding to the current state of the electronic device further includes: Determine that the current state of the electronic device is the third state, and output the sampling data.

3. The data processing method according to claim 1, characterized in that, Determine that the current state of the electronic device is the first state, and compress the sampling data in a first compression method, including: Determine that the current state of the electronic device is the first state, and the sampling data is the first sampling data. For the i-th sampling data after the first sampling data, calculate the difference between the i-th sampling data and the (i - 1)-th sampling data, where i is greater than or equal to 1; Compress the difference between the i-th sampling data and the (i - 1)-th sampling data according to the maximum number of bits, wherein the maximum number of bits is less than the number of bits of the first sampling data.

4. The data processing method according to claim 3, characterized in that, After compressing the difference between the i-th sampling data and the (i - 1)-th sampling data according to the maximum number of bits, further includes: When it is determined that the number of compressed sampling data exceeds a preset number, use the next sampling data as the first sampling data and repeat the steps of calculating the difference between the i-th sampling data and the (i - 1)-th sampling data after the first sampling data, and compressing the difference between the i-th sampling data and the (i - 1)-th sampling data according to the maximum number of bits.

5. The data processing method according to claim 1, characterized in that, Determine that the current state of the electronic device is the second state, and compress the sampling data in a second compression method, including: Determine that the current state of the electronic device is the second state, and the sampling data is the first sampling data. For the i-th sampling data after the first sampling data, calculate the difference between the i-th sampling data and the (i - 1)-th sampling data, where i is greater than or equal to 1; Compress the difference between the i-th sampled data and the (i - 1)-th sampled data according to a preset number of bits, where the preset number of bits is less than the maximum number of bits, and the maximum number of bits is less than the number of bits of the first sampled data.

6. The data processing method according to claim 5, wherein, after compressing the difference between the i-th sampled data and the (i - 1)-th sampled data according to the preset number of bits, further comprising: when it is determined that the number of compressed sampled data exceeds a preset number, taking the next sampled data as the first sampled data and repeating the steps of calculating the difference between the i-th sampled data after the first sampled data and the (i - 1)-th sampled data, and compressing the difference between the i-th sampled data and the (i - 1)-th sampled data according to the preset number of bits.

7. The data processing method according to claim 3 or 5, wherein, the maximum number of bits Lmax satisfies: Among them, represents the ceiling function, f is the signal frequency of the analog signal corresponding to the sampled data, A is the maximum amplitude of the analog signal, k is the sampling rate of the analog-to-digital converter, Vref is the reference voltage of the analog-to-digital converter, and P is the number of bits of the analog-to-digital converter.

8. The data processing method according to claim 1, wherein, the first state includes a plurality of first sub-states, the first compression method includes a plurality of first compression sub-methods, and the plurality of first sub-states correspond to the plurality of first compression sub-methods one by one; determining that the current state of the electronic device is the first state and compressing the sampled data in the first compression method includes: determining that the current state of the electronic device is the target first sub-method, and compressing the sampled data in the first compression sub-method corresponding to the target first sub-method, where the target first sub-method is one of the plurality of first sub-states.

9. The data processing method according to claim 1, wherein, the second state includes a plurality of second sub-states, the second compression method includes a plurality of second compression sub-methods, and the plurality of second sub-states correspond to the plurality of second compression sub-methods one by one; determining that the current state of the electronic device is the second state and compressing the sampled data in the second compression method includes: determining that the current state of the electronic device is the target second sub-method, and compressing the sampled data in the second compression sub-method corresponding to the target second sub-method, where the target second sub-method is one of the plurality of second sub-states.

10. A measurement circuit, wherein, the measurement circuit is disposed in an electronic device, and the measurement circuit includes an analog-to-digital converter, a control circuit, and a compression circuit; the control circuit is configured to obtain the current state of the electronic device and send a control signal to the compression circuit based on the correspondence between the state of the electronic device and the compression method; the compression circuit is configured to process the sampled data acquired by the analog-to-digital converter according to the control signal in a preset compression method, where the preset compression method is the compression method corresponding to the current state of the electronic device; The current state of the electronic device is the first state, and the compression circuit is used to compress the sampled data in a first compression manner. The first state includes the state where the electronic device runs at least one application or task, and the first compression manner includes a lossless compression manner; The current state of the electronic device is the second state, and the compression circuit is used to compress the sampled data in a second compression manner. The second state includes the standby state of the electronic device, and the second compression manner includes a lossy compression manner.

11. The measurement circuit according to claim 10, wherein, The current state of the electronic device is the third state, and the compression circuit is further used to directly output the sampled data.

12. The measurement circuit according to claim 10, wherein, The current state of the electronic device is the first state, and the compression circuit is used to, when the sampled data is the first sampled data, calculate the difference between the i-th sampled data and the (i - 1)-th sampled data for the i-th sampled data after the first sampled data, where i is greater than or equal to 1; and compress the difference between the i-th sampled data and the (i - 1)-th sampled data according to the maximum bit position, and the maximum bit position is less than the bit position of the first sampled data.

13. The measurement circuit according to claim 12, wherein, The compression circuit is further used to: when it is determined that the number of sampled data to be compressed exceeds a preset number, use the next sampled data as the first sampled data and repeat the steps of calculating the difference between the i-th sampled data and the (i - 1)-th sampled data for the i-th sampled data after the first sampled data, and compressing the difference between the i-th sampled data and the (i - 1)-th sampled data according to the maximum bit position.

14. The measurement circuit according to claim 10, wherein, The current state of the electronic device is the second state, and the compression circuit is used to, when the sampled data is the first sampled data, calculate the difference between the i-th sampled data and the (i - 1)-th sampled data for the i-th sampled data after the first sampled data, where i is greater than or equal to 1; and compress the difference between the i-th sampled data and the (i - 1)-th sampled data according to a preset bit position, where the preset bit position is less than the maximum bit position, and the maximum bit position is less than the bit position of the first sampled data.

15. The measurement circuit according to claim 14, wherein, The compression circuit is further used to: when it is determined that the number of sampled data to be compressed exceeds a preset number, use the next sampled data as the first sampled data and repeat the steps of calculating the difference between the i-th sampled data and the (i - 1)-th sampled data for the i-th sampled data after the first sampled data; Compressing the difference between the i-th sampled data and the (i - 1)-th sampled data according to the preset bit position.

16. The measurement circuit according to claim 12 or 14, wherein, The maximum bit position Lmax satisfies: wherein, represents a ceiling function, f is the signal frequency of the analog signal corresponding to the sampled data, A is the maximum amplitude of the analog signal, k is the sampling rate of the analog-to-digital converter, Vref is the reference voltage of the analog-to-digital converter, and P is the number of bits of the analog-to-digital converter.

17. The measurement circuit according to claim 10, wherein, The first state includes a plurality of first sub-states, and the first compression method includes a plurality of first compression sub-methods, and the plurality of first sub-states correspond to the plurality of first compression sub-methods one by one; The current state of the electronic device is the target first sub-method, and the compression circuit is configured to: compress the sampled data by using the first compression sub-method corresponding to the target first sub-method, where the target first sub-method is one of the plurality of first sub-states.

18. The measurement circuit according to claim 10, wherein, The second state includes a plurality of second sub-states, and the second compression method includes a plurality of second compression sub-methods, and the plurality of second sub-states correspond to the plurality of second compression sub-methods one by one; The current state of the electronic device is the target second sub-method, and the compression circuit is configured to: compress the sampled data by using the second compression sub-method corresponding to the target second sub-method, where the target second sub-method is one of the plurality of second sub-states.

19. An electronic device, wherein, comprising: one or more processors; one or more memories; the one or more memories store one or more programs, and when the one or more programs are executed by the one or more processors, the electronic device is caused to execute the data processing method according to any one of claims 1 to 9.

20. A computer-readable storage medium, comprising a computer program, wherein, when the computer program runs on an electronic device, the electronic device is caused to execute the data processing method according to any one of claims 1 to 9.

21. A chip, comprising one or more interface circuits and one or more processors; wherein, the interface circuit is configured to receive a signal from a memory of an electronic device and send the signal to the processor, the signal includes computer instructions stored in the memory; and when the processor executes the computer instructions, the electronic device is caused to execute the data processing method according to any one of claims 1 to 9.

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