Programmable logic controller, cpu unit, control method, and recording medium

Abstract

Each of the CPU units (310, 320, 330, 340) is capable of independently performing FA control. In the first CPU unit (310), the first output selection section (316) selects whether or not to stop the operation of the second CPU unit (320) in the case where a voltage drop of the internal power supply is detected. The first reset signal output control section (313) stops the operation of the second CPU unit (320) in the case where the first output selection section (316) selects to stop the operation, and on the other hand, does not stop the operation of the second CPU unit (320) in the case where the first output selection section (316) selects not to stop the operation.

Description

Technical Field

[0001] This invention relates to a programmable logic controller, a CPU unit, a control method, and a recording medium. Background Technology

[0002] Currently, factory automation, or FA (Factory Automation), is being implemented on the manufacturing floor. Instruments and equipment within the factory are controlled by devices such as Programmable Logic Controllers (PLCs). In control systems using such devices, it is crucial to respond quickly to anomalies to prevent a decline in production capacity.

[0003] Patent Document 1 discloses a control system in which a user, through an auxiliary device connected to a PLC, groups multiple devices controlled by the CPU (Central Processing Unit) of the PLC according to the control objective. Patent Document 1 discloses that the user can use the auxiliary device to set the operation of the remaining devices in the group to which the device that malfunctioned belongs, based on the nature of the malfunction, from "operation stop," "degraded operation," to "continue operation."

[0004] Furthermore, Patent Document 2 discloses a board processing apparatus having multiple controllers that control multiple processing blocks and a main controller that centralizes the multiple controllers. Patent Document 2 discloses that, in the event of a failure of one of the multiple controllers, the user can restart the remaining controllers by operating the main controller, thereby performing degraded operation.

[0005] Furthermore, Patent Document 3 discloses a control system in which multiple controllers capable of controlling external instruments are interconnected and can communicate with each other, with one controller instructing another controller to control the external instruments. Patent Document 3 also discloses that a PLC, motion controller, numerical controller, and robot controller are installed in a basic unit, and the PLC, if installed in a designated location, becomes the master controller.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-200731

[0007] Patent Document 2: Japanese Patent Application Publication No. 2015-156105

[0008] Patent Document 3: Japanese Patent No. 4795260 Summary of the Invention

[0009] In the control system described in Patent Document 1, when a certain device malfunctions, the remaining devices can continue to operate. However, there is a problem: if the CPU unit of the PLC malfunctions, the system cannot continue to operate even if all devices are functioning correctly.

[0010] On the other hand, the substrate processing apparatus described in Patent Document 2 is controlled by multiple controllers, so even if one controller malfunctions, it can continue to operate through the remaining controllers. However, in order to continue operating, the substrate processing apparatus described in Patent Document 2 requires restarting the remaining controllers, resulting in a temporary halt in operation. Furthermore, the substrate processing apparatus described in Patent Document 2 has the following problem: when the main controller malfunctions, it cannot continue operating even if all controllers are functioning correctly.

[0011] Furthermore, the control system described in Patent Document 3, like that in Patent Document 2, if the PLC, which acts as the main controller and performs timing control, malfunctions, the remaining controllers will stop, thus preventing the overall operation of the system from continuing. Specifically, a power monitoring IC (Integrated Circuit) installed inside the PLC detects a voltage drop in the internal power supply and outputs a reset signal to the remaining controllers installed in the basic unit. Therefore, not only does the malfunctioning PLC stop, but the remaining controllers also stop. Additionally, in the control system described in Patent Document 3, multiple controllers can control each other. Thus, similar to when a controller other than the PLC malfunctions, the malfunctioning controller outputs a reset signal to the remaining controllers, causing not only the malfunctioning controller to stop, but also the remaining controllers, including the PLC, to stop. As a result, the control system described in Patent Document 3 has the problem that when one of the multiple controllers malfunctions, the remaining controllers also stop.

[0012] The present invention was proposed in view of the above circumstances, and its purpose is to enable the selection of whether to stop or continue the operation of the whole when an abnormality occurs.

[0013] To achieve the above objectives, the programmable logic controller (PLC) of the present invention enables independent control of the instrument being controlled by a first CPU unit and a second CPU unit. The PLC includes a selection unit that, upon detecting a voltage drop in the internal power supply of the first CPU unit, selects whether to stop the operation of the second CPU unit. Furthermore, the PLC includes an operation control unit that stops the operation of the second CPU unit when the selection unit selects to stop its operation, and prevents the operation of the second CPU unit from stopping when the selection unit selects not to stop its operation.

[0014] The effects of the invention

[0015] According to the present invention, if the programmable logic controller (PLC) detects a voltage drop in the internal power supply of the first CPU unit and selects to stop the operation of the second CPU unit, then not only the first CPU unit stops operating, but the second CPU unit also stops operating, thus ceasing operation. Conversely, if the PLC detects a voltage drop in the internal power supply of the first CPU unit and selects not to stop the operation of the second CPU unit, then the second CPU unit does not stop operating, thus continuing operation. Therefore, the PLC can select between an "operation stop mode" that stops the operation of all CPU units and halts overall operation, and a "degraded operation mode" that allows the operation of CPU units that have not generated abnormalities to continue, thus continuing overall operation instead of temporarily stopping. Therefore, the PLC can choose whether to stop or continue overall operation when an abnormality occurs. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating the structure of the programmable logic controller according to Embodiment 1 of the present invention.

[0017] Figure 2 This is a block diagram illustrating the functional structure of the programmable logic controller involved in Implementation 1.

[0018] Figure 3 This is a block diagram illustrating the hardware structure of each CPU unit involved in Implementation Method 1.

[0019] Figure 4 This is a diagram showing the communication circuit for the reset signals between the units involved in Implementation Method 1.

[0020] Figure 5 This is a diagram showing the communication circuit for the reset signals between the units involved in Implementation Method 1.

[0021] Figure 6This is a block diagram illustrating the structure of the control system according to Embodiment 2 of the present invention.

[0022] Figure 7 This is a block diagram illustrating the functional structure of the control system involved in Implementation Method 2.

[0023] Figure 8 This is a diagram showing an example of the setting information involved in Implementation Method 2.

[0024] Figure 9 This is a flowchart of the first action stop selection process involved in Implementation Method 2. Detailed Implementation

[0025] Hereinafter, with reference to the accompanying drawings, the programmable logic controller, CPU unit, control method, and program involved in implementing the present invention will be described in detail. Furthermore, the same or corresponding parts in the drawings will be labeled with the same reference numerals. Also, "programmable logic controller" will be referred to as "PLC" below.

[0026] [Implementation Method 1]

[0027] (Regarding PLC 1 involved in Implementation Method 1)

[0028] The PLC 1 involved in Embodiment 1 of the present invention is as follows: Figure 1 As shown, the PLC 1 includes a basic unit 10 that houses various units. Additionally, the PLC 1 includes a power supply unit 20 that supplies power to each unit via the installed basic unit 10. Furthermore, the PLC 1 includes a CPU (Central Processing Unit) unit 30 that performs Factory Automation (FA) control via the installed basic unit 10. Finally, the PLC 1 includes an I / O (Input / Output) unit 40 that handles the input and output of control signals between the CPU unit 30 and external instruments and equipment via the installed basic unit 10.

[0029] In recent years, FA's control systems have been seeking to improve factory productivity by introducing new technologies such as IoT (Internet of Things) and big data applications to collect and analyze large amounts of data.

[0030] For example, FA's control system is seeking to go beyond traditional timing control, also collecting, analyzing, and applying operational data such as logs and image logs from network-connected instruments and devices. In particular, for the control system, by performing the aforementioned data collection control, it becomes important to collect and analyze operational data from multiple instruments and devices before and after an anomaly occurs.

[0031] Furthermore, for example, the globalization of the market for industrial products has led to increased production in multiple factories, both domestically and internationally, at greater distances. Therefore, FA's control systems also seek to achieve remote monitoring and control, enabling the confirmation of the status of instruments and equipment on the production floor from remote offices or other remote locations, allowing for detailed understanding of the situation and immediate response when malfunctions occur.

[0032] Furthermore, for example, the safety controls currently required to protect people, property, and the environment are constructed from systems different from the control system. However, this presents the problem that separate systems not only increase equipment investment costs but also increase engineering design costs due to differences in operability and separate management of procedures. Therefore, FA's control system also seeks to reduce their costs by integrating these different systems through the aforementioned safety controls.

[0033] Therefore, regarding the PLC 1 used in the FA control system, the CPU unit 30 performs FA control on external instruments and equipment, such as timing control, data collection control, remote monitoring control, and safety control, via the I / O unit 40.

[0034] (Regarding the CPU unit 30 involved in Implementation Method 1)

[0035] CPU unit 30 includes a first CPU unit 310, a second CPU unit 320, a third CPU unit 330, and a fourth CPU unit 340. CPU unit 30 is a so-called redundant multi-CPU structure that allows these multiple CPU units 310, 320, 330, and 340 to perform distributed control. That is, each CPU unit 310, 320, 330, and 340 does not become the main controller for the overall control of PLC 1, but rather independently performs FA control related to external instruments and equipment. For example, each CPU unit 310, 320, 330, and 340 does not perform overall control of PLC 1, but independently performs one of the aforementioned timing control, data collection control, remote monitoring control, or safety control.

[0036] The first CPU unit 310 is, for example, a CPU unit that performs timing control. Figure 2As shown, the first CPU unit 310 includes a first input / output control unit 311, which is an example of an input / output control unit that controls the input and output of control signals between the CPU unit 40 and the I / O unit 40. Additionally, the first CPU unit 310 includes a first voltage drop detection unit 312, which is an example of a voltage drop detection unit that detects a voltage drop in the internal power supply. Furthermore, the first CPU unit 310 includes a first reset signal output control unit 313, which is an example of an operation control unit and an output control unit that controls the output of a reset signal, which is an example of an operation stop signal capable of stopping the operation of the CPU unit. Additionally, the first CPU unit 310 includes a first reset signal acquisition unit 314, which is an example of an acquisition unit that acquires a reset signal. Furthermore, the first CPU unit 310 includes a first reset execution unit 315, which is an example of an operation control unit and an operation stop control unit that performs reset processing based on the acquired reset signal. Finally, the first CPU unit 310 includes a first output selection unit 316, which is an example of a selection unit that selects whether to output a reset signal to other CPU units 320, 330, and 340.

[0037] The second CPU unit 320 is, for example, a CPU unit that controls data collection. The second CPU unit 320 includes a second input / output control unit 321, which is the same as the first input / output control unit 311 and is an example of an input / output control unit. The second CPU unit 320 includes a second voltage drop detection unit 322, which is the same as the first voltage drop detection unit 312 and is an example of a voltage drop detection unit. Furthermore, the second CPU unit 320 includes a second reset signal output control unit 323, which is the same as the first reset signal output control unit 313 and is an example of an operation control unit and an output control unit. Furthermore, the second CPU unit 320 includes a second reset signal acquisition unit 324, which is the same as the first reset signal acquisition unit 314 and is an example of an acquisition unit. Furthermore, the second CPU unit 320 includes a second reset execution unit 325, which is the same as the first reset execution unit 315 and is an example of an operation control unit and an operation stop control unit. Furthermore, the second CPU unit 320 includes a second output selection unit 326, which is the same as the first output selection unit 316 and is an example of a selection unit and an output selection unit.

[0038] The third CPU unit 330 is, for example, a CPU unit for remote monitoring and control. The third CPU unit 330 includes the same third input / output control unit 331, third voltage drop detection unit 332, third reset signal output control unit 333, third reset signal acquisition unit 334, third reset execution unit 335, and third output selection unit as the respective units 311-316 and 321-326 of each CPU unit 310 and 320.

[0039] The fourth CPU unit 340 is, for example, a CPU unit that performs safety control. The fourth CPU unit 340 includes the same fourth input / output control unit 341, fourth voltage drop detection unit 342, fourth reset signal output control unit 343, fourth reset signal acquisition unit 344, fourth reset execution unit 345, and fourth output selection unit as the respective units 311-316, 321-326, and 331-336 of each of the CPU units 310, 320, and 330.

[0040] (Regarding the I / O unit 40 involved in Implementation Method 1)

[0041] return Figure 1 The I / O unit 40 includes a first input / output unit 410 for inputting and outputting control signals related to timing control between the first CPU unit 310 and external instruments and devices. Additionally, the I / O unit 40 includes a second input / output unit 420 for inputting and outputting control signals related to data collection control between the second CPU unit 320 and external instruments and devices. Furthermore, the I / O unit 40 includes a third input / output unit 430 for inputting and outputting control signals related to remote monitoring control between the third CPU unit 330 and external instruments and devices. Additionally, the I / O unit 40 includes a fourth input / output unit 440 for inputting and outputting control signals related to safety control between the fourth CPU unit 340 and external instruments and devices. Finally, the I / O unit 40 includes a fifth input / output unit 450 for inputting and outputting control signals related to FA control between all CPU units 310, 320, 330, and 340 and external instruments and devices.

[0042] (Regarding the hardware structure of each CPU unit 310, 320, 330, and 340 involved in Implementation Method 1)

[0043] like Figure 3 As shown, each CPU unit 310, 320, 330, and 340 has a control unit 51 that executes processing according to control program 59. The control unit 51 has a CPU (Central Processing Unit). The control unit 51 executes processing according to control program 59. Figure 2The input / output control units 311, 321, 331, 341, voltage drop detection units 312, 322, 332, 342, and reset execution units 315, 325, 335, 345 shown are functioning.

[0044] return Figure 3 Each CPU unit 310, 320, 330, and 340 has a main storage unit 52 that loads the control program 59 and serves as the working area of ​​the control unit 51. The main storage unit 52 has RAM (Random Access Memory).

[0045] In addition, each CPU unit 310, 320, 330, and 340 has an external storage unit 53 that pre-stores the control program 59. The external storage unit 53, according to the instructions of the control unit 51, supplies the data stored in the program to the control unit 51 and stores the data supplied from the control unit 51. The external storage unit 53 has a non-volatile memory such as flash memory.

[0046] In addition, each CPU unit 310, 320, 330, and 340 has an operation unit 54 for user operation. Information input via the operation unit 54 is supplied to the control unit 51. The operation unit 54 includes, for example, an information input component such as a switch described later. The operation unit 54 serves as... Figure 2 The output selection units 316, 326, 336, and 346 shown are operational.

[0047] return Figure 3 Each CPU unit 310, 320, 330, and 340 has a transceiver unit 56 for transmitting and receiving information. The transceiver unit 56 includes information communication components such as a communication network terminal device and a wireless communication device that are connected to a network. The transceiver unit 56 serves as… Figure 2 The reset signal output control units 313, 323, 333, 343 and the reset signal acquisition units 314, 324, 334, 344 shown are functioning.

[0048] return Figure 3 In each CPU unit 310, 320, 330, and 340, the main storage unit 52, the external storage unit 53, the operation unit 54, and the transceiver unit 56 are all connected to the control unit 51 via the internal bus 50.

[0049] Each CPU unit 310, 320, 330, and 340 utilizes the main storage unit 52, external storage unit 53, operation unit 54, and transceiver unit 56 as resources through the control unit 51. Figure 2 The functions of the above-described parts 311-316, 321-326, 331-336, and 341-346 are shown.

[0050] For example, the first CPU unit 310 executes a first input / output control step, an example of an input / output control step performed by the first input / output control unit 311. Additionally, for example, the first CPU unit 310 executes a first voltage drop detection step, an example of a voltage drop detection step performed by the first voltage drop detection unit 312. Furthermore, for example, the first CPU unit 310 executes a first reset signal output control step, an example of an operation control step and an output control step performed by the first reset signal output control unit 313. Furthermore, for example, the first CPU unit 310 executes a first reset signal acquisition step, an example of an acquisition step performed by the first reset signal acquisition unit 314. Furthermore, for example, the first CPU unit 310 executes a first reset execution step, an example of an operation control step and an operation stop control step performed by the first reset execution unit 315. Furthermore, for example, the first CPU unit 310 executes a first output selection step, an example of a selection step and an output selection step performed by the first output selection unit 316.

[0051] Additionally, for example, the second CPU unit 320 executes a second input / output control step, as an example of an input / output control step, performed by the second input / output control unit 321. Additionally, for example, the second CPU unit 320 executes a second voltage drop detection step, as an example of a voltage drop detection step, performed by the second voltage drop detection unit 322. Additionally, for example, the second CPU unit 320 executes a second reset signal output control step, as an example of an operation control step and an output control step, performed by the second reset signal output control unit 323. Additionally, for example, the second CPU unit 320 executes a second reset signal acquisition step, as an example of an acquisition step, performed by the second reset signal acquisition unit 324. Additionally, for example, the second CPU unit 320 executes a second reset execution step, as an example of an operation control step and an operation stop control step, performed by the second reset execution unit 325. Additionally, for example, the second CPU unit 320 executes a second output selection step, as an example of a selection step and an output selection step, performed by the second output selection unit 326.

[0052] Additionally, for example, the third CPU unit 330 executes a third input / output control step, as an example of an input / output control step, performed by the third input / output control unit 331. Additionally, for example, the third CPU unit 330 executes a third voltage drop detection step, as an example of a voltage drop detection step, performed by the third voltage drop detection unit 332. Additionally, for example, the third CPU unit 330 executes a third reset signal output control step, as an example of an operation control step and an output control step, performed by the third reset signal output control unit 333. Additionally, for example, the third CPU unit 330 executes a third reset signal acquisition step, as an example of an acquisition step, performed by the third reset signal acquisition unit 334. Additionally, for example, the third CPU unit 330 executes a third reset execution step, as an example of an operation control step and an operation stop control step, performed by the third reset execution unit 335. Additionally, for example, the third CPU unit 330 executes a third output selection step, as an example of an output selection step, performed by the third output selection unit 336.

[0053] Additionally, for example, the fourth CPU unit 340 executes a fourth input / output control step, which is an example of an input / output control step performed by the fourth input / output control unit 341. Additionally, for example, the fourth CPU unit 340 executes a fourth voltage drop detection step, which is an example of a voltage drop detection step performed by the fourth voltage drop detection unit 342. Additionally, for example, the fourth CPU unit 340 executes a fourth reset signal output control step, which is an example of an operation control step and an output control step performed by the fourth reset signal output control unit 343. Additionally, for example, the fourth CPU unit 340 executes a fourth reset signal acquisition step, which is an example of an acquisition step performed by the fourth reset signal acquisition unit 344. Additionally, for example, the fourth CPU unit 340 executes a fourth reset execution step, which is an example of an operation control step and an operation stop control step performed by the fourth reset execution unit 345. Additionally, for example, the fourth CPU unit 340 executes a fourth output selection step, which is an example of an output selection step performed by the fourth output selection unit 346.

[0054] (Details regarding the functional structure of each CPU unit 310, 320, 330, and 340 involved in Implementation Method 1)

[0055] return Figure 2 The first input / output control unit 311 controls the input and output of control signals between itself and the first input / output unit 410, and also controls the input and output of control signals between itself and the fifth input / output unit 450.

[0056] The first reset signal acquisition unit 314 acquires the reset signal output from the first CPU unit 310 or other CPU units 320, 330, 340.

[0057] The first reset execution unit 315 performs a reset process when the first reset signal acquisition unit 314 acquires a reset signal, thereby stopping the operation of the first CPU unit 310.

[0058] Here, the transmission and reception of reset signals in the power supply unit 20 and each CPU unit 310, 320, 330, and 340 can be, for example, by... Figure 4 , Figure 5 The circuit shown is implemented. The functions of the first voltage drop detection unit 312 and the first reset signal output control unit 313, for example, can be achieved by... Figure 4 , Figure 5 The output section shown is implemented by a first power monitoring IC 317, as an example. Additionally, the function of the first output selection section 316 can be implemented by, for example, a... Figure 4 , Figure 5 The first switch 318 is implemented as an example of a switching switch shown. The first switch 318 is, for example, a user-operable so-called single-pole double-throw switch located on the external part of the first CPU unit 310.

[0059] exist Figure 4 , Figure 5 In the circuit shown, power supply unit 20 is connected to each CPU unit 310, 320, 330, and 340 via a first communication line 501, the potential of which is +5V. Power supply unit 20 is also connected to the cathode of first diode 502 via a second communication line 503. The anode of first diode 502 is connected to the cathode of Zener diode 504 via a third communication line 505. The anode of Zener diode 504 is connected to the base of transistor 506 via a fourth communication line 507. The emitter of transistor 506 is grounded, and the collector of transistor 506 is connected to each CPU unit 310, 320, 330, and 340 via a fifth communication line 508.

[0060] Furthermore, the first contact 509 of the second communication line 503 is connected to the cathode of the second diode 510 via the sixth communication line 511. The anode of the second diode 510 is connected to the first terminal 512 of the first switch 318 via the seventh communication line 513. The second contact 514 of the second communication line 503 is connected to the second terminal 515 of the first switch 318 via the eighth communication line 516. Finally, the third terminal 517 of the first switch 318 is connected to the contact 518 of the communication line 500 of the internal circuitry of the first CPU unit 310 via the ninth communication line 519.

[0061] Furthermore, the first contact 520 of the first communication line 501 is connected to one end of the first pull-up resistor 521 via the tenth signal line 522. The other end of the first pull-up resistor 521 is connected to the contact 523 of the seventh communication line 513 via the eleventh signal line 524. The second contact 525 of the first communication line 501 is connected to one end of the second pull-up resistor 526 via the twelfth signal line 527. The other end of the second pull-up resistor 526 is connected to the contact 528 of the third communication line 505 via the thirteenth signal line 529. The third contact 530 of the first communication line 501 is connected to one end of the third pull-up resistor 531 via the fourteenth signal line 532. The other end of the third pull-up resistor 531 is connected to the contact 533 of the fifth communication line 508 via the fifteenth signal line 534. In addition, the contact 535 of the fourth communication line 507 is connected to one end of the fourth pull-up resistor 536 through the sixteenth signal line 537, and the other end of the fourth pull-up resistor 536 is grounded.

[0062] Therefore, the power supply unit 20 is electrically connected to each of the CPU units 310, 320, 330, and 340 via components 502 to 508. Thus, if a voltage drop is detected due to a fault in the power supply unit 20, the power supply unit 20 outputs a reset signal to each of the CPU units 310, 320, 330, and 340 via components 502 to 508. Specifically, by changing the potential of the second communication line 503, the potential of the base of the transistor 506, which acts as a switching element, changes, causing current to flow between the collector and emitter of each of the CPU units 310, 320, 330, and 340. Therefore, each of the CPU units 310, 320, 330, and 340 detects the reset signal output from the power supply unit 20 and performs a reset process.

[0063] As a result, in the event of a failure in the power supply unit 20, all CPU units 310, 320, 330, and 340 cease operation and stop transmitting and receiving control signals with all input / output units 410 to 450.

[0064] Here, we consider the scenario where the first CPU unit 310 malfunctions. In this case, as... Figure 5 As indicated by the arrow, when the first power monitoring IC 317 detects a voltage drop in the internal power supply of the first CPU unit 310, it outputs a reset signal to the control unit 51 of the first CPU unit 310 via the communication line 500. Therefore, in the first CPU unit 310 that has malfunctioned, the first reset signal acquisition unit 314 acquires the reset signal, and the first reset execution unit 315 performs a reset process and stops operating.

[0065] At this time, when the first switch 318 is connected to the second terminal 515 and the third terminal 517, such as Figure 4 As shown, the first switch 318 and the second communication line 503 are connected via the eighth communication line 516. Therefore, if the first power monitoring IC 317... Figure 4 As indicated by the arrow, a reset signal is output to the first CPU unit 310 via communication line 500. Then, the same reset signal is also output to the remaining CPU units 320, 330, and 340 via components 519, 517, 515, 516, and 502-508. Therefore, in the same manner as when a reset signal is output from power supply unit 20, each CPU unit 310, 320, 330, and 340 receives the reset signal, performs the reset process, and stops operating.

[0066] As a result, when the first switch 318 is connected to the second terminal 515 and the third terminal 517, all CPU units 310, 320, 330, and 340, including the faulty first CPU unit 310, stop operating and cease sending and receiving control signals with all input / output units 410 to 450.

[0067] On the other hand, when the first switch 318 is connected to the first terminal 512 and the third terminal 517, such as Figure 5 As shown, the first power monitoring IC 317 connects components 510, 524, and 521 between the first switch 318 and the second communication line 503. Therefore, with... Figure 4 Unlike the circuit shown, the first power monitoring IC 317, even if... Figure 5 As indicated by the arrow, a reset signal is output to the first CPU unit 310 via communication line 500, but not to the remaining CPU units 320, 330, and 340. Specifically, the potential of the second communication line 503 cannot be changed, and the potential of the base of the transistor 506, which serves as a switching element, does not change. Therefore, the faulty first CPU unit 310 performs a reset process, while the remaining CPU units 320, 330, and 340 do not perform a reset process.

[0068] As a result, when the first switch 318 is connected to the first terminal 512 and the third terminal 517, only the faulty first CPU unit 310 stops operating, while the remaining CPU units 320, 330, and 340 can continue operating without temporarily stopping. Thus, the transmission and reception of control signals between the faulty first CPU unit 310 and the first input / output unit 410 ceases, while the transmission and reception of control signals between the remaining CPU units 320, 330, and 340 and the remaining input / output units 420-450 continue.

[0069] Furthermore, regarding each part 321 to 325 of the second CPU unit 320, simply replace "first CPU unit 310" with "second CPU unit 320", "first input / output control unit 311" with "second input / output control unit 321", "first voltage drop detection unit 312" with "second voltage drop detection unit 322", "first reset signal output control unit 313" with "second reset signal output control unit 323", "first reset signal acquisition unit 314" with "second reset signal acquisition unit 324", "first reset execution unit 315" with "second reset execution unit 325", "first output selection unit 316" with "second output selection unit 326", and "first power monitoring IC" with "second reset signal acquisition unit 324". Replace "317" with "Second Power Monitoring IC 327", replace "First Switch 318" with "Second Switch 328", replace "CPU Units 320, 330, 340" with "CPU Units 310, 330, 340", replace "First Input / Output Unit 410" with "Second Input / Output Unit 420", and replace "Input / Output Units 420-450" with "Input / Output Units 410, 430-450" to obtain the same description as above. Therefore, to avoid redundant descriptions, detailed explanations are omitted.

[0070] Furthermore, regarding each part 331 to 335 of the third CPU unit 330, simply replace "first CPU unit 310" with "third CPU unit 330", "first input / output control unit 311" with "third input / output control unit 331", "first voltage drop detection unit 312" with "third voltage drop detection unit 332", "first reset signal output control unit 313" with "third reset signal output control unit 333", "first reset signal acquisition unit 314" with "third reset signal acquisition unit 334", "first reset execution unit 315" with "third reset execution unit 335", "first output selection unit 316" with "third output selection unit 336", and "first power monitoring IC 317" with "third power monitoring IC". Replace “337” with “first switch 318”, “third switch 338”, “CPU units 320, 330, 340” with “CPU units 310, 320, 340”, “first input / output unit 410” with “third input / output unit 430”, and “input / output units 420-450” with “input / output units 410, 420, 440, 450”, and the result will be the same description as above. Therefore, to avoid redundant descriptions, detailed explanations are omitted.

[0071] Furthermore, regarding each part 341 to 345 of the fourth CPU unit 340, simply replace "first CPU unit 310" with "fourth CPU unit 340", "first input / output control unit 311" with "fourth input / output control unit 341", "first voltage drop detection unit 312" with "fourth voltage drop detection unit 342", "first reset signal output control unit 313" with "fourth reset signal output control unit 343", "first reset signal acquisition unit 314" with "fourth reset signal acquisition unit 344", "first reset execution unit 315" with "fourth reset execution unit 345", "first output selection unit 316" with "fourth output selection unit 346", and "first power monitoring IC 317" with "fourth power monitoring IC". Replace “first switch 318” with “fourth switch 348”, replace “CPU units 320, 330, 340” with “CPU units 310, 320, 330”, replace “first input / output unit 410” with “fourth input / output unit 440”, and replace “input / output units 420-450” with “input / output units 410-430, 450” to obtain the same description as above. Therefore, to avoid redundant descriptions, detailed explanations are omitted.

[0072] As explained above, according to the PLC 1 of this embodiment, in each CPU unit 310, 320, 330, 340, the input and output of control signals between each input and output unit 410 to 450 are controlled by each input and output control unit 311, 321, 331, 341, thereby enabling independent FA control related to external instruments and equipment.

[0073] In the first CPU unit 310, the first voltage drop detection unit 312 detects a voltage drop in the internal power supply, and the first reset signal output control unit 313 outputs a reset signal. Additionally, the first reset signal acquisition unit 314 acquires the reset signals output from each of the CPU units 310, 320, 330, and 340, and the first reset execution unit 315 performs a reset process based on the acquired reset signals, stopping the operation of the first CPU unit 310. Furthermore, the first output selection unit 316 selects whether to output reset signals to other CPU units 320, 330, and 340, thereby selecting whether to stop the operation of the other CPU units 320, 330, and 340.

[0074] Furthermore, if the first reset signal output control unit 313 selects to output a reset signal in the first output selection unit 316, it also outputs reset signals to other CPU units 320, 330, and 340, thereby stopping the operation. On the other hand, if the first reset signal output control unit 313 selects not to output a reset signal in the first output selection unit 316, it does not output reset signals to other CPU units 320, 330, and 340, thus not stopping the operation.

[0075] Furthermore, the parts 322-326, 332-336, and 342-346 of the remaining CPU units 320, 330, and 340 are the same as the parts 312-316 of the first CPU unit 310.

[0076] By configuring it in the above manner, for the PLC 1 according to this embodiment, for example, if the first CPU unit 310 that has generated an abnormality chooses to output a reset signal to the other CPU units 320, 330, and 340, then the other CPU units 320, 330, and 340 will also stop operating, thus ceasing operation. On the other hand, for the PLC 1 according to this embodiment, if the first CPU unit 310 that has generated an abnormality does not choose to output a reset signal to the other CPU units 320, 330, and 340, then the other CPU units 320, 330, and 340 will not stop operating, thus continuing operation.

[0077] Therefore, the PLC 1 according to this embodiment, through the aforementioned selection of the first CPU unit 310 that has generated an anomaly, can select either an "operation stop mode" that stops the operation of all CPU units 310, 320, 330, and 340 and thus stops the operation of the entire control system, or a "degraded operation mode" that allows the operation of each CPU unit 320, 330, and 340 that has not generated an anomaly to continue, thus allowing the overall operation of the control system to continue rather than be temporarily stopped. Therefore, the PLC 1 according to this embodiment can select whether to stop or continue the operation of the entire control system when an anomaly occurs.

[0078] Furthermore, according to the PLC 1 of this embodiment, the first output selection unit 316 can select outputs based on the input from... Figure 4 , Figure 5 The output of the first switch 318 is used to select whether to output a reset signal to other CPU units 320, 330, and 340. Furthermore, the first switch 318 is located on the external part of the first CPU unit 310 and is operable by the user. Additionally, the output selection units 326, 336, and 346 and the switches 328, 338, and 348 of the remaining CPU units 320, 330, and 340 are identical to the first output selection unit 316 and the first switch 318 of the first CPU unit 310.

[0079] By configuring the above method, users can operate each switch 318, 328, 338, 348 to pre-select whether to use each CPU unit 310, 320, 330, 340 in "operation stop mode" or "degraded operation mode" before an abnormality occurs.

[0080] Here, some users have the following requirement: in a redundant multi-CPU architecture like PLC 1, even if a CPU unit malfunctions, the overall operation should continue, rather than temporarily stopping, and they want to continue collecting data at the time of the malfunction and before and after it. In this case, the PLC needs to be able to perform online replacement and repair of the malfunctioning CPU unit while it continues to operate.

[0081] However, in currently known FA PLCs, such as those in Patent Documents 1-3 mentioned above, in the event of a CPU unit failure, the entire system is typically shut down for safe recovery operations. Therefore, currently known PLCs fail to meet the aforementioned user requirements.

[0082] In contrast, in the PLC 1 described in this embodiment, as long as the "degraded operation mode" is selected as described above, the replacement and maintenance of the CPU unit that has malfunctioned can be carried out online, and data can continue to be collected at the time of the malfunction and before and after the malfunction. As a result, the PLC 1 described in this embodiment can meet the user's requirements as described above.

[0083] [Implementation Method 2]

[0084] In the PLC 1 according to Embodiment 1, by selecting whether to output a reset signal to the remaining CPU units 310, 320, 330, and 340 when an abnormality occurs, it is possible to select whether to stop or continue the overall operation, but this is not limited to this. For example, each CPU unit 310, 320, 330, and 340 may periodically confirm each other's actions, and when it cannot confirm the actions of other CPU units 310, 320, 330, and 340, it can select whether to stop its own operation, thereby selecting whether to stop or continue the overall operation. Hereinafter, refer to Figures 6-9 The control system 2 according to Embodiment 2 will be described in detail. Furthermore, in Embodiment 2, structures different from those in Embodiment 1 will be described; structures identical to those in Embodiment 1 are redundant and will therefore be omitted from description.

[0085] (Regarding the control system 2 involved in Implementation Method 2)

[0086] like Figure 6 As shown, the control system 2 according to Embodiment 2 of the present invention includes a PLC 1 and an engineering design tool 600. The PLC 1 and the engineering design tool 600 are connected via the Internet 700, which is an example of a network.

[0087] (Regarding the CPU unit 30 involved in Implementation Method 2)

[0088] The first CPU unit 310 replaced Figure 2 The first reset signal output control unit 313 shown includes, as an example, an output unit that outputs a signal indicating the operation of the first CPU unit 310, namely an operation confirmation signal. Figure 7 The first action confirmation signal output unit 363 is shown. Additionally, the first CPU unit 310 replaces... Figure 2 The first reset signal acquisition unit 314 shown includes, as an example, an acquisition unit that acquires operation confirmation signals from the other CPU units 320, 330, and 340. Figure 7 The first action confirmation signal acquisition unit 364 is shown. Additionally, the first CPU unit 310 replaces... Figure 2 The first output selection unit 316 shown includes, as an example, a selection unit for selecting whether to stop the operation of the first CPU unit 310 and an operation stop selection unit. Figure 7 The first action stop selection unit 366 is shown. Additionally, as... Figure 7 As shown, the first CPU unit 310 includes a first setting information acquisition unit 367, which is an example of a setting information acquisition unit for acquiring setting information, and a first setting information storage unit 368, which is an example of a setting information storage unit for storing setting information.

[0089] The second CPU unit 320 replaced Figure 2 The second reset signal output control unit 323 shown includes, as an example, the same type of output unit as the first action confirmation signal output unit 363. Figure 7 The second action confirmation signal output unit 373 is shown. Additionally, the second CPU unit 320 replaces... Figure 2 The second reset signal acquisition unit 324 shown includes, as an example, the same acquisition unit as the first action confirmation signal acquisition unit 364. Figure 7 The second action confirmation signal acquisition unit 374 is shown. Additionally, the second CPU unit 320 replaces... Figure 2 The second output selection unit 326 shown includes an example of a selection unit and an action stop selection unit identical to the first action stop selection unit 366. Figure 7 The second action stop selection unit 376 is shown. Additionally, as... Figure 7As shown, the second CPU unit 320 includes a second setting information acquisition unit 377, which is the same as the first setting information acquisition unit 367 and is an example of a setting information acquisition unit. Additionally, the second CPU unit 320 includes a second setting information storage unit 378, which is the same as the first setting information storage unit 368 and is an example of a setting information storage unit.

[0090] The third CPU unit 330 replaces Figure 2 The third reset signal output control unit 333, the third reset signal acquisition unit 334, and the third output selection unit 336 shown are included in the same category as... Figure 7 The third action confirmation signal output unit 383, the third action confirmation signal acquisition unit 384, and the third action stop selection unit 386 shown are identical to those in the units 363, 364, 366, 373, 374, and 376. Additionally, the third CPU unit 330 includes the same components as... Figure 7 The third setting information acquisition unit 387 and the third setting information storage unit 388 shown are the same as those in the units 367, 368, 377, and 378.

[0091] The fourth CPU unit 340 replaces Figure 2 The fourth reset signal output control unit 343, the fourth reset signal acquisition unit 344, and the fourth output selection unit 346 shown are included in the same category as... Figure 7 The fourth action confirmation signal output unit 393, the fourth action confirmation signal acquisition unit 394, and the fourth action stop selection unit 396 shown are identical to those in the units 363, 364, 366, 373, 374, 376, 383, 384, and 386. Additionally, the fourth CPU unit 340 includes the same... Figure 7 The fourth setting information acquisition unit 397 and the fourth setting information storage unit 398 shown in each of the units 367, 368, 377, 378, 387, and 388 are the same.

[0092] (Regarding the engineering design tool 600 involved in implementation method 2)

[0093] The engineering design tool 600 is, for example, a personal computer with engineering design tool software installed. The engineering design tool 600 includes a setting information generation unit 610 for generating setting information and a setting information output unit 620 for outputting setting information.

[0094] (Regarding the hardware structure of each CPU unit 310, 320, 330, and 340 involved in Implementation Method 2)

[0095] return Figure 3 In each of the CPU units 310, 320, 330, and 340 involved in Embodiment 2, the control unit 51 serves as... Figure 7The action stop selection units 366, 376, 386, and 396 shown in the diagram function. Additionally, the transceiver unit 56 functions as the action confirmation signal output units 363, 373, 383, and 393, the action confirmation signal acquisition units 364, 374, 384, and 394, and the setting information acquisition units 367, 377, 387, and 397. Furthermore, the external storage unit 53 functions as the setting information storage units 368, 378, 388, and 398.

[0096] return Figure 3 Each CPU unit 310, 320, 330, and 340 utilizes the main storage unit 52, external storage unit 53, operation unit 54, and transceiver unit 56 as resources through the control unit 51, thereby achieving... Figure 7 The functions of the above-mentioned parts 363, 364, 366-368, 373, 374, 376-378, 383, 384, 386-388, 393, 394, 396-398 are shown.

[0097] For example, the first CPU unit 310 executes a first action confirmation signal output control step, as an example of an output step, performed by the first action confirmation signal output unit 363. Additionally, for example, the first CPU unit 310 executes a first action confirmation signal acquisition step, as an example of an acquisition step, performed by the first action confirmation signal acquisition unit 364. Furthermore, for example, the first CPU unit 310 executes a first action stop selection step, as an example of a selection step and an action stop selection step, performed by the first action stop selection unit 366. Furthermore, for example, the first CPU unit 310 executes a first setting information acquisition step, as an example of a setting information acquisition step, performed by the first setting information storage unit 368. Finally, for example, the first CPU unit 310 executes a first setting information storage step, as an example of a setting information storage step, performed by the first setting information storage unit 368.

[0098] Additionally, for example, the second CPU unit 320 executes a second action confirmation signal output control step, as an example of an output step, performed by the second action confirmation signal output unit 373. Additionally, for example, the second CPU unit 320 executes a second action confirmation signal acquisition step, as an example of an acquisition step, performed by the second action confirmation signal acquisition unit 374. Additionally, for example, the second CPU unit 320 executes a second action stop selection step, as an example of a selection step and an action stop selection step, performed by the second action stop selection unit 376. Additionally, for example, the second CPU unit 320 executes a second setting information acquisition step, as an example of a setting information acquisition step, performed by the second setting information storage unit 378. Additionally, for example, the second CPU unit 320 executes a second setting information storage step, as an example of a setting information storage step, performed by the second setting information storage unit 378.

[0099] Additionally, for example, the third CPU unit 330 executes a third action confirmation signal output step, as an example of an output step, performed by the third action confirmation signal output unit 383. Additionally, for example, the third CPU unit 330 executes a third action confirmation signal acquisition step, as an example of an acquisition step, performed by the third action confirmation signal acquisition unit 384. Additionally, for example, the third CPU unit 330 executes a third action stop selection step, as an example of a selection step and an action stop selection step, performed by the third action stop selection unit 386. Additionally, for example, the third CPU unit 330 executes a third setting information acquisition step, as an example of a setting information acquisition step, performed by the third setting information storage unit 388. Additionally, for example, the third CPU unit 330 executes a third setting information storage step, as an example of a setting information storage step, performed by the third setting information storage unit 388.

[0100] Additionally, for example, the fourth CPU unit 340 executes a fourth action confirmation signal output step, as an example of an output step, performed by the fourth action confirmation signal output unit 393. Additionally, for example, the fourth CPU unit 340 executes a fourth action confirmation signal acquisition step, as an example of an acquisition step, performed by the fourth action confirmation signal acquisition unit 394. Additionally, for example, the fourth CPU unit 340 executes a fourth action stop selection step, as an example of a selection step and an action stop selection step, performed by the fourth action stop selection unit 396. Additionally, for example, the fourth CPU unit 340 executes a fourth setting information acquisition step, as an example of a setting information acquisition step, performed by the fourth setting information acquisition unit 397. Additionally, for example, the fourth CPU unit 340 executes a fourth setting information storage step, as an example of a setting information storage step, performed by the fourth setting information storage unit 398.

[0101] (Regarding the hardware structure of the engineering design tool 600 involved in Implementation Method 2)

[0102] Furthermore, although not shown in the diagram, the engineering design tool 600, like each of the CPU units 310, 320, 330, and 340, includes a control unit 51, a main storage unit 52, an external storage unit 53, an operation unit 54, and a transceiver unit 56. Additionally, the engineering design tool 600 has a display unit (not shown) that displays information input via the operation unit 54 and information output via the control unit 51. The display unit may be a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro-Luminescence) display.

[0103] In the engineering design tool 600, the control unit 51 operates according to the control program 59. Figure 7 The setting information generation unit 610 shown functions. Additionally, the transceiver unit 56 functions as the setting information output unit 620. The engineering design tool 600 uses the main storage unit 52, external storage unit 53, operation unit 54, display unit, and transceiver unit 56 as resources via the control unit 51, thereby realizing the functions of the setting information generation unit 610 and the setting information output unit 620. For example, the engineering design tool 600 executes the setting information generation step performed by the setting information generation unit 610 and the setting information output step performed by the setting information output unit 620.

[0104] (Details regarding the functional structure of each CPU unit 310, 320, 330, and 340 involved in Implementation Method 2)

[0105] When the first voltage drop detection unit 312 detects a voltage drop in the internal power supply, the first reset execution unit 315 performs a reset process to stop the operation of the first CPU unit 310.

[0106] The first action confirmation signal output unit 363 outputs an action confirmation signal to each of the other CPU units 320, 330, and 340 each time a predetermined time has elapsed.

[0107] The first action confirmation signal acquisition unit 364 acquires action confirmation signals output from other CPU units 320, 330, and 340.

[0108] The first setting information acquisition unit 367 acquires the setting information output from the engineering design tool 600. Furthermore, at this time, the control unit 51 of the first CPU unit 310 stores the acquired setting information in the first setting information storage unit 368.

[0109] Here, the configuration information is user-defined information that determines the operating mode of PLC 1 when each CPU unit 310, 320, 330, or 340 malfunctions. The configuration information, for example, can be configured to... Figure 8 The information is displayed in the form of a table. The configuration information corresponds to the items representing "First CPU Unit," "Second CPU Unit," "Third CPU Unit," and "Fourth CPU Unit" for each CPU unit 310, 320, 330, and 340. For example, the configuration information is shown in... Figure 8 As shown, when all the above items are set to "Continue," it indicates that each CPU unit 310, 320, 330, and 340 continues its operation when it determines that the operation of other CPU units 310, 320, 330, and 340 has stopped. Furthermore, if the above items are set to "Stop," it indicates that each CPU unit 310, 320, 330, and 340 stops its operation when it determines that the operation of other CPU units 310, 320, 330, and 340 has stopped.

[0110] return Figure 7 When the first action stop selection unit 366 determines that the other CPU units 320, 330, and 340 have stopped operating based on action confirmation signals obtained from the other CPU units 320, 330, and 340, it selects whether to stop the operation of the first CPU unit 310 based on setting information. When there is a CPU unit 320, 330, or 340 among the other CPU units 320, 330, and 340 where the period for which no action confirmation signal has been obtained exceeds a predetermined maximum allowable period, the first action stop selection unit 366 determines that that CPU unit 320, 330, or 340 has stopped operating.

[0111] At this time, the first action stop selection unit 366, referring to the setting information stored in the first setting information storage unit 368, selects to stop the operation of the first CPU unit 310 when the item for "first CPU unit" is "stop". Furthermore, if the first action stop selection unit 366 selects to stop the operation, the first reset execution unit 315 performs a reset process, stopping the operation of the first CPU unit 310. On the other hand, if the first action stop selection unit 366 selects to continue the operation of the first CPU unit 310 when the item for "first CPU unit" is "continue". Furthermore, if the first action stop selection unit 366 selects to continue the operation, the first reset execution unit 315 does not perform a reset process, and the first CPU unit 310 continues to operate. Additionally, at this time, the first CPU unit 310 operates under the assumption that the CPU units 320, 330, and 340, which stopped operating due to an abnormality, are not present, or operates at a degraded level. Furthermore, if the first CPU unit 310 performs a recovery operation performed by the administrator, such as replacing or repairing the stopped CPU units, and obtains an operation confirmation signal output from the recovered CPU unit, it resumes normal operation.

[0112] Furthermore, regarding the various parts 322, 373, 374, 325, and 376-378 of the second CPU unit 320, simply replace "first CPU unit 310" with "second CPU unit 320", "first voltage drop detection unit 312" with "second voltage drop detection unit 322", "first action confirmation signal output unit 363" with "second action confirmation signal output unit 373", and "first action confirmation signal acquisition unit 364" with "second action confirmation signal acquisition unit 374". Replacing "first reset execution unit 315" with "second reset execution unit 325", "first action stop selection unit 366" with "second action stop selection unit 376", "first setting information acquisition unit 367" with "second setting information acquisition unit 377", "first setting information storage unit 368" with "second setting information storage unit 378", and "CPU units 320, 330, 340" with "CPU units 310, 330, 340" yields the same description as above. Therefore, to avoid redundant explanations, detailed descriptions are omitted.

[0113] Furthermore, regarding the various parts 332, 383, 384, 335, and 386-388 of the third CPU unit 330, similarly, simply replace "first CPU unit 310" with "third CPU unit 330", "first voltage drop detection unit 312" with "third voltage drop detection unit 332", "first action confirmation signal output unit 363" with "third action confirmation signal output unit 383", and "first action confirmation signal acquisition unit 364" with "third action confirmation signal acquisition unit 384". If we replace "first reset execution unit 315" with "third reset execution unit 335", "first action stop selection unit 366" with "third action stop selection unit 386", "first setting information acquisition unit 367" with "third setting information acquisition unit 387", "first setting information storage unit 368" with "third setting information storage unit 388", and "CPU units 320, 330, 340" with "CPU units 310, 320, 340", the result will be the same as described above. Therefore, to avoid redundant descriptions, detailed explanations are omitted.

[0114] Furthermore, regarding the various parts 342, 393, 394, 345, and 396-398 of the fourth CPU unit 340, similarly, simply replace "first CPU unit 310" with "fourth CPU unit 340", "first voltage drop detection unit 312" with "fourth voltage drop detection unit 342", "first action confirmation signal output unit 363" with "fourth action confirmation signal output unit 393", and "first action confirmation signal acquisition unit 364" with "fourth action confirmation signal acquisition unit 394". If we replace "first reset execution unit 315" with "fourth reset execution unit 345", "first action stop selection unit 366" with "fourth action stop selection unit 396", "first setting information acquisition unit 367" with "fourth setting information acquisition unit 397", "first setting information storage unit 368" with "fourth setting information storage unit 398", and "CPU units 320, 330, 340" with "CPU units 310, 320, 330", the result will be the same as described above. Therefore, to avoid redundant descriptions, detailed explanations are omitted.

[0115] (Details regarding the functional structure of the engineering design tool 600 involved in Implementation Method 2)

[0116] The setting information generation unit 610 generates setting information based on information input by the user using the operation unit 54 in a setting screen (not shown).

[0117] When the setting information generation unit 610 generates setting information, the setting information output unit 620 outputs the setting information to PLC 1.

[0118] (Flowchart regarding the action stop selection process involved in Implementation Method 2)

[0119] Next, using flowcharts, the control of each CPU unit 310, 320, 330, and 340 in selecting whether to stop an action based on an action confirmation signal will be explained. Furthermore, as mentioned above, the structures of each CPU unit 310, 320, 330, and 340 are identical. Therefore, to avoid redundant explanations regarding the action stop selection process, only the first action stop selection process of the first CPU unit 310 will be described, omitting the explanations of the remaining CPU units 320, 330, and 340. If the first CPU unit 310 begins normal operation after power-on, it begins... Figure 9 The first action shown stops the execution of the selection process.

[0120] First, the first action stop selection unit 366 determines whether there are other CPU units 320, 330, and 340 that have stopped operating by determining whether there are any CPU units 320, 330, and 340 that have not received an action confirmation signal for a period exceeding the maximum allowable period (step S101). If there are no other CPU units 320, 330, and 340 that have stopped operating (step S101; N), the first action stop selection unit 366 repeatedly executes the process of step S101 until it is determined that there are other CPU units 320, 330, and 340 that have stopped operating.

[0121] On the other hand, if other CPU units 320, 330, and 340 have stopped operating (step S101; Y), the first action stop selection unit 366 determines whether the item for "first CPU unit" is "stopped" by referring to the setting information stored in the first setting information storage unit 368 (step S102). If the first action stop selection unit 366 selects to stop the operation of the first CPU unit 310 (step S102; Y), the first reset execution unit 315 performs a reset process to temporarily stop the operation of the first CPU unit 310 (step S103), and the process ends. On the other hand, if the first action stop selection unit 366 selects to continue the operation of the first CPU unit 310 instead of "stopped" (step S102; N), the first CPU unit 310 continues to operate in degraded operation (step S104).

[0122] Furthermore, the first CPU unit 310 determines whether it has obtained an action confirmation signal output from the other CPU units 320, 330, and 340 after recovery for performing recovery work (step S105). If the first CPU unit 310 does not obtain an action confirmation signal from the other CPU units 320, 330, and 340 after recovery (step S105; N), it repeatedly executes the process of step S105 until an action confirmation signal is obtained. And if the first CPU unit 310 obtains an action confirmation signal from the other CPU units 320, 330, and 340 after recovery (step S105; Y), it continues to perform the operation in normal operation (step S106) and ends the process.

[0123] As explained above, in the control system 2 according to this embodiment, in the first CPU unit 310, the first reset execution unit 315 performs a reset process to stop the operation of the first CPU unit 310 when the first voltage drop detection unit 312 detects a voltage drop in the internal power supply. Furthermore, the first action confirmation signal output unit 363 outputs action confirmation signals to the other CPU units 320, 330, and 340, and the first action confirmation signal acquisition unit 364 acquires the action confirmation signals output from the other CPU units 320, 330, and 340.

[0124] Furthermore, the first action stop selection unit 366 determines whether there are other CPU units 320, 330, and 340 that have stopped operating based on the action confirmation signal. If other CPU units 320, 330, and 340 have stopped operating, the first action stop selection unit 366 selects whether the first CPU unit 310 should also stop operating based on the setting information stored in the first setting information storage unit 368. Additionally, if the first action stop selection unit 366 selects a stop operation, the first reset execution unit 315 performs a reset process, stopping the operation of the first CPU unit 310. Conversely, if the first action stop selection unit 366 selects a continue operation, the first reset execution unit 315 does not perform a reset process, and the first CPU unit 310 continues operating.

[0125] Furthermore, the parts 322, 373, 374, 325, 376-378, 332, 383, 384, 335, 386-388, 342, 393, 394, 345, 396-398 of the remaining CPU units 320, 330, and 340 are the same as the parts 312, 363, 364, 315, 366-368 of the first CPU unit 310.

[0126] By configuring the control system 2 according to the above method, for example, when all items in the setting information are "stop", all CPU units 310, 320, 330, and 340 stop operating, thus stopping the operation of PLC 1. On the other hand, for example, when all items in the setting information are "continue", the remaining CPU units 310, 320, 330, and 340 that have not experienced a fault do not stop operating, thus continuing the operation of PLC 1. Therefore, the control system 2 according to this embodiment can select between "operation stop mode" and "degraded operation mode" based on the selection of each CPU unit 310, 320, 330, and 340 based on the setting information. Therefore, the control system 2 according to this embodiment can choose whether to stop or continue the overall operation of PLC 1 when an abnormality occurs.

[0127] Furthermore, according to the control system 2 of this embodiment, in the engineering design tool 600, the setting information generation unit 610 generates setting information based on the information input by the user using the operation unit 54, and the setting information output unit 620 outputs the setting information to the PLC 1. Additionally, in the first CPU unit 310, the first setting information acquisition unit 367 acquires the setting information, and the acquired setting information is stored in the first setting information storage unit 368. Furthermore, the units 377, 378, 387, 388, 397, and 398 of the remaining CPU units 320, 330, and 340 are also the same as the units 367 and 368 of the first CPU unit 310.

[0128] By configuring it in the above manner, users can use the engineering design tool 600 to pre-select whether to use each CPU unit 310, 320, 330, or 340 in the "operation stop mode" or "degraded operation mode" before an anomaly occurs.

[0129] (Example of Change)

[0130] Furthermore, in the above embodiments 1 and 2, the PLC 1 is equipped with 4 CPU units 310, 320, 330 and 340 in the basic unit 10. However, the number of CPU units installed in the basic unit 10 is not limited to 2 units as long as it is greater than or equal to 2 units. For example, 2 CPU units 310 and 320 can be installed in the basic unit 10, or 5 or more CPU units can be installed.

[0131] Furthermore, in the PLC 1 described in embodiments 1 and 2 above, five input / output units 410 to 450 are installed in the basic unit 10. However, the number of input / output units installed in the basic unit 10 is not limited to this. For example, one input / output unit 450 may be installed in the basic unit 10, or more than or equal to six input / output units may be installed.

[0132] Furthermore, the PLC 1 described in Embodiment 1 implements the functions of each output selection unit 316, 326, 336, and 346 through each switching switch 318, 328, 338, and 348. However, the functions of each output selection unit 316, 326, 336, and 346 are not limited to each switching switch 318, 328, 338, and 348, as long as they can be implemented. For example, each output selection unit 316, 326, 336, and 346 can also be implemented through control by the control unit 51. Specifically, each output selection unit 316, 326, 336, and 346 can select whether to output a reset signal to other CPU units 310, 320, 330, and 340 based on setting information obtained from the engineering design tool 600. In this case, each reset signal output control unit 313, 323, 333, and 343 can output reset signals only to the faulty CPU units 310, 320, 330, and 340 via internal circuitry, and needs to be able to output reset signals to all CPU units 310, 320, 330, and 340 via the basic unit 10.

[0133] Furthermore, regarding the control system 2 according to Embodiment 2 described above, each operation stop selection unit 366, 376, 386, and 396 selects whether each CPU unit 310, 320, 330, and 340 should stop operating based on setting information generated and output by the engineering design tool 600. However, the setting information may not be generated and output by the engineering design tool 600. For example, switches may be provided on the external parts of each CPU unit 310, 320, 330, and 340, and setting information indicating whether each CPU unit 310, 320, 330, and 340 should stop or continue may be generated based on the on / off state of each switch operated by the user.

[0134] Furthermore, as is preferably the case in Embodiments 1 and 2 described above, the PLC 1 can select an "operation stop mode" and a "degraded operation mode" for each CPU unit 310, 320, 330, and 340, but is not limited to this. For example, the PLC 1 can also select either the "operation stop mode" or the "degraded operation mode" for all CPU units 310, 320, 330, and 340. In this case, in Embodiment 1 described above, for example, instead of the single-pole double-throw switches 318, 328, 338, and 348, a four-pole double-throw switch, i.e., a switching switch, can be provided on the external part of the basic unit 10, and the stop or continue of all CPU units 310, 320, 330, and 340 can be selected based on the on / off state of the switching switch operated by the user. In addition, in this case, if it is the above-described implementation 2, for example, the user can also select whether all CPU units 310, 320, 330, and 340 are in "operation stop mode" or "degraded continuation mode" through the engineering design tool 600.

[0135] Furthermore, the central part that serves as the processing center for each CPU unit 310, 320, 330, and 340, which includes a control unit 51, a main storage unit 52, an external storage unit 53, an operation unit 54, a transceiver unit 56, and an internal bus 50, can be configured such that the CPU units 310, 320, 330, and 340 perform the aforementioned processing. Alternatively, the program for performing the aforementioned actions can be stored in a recording medium such as flash memory that is readable by each CPU unit 310, 320, 330, and 340 and then distributed to it, thereby constituting each CPU unit 310, 320, 330, and 340. Alternatively, the program can be pre-stored in a storage device on a server device located on a communication network such as a LAN (Local Area Network) or the Internet and then downloaded to each CPU unit 310, 320, 330, and 340, thus constituting a computer.

[0136] In addition, if the functions of each CPU unit 310, 320, 330, and 340 are implemented through the sharing of the OS (operating system) and applications or the cooperation between the OS and applications, then only the application portion may be stored on the recording medium or storage device.

[0137] Alternatively, the program can be overlaid on a carrier wave and provided via a communication network. For example, the program can be announced on a bulletin board system (BBS) on the communication network and provided via the network. Furthermore, the program can be launched and executed under the control of the OS in the same way as other applications, thereby performing the aforementioned processing.

[0138] This invention allows for various embodiments and modifications without departing from its broad spirit and scope. Furthermore, the above embodiments are illustrative and do not limit the scope of the invention. That is, the scope of the invention is defined not by the embodiments, but by the claims. Moreover, various modifications implemented within the scope of the claims and their equivalents are considered to be included within the scope of this invention.

[0139] Explanation of the label

[0140] 1…PLC, 2…Control system, 10…Basic unit, 20…Power supply unit, 30…CPU unit, 40…I / O unit, 50…Internal bus, 51…Control unit, 52…Main storage unit, 53…External storage unit, 54…Operation unit, 56…Transceiver unit, 59…Control program, 310…First CPU unit, 311…First input / output control unit, 312…First voltage drop detection unit, 313…First reset signal output control unit, 314…First reset signal acquisition unit, 315…First reset execution unit, 316…First output selection unit, 317…First power monitoring IC, 318…First switching switch, 320…Second CPU unit, 321…Second input / output control unit, 322… Second voltage drop detection unit, 323… Second reset signal output control unit, 324… Second reset signal acquisition unit, 325… Second reset execution unit, 326… Second output selection unit, 327… Second power supply monitoring IC, 328… Second switch, 330… Third CPU unit, 331… Third input / output control unit, 332… Third voltage drop detection unit, 333… Third reset signal output control unit, 334… Third reset signal acquisition unit, 335… Third reset execution unit, 336… Third output selection unit, 337… Third power supply monitoring IC, 338… Third switch, 340… Fourth CPU unit, 341… Fourth input / output control unit, 342… Fourth voltage drop detection unit, 343… 344...Fourth reset signal output control unit, 345...Fourth reset execution unit, 346...Fourth output selection unit, 347...First power monitoring IC, 348...First switch, 363...First action confirmation signal output unit, 364...First action confirmation signal acquisition unit, 366...First action stop selection unit, 367...First setting information acquisition unit, 368...First setting information storage unit, 373...Second action confirmation signal output unit, 374...Second action confirmation signal acquisition unit, 376...Second action stop selection unit, 377...Second setting information acquisition unit, 378...Second setting information storage unit, 383...Third action confirmation signal output unit, 384...Third action confirmation signal acquisition unit 386… Third Action Stop Selection Unit, 387… Third Setting Information Acquisition Unit, 388… Third Setting Information Storage Unit, 393… Fourth Action Confirmation Signal Output Unit, 394… Fourth Action Confirmation Signal Acquisition Unit, 396… Fourth Action Stop Selection Unit, 397… Fourth Setting Information Acquisition Unit, 398… Fourth Setting Information Storage Unit, 410… First Input / Output Unit, 420… Second Input / Output Unit, 430… Third Input / Output Unit, 440… Fourth Input / Output Unit, 450… Fifth Input / Output Unit, 500… Communication Line, 501… First Communication Line, 502… First Diode, 503… Second Communication Line, 504… Zener Diode, 505… Third Communication Line, 506… Transistor,507…Fourth communication line, 508…Fifth communication line, 509, 520…First contact, 510…Second diode, 511…Sixth communication line, 512…First terminal, 513…Seventh communication line, 514, 525…Second contact, 515…Second terminal, 516…Eighth communication line, 517…Third terminal, 518, 523, 528, 533, 535…Contacts, 519…Ninth communication line, 521…First pull-up resistor, 52… 2…Tenth signal line, 524…Eleventh signal line, 526…Second pull-up resistor, 527…Twelfth signal line, 529…Thirteenth signal line, 530…Third contact, 531…Third pull-up resistor, 532…Fourteenth signal line, 534…Fifteenth signal line, 536…Fourth pull-up resistor, 537…Sixteenth signal line, 600…Engineering design tool, 610…Setting information generation unit, 620…Setting information output unit, 700…Internet.

Claims

1. A programmable logic controller, comprising a first CPU unit performing a first control and a second CPU unit performing a second control different from the first control, independently controlling an instrument that is the object of control. The first CPU unit has an output section that, in the absence of a detected voltage drop in the internal power supply of the first CPU unit, outputs an operation confirmation signal to the second CPU unit to confirm the operation of the first CPU unit. This programmable logic controller has: The action stop selection unit, when the second CPU unit does not receive the action confirmation signal from the first CPU unit, selects whether to stop the action of the second CPU unit by referring to setting information generated based on information input by the user; and The action stop control unit stops the operation of the second CPU unit when the action stop selection unit selects to stop the operation of the second CPU unit; on the other hand, it does not stop the operation of the second CPU unit when the action stop selection unit selects not to stop the operation of the second CPU unit, but instead allows the second CPU unit to continue performing the second control.

2. A programmable logic controller, comprising a first CPU unit performing a first control and a second CPU unit performing a second control different from the first control, independently controlling an instrument that is the object of control. This programmable logic controller has: The output selection unit selects whether to output an operation stop signal used to stop the operation of the second CPU unit from the first CPU unit to the second CPU unit when it detects a voltage drop in the internal power supply of the first CPU unit. as well as The output control unit, when the output selection unit selects to output the action stop signal, causes the first CPU unit to output the action stop signal; conversely, when the output selection unit selects not to output the action stop signal, it does not cause the first CPU unit to output the action stop signal. The first CPU unit has an output section that, in the absence of a detected voltage drop in the internal power supply of the first CPU unit, outputs an operation confirmation signal to the second CPU unit to confirm the operation of the first CPU unit. The programmable logic controller also features: The action stop selection unit selects whether to stop the action of the second CPU unit when the second CPU unit does not receive the action confirmation signal from the first CPU unit, referring to setting information generated based on information input by the user. as well as The action stop control unit stops the operation of the second CPU unit when the action stop selection unit selects to stop the operation of the second CPU unit; on the other hand, it does not stop the operation of the second CPU unit when the action stop selection unit selects not to stop the operation of the second CPU unit, but instead allows the second CPU unit to continue performing the second control.

3. A CPU unit that controls an instrument independently of other CPU units by performing a second control, which is different from the first control performed by other CPU units installed in a programmable logic controller. This CPU unit has: The action stop selection unit, when it does not receive an action confirmation signal from the other CPU units to confirm the action of those other CPU units, selects whether to stop the action of the CPU unit by referring to setting information generated based on user input; and The action stop control unit, if it does not receive the action confirmation signal from the other CPU units, stops the operation of the CPU unit if the action stop selection unit selects to stop the operation of the CPU unit, and on the other hand, if the action stop selection unit selects not to stop the operation of the CPU unit, does not stop the operation of the CPU unit, but allows the CPU unit to continue performing the second control.

4. A control method for a programmable logic controller (PLC), wherein the PLC independently controls an instrument being controlled by a first CPU unit performing a first control and a second CPU unit performing a second control different from the first control. The control method includes the following steps: The action stop selection step, in the case that the second CPU unit has not received an action confirmation signal from the first CPU unit to confirm the action of the first CPU unit, selects whether to stop the action of the second CPU unit by referring to setting information generated based on information input by the user; and The action stop control step, when the action stop selection step selects to stop the action of the second CPU unit, stops the action of the second CPU unit; on the other hand, when the action stop selection step selects not to stop the action of the second CPU unit, does not stop the action of the second CPU unit, but allows the CPU unit to continue performing the second control.

5. A non-transitory recording medium readable by a computer that records a program that causes a programmable logic controller (PLC) to function as an action stop selection unit and an action stop control unit, wherein the PLC is independently controlled by a first CPU unit performing a first control and a second CPU unit performing a second control different from the first control. If the second CPU unit does not receive an action confirmation signal from the first CPU unit to confirm the action of the first CPU unit, the action stop selection unit selects whether to stop the action of the second CPU unit by referring to setting information generated based on information input by the user. If the action stop control unit selects to stop the action of the second CPU unit when the action stop selection unit selects to stop the action of the second CPU unit, the action stop control unit stops the action of the second CPU unit. On the other hand, if the action stop selection unit selects not to stop the action of the second CPU unit, the action stop control unit does not stop the action of the second CPU unit, but allows the second CPU unit to continue performing the second control.

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