Droop detection and control for digital phase-locked loops

Abstract

An apparatus includes a reference signal generator, a voltage droop detection circuit, a digital frequency locked loop (DFLL), and a DFLL control circuit. The reference signal generator receives a digital value and generates a pulse density modulated signal based on the digital value. The voltage droop detection circuit converts the pulse density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and generates a voltage droop detection signal in response to detecting that the monitored supply voltage is lower than a specified value relative to the analog signal. The DFLL provides a clock signal for a circuit within a domain of the monitored supply voltage. The DFLL control circuit causes the DFLL to slow the clock signal in response to receiving the voltage droop detection signal.

Description

BACKGROUND

[0001] Integrated and discrete circuits include terminals for receiving power from a power supply to provide a source voltage to associated circuitry. Circuitry, such as inverters, is typically connected between the power supply and a circuit common or ground. In the case of a metal oxide semiconductor field effect transistor (MOSFET), a specified voltage at the gate terminal activates the transistor to create a circuit path for driving circuit elements connected between the output terminal and the power supply or ground and driving subsequent circuitry connected to the output terminal. Typically, the amount of current and circuit load is related to both operating speed and power supply voltage. Due to the active nature of many circuits, the load sometimes varies and sometimes causes the supply voltage level to drop or decrease from the desired level.

[0002] Voltage droop is a term used to refer to the drop in voltage from a desired voltage level when a power supply drives a load. In a regulated system, the output voltage can drop when the load increases suddenly and very rapidly. For example, a transient load condition can occur that causes voltage droop. If the droop is too great, circuit failure results.

[0003] In prior art systems, a supply regulation circuit or "head" circuit is operatively disposed between the power supply and the circuitry and is regulated to adjust or compensate for such variations in the power supply. For example, some solutions include a head circuit that switches constantly at a relatively high frequency with respect to other power management features such as power state changes in order to minimize the load from transient responses and regulate the supply voltage. These head circuits are typically optimized to respond very quickly to voltage droop due to transient load conditions and other load conditions.

[0004] These prior art systems typically have a large number of custom analog design blocks and add significant overhead when they switch in and out relatively large field effect transistors in order to respond to transient load conditions. This overhead occurs even when operating in steady state mode. Thus, such systems not only consume valuable integrated circuit substrate area, but are also inefficient from a power perspective. BRIEF DESCRIPTION OF DRAWINGS

[0005] FIG. 1 shows, in block diagram form, a system for regulating the supply voltage to a plurality of processor cores according to the prior art;

[0006] FIG. 2 shows, in part block diagram form and in part schematic form, further details of a droop compensation regulator system according to the prior art;

[0007] Figure 3A A block diagram of a power monitor capable of responding more quickly to voltage droop is shown according to some implementations;

[0008] Figure 3BA power monitor according to additional implementations is shown in block diagram form;

[0009] Figure 4 A power monitor according to additional implementations is shown in mixed block and circuit diagram form;

[0010] Figure 5 A voltage drop detection circuit according to additional implementations is shown in mixed block and circuit diagram form that can respond more quickly to voltage drops while employing reduced area silicon for the circuit;

[0011] Figure 6 Graphs depicting respective signals associated with a power monitor circuit of Figure 4 are shown;

[0012] Figure 7 Block diagrams of power monitors according to some additional implementations are shown;

[0013] Figure 8 Flowcharts showing the operation of an electrical design current mitigation process according to some implementations that provide reduced power consumption are shown;

[0014] Figure 9 Graphs depicting respective signals associated with a power monitor circuit of Figure 7 are shown; and

[0015] Figure 10 An accelerated processing unit (APU) according to some implementations is shown in block diagram form.

[0016] In the following description, like or similar items are denoted by the same reference numbers throughout the different drawings. Unless otherwise stated, the word "coupled" and its associated verb forms mean both directly connected and indirectly connected with intervening items between the items that are coupled, and unless otherwise stated, any description of direct connection implies another alternative implementation of indirect electrical connection using suitable forms. DETAILED DESCRIPTION

[0017] An apparatus includes a reference signal generator, a voltage drop detection circuit, a digital frequency locked loop (DFLL), and a DFLL control circuit. The reference signal generator receives a digital value and produces a pulse density modulated signal based on the digital value. The voltage drop detection circuit converts the pulse density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and produces a voltage drop detection signal in response to detecting that the monitored supply voltage is lower than a specified value relative to the analog signal. The DFLL provides a clock signal for synchronizing circuits within a domain of the monitored supply voltage. The DFLL control circuit causes the DFLL to slow the clock signal in response to receiving the voltage drop detection signal.

[0018] A method of monitoring a power supply. The method includes receiving a binary number and creating a pulse density modulated signal that is scaled based on the binary number. The pulse density modulated signal is converted to an analog signal and compared to a monitored supply voltage. In response to detecting a droop in the monitored supply voltage relative to the analog signal that is lower than a specified value, a droop detection signal is generated. In response to the droop detection signal, the method causes a digital frequency locked loop (DFLL) that provides a clock signal for synchronizing circuitry in a domain of the monitored supply voltage to slow the clock signal.

[0019] A data processing system includes an integrated circuit having at least two processor tiles. Each processor tile includes digital logic, a local DFLL that provides a clock signal for synchronizing the digital logic, and a local power monitor for monitoring a respective monitored local supply voltage. Each power monitor includes a reference signal generator, a droop detection circuit, and a DFLL control circuit. The reference signal generator receives a digital value and generates a pulse density modulated signal based on the digital value. The droop detection circuit converts the pulse density modulated signal to an analog signal, compares the analog signal to the respective monitored local supply voltage, and generates a droop detection signal in response to detecting a droop in the respective monitored local supply voltage relative to the analog signal that is lower than a specified value. The DFLL control circuit causes the local DFLL to slow the clock signal in response to receiving the droop detection signal.

[0020] FIG. 1 shows in block diagram form a system for regulating supply voltages to a plurality of processor cores according to the prior art. A supply voltage VDD 12 is connected to a plurality of supply adjustment blocks (SABs) 14A-C. Each of the supply adjustment blocks 14A-C is connected to produce an adjusted supply voltage to a processor core 16A-C. Each of the processor cores 16A-C includes a power supply monitor (PSM) 30A-C, a fast droop detector (FDD) 26A-C, and a digital low voltage regulator (DLVR) 22A-C. Each DLVR 22A-C is formed within the respective processor core 16A-C. The processor core and its associated circuitry can be referred to as a "processor tile."

[0021] In some versions, a supply adjustment block (SAB) 60 can be used in addition to, or in place of, the supply adjustment block 14. As can be seen, the supply adjustment block 60 is a foot circuit rather than a head circuit, meaning that the supply adjustment block is connected between the processor core and ground rather than between the processor core and the power supply. In versions of the system of Figure 1 that include the adjustment block 60 in the power supply, the particular discrete logic is modified to support the desired operation, and such changes can be readily made in the design by one of ordinary skill in the art. The first voltage regulators (22A-C) and FDDs (26A-C) would remain the same. Thus, for example, the charge injection signals generated by the FDDs 26A-C would be used to activate or select the resistive elements within the supply adjustment block 60. While only one supply adjustment block 60 is shown in dashed lines, it should be understood that multiple supply adjustment blocks 60 can be included in versions of Figure 1. As with the supply adjustment block 14 that includes a head circuit, the second voltage regulator (i.e., the FDD 26A-C) generates a charge injection signal that causes the selected resistive element to be activated to adjust the voltage drop across the supply adjustment block 14A-C, and thus the voltage generated to the processor core 16A-C.

[0022] Figure 2 shows further details of a voltage regulator system that compensates for voltage drops in accordance with one implementation of the present application, in part as a block diagram and in part as a schematic diagram. The supply voltage VDD 12 is connected to a supply adjustment block 14, which in turn generates an adjusted supply voltage to the processor core 16. The magnitude of the adjusted supply voltage is based on a control word, a charge control word, and the value of a charge injection signal generated by the FDD 26 (shown as an additional input to the SAB 14). In the version described, the PSM 30, the DLVR 22, and the FDD 26 are all formed within the processor core block 16 in the version of Figure 2.

[0023] The adjusted supply voltage is provided to the PSM 30, which in turn generates a digital representation of the adjusted supply voltage magnitude to the DLVR 22. The adjusted supply voltage is also generated to the FDD 26. The DLVR 22 is also connected to receive a target adjusted supply voltage (shown as "target") and a voltage drop threshold level from an external source. In one implementation, the external source can be a power management block. The DLVR 22 generates the voltage drop threshold level to the FDD 26. The DLVR 22 also generates the control word "ctrl[(n-1):0]" and the charge control word "chg_ctrl[(n-1):0]" to the supply adjustment block 14.

[0024] FDD 26 includes a digital-to-analog converter (DAC) 62 connected to receive the drop threshold level from DLVR 22 and configured to produce an analog signal to the positive (+) input of comparator 64 of a magnitude corresponding to the received drop threshold level. In the depicted version, DAC 62 is a sigma-delta converter. The negative (-) of comparator 64 is connected to receive the regulated supply voltage produced by supply regulation block 14. Comparator 64 generates a charge injection signal that activates supply regulation block 14 whenever the regulated supply voltage drops below the analog drop threshold level or voltage. It should be noted that with NAND logic in the charge selection block, a logic 1 for the charge injection signal triggers charge injection, or more specifically, triggers the supply voltage regulation for the selected MOSFET. A logic 0 is generated only when the drop threshold is below the regulated supply voltage. It should also be noted that the version of FIG. 2 includes a first voltage regulator (DLVR 22) formed within processor core block 16. In alternative versions, the first voltage regulator (i.e., DLVR 22) can be formed outside of processor core 16.

[0025] FDD 26 performs its processing very quickly by performing an analog comparison of the regulated supply voltage and the drop threshold. Thus, the charge injection signal can be generated almost instantaneously and much faster than based on processor-based digital logic that takes multiple clock cycles to obtain and process all of the necessary data. As such, the second control loop including FDD 26 is a fast-acting control loop to correct or regulate the regulated supply voltage as soon as it drops below the drop threshold level. In contrast, the first regulation loop including the first voltage regulator (DLVR 22) is a slower-acting loop that compares the regulated supply voltage to a target regulated supply voltage value. By utilizing the fast-acting second control loop with FDD 26, a simpler and slower first regulation loop can be utilized to reduce IC board space and associated power consumption. Moreover, because decisions in the second control loop are made in an analog (real-time) manner, the first control loop can be clocked at a lower rate, thereby saving power.

[0026] FIG. 3 shows, in block diagram form, two implementations of a power monitor, labeled 300 Figure 3A ) and 302 Figure 3B ) in accordance with some implementations. Power monitor 300 includes a reference signal generator 320, a fast drop detector 340, a DFLL control circuit 350, a digital frequency locked loop (DFLL) 360, and a finite state machine (FSM) 370. In this implementation, drop detection performed by fast drop detector 340 is used to control DFLL 360 to increase or decrease its output clock signal.

[0027] The reference signal generator 320 has an input connected to the local power controller and receiving a digital number indicative of the reference voltage, and an output providing a modulated digital signal indicative of the reference voltage. The reference voltage is associated with a desired level of the local supply voltage "VDD_CORE" to be monitored. The fast droop detector 340 has an input connected to the output of the reference signal generator 320, an input receiving the VDD_CORE supply voltage, a third input, and an output.

[0028] The DFLL control circuit 350 has an input connected to the output of the fast droop detector 340, and an output connected to the DFLL 360. The DFLL 360 has a plurality of control and enable inputs (not shown), and an output providing a clock signal for circuits within the domain of the supply voltage being monitored.

[0029] The FSM 370 has an input connected to the output of the fast droop detector 340, an output connected to the second input of the fast droop detector 340, and can include a plurality of other control inputs (not shown).

[0030] In operation, the local power controller of the voltage domain of the supply voltage being monitored (in this case VDD_CORE) is operable to adjust the supply voltage being monitored and provide a new value of a binary number corresponding to the adjusted supply voltage being monitored to the reference signal generator 320. The reference signal generator 320 provides a digital modulated signal carrying the provided value. The fast droop detector 340 compares the VDD_CORE supply voltage to the analog signal based on the digital modulated signal to detect a droop in the VDD_CORE supply voltage. Based on detecting such a droop, the fast droop detector 340 sends a droop detection signal to the DFLL control circuit 350. Based on this signal, the DFLL control circuit 350 commands the DFLL 360 to slow the clock, or to stop and subsequently slow the clock for a specified period.

[0031] The power monitor 302 includes the reference signal generator 320, the fast droop detector 340, the DFLL control circuit 350, the digital frequency locked loop DFLL 360, the clock gating 380, and the finite state machine 370. In this particular implementation, Figure 3B The DFLL control scheme is used with the clock gating 380 to provide a faster response to detected droops.

[0032] Figure 3BThe reference signal generator 320 in the reference signal generator 320 has an input connected to the local power controller and receiving a digitally quantized value indicative of a reference voltage and an output providing a modulated digital signal indicative of the reference voltage. The reference voltage is associated with a desired level of the local supply voltage "VDD_CORE" to be monitored. The fast droop detector 340 has an input connected to the output of the reference signal generator 320, an input receiving the VDD_CORE supply voltage, a second input, and an output.

[0033] The DFLL control circuit 350 has an input connected to the output of the fast droop detector 340 and an output connected to the DFLL 360. The DFLL 360 has a plurality of control and enable inputs (not shown) and an output providing a clock signal for circuits within the domain of the monitored supply voltage. The clock gate 380 has a first input connected to the output of the DFLL 360, a second input connected to the output of the fast droop detector 340, and an output for selectively providing the clock signal from the DFLL 360.

[0034] The FSM 370 has an input connected to the output of the fast droop detector 340, an output connected to the second input of the fast droop detector 340, and can include a plurality of other control inputs (not shown).

[0035] In operation of the PSM 302, the local power controller of the voltage domain of the monitored supply voltage is operable to adjust the monitored supply voltage and provide the reference signal generator with a new value of the binary number corresponding to the adjusted monitored supply voltage. The reference signal generator 320 provides a digital modulated signal carrying the provided value. The fast droop detector 340 compares the VDD_CORE supply voltage to the analog signal based on the digital modulated signal to detect a droop in the VDD_CORE supply voltage. Based on detecting such a droop, the fast droop detector 340 sends a droop detection signal to the clock gate 380 and the DFLL control circuit 350. Based on the signal, the clock gate 380 gates the clock to immediately gate the clock, while the DFLL control circuit 350 commands the DFLL 360 to slow down the clock for a specified period. Because the DFLL 360 is relatively slow in responding to the command to effect a change in the clock frequency, the fast droop detector 340 also controls the clock gate 380 to gate the clock signal for the specified period in response to the droop detection signal, thereby reducing the power consumed by the circuits and mitigating the drooped voltage on the VDD_CORE power supply. The FSM 370 controls the specified period by resetting the clock gate signal, such as by controlling a latch.

[0036] Figure 4The power monitor 400 is shown in mixed schematic and circuit diagram form in accordance with a further additional specific implementation. The power monitor 400 includes a limit voltage minimum (XVMIN) detection circuit 410, a digital frequency locked loop DFLL 460, a clock gating 480, and a graphical DFLL FSM 490 (GDFLL FSM). The power monitor 400 is an exemplary implementation of the power monitor of Figure 3B

[0037] The XVMIN detection circuit 410 includes a first input that receives a graphics supply voltage to be monitored labeled "VDDGFX", a second input that receives a system network clock signal labeled "SMNCLK(VDDGFX)", a first output that provides a signal labeled "Xvmin_trig", a second output labeled "Xvmin_clk_stop", a fast drop detector 420, a limit voltage minimum trigger circuit 470 labeled "Xvmin_trigger", an AND gate 472, an OR gate 474, and an AND gate 476.

[0038] In this implementation, the fast drop detector 420 generally includes a reference signal generator that receives a digital value and produces a pulse density modulated signal based on the digital value, and a drop detection circuit that converts the pulse density modulated signal to an analog signal, compares the analog signal to the monitored supply voltage, and produces a drop detection signal in response to detecting a drop in the monitored supply voltage relative to the analog signal that is lower than a specified value. For example, Figure 5 An implementation of a fast drop detector suitable for use as the fast drop detector 420 is shown. The fast drop detector 420 has an input that receives a voltage VDDGFX to be monitored, an input that receives a clock signal SMNCLK(VDDGFX), an input that receives a signal labeled "ResetDD_Xvmin", and an output that provides a signal labeled "DDlatched_sync".

[0039] ​In this implementation of the FSM, Xvmin_trigger 470 is a control circuit and includes an input that receives the DDlatched_sync signal from the fast drop detector 420, an output that provides the ResetDD_Xvmin signal to the fast drop detector 420, an input that receives the clock signal SMNCLK(VDDGFX), and an output that provides the signal labeled "clk_gator."

[0040] Or gate 474 has a first input that receives the signal DDlatched_sync from the fast drop detector 420, a second input that receives the signal clk_gator from the Xvmin_trigger 470, and an output. And gate 472 has a first input that is connected to the output of or gate 474, a second input that receives a clock stop enable signal labeled "Reg_Xvmin_clkstop_en" from a configuration register (not shown), and an output that provides a signal labeled "Xvmin_clk_stop."

[0041] And gate 476 has a first input that receives the signal DDlatched_sync from the fast drop detector 420, a second input that receives an enable signal labeled "Reg_Xvmin_en" from a configuration register (not shown), and an output that provides the signal Xvmin_trig.

[0042] DFLL 460 has a first input that receives a clock signal labeled "RefCLK," a second input that receives a signal labeled "DFLLConfigC[4:0]," a third input that receives a signal labeled "FcsTrig," and an output that provides a clock signal for circuits within the domain of the supply voltage VDDGFX that are used for synchronization monitoring, which in this implementation is the graphics processing core clock labeled "GFXCLK." Clock gating 480 has a first input that receives the clock signal GFXCLK from the DFLL 460, a second input that receives the signal Xvmin_clk_stop from the and gate 472 of the XVMIN detection circuit 410, and an output that provides a gated version of the clock signal GFXCLK.

[0043] The GDFLL FSM 490 includes an input connected to receive the signal Xvmin_trig from the XVMIN detection circuit 410, a frequency control stretch trigger output that provides the signal FcsTrig, a second output that provides a signal DFLLConfigC[4:0] containing the frequency control word (FCW) for the DFLL 460, a control arbitration circuit 495 labeled "Arbitration," a peak current control (PCC) client stretch control circuit 491, a power brake client stretch control circuit 492 labeled "Power Brake," an adaptive PCC client stretch control circuit 493 labeled "APCC," and an XVMIN client stretch control circuit 494 labeled "Xvmin Stretch."

[0044] The PCC client stretch control circuit 491 receives a signal (not shown) from the voltage regulator of the host IC that indicates whether the inductor current associated with the overall IC power supply is at risk of exceeding a maximum threshold. Based on this signal, the PCC client stretch control circuit 491 generates an output that indicates the amount of requested clock stretch (slowdown) that is provided to the control arbitration circuit 495 as the amount of requested frequency control stretch (FCS). The power brake client stretch control circuit 492 receives a signal (not shown) from the system state controller for suppressing power consumption based on workload and generates an output that is provided to the control arbitration circuit 495 that indicates the amount of requested FCS. The APCC 493 has an input that receives a signal (not shown) from the adaptive peak current control circuit that is generated based on the amount of time that the peak current control signal has been active. The APCC 493 generates an output that is provided to the control arbitration circuit 495 that indicates the amount of requested FCS. The Xvmin stretch 494 has an input that receives the signal Xvmin_trig and an output that is connected to the control arbitration circuit 495. The Xvmin stretch 494 generates an output signal to the control arbitration circuit 495 that indicates the amount of requested FCS based on the amount of time that the signal Xvmin_trig has been active.

[0045] The control arbitration circuit 495 has four inputs connected to the outputs of the PCC 491, the power brake 492, the APCC 493, and the Xvmin stretch 494, respectively, and also has respective inputs (not shown) for receiving signals related to their functions. The control arbitration circuit 495 is generally used to select which of the four connected stretch clients will control the amount of clock stretch required by the DFLL 460, as described further below.

[0046] In operation, Figure 4A fast droop detector 420 monitors the supply voltage VDDGFX and will assert an internal signal "Droopdetected" if the voltage crosses some predetermined threshold level. In normal operation, this internal signal is latched at the output of the fast droop detector 420 and is shown as signal DDlatched_sync. The Xvmin_Trig state machine receives the signal DDlatched_sync as an input and initiates the gating of the clock signal GFXCLK through the signal Xvmin_clk_stop. When the frequency of this clock is reduced to no clock, the current drawn from the supply voltage VDDGFX is reduced, causing the VDDGFX rail voltage to come off droop. The signal internal Droopdetected that triggers this sequence is a latched signal so that it remains high regardless of the voltage of VDDGFX unless it is reset by the ResetDD_Xvmin signal from the Xvmin_trig 470. This Droopdetected signal will also be sent as a trigger signal (Xvmin_Trig) to the GDFLL FSM 490.

[0047] The GDFLL FSM 490 has different clients 491, 492, 493, and 494 that request different amounts of extension for different programmable durations. While these particular clients are shown, other clients employed in performance control and power control can be employed, and of course fewer clients can be used in various implementations. The Xvmin extension 494 is one of the clients that requests extension and is triggered by the signal Xvmin_Trig. In response, the Xvmin extension 494 initiates a state sequence to control how the clock frequency is increased back to its earlier state. This sequence is performed by the force extension mode of the DFLL 460 in which a frequency control word that controls the DCO clock frequency in the DFLL 460 is gradually increased to its initial operating state. Typically, when a power delivery network (PDN) that provides the supply voltage VDDGFX responds to a large current change event (referred to as a di / dt event), such as the extreme extension produced by the trigger described above, the supply voltage tends to oscillate between droop and overshoot at the PDN resonant frequency for a few cycles before finally being damped. By increasing the clock frequency in this gradual manner, the circuit depicted ensures that the frequency of the power supply voltage change is much lower than the substantial resonant frequency of the PDN and prevents further oscillation. Different clients can request different amounts of extension at different times, and the control arbitration circuit 495 arbitrates between all of these requests. Preferably, the client that requests the largest amount of extension will get priority and control the DFLL 460.

[0048] Referring in more detail to the triggering process, in this particular implementation, the logic of the GDFLL FSM 490 runs on a clock signal SMNCLK that is shown as exceeding 400 Mhz, rather than on a lower speed system reference clock that is typically about 100 Mhz, to reduce the latency of starting the foldback event. Once the signal DDlatched_sync toggles high, the Xvmin_trigger 470 will be triggered. For a minimum voltage event, the goal of the power monitor 400 is to reduce the frequency of the clock signal GFXCLK as fast as possible, and to foldback as deep as possible. However, any change clock frequency update to the FCW to DFLL 460 will need to go through the GDFLL FSM 490, and the arbitration therein will take several clock cycles. Therefore, in contrast, the Xvmin_trigger 470 generates a signal Xvmin_clock_gator that goes to the clock gating 480. However, even this fast path will take 2-3 SMNCLK (VDDGFX) clock cycles, over which the power monitor 400 operates to synchronize after a voltage drop event. To avoid this additional delay, the signal DDlatched_sync is OR-ed with the clock_gator signal generated by the Xvmin_Trig 470 to control the clock gating 480. DDlatched_sync will remain high once triggered, and therefore it should be free of glitching. Furthermore, the clock gating 480 will synchronize its input internally (over 2-3 GFXCLK cycles and GFXCLK runs at a relatively high frequency), so that no glitching can pass through. In this way, within 2-3 GFXCLK cycles of a voltage drop event (plus logic and propagation delays), the GFXCLK will be stopped.

[0049] In the preferred implementation, the Xvmin_trigger 470 will first reset the latch of the fast voltage drop detector 420 with the ResetDD_Xvmin signal ( Figure 6 ) to make the signal DDlatched_sync signal go low after a programmable count, and then release the clock gating after an additional programmable count of cycles. This sequence ensures the following constraints are followed. First, DDlatched_sync will remain high and stable long enough to be properly synchronized and to enable the Xvmin foldback 494 within the GDFLL FSM 490. Second, by resetting DDlatched_sync before releasing the clock gating, the circuit ensures that the mafdd is ready to react if there is a new voltage drop event (when GFXCLK suddenly recovers).

[0050] The programmability of the signal Xvmin_clock_stop ensures that the circuit is able to stop the clock for at least a few cycles longer than it takes for the FCS extension to propagate through the GDFLL FSM 490 (including arbitration and synchronization) and finally to the DFLL 460 to update its FCW and change to the extended clock frequency.

[0051] Because the DFLL 460 supports an external trigger to extend the output CLK, different parts of the host system can use this extension trigger to implement different features that leverage the DFLL extension functionality. One of these different features is a peak current control (PCC) feature that limits the amount of current that the VDDGFX domain consumes in order to protect the off-chip voltage regulator. There is similar functionality for a power brake (PB) feature for throttling performance. The extension amount for both of these features is the same and can be programmed between 3% and 97.5% of the clock speed. The GDFLL FSM 490 supports a hysteresis counter for both inputs that can be used to filter the extension inputs and make the extension last longer.

[0052] Adaptive PCC (or APCC) is a feature that dynamically changes the extension amount depending on how long the PCC signal has been asserted. The longer the PCC assertion, the higher the extension amount. When the PCC input is de-asserted, the extension amount is decreased instead of switching to 0 abruptly. To implement this feature, the APCC 493 is a programmable state machine within the GDFLL block to control the initial extension, increment extension, maximum extension, decrement extension, final extension, and the time for each step.

[0053] In previous clock extension arbitration schemes, the triggers from different features were ORed or ANDed, i.e., the trigger from any feature would similarly program the DFLL extension amount. Since the XVMIN 410 protects against any voltage excursion above a specified minimum voltage, "Vmin", the Xvmin extension 494 would request more extension amount than other force extension events. However, when the XVMIN 410 disengages from deep extension, the GDFLL FSM 490 would need to compare its own FCS request with other FCS requests from other clients, and whichever client needs the maximum extension would be considered the final FCWoffset. This would ensure that all clients get the protection they need. This arbitration process is implemented within the GDFLL FSM.

[0054] Upon assertion of Xvmin_Trig, Xvmin stretch 494 will generate a maximum FCS stretch amount. This stretch amount is preferably programmable. Upon de-assertion of the Xvmin_Trig input, the stretch amount will gradually decrease to zero, not a non-sudden switch to zero. It will utilize a programmable state machine within the GDFLL block to control the initial stretch, increment stretch, maximum stretch, decrement stretch, final stretch, and time per step. All of the mentioned settings are preferably programmable and controlled through a register interface.

[0055] Figure 5 A portion of a power monitor 500 is shown in mixed block and circuit diagram form in accordance with a further additional implementation. The depicted portion of the power monitor 500 is suitable for use with the monitoring and control topology shown in FIG. 3, Figure 4 and Figure 5 and other circuitry in which the power supply is monitored to detect a fast voltage dip. For example, the design of the power monitor 500 is employed in some implementations to control a charge injection system, such as the prior art systems shown in FIG. 1 and FIG. 2. The power monitor 500 generally includes a reference signal generator 510 and a fast voltage dip detector circuit 550.

[0056] In this implementation, the reference signal generator 510 has an input labeled "fddConfigln" that receives a binary number and an output labeled "LSIN" that provides a pulse density modulated signal. Generally, the reference signal generator 510 operates to scale the pulse density modulated signal based on the binary number. The reference signal generator 510 includes a control circuit 512, an expander 514, and a second order delta sigma modulator 516. The control circuit 512 has a first input that receives a 10-bit binary number carried on the fddConfigln input, a second input that receives a reset signal labeled "resetDD," and an output labeled "ref" that carries a 10-bit binary number. The control circuit 512 generally operates to stop the transfer of the 10-bit binary number when the resetDD indicates that the fast voltage dip detector circuit 550 is disabled or reset, and to transfer the 10-bit binary number to its output when the fast voltage dip detector is operating. The expander 514 has an input that is connected to the output of the control circuit 512 and an output. The expander 514 expands the 10-bit number to a 16-bit number.

[0057] In this implementation, the delta sigma modulator 516 is a second order delta sigma modulator that has an input connected to the output of the expander 514 and an output that provides the pulse density modulated binary signal LSIN. Although a delta sigma modulation is used in this implementation, other suitable modulation schemes can be employed to provide a pulse density modulated signal based on a binary number that represents a desired voltage level of the monitored power supply.

[0058] The reference signal generator 510 generates a bit stream whose average value (ideally) equals the supply voltage VDD at which the reference signal generator 510 operates, scaled by the 10-bit binary number received at the fddConfigln input as a reference. The long-term average output voltage of the bit stream LSIN will correspond to the following Equation 1, where "ref value" is the value of the 10-bit number supplied to the fddConfigln input:

[0059] (1) <lsin>avg = ref_value * VDD

[0060] While this particular modulator design is used in this specific implementation, other specific implementations use other suitable delta-sigma modulator designs or other types of modulators for generating a pulse density modulated signal. The pulse density modulated signal LSIN is fed to an input of the fast droop detector circuit 550.

[0061] The fast droop detector circuit 550 includes a power sniffer 552, a level shifter 554, a low pass filter 551, a comparator 561, a second level shifter 574, a latch 580, a two-to-one multiplexer 576, and an AND gate 578. The fast droop detector circuit 550 is suitable for use in the power monitor circuits of FIGS. 3, Figure 4 and Figure 5 as well as other power monitor circuits.

[0062] The level shifter 554 has a first input that receives the pulse density modulated signal LSIN, a second input that receives an enable signal from the power sniffer 552, and an output that provides the pulse density modulated signal referenced to a clean supply voltage labeled "VDDCR_SOC" at a node labeled 555 (the voltage on this node is referred to as "voltage 555"). The level shifter 554 can also include an inverting input 553 to provide an inverter version of the signal LSIN for use in level shifting. The level shifter 554 is supplied with two voltages for the two domains across which the level shifter converts voltage levels from VDD to VDDCR_SOC.

[0063] The power sniffer 552 has a first input that receives a power indication signal labeled "PwrOkVDD," a second input that receives the clean supply voltage VDDCR_SOC, and an output that is connected to the level shifter 554. The power sniffer 552 enables the level shifter 554 in response to its two inputs when VDD is within a specified range.

[0064] The low pass filter 551 has an input that is coupled to the output of the level shifter 254 and an output. Many low pass filter designs and component values are suitable for use in various implementations.

[0065] The comparator 561 has a first input coupled to the output of the low pass filter 551, a second input that receives the monitored supply voltage VDDCORE, and an output. Generally, the comparator 561 provides a voltage drop detection signal at its output in response to the monitored supply voltage VDDCORE falling below a predetermined level with respect to the first input. In this implementation, the comparator 561 includes a series of four inverters including a first complementary metal-oxide-semiconductor (CMOS) inverter 562, a second CMOS inverter 564, a third CMOS inverter 566, and a fourth CMOS inverter 568. Each inverter 562, 564, 566, and 568 includes a positive supply terminal connected to the second input of the comparator to provide VDDCORE as the supply voltage for the inverter. The CMOS inverter 562 has an input connected to the first input of the comparator, and the inverters 564, 566, and 568 are connected in series after the inverter 562. The output of the inverter 568 provides the voltage drop detection signal to a level shifter 574.

[0066] In this implementation, the inverters 562, 564, 566, and 568 are biased such that they are configured to operate in an "arc-elimination" mode or arc-elimination operating region, in which both the p-type metal-oxide-semiconductor (PMOS) and n-type metal-oxide-semiconductor (NMOS) sides of the inverters are turned on when the monitored supply voltage is at approximately the predetermined level with respect to the voltage on the respective inverter input. In this implementation, the predetermined level is twice the voltage level at the inverter input. Thus, when half of VDDCORE drops below the voltage at the output of the low pass filter 551, the inverters 562, 564, 566, and 568 enter the arc-elimination mode and switch from digital low to digital high to signal a voltage drop. Such operation provides high gain and fast response for detecting a voltage drop below a specified level with respect to a threshold voltage provided at the input of the inverter 562. Since the inverters are biased in the arc-elimination state, they are highly sensitive to any noise on the input VDD rail. In some implementations, at least the inverter 562 or the inverters 562 and 564 are biased in such an arc-elimination state.

[0067] The level shifter 574 has an input connected to the output of the comparator 561 and an output. The level shifter 574 is supplied with both the VDDCORE supply voltage (the monitored voltage) and the VDD supply voltage. The level shifter 574 can also include an inverting input 573 to provide an inverter version of the voltage drop comparator output for use in the level shifting. The level shifter 574 operates to convert the voltage drop detection signal to be referenced to the VDD voltage.

[0068] The multiplexer 576 has a first input connected to the output of the level shifter 574 for receiving the droop detection signal, a second input, a selector input labeled "latchMode," and an output coupled to a clock gate (i.e., 560 in FIG. 3, Figure 5 ) for gating the clock signal in response to the droop detection signal.

[0069] The latch 580 is a set-reset (SR) flip-flop having an "S" input connected to the output of the level shifter 574, an "R" input receiving a reset signal labeled "resetDD_X," a "Q" output connected to the second input of the multiplexer 576, and a "Q-NOT" output which is not used in this implementation. The latchMode input of the multiplexer 576 is used to select between the two inputs.

[0070] The AND gate 578 has a first input receiving an enable signal for the droop detection circuit labeled "FDDEN," a second input receiving the droop detection signal from the output of the multiplexer 576, and an output providing the final output of the fast droop detector circuit 550 labeled "droopDetected."

[0071] In operation, the fast droop detector circuit 550 receives the LSIN pulse density modulated signal. Due to the variability of VDD, this signal needs to be translated to a fixed voltage, which is accomplished by the level shifter 554 provided by VDDCR_SOC. This VDDCR_SOC voltage is a stable regulated voltage that provides a fixed amplitude for the level shifting of the pulse density modulated output of the level shifter 554. The new fixed amplitude signal is fed to the low pass filter 551, which averages the value of the pulse density modulated signal to produce a stable analog voltage for use by the comparator 561. This stable analog value provides a threshold for detecting a droop in the VDDCORE voltage supply. In this implementation, the threshold ("fdd threshold,", Figure 7 ) is twice the voltage of the stable analog value. The low pass filter 551 is a dual RC low pass filter operating with a cutoff frequency below 10 MHz.

[0072] The output of the low pass filter 561 is fed through a series of inverters from the VDDCORE supply acting as an analog comparator 561. Because they are biased in the "snubbing" region, the series of inverters respond quickly to a droop below the specified threshold. Preferably, at least two inverters are used to provide stability to the droop detection signal, and more preferably, at least three or four inverters are used (as shown). The droop detection signal at the output of the comparator 561 is level shifted back into the VDD domain for use in controlling various circuits to mitigate power supply droop, such as FIG. 3, Figure 4 and Figure 5 The clock gating and PLL circuitry depicted. The latch 580 is included to hold the droop detect signal at a digital HIGH for a specified period, providing proper timing for controls that operate such as one-time charge injection operations or PLL adjustments. When the latch 580 is enabled, once triggered, the droop detect signal remains on until actively turned off by the local FSM.

[0073] Figure 6 A plot 600 of the respective signals associated with the power monitoring circuitry 400 of Figure 4 The plot 600 depicts the respective signals associated with the power monitoring circuitry 400 of

[0074] For signal 601, the monitored supply voltage VDDCORE is shown relative to the Xvmin threshold at which the fast droop detector 420 detects a droop. In the depicted scenario, VDDCORE droops below the threshold twice. The fast droop detector 420 detects the droops and generates the "Droop detected" signal shown in plot 602. The XVmin FSM 440 provides the signal "Reset DD_Xvmin" in plot 603, which controls the latch that holds the Droop detected signal to reset it after a droop is detected.

[0075] The signal 604 is the latched droop detect signal DDlatched_sync, which is activated to go HIGH when the droop detect signal activates the latch output, and remains HIGH until it is reset. The XVmin FSM 440 has a programmable period that can be adjusted depending on the use of the DDlatched_sync signal. The signal 605 shows the signal Xvmin_clk_stop, which is generated by the XVMIN detection circuitry 410 in the implementation of Figure 4 The signal 606 shows the normalized clock speed of the DFLL 460 relative to its highest operating speed prior to the droop detection event. As shown in the plot, the DDlatched_sync signal initially gates the clock in the clock gating 408, falling to no clock or 0 normalized level. Then, when the control arbitration circuitry 495 responds to its inputs to start controlling the frequency of the DFLL 460, after three cycles of RefClk, it gradually ramps up the speed of GFXCLK for the DFLL 460. Because in the depicted scenario, a second droop is detected before GFXCLK reaches its fully normalized value, GFXCLK is again gated, and the ramping up process is subsequently completed.

[0076] Figure 7 A block diagram of a power monitor 700 is shown, according to some additional specific implementations for mitigating potential electrical design current (EDC) events. The power monitor 700 includes the reference signal generator 320, the fast droop detector 340, a digital locked loop (DFLL) 360, a DFLL control circuit 745, and a finite state machine 370. Similar to Figure 3A , the fast droop detector 340 performs droop detection for controlling the DFLL 360 to increase or decrease its output clock signal frequency. The FSM 370 also functions similarly to Figure 3A the FSM of

[0077] In this specific implementation, the DFLL control circuit 745 includes additional features for mitigating potential EDC events that can violate peak current constraints of a power supply associated with a socket, e.g., powering a host IC via the socket. Traditionally, EDC events are managed by PCC signals such as the PCC signal provided to the PCC client extension control circuit 491 Figure 4 ) of FIG. 4. Typically, such EDC events are not transient and develop over a time period such as 500 nanoseconds or 1 microsecond. However, because PCC signals are typically generated outside of the host IC, they take a relatively large amount of time to reach the IC’s internal circuitry for throttling and power control functions. The power monitor 700 provides an additional way of measuring such events that occur on-chip, thus enabling a faster response to potential EDC events, and more effectively preventing them.

[0078] The DFLL control circuit 745 has an input connected to the output of the fast droop detector 340, an output connected to the DFLL 360, various digital control logic (not shown) that can be implemented as described above, and a counter 747. The counter value is incremented upon detection of a droop, and decremented towards a 0 value when no droop is detected. In response to the counter value exceeding a specified threshold, the DFLL control circuit 745 provides a signal indicating that there is a potential EDC event that can violate the peak current constraints.

[0079] Figure 8 A flowchart 800 is shown of the operation of an electrical design current mitigation process, according to some specific implementations. The depicted process is suitable for use with the power monitor 700 of Figure 7 or other power monitor circuitry.

[0080] The process begins at block 802, where it is determined whether a droop is detected that is below a defined load line level. The process then continues. If a droop is detected at block 802, the process proceeds to block 804, where a counter such as counter 747 is incremented. If no droop is detected, the process proceeds to block 808, where the counter is decremented. (No action is taken if the counter is already at 0.)

[0081] At block 810, if the counter is above a predetermined threshold for detecting a potential EDC event, the process proceeds to block 812, where an EDC event trigger signal is activated or maintained. Such a signal can be used in various locations on the host IC to trigger a response to a potential EDC event. For example, the process can provide a signal to a stretch client such as the stretch client described with respect to Figure 4 At block 810, if the counter is not above the EDC event threshold, the process starts a separate hysteresis counter to deactivate the EDC event trigger signal. If another is above the threshold at block 810, the hysteresis counter is reset when the EDC threshold is exceeded again. When the hysteresis counter reaches a specified value without being reset, the EDC event trigger signal from block 812 is deactivated. The process is continuous in response to detecting or not detecting a droop, as indicated by the arrow back to block 802.

[0082] Figure 9 A plot 900 is shown that depicts the respective signals associated with the power monitoring circuit 700 of Figure 7 The signals 901, 902, 903, and 904, and 905 depict operation over time as three droops are detected in the monitored supply voltage VDDCORE. The depicted signals are aligned with respect to time.

[0083] In signal 901, the monitored supply voltage (labeled "RVDD" in this example) is shown relative to the Xvmin threshold at which the fast droop detector 420 detects a droop. In this implementation, the Xvmin threshold is set relative to the bottom of the load line (LL) region to enable detection of a potential EDC event. In the depicted scenario, the RVDD droops below the threshold twice. The fast droop detector 420 detects the droops and generates the "Droopdetected" signal shown in plot 902.

[0084] In signal 903, the value of a counter such as counter 747 is incremented each time the Droopdetected signal is valid. As described with respect to Figure 7 Figure 5 ​The depicted unlatched droop detection signal is used for this functionality to provide an accurate value of the counter. The counter is decremented in response to the droop no longer being detected. After the second depicted droop in signal 901, a third droop begins before the counter has fully decremented, causing it to increment again. This droop lasts long enough for the counter to exceed the specified threshold labeled "Xvmin_count_threshold".

[0085] Signal 904 shows the EDC event trigger signal "Xvmin_Trig_filt" generated at block 812 in the process of Figure 8 to indicate an EDC event. Signal Xvmin_trig shows the signal provided by the DFLL control circuit 745 Figure 7 (as shown at block 814 of Figure 8 ) to control the programmable delay "Hysteresis_2" of the period for which the signal Xvmin_trig_filt remains HIGH after being triggered. Signal 905 shows the signal "Xvmin_Trig" which functions similarly to the signal DDLatched_sync shown in Figure 6 to provide a latched version of the Droopdetected signal for stabilizing the functionality of the droop detection circuit. Signal Xvmin_trig shows the programmable delay "Hysteresis_1" provided in this particular implementation by the FSM 370 Figure 7 to control the latch of the fast droop detection circuit 340. As can be seen by comparing signals 904 and 905, the use of the counter process acts as a filter on the Xvmin_trig events such that only events that last a specified number of clock cycles cause a potential EDC event to be recognized and the Xvmin_trig_filt trigger to be activated.

[0086] Figure 10 An accelerated processing unit (APU) 1000 is shown in block diagram form in accordance with some implementations. The APU 1000 is implemented as a system on a chip (SoC), which in various implementations can be part of various host data processing platforms. While an APU is shown in this implementation, other data processing platforms such as central processing units (CPUs) or graphics processing units (GPUs) can be used. For example, in some implementations, the fine-grained memory access techniques herein are embodied in a GPU chip employed in a graphics card or other graphics processing module. In other implementations, a special purpose processor core such as an intelligent processing unit (IPU) can be employed. In this implementation, the APU 1000 generally includes a CPU core complex 1010, graphics cores 1020, a set of display engines 1030, a memory management hub 1040, a data fabric 1050, a set of peripheral controllers 1060, a set of peripheral bus controllers 1070, a system management unit (SMU) 1080, a flash 205, and a set of FG DRAM memory controllers 1090.

[0087] The CPU core complex 1010 includes processor blocks 1012 and 1014, each of which includes a CPU core, a power supply monitor (PSM), a fast drop detector (FDD), and a digital low voltage regulator (DLVR). In this example, the CPU core complex 1010 includes two processor blocks, but in other implementations, the processor block complex 1010 can include any number of processor blocks. Each of the processor blocks 1012 and 1014 is bidirectionally connected to a system management network (SMN) 1045 forming a control fabric, and to the data fabric 1050, and is capable of providing memory access requests to the data fabric 1050. Each of the processor blocks 1012 and 1014 can be a monolithic core, or can also be a core complex of two or more monolithic cores with some resources shared, such as a cache. FIGS. 3 through Figure 5 and Figure 7 The FDD implementations of FIGS. 3 through 6 are applicable to the processor blocks 1012 and 1014 in various implementations. Each FDD controls a local PLL or DFLL for its local CPU core in accordance with the techniques described above.

[0088] Each of the graphics cores 1020 is a high-performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, texture blending, etc., in a highly integrated and parallel manner. In various implementations, the use of an FDD such as FIGS. 3 through 6 can also be implemented in each of the graphics cores 1020. Figure 5 and Figure 7 Power monitoring for FDD. Each graphics core 1020 is bidirectionally connected to the SMN 1045 and to the data fabric 1050, and is able to provide memory access requests to the data fabric 1050. In this regard, the APU 1000 can support a unified memory architecture in which the CPU core complex 1010 and the graphics core complex 1020 share the same memory space, or a memory architecture in which the CPU core complex 1010 and the graphics core complex 1020 share a portion of memory space, while the graphics core complex 1020 also uses private graphics memory that is inaccessible to the CPU core complex 1010.

[0089] The display engine 1030 renders and rasterizes objects generated by the graphics cores 1020 for display on a monitor. The graphics cores 1020 and the display engine 1030 are bidirectionally connected to a common memory management hub 1040 for unified translation to appropriate addresses in memory, and the memory management hub 1040 is bidirectionally connected to the data fabric 1050 for generating such memory accesses and receiving read data returned from the memory system.

[0090] The data fabric 1050 includes a crossbar for routing memory access requests and memory responses between any memory access agent and the memory controller 1090. The data fabric also includes a system memory map defined by the basic input / output system (BIOS) for determining the destination of memory accesses based on system configuration, and buffers for each virtual connection.

[0091] The peripheral controllers 1060 include a USB controller 1062 and a serial advanced technology attachment (SATA) interface controller 1064, each of which is bidirectionally connected to the system hub 1066 and the SMN 1045. These two controllers are merely examples of peripheral controllers that can be used in the APU 1000.

[0092] The peripheral bus controller 1070 includes a system controller hub 1072 and a peripheral controller hub 1074, each of which is bidirectionally connected to an input / output (I / O) hub 1076 and the SMN 1045. The system controller hub 1072 is connected to the flash memory 205 via a suitable communication link. The I / O hub 1076 is also bidirectionally connected to the system hub 1066 and the data fabric 1050. Thus, for example, a CPU core can encode an access to a register in the USB controller 1062, the SATA interface controller 1064, the system controller hub 1072, or the peripheral controller hub 1074 through the I / O hub 1076 via the data fabric 1050.

[0093] The SMU 1080 is a local controller that controls the operation of resources on the APU 1000 and synchronizes communication between those resources. The SMU 1080 manages the power-up sequencing of the various processors on the APU 1000 and controls multiple off-chip devices via reset, enable, and other signals. The SMU 1080 also manages power for the various processors and other functional blocks.

[0094] While a SoC implementation is shown, this is not limiting and other computing platforms can also benefit from the techniques set forth herein.

[0095] Figure 3A Figure 3B Figure 4 Figure 5 Figure 7 The circuitry of Figure 10 or any portion thereof can be described or represented by a computer accessible data structure in the form of a database or other data structure, which can be read by a program and used, directly or indirectly, to fabricate the integrated circuit. For example, the data structure can be a behavioral level description or register transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description can be read by a synthesis tool, which can synthesize the description to produce a netlist comprising a list of gates from a synthesis library. The netlist includes a set of gates and represents the functionality of the hardware. The netlist can then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks are then used in various semiconductor fabrication steps to produce the integrated circuit. Alternatively, the database on the computer accessible memory medium can be the netlist (with or without the synthesis library) or the data set (as required) or a graphical data system (GDS) II data.

[0096] While specific implementations have been described in some detail, various modifications are possible that will be apparent to those skilled in the art. For example, well-known structures have not been described in detail, or have been described only generally, in order to avoid obscuring the present disclosure. Therefore, the accompanying claims are intended to cover all such modifications as fall within the scope of the disclosed implementations.​​​​​​< / lsin>

Claims

1. A device for monitoring power supply, the device comprising: A reference signal generator that receives digital values ​​and generates a pulse density modulation signal based on the digital values; A voltage drop detection circuit converts the pulse density modulation signal into an analog signal, compares the analog signal with a monitored supply voltage, and generates a voltage drop detection signal in response to detecting that the voltage drop of the monitored supply voltage relative to the analog signal is lower than a specified value. A digital frequency-locked loop (DFLL) provides a clock signal for synchronizing circuits within the domain of the monitored supply voltage; and A DFLL control circuit that slows down the clock signal in response to receiving the voltage drop detection signal.

2. The apparatus according to claim 1, further comprising: A clock gating system, coupled to the DFLL, is used to select the clock signal. and A latch having an input that receives the voltage drop detection signal and an output coupled to the clock gating for gating the clock signal in response to the voltage drop detection signal.

3. The apparatus of claim 2, further comprising a state machine having an input for receiving the voltage drop detection signal and an output coupled to control the latch, wherein the state machine controls the latch to hold the voltage drop detection signal for a specified time period after the voltage drop detection circuit no longer detects the voltage drop, and to reset the voltage drop detection signal after the specified time period.

4. The apparatus according to claim 1, wherein the DFLL control circuit comprises: First input, the first input receives the voltage drop detection signal; One or more additional inputs, each receiving a clock extension request signal from a corresponding additional circuit in the integrated circuit; and Arbitration logic, which is used to select which of the voltage drop detection signal and the one or more additional inputs should determine how much the DFLL should be slowed down.

5. The apparatus of claim 1, wherein the DFLL control circuit is further operable to set a DFLL increment at the DFLL for controlling how quickly the DFLL increases the speed of the clock signal after the clock signal is slowed down.

6. The apparatus of claim 1, wherein the voltage drop detection circuit includes a level converter for converting the pulse density modulation signal to a stable and regulated supply voltage as a reference.

7. The apparatus of claim 1, wherein the voltage drop detection circuit includes a comparator, the comparator including a series of inverters, the series of inverters including at least a first complementary metal-oxide-semiconductor (CMOS) inverter and a second CMOS inverter, each including a positive power supply terminal for receiving the monitored supply voltage, the first CMOS inverter including an input for receiving the analog signal, the first CMOS inverter being configured to operate in an arc suppression mode when the monitored supply voltage approaches a specified level.

8. The apparatus according to claim 1, further comprising: A counter receives the voltage drop detection signal from the voltage drop detection circuit, the counter includes a counter value, the counter value increments when the voltage drop detection signal indicates that a voltage drop has been detected, and decrements when the voltage drop detection signal indicates that no voltage drop has been detected. The DFLL control circuit is also operable to compare the counter value with a threshold and, in response to the counter value exceeding the threshold, provide a signal indicating the presence of a potential electrical design current event that may violate peak current constraints.

9. The apparatus of claim 1, wherein the apparatus is a processor.

10. The apparatus of claim 1, wherein the apparatus further comprises a device, the device being one of a laptop computer, desktop computer, smartphone, tablet computer, server, game console, and multimedia device.

11. A method for monitoring a power supply, the method comprising: Receive digital quantized values; Create a pulse density modulated signal scaled based on the digital quantization value; The pulse density modulation signal is converted into an analog signal, and the analog signal is compared with the monitored supply voltage; A voltage drop detection signal is generated in response to the detection that the voltage drop in the monitored supply voltage relative to the analog signal is lower than a specified value; as well as In response to the voltage drop detection signal, a digital frequency-locked loop (DFLL) that provides a clock signal for the circuitry within the domain used to synchronize the monitored supply voltage slows down the clock signal.

12. The method of claim 11, further comprising, in response to the voltage drop detection signal, activating the clock signal within a specified time period.

13. The method of claim 11, further comprising, in response to the voltage drop detection signal, controlling a latch to hold the voltage drop detection signal for a specified time period after the voltage drop detection circuit no longer detects the voltage drop, and resetting the voltage drop detection signal after the specified time period.

14. The method of claim 11, further comprising, after slowing down the clock signal, increasing the speed of the clock signal in a specified periodic increment over time.

15. The method of claim 14, further comprising setting a DFLL increment for controlling how quickly the DFLL increases the speed of the clock signal after the clock signal is slowed down.

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