Semiconductor device and method for manufacturing the same, and electronic device

Abstract

The present disclosure provides a semiconductor device and a method for preparing the same, and an electronic device, which relate to the field of semiconductor chip technology, and can simultaneously form a source ohmic contact and a gate ohmic contact of a semiconductor device. The semiconductor device includes: a substrate and an epitaxial layer stacked on one side of the substrate, a first insulating layer, a gate, a source ohmic contact layer, and a gate ohmic contact layer. The first insulating layer is located on a side of the epitaxial layer away from the substrate, and the gate is located on a side of the first insulating layer away from the substrate; the source ohmic contact layer is located on a side of the epitaxial layer away from the substrate, and the gate ohmic contact layer is located on a side of the gate away from the substrate; wherein the semiconductor device also includes: a second insulating layer, the second insulating layer includes a first sub-portion, and the first sub-portion covers the side of the gate. The above-mentioned semiconductor device is applied to electronic devices.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a preparation method thereof, and an electronic device. Background Art

[0002] Silicon carbide (SiC) has the characteristics of wide bandgap, high breakdown field, high electron saturation drift velocity and high thermal conductivity. It is a semiconductor material often used in high-temperature, high-power and high-frequency devices.

[0003] The performance of semiconductor devices with SiC substrates under forward bias voltage is usually limited by their contact resistance. The ohmic contact between metal and semiconductor means that the contact between metal and semiconductor can act as a pure resistor, which can prevent most of the voltage from acting on the contact surface between metal and semiconductor when the semiconductor device is operating, thereby improving the performance of electronic devices.

[0004] When forming a semiconductor device, for example, the semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the ohmic contact of the source / drain and the ohmic contact of the gate of the MOSFET can be formed step by step, but the process operation of forming the ohmic contact of the source / drain and the ohmic contact of the gate of the MOSFET step by step is more complicated. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor device and a method for preparing the same, and an electronic device, which can simultaneously form a source ohmic contact and a gate ohmic contact of the semiconductor device and improve the uniformity of the ohmic contact layer, thereby improving the electrical performance of the semiconductor device.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a semiconductor device is provided, comprising: a substrate and an epitaxial layer, a first insulating layer, a gate, a source ohmic contact layer and a gate ohmic contact layer stacked on one side of the substrate. The first insulating layer is located on a side of the epitaxial layer away from the substrate, and the gate is located on a side of the first insulating layer away from the substrate; the source ohmic contact layer is located on a side of the epitaxial layer away from the substrate, and the gate ohmic contact layer is located on a side of the gate away from the substrate; wherein the semiconductor device further comprises: a second insulating layer, the second insulating layer comprising a first sub-portion, and the first sub-portion covers the side of the gate.

[0008] The semiconductor device provided by the above-mentioned embodiment of the present disclosure can form a source ohmic contact layer and a gate ohmic contact layer simultaneously. When the source ohmic contact layer and the gate ohmic contact layer are formed simultaneously, due to the setting of the first sub-portion of the second insulating layer, the side of the gate is covered by the second insulating layer, which can effectively avoid the short circuit problem caused by the connection between the source ohmic contact layer and the gate. Therefore, by setting the second insulating layer covering the side of the gate, the ohmic contact of the source and the ohmic contact of the gate of the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can be formed simultaneously.

[0009] In some embodiments, the oxygen content in the first insulating layer is greater than the oxygen content in the second insulating layer.

[0010] In some embodiments, a dimension of the first insulating layer in a direction perpendicular to the substrate ranges from 10 angstroms to 40 angstroms.

[0011] In some embodiments, the second insulating layer further includes a second sub-portion connected to the first sub-portion, and the second sub-portion is located on a side of the gate close to the first insulating layer.

[0012] In some embodiments, a size of the second sub-portion in the direction perpendicular to the substrate is smaller than or equal to a size of the first insulating layer in the direction perpendicular to the substrate.

[0013] In some embodiments, a dimension of the second sub-portion in the direction perpendicular to the substrate ranges from 10 angstroms to 30 angstroms.

[0014] In some embodiments, the semiconductor device further includes: a gate interconnection layer and a gate connection portion, the gate interconnection layer is located on a side of the gate ohmic contact layer away from the substrate; the gate connection portion is located between the gate interconnection layer and the gate ohmic contact layer, and connects the gate interconnection layer and the gate ohmic contact layer.

[0015] In some embodiments, the semiconductor device further includes: a source interconnection layer and a source connecting portion, the source interconnection layer is located on a side of the source ohmic contact layer away from the substrate; the source connecting portion is located between the source interconnection layer and the source ohmic contact layer, and connects the source interconnection layer and the source ohmic contact layer.

[0016] In some embodiments, the gate ohmic contact layer and the source ohmic contact layer include metal silicide, and the metal silicide includes a first metal element; the gate interconnection layer and the source interconnection layer include a second metal element; the material of the gate connection part and the source connection part includes a first metal element, a second metal element and silicon that are mutually fused.

[0017] In some embodiments, the second metal element includes aluminum; wherein the aluminum is embedded in the gate connection portion and the source connection portion in a spike structure.

[0018] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: forming an epitaxial layer on one side of a substrate; forming a first insulating layer, a second insulating layer and a gate in sequence on a side of the epitaxial layer away from the substrate; the gate is located on a side of the first insulating layer away from the substrate, and the first insulating layer does not cover the epitaxial layers on both sides of the gate; forming a first metal layer, the first metal layer covering the gate and the epitaxial layer not covered by the first insulating layer; performing annealing treatment, the first metal layer and part of the epitaxial layer forming a source ohmic contact layer, and the first metal layer and part of the gate forming a gate ohmic contact layer; forming a source interconnection layer and a gate interconnection layer, the source interconnection layer being located on a side of the source ohmic contact layer away from the substrate, and the gate interconnection layer being located on a side of the gate ohmic contact layer away from the substrate, to obtain a semiconductor device.

[0019] In some embodiments, the annealing treatment is performed, and the first metal layer and a portion of the epitaxial layer form a source ohmic contact layer, and the first metal layer and a portion of the gate form a gate ohmic contact layer, including: performing a first annealing treatment, and the first metal layer and a portion of the gate and a portion of the epitaxial layer form a first metal silicide; performing a second annealing treatment, and the first metal silicide forms a second metal silicide, and the second metal silicide on a side of the epitaxial layer away from the substrate forms a source ohmic contact layer, and the second metal silicide on a side of the gate away from the substrate forms a gate ohmic contact layer.

[0020] In some embodiments, before forming the first metal layer, the method further includes: injecting silicon atoms into the epitaxial layer not covered by the first insulating layer; or forming a first silicon film on a side of the epitaxial layer not covered by the first insulating layer away from the substrate.

[0021] In some embodiments, in the epitaxial layer, the ratio of the number of silicon atoms implanted to the number of atoms contained in the material of the epitaxial layer is in the range of 0.5% to 3%.

[0022] In some embodiments, the temperature range of the first annealing treatment is 200°C to 300°C; the temperature range of the second annealing treatment is 400°C to 450°C.

[0023] In some embodiments, the forming of the source interconnection layer and the gate interconnection layer includes: forming an interlayer dielectric layer, the interlayer dielectric layer having a first via hole exposing the source ohmic contact layer and a second via hole exposing the gate ohmic contact layer; injecting silicon atoms into the source ohmic contact layer and the gate ohmic contact layer through the first via hole and the second via hole, or forming a second silicon film on a side of the source ohmic contact layer and the gate ohmic contact layer away from the substrate; forming a second metal layer on a side of the interlayer dielectric layer away from the substrate, a portion of the second metal layer filling the first via hole and contacting the source ohmic contact layer, and another portion of the second metal layer filling the second via hole and contacting the gate ohmic contact layer; performing a third annealing treatment, a portion of the second metal layer and a portion of the source ohmic contact layer fuse to form a source connection portion, and a portion of the second metal layer and a portion of the gate ohmic contact layer fuse to form a gate connection portion; the remaining second metal layer located in the first via hole forms a source interconnection layer, and the remaining second metal layer located in the second via hole forms a gate interconnection layer.

[0024] In some embodiments, in the source ohmic contact layer, the ratio of the number of silicon atoms injected to the number of atoms contained in the material of the source ohmic contact layer is in the range of 0.5% to 3%; and / or, in the gate ohmic contact layer, the ratio of the number of silicon atoms injected to the number of atoms contained in the material of the gate ohmic contact layer is in the range of 0.5% to 3%.

[0025] In some embodiments, the temperature of the third annealing treatment ranges from 200°C to 400°C.

[0026] In some embodiments, the second insulating layer includes: a first sub-portion and a second sub-portion, the first sub-portion covers a side surface of the gate, and the second sub-portion is located on a side of the gate close to the first insulating layer.

[0027] In some embodiments, the first insulating layer, the second insulating layer and the gate are formed on the side of the epitaxial layer away from the substrate, including: forming an initial first insulating layer on the side of the epitaxial layer away from the substrate; forming an initial second insulating layer on the side of the initial first insulating layer away from the substrate; forming a groove on the initial second insulating layer; forming a gate filled in the groove; removing the initial second insulating layer located in the target area to form the second insulating layer; the target area is located on both sides of the gate and has a gap between the gate, and the initial second insulating layer located in the gap is retained to form a first sub-portion of the second insulating layer covering the side of the gate; the initial second insulating layer located on the side of the gate close to the initial first insulating layer forms the second sub-portion; removing the initial first insulating layer located in the target area to form the first insulating layer.

[0028] In some embodiments, before the first annealing treatment, the process further includes: forming a cap layer on a side of the first metal layer away from the substrate; after the first annealing treatment and before the second annealing treatment, the process further includes: removing the cap layer and the remaining first metal layer.

[0029] On the other hand, an electronic device is provided, comprising: a semiconductor device as described in any of the above embodiments; the electronic device further comprises: a substrate, and the semiconductor device is arranged on the substrate.

[0030] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor device and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, etc.

[0032] Figure 1 is a schematic structural diagram of a semiconductor device according to some embodiments;

[0033] Figure 2 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0034] Figure 3is a schematic diagram of the structure of a silicon film layer and an aluminum film layer in contact with each other after rapid annealing according to some embodiments;

[0035] Figure 4 is a scanning electron microscope image of the interface between a silicon film layer and an aluminum film layer in contact with each other after rapid annealing according to some embodiments;

[0036] Figure 5 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0037] Figure 6 to Figure 8 Schematic diagrams of structures corresponding to steps of a method for preparing a semiconductor device according to some embodiments;

[0038] Fig. 9 is a schematic structural diagram of an electronic device according to some embodiments. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0040] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplary" or "some examples" are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner. Words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0043] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0044] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0045] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0046] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc.

[0047] Semiconductor: A semiconductor is a material whose electrical conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor.

[0048] The technical solution of the present application can be applied to electronic devices, which are different types of user devices or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices; the electronic device can also be a network device such as a base station. The electronic device can also be a device such as a power amplifier used in the above electronic devices. The embodiments of the present application do not impose any special restrictions on the specific form of the above electronic devices.

[0049] In some embodiments, in order to improve the contact resistance of the polysilicon gate and source / drain of the transistor, a metal silicide is formed on the polysilicon gate and source / drain to form an ohmic contact between the metal and the semiconductor. The conductive properties of the metal silicide are between those of metal and silicon, which can reduce the contact resistance between the metal and the semiconductor.

[0050] A preparation method for forming an ohmic contact between a metal and a semiconductor may be to deposit a metal on a semiconductor and then perform a rapid annealing process in a rapid thermal annealing (RTA) device to form a metal silicide between the metal and the semiconductor.

[0051] In some examples, when forming a semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET), the ohmic contact of the source / drain and the ohmic contact of the gate of the MOSFET can be formed step by step. For example, after forming the ohmic contact of the source / drain of the MOSFET, the ohmic contact of the gate is formed.

[0052] In order to more conveniently understand the formation of metal silicide on the polysilicon gate and source / drain of MOSFET, the structure of a MOSFET is introduced below.

[0053] In some examples, such as Figure 1As shown, a semiconductor device 100 is provided, which includes: a substrate 10, an epitaxial layer 20 and a gate 30. The epitaxial layer 20 is located on one side of the substrate 10, and the gate 30 is located on a side of the epitaxial layer 20 away from the substrate 10, wherein an insulating layer 40 is further disposed between the gate 30 and the epitaxial layer 20.

[0054] The semiconductor device 100 further includes: a source ohmic contact layer 51 and a gate ohmic contact layer 52, wherein the source ohmic contact layer 51 is located on a side of the epitaxial layer 20 away from the substrate 10, and the gate ohmic contact layer 52 is located on a side of the gate 30 away from the substrate 10. The material of the source ohmic contact layer 51 and the material of the gate ohmic contact layer 52 include metal silicide.

[0055] The source ohmic contact layer 51 is formed by forming a metal silicide by the semiconductor material (e.g., silicon carbide) of the epitaxial layer 20 and a metal deposited on the side of the epitaxial layer 20 away from the substrate 10. The gate ohmic contact layer 52 is formed by forming a metal silicide by the semiconductor material (e.g., polysilicon) of the gate 30 and a metal deposited on the side of the gate 30 away from the substrate 10. The material of the source ohmic contact layer 51 and the material of the gate ohmic contact layer 52 may be the same or different.

[0056] The semiconductor device 100 further includes: an interlayer dielectric layer 60, a source interconnection layer 71 and a gate interconnection layer 72, wherein the interlayer dielectric layer 60 is located on the side of the source ohmic contact layer 51 and the gate ohmic contact layer 52 away from the substrate 10, and the source interconnection layer 71 and the gate interconnection layer 72 both penetrate the interlayer dielectric layer 60. The source interconnection layer 71 is located on the side of the source ohmic contact layer 51 away from the substrate 10, and the gate interconnection layer 72 is located on the side of the gate ohmic contact layer 52 away from the substrate 10. The source interconnection layer 71 is used to input an electrical signal to the source, and the gate interconnection layer 72 is used to input an electrical signal to the gate.

[0057] Exemplarily, the semiconductor device 100 further includes a drain (not shown in the figure), which is located on the side of the substrate 10 away from the epitaxial layer 20, that is, this example is a vertically conductive MOSFET structure. The drain can also be located on the same side of the substrate 10 as the source, and the source and the drain are located on opposite sides of the gate 30.

[0058] In some examples, when metal is deposited on a semiconductor and rapidly annealed by an RTA device to form a metal silicide, one of the factors based on which the required rapid annealing temperature is based includes: the silicon content in the semiconductor. Generally, the higher the silicon content in the semiconductor, the lower the required rapid annealing temperature.

[0059] For example, Figure 1As shown, the material of the epitaxial layer 20 includes silicon carbide (SiC), and the material of the gate 30 includes polysilicon, and the silicon content in the gate 30 material is relatively high. Therefore, the formation temperature of the gate ohmic contact (e.g., 400°C) is generally lower than the formation temperature of the source / drain ohmic contact (e.g., 950°C). Therefore, the source / drain ohmic contact and the gate ohmic contact of the MOSFET are generally formed step by step through different rapid annealing temperatures, and the process operation is relatively complicated.

[0060] If the process conditions and steps for forming the ohmic contact are adjusted to form the ohmic contact of the source / drain and the ohmic contact of the gate of the MOSFET simultaneously, the ohmic contact of the source / drain and the ohmic contact of the gate of the MOSFET can be formed simultaneously in one process, thereby simplifying the process steps.

[0061] However, if Figure 1 As shown, if the ohmic contact of the source / drain and the ohmic contact of the gate of the MOSFET are formed simultaneously, it is necessary to deposit metal simultaneously on the side of the epitaxial layer 20 away from the substrate 10 and the side of the gate 30 away from the substrate 10, so as to form a metal silicide with a semiconductor (for example, including: silicon carbide and polysilicon). However, since the distance d1 between the gate 30 and the epitaxial layer 20 in the first direction Y is small, when the metal is deposited simultaneously on the side of the epitaxial layer 20 away from the substrate 10 and the side of the gate 30 away from the substrate 10, the metal on the side of the epitaxial layer 20 away from the substrate 10 is easily connected to the gate 30, causing a short circuit in the semiconductor device 100. Moreover, the metal silicide formed by the metal and the semiconductor may have residues after etching, and the residual metal silicide may also cause a short circuit in the semiconductor device 100.

[0062] Based on this, Figure 2 As shown, an embodiment of the present disclosure provides a semiconductor device 100 , which includes: a substrate 10 and an epitaxial layer 20 stacked on one side of the substrate 10 .

[0063] Exemplarily, the material of the substrate 10 and the material of the epitaxial layer 20 both include silicon carbide. Compared with the substrate 10 , the epitaxial layer 20 has a controllable crystal structure, which is beneficial to improving the electrical performance of the semiconductor device 100 .

[0064] Exemplarily, the semiconductor device 100 is a MOSFET.

[0065] The semiconductor device 100 further includes: a first insulating layer 41, a gate 30, a source ohmic contact layer 51 and a gate ohmic contact layer 52, wherein the first insulating layer 41 is located on a side of the epitaxial layer 20 away from the substrate 10, the gate 30 is located on a side of the first insulating layer 41 away from the substrate 10, and the gate ohmic contact layer 52 is located on a side of the gate 30 away from the substrate 10. The source ohmic contact layer 51 is located on a side of the epitaxial layer 20 away from the substrate 10.

[0066] Exemplarily, the source ohmic contact layer 51 and the gate 30 do not overlap in the first direction Y, and the first direction Y is a direction perpendicular to the substrate 10 .

[0067] Exemplarily, the material of the first insulating layer 41 includes silicon dioxide.

[0068] Exemplarily, the material of the gate 30 includes polysilicon, and the materials of the source ohmic contact layer 51 and the gate ohmic contact layer 52 both include NiSi2 of C54 phase or TiSi2 of C54 phase. The C54 phase is a face-centered orthorhombic structure. Both NiSi2 of C54 phase and TiSi2 of C54 phase have low resistance and are used to form ohmic contact between semiconductor and metal.

[0069] like Figure 2 As shown, the semiconductor device 100 further includes: a second insulating layer 42 , the second insulating layer 42 includes a first sub-portion 42 a , and the first sub-portion 42 a covers a side surface m3 of the gate 30 .

[0070] Exemplarily, the material of the second insulating layer 42 includes silicon dioxide.

[0071] Exemplarily, the gate 30 includes a first surface m1 and a second surface m2 disposed opposite to each other in the first direction Y, and a side surface m3 connecting the first surface m1 and the second surface m2.

[0072] For example, Figure 2 As shown, the first surface m1 of the gate 30 is the upper surface of the gate 30, the second surface m2 of the gate 30 is the lower surface of the gate 30, and the surface between the upper surface and the lower surface of the gate 30 is the side surface m3 of the gate 30. The first sub-portion 42a of the second insulating layer 42 covers the side surface m3 of the gate 30, that is, the first sub-portion 42a of the second insulating layer 42 covers the side surface m3 of the gate 30.

[0073] When the source ohmic contact layer 51 and the gate ohmic contact layer 52 are formed simultaneously, due to the setting of the first sub-portion 42a of the second insulating layer 42, the side m3 of the gate 30 is covered by the second insulating layer 42, which can effectively avoid the short circuit problem caused by the connection between the source ohmic contact layer 51 and the gate 30. Therefore, by setting the second insulating layer 42 covering the side m3 of the gate 30, the ohmic contact of the source and the ohmic contact of the gate of the MOSFET can be formed simultaneously.

[0074] For example, in Figure 1 In the structure of the semiconductor device 100 shown, if the epitaxial layer 20 is to be connected to the gate 30, the metal or metal silicide can be extended from the epitaxial layer 20 to the lower surface of the gate 30, and the distance is the spacing d1 between the gate 30 and the epitaxial layer 20 in the first direction Y.

[0075] In such Figure 2 In the structure of the semiconductor device 100 shown, if the connection between the epitaxial layer 20 and the gate 30 is to be achieved, the metal or metal silicide needs to extend from the epitaxial layer 20 to the first surface m1 (i.e., the upper surface) of the gate 30, and the distance is the distance d2 from the epitaxial layer 20 to the first surface m1 of the gate 30, and the distance d2 is greater than the spacing d1 between the gate 30 and the epitaxial layer 20 in the first direction Y, i.e., d2>d1. If the ohmic contact of the source and the ohmic contact of the gate of the MOSFET are prepared simultaneously, the second insulating layer 42 can effectively prevent the problem of short circuit of the semiconductor device 100 caused by the connection between the epitaxial layer 20 and the gate 30, so that the process flow of preparing the ohmic contact of the source and the ohmic contact of the gate of the MOSFET can be simplified.

[0076] For an introduction to the preparation method for simultaneously forming the ohmic contacts of the source / drain and the gate of the MOSFET, please refer to the subsequent content and will not be described in detail here.

[0077] In some embodiments, Figure 2 As shown, the oxygen content in the first insulating layer 41 is greater than the oxygen content in the second insulating layer 42 .

[0078] For example, the oxygen content may be the mass percentage or atomic percentage of oxygen in the film layer.

[0079] Exemplarily, the material of the first insulating layer 41 and the material of the second insulating layer 42 both include silicon dioxide. For example, the first insulating layer 41 is formed by a thermal oxidation process, wherein the thermal oxidation process refers to a process in which silicon (Si) reacts with a gas containing an oxidizing substance, such as water vapor and oxygen, at a high temperature to form a dense silicon dioxide (SiO2) film.

[0080] The oxygen content in the first insulating layer 41 is greater than the oxygen content in the second insulating layer 42, so that the first insulating layer 41 has better compactness, wherein compactness refers to the structure of the first insulating layer 41 and the density between the components, and better compactness means that the internal structure of the material of the first insulating layer 41 is more uniform. Moreover, the first insulating layer 41 with better compactness can effectively prevent structural defects caused by carbon aggregation, so that the anti-leakage performance of the first insulating layer 41 can be improved.

[0081] In some examples, such as Figure 2 As shown, a dimension d3 of the first insulating layer 41 in a direction perpendicular to the substrate 10 ranges from 10 angstroms to 40 angstroms.

[0082] It is understood that the dimension d3 of the first insulating layer 41 in the direction perpendicular to the substrate 10 is the thickness of the first insulating layer 41. Exemplarily, the dimension d3 of the first insulating layer 41 in the direction perpendicular to the substrate 10 is 10 angstroms, 20 angstroms, 30 angstroms, 35 angstroms or 40 angstroms, etc., which is not limited here.

[0083] Exemplarily, when the first insulating layer 41 is formed by a thermal oxidation process, the longer the time for forming the first insulating layer 41 is, the larger the size d3 of the first insulating layer 41 in the direction perpendicular to the substrate 10 is. However, in the silicon carbide material of the epitaxial layer 20, the bonding force between carbon and silicon will be affected by the thermal oxidation process. A long thermal oxidation process time will cause the chemical bonds between carbon and silicon to break, thereby causing carbon aggregation and causing structural defects in the epitaxial layer 20. Therefore, the time for forming the first insulating layer 41 by the thermal oxidation process is controlled to obtain a first insulating layer 41 of appropriate thickness. The first insulating layer 41 with a size d3 ranging from 10 angstroms to 40 angstroms in the direction perpendicular to the substrate 10 can meet the requirements of preventing leakage, while avoiding the influence of the thermal oxidation process on the structure of the epitaxial layer 20.

[0084] In some examples, such as Figure 2 As shown, due to the influence of the thermal oxidation process, the thickness of the first insulating layer 41 should not be too thick, and the thickness of the insulating layer 40 between the gate 30 and the epitaxial layer 20 needs to effectively prevent the semiconductor device 100 from being broken down. Therefore, the second insulating layer 42 further includes a second sub-portion 42b connected to the first sub-portion 42a; the second sub-portion 42b is located on the side of the gate 30 close to the second insulating layer 42.

[0085] By disposing the second sub-portion 42 b of the second insulating layer 42 , the thickness of the insulating layer 40 between the gate 30 and the epitaxial layer 20 can be further increased to effectively prevent the semiconductor device 100 from being broken down.

[0086] In some examples, such as Figure 2 As shown, a dimension d4 of the second sub-portion 42 b in a direction perpendicular to the substrate 10 is less than or equal to a dimension d3 of the first insulating layer 41 in a direction perpendicular to the substrate 10 .

[0087] Exemplarily, the dimension d4 of the second sub-portion 42b in the direction perpendicular to the substrate 10 ranges from 10 angstroms to 30 angstroms. For example, the dimension d4 of the second sub-portion 42b in the direction perpendicular to the substrate 10 is 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms or 30 angstroms, etc., which is not limited here.

[0088] By setting the dimension d4 of the second sub-portion 42b in the direction perpendicular to the substrate 10 to be in the range of 10 angstroms to 30 angstroms, and the dimension d3 of the first insulating layer 41 in the direction perpendicular to the substrate 10 to be in the range of 10 angstroms to 40 angstroms, the thickness of the insulating layer 40 between the gate 30 and the epitaxial layer 20 can be made to range from 20 angstroms to 70 angstroms, thereby effectively preventing the semiconductor device 100 from being broken down.

[0089] In some embodiments, Figure 1 and Figure 2 As shown, the semiconductor device 100 further includes: a source interconnection layer 71 , and the source interconnection layer 71 is located on a side of the source ohmic contact layer 51 away from the substrate 10 .

[0090] Since the connection force (for example, intermolecular force) between the material of the source interconnection layer 71 and the material of the source ohmic contact layer 51 is weak, cracks will be generated between the source interconnection layer 71 and the source ohmic contact layer 51 when the semiconductor device 100 operates for a long time, affecting the reliability of the semiconductor device 100.

[0091] The semiconductor device 100 further includes a source connecting portion 81 , which is located between the source interconnection layer 71 and the source ohmic contact layer 51 and connects the source interconnection layer 71 and the source ohmic contact layer 51 .

[0092] The connection force between the source connection portion 81 and the source interconnection layer 71 is greater than the connection force between the source interconnection layer 71 and the source ohmic contact layer 51, and the connection force between the source connection portion 81 and the source ohmic contact layer 51 is greater than the connection force between the source interconnection layer 71 and the source ohmic contact layer 51. Therefore, when the semiconductor device 100 is in a long-term operation state, the provision of the source connection portion 81 can effectively prevent cracks from being generated between the source interconnection layer 71 and the source ohmic contact layer 51, thereby improving the reliability of the semiconductor device 100.

[0093] In some embodiments, Figure 1 and Figure 2 As shown, the semiconductor device 100 further includes a gate interconnection layer 72 , and the gate interconnection layer 72 is located on a side of the gate ohmic contact layer 52 away from the substrate 10 .

[0094] Since the connection force (for example, intermolecular force) between the material of the gate interconnection layer 72 and the material of the gate ohmic contact layer 52 is weak, cracks may be generated between the gate interconnection layer 72 and the gate ohmic contact layer 52 when the semiconductor device 100 is in operation for a long time, thus affecting the reliability of the semiconductor device 100.

[0095] The semiconductor device 100 further includes a gate connecting portion 82 , which is located between the gate interconnection layer 72 and the gate ohmic contact layer 52 and connects the gate interconnection layer 72 and the gate ohmic contact layer 52 .

[0096] The connection force between the gate connection portion 82 and the gate interconnection layer 72 is greater than the connection force between the gate interconnection layer 72 and the gate ohmic contact layer 52, and the connection force between the gate connection portion 82 and the gate ohmic contact layer 52 is greater than the connection force between the gate interconnection layer 72 and the gate ohmic contact layer 52. Therefore, when the semiconductor device 100 is in a long-term operation state, the provision of the gate connection portion 82 can effectively prevent cracks from being generated between the gate interconnection layer 72 and the gate ohmic contact layer 52, thereby improving the reliability of the semiconductor device 100.

[0097] In some embodiments, Figure 2 As shown, the source ohmic contact layer 51 and the gate ohmic contact layer 52 include metal silicide, and the metal silicide includes a first metal element; the source interconnection layer 71 and the gate interconnection layer 72 include a second metal element.

[0098] The materials of the source connecting portion 81 and the gate connecting portion 82 include a first metal element, a second metal element and silicon that are mutually melted.

[0099] For example, the first metal element includes nickel, and the second metal element includes aluminum.

[0100] In some examples, such as Figure 3 and Figure 4 As shown, Figure 3 This is a structural diagram of the contacting silicon film layer 01 and aluminum film layer 02 after rapid annealing. Figure 4 The scanning electron microscope image of the interface m4 between the contacting silicon film layer 01 and the aluminum film layer 02 after rapid annealing. Figure 3 and Figure 4 It can be seen that after the contacting silicon film layer 01 and aluminum film layer 02 are rapidly annealed, at the interface m4 between the silicon film layer 01 and the aluminum film layer 02 , the material of the aluminum film layer 02 diffuses into the silicon film layer 01 to form an aluminum spike structure 03 embedded in the silicon film layer 01 .

[0101] Therefore, if Figure 2As shown, silicon is injected into the source ohmic contact layer 51 or a silicon film is formed on the surface of the source ohmic contact layer 51 so that the source interconnection layer 71 is in contact with silicon, and a rapid annealing process is performed so that aluminum is embedded in the source connection part 81 in a spike structure. Silicon is injected into the gate ohmic contact layer 52 or a silicon film is formed on the surface of the gate ohmic contact layer 52 so that the gate interconnection layer 72 is in contact with silicon, and a rapid annealing process is performed so that aluminum is embedded in the gate connection part 82 in a spike structure. The steps for forming the source connection part 81 and the gate connection part 82 can refer to the subsequent content on the preparation method of the semiconductor device, which will not be described in detail here.

[0102] Since the spike structure formed by aluminum is embedded in the source connection part 81, a strong connection force can be provided between the source interconnection layer 71 and the source connection part 81. In addition, the source connection part 81 includes mutually fused aluminum, silicon, and nickel in the source ohmic contact layer 51, so the connection force between the source connection part 81 and the source ohmic contact layer 51 is greater than the connection force between the source interconnection layer 71 and the source ohmic contact layer 51. Therefore, the provision of the source connection part 81 can effectively prevent cracks from being generated between the source interconnection layer 71 and the source ohmic contact layer 51, thereby improving the reliability of the semiconductor device 100.

[0103] Similarly, since the spike structure formed by aluminum is embedded in the gate connection part 82, a strong connection force can be provided between the gate interconnection layer 72 and the gate connection part 82, and the gate connection part 82 includes mutually fused aluminum, silicon and nickel in the gate ohmic contact layer 52, and the connection force between the gate connection part 82 and the gate ohmic contact layer 52 is greater than the connection force between the gate interconnection layer 72 and the gate ohmic contact layer 52. Therefore, the provision of the gate connection part 82 can effectively prevent cracks from being generated between the gate interconnection layer 72 and the gate ohmic contact layer 52, thereby improving the reliability of the semiconductor device 100.

[0104] In some embodiments, Figure 2 As shown, the semiconductor device 100 further includes: an interlayer dielectric layer 60, which is located on a side of the source ohmic contact layer 51 and the gate ohmic contact layer 52 away from the substrate 10. The interlayer dielectric layer 60 includes: a first via hole H1 and a second via hole H2, the first via hole H1 overlaps with the source ohmic contact layer 51 in a direction perpendicular to the substrate 10, and the second via hole H2 overlaps with the gate ohmic contact layer 52 in a direction perpendicular to the substrate 10.

[0105] The source interconnection layer 71 fills the first via hole H1 and is connected to the source ohmic contact layer 51 and the source connection portion 81, so as to realize the connection between the source interconnection layer 71 and the epitaxial layer 20. The gate interconnection layer 72 fills the second via hole H2 and is connected to the gate ohmic contact layer 52 and the gate connection portion 82, so as to realize the connection between the gate interconnection layer 72 and the gate 30.

[0106] In some embodiments, Figure 5 and Figure 6 As shown, an embodiment of the present disclosure further provides a method for preparing a semiconductor device, the method comprising steps: R1 to R5.

[0107] R1, such as Figure 6 As shown, an epitaxial layer 20 is formed on one side of the substrate 10 .

[0108] Exemplarily, the material of the substrate 10 includes silicon carbide.

[0109] Exemplarily, the material of the epitaxial layer 20 includes silicon carbide.

[0110] R2, such as Figure 6 As shown, a first insulating layer 41, a second insulating layer 42 and a gate 30 are sequentially formed on the side of the epitaxial layer 20 away from the substrate 10. The gate 30 is located on the side of the first insulating layer 41 away from the substrate 10, and the first insulating layer 41 does not cover the epitaxial layer 20 on both sides of the gate 30.

[0111] In some examples, such as Figure 6 As shown, the steps of forming the first insulating layer 41 , the second insulating layer 42 and the gate 30 on the side of the epitaxial layer 20 away from the substrate 10 include: R21 - R26 .

[0112] R21 . Form an initial first insulating layer 411 on a side of the epitaxial layer 20 away from the substrate 10 .

[0113] Exemplarily, the initial first insulating layer 411 is formed by a thermal oxidation process.

[0114] R22. Form an initial second insulating layer 421 on a side of the initial first insulating layer 411 away from the substrate 10.

[0115] Exemplarily, the initial second insulating layer 421 is formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

[0116] R23. Form a groove 421 a on the initial second insulating layer 421 .

[0117] Illustratively, the groove 421 a is formed by an etching process.

[0118] R24. Form a gate 30 filled in the groove 421 a.

[0119] Exemplarily, the initial gate 300 is formed first, and the portion of the initial gate 300 filling the groove 421 a forms the gate 30 .

[0120] Exemplarily, the initial gate 300 is formed by a low pressure chemical vapor deposition process.

[0121] Exemplarily, the portion of the initial gate 300 located outside the groove 421 a is removed by chemical mechanical polishing technology, so that the portion of the initial gate 300 filled in the groove 421 a is formed into the gate 30 .

[0122] R25. Remove the initial second insulating layer 421 located in the target area S1 to form a second insulating layer 42; the target area S1 is located on both sides of the gate 30 and has a gap between the gate 30, and the initial second insulating layer 421 located in the gap is retained to form a first sub-portion 42a of the second insulating layer 42 covering the side of the gate 30; the initial second insulating layer 421 located on the side of the gate 30 close to the initial first insulating layer 411 forms a second sub-portion 42b.

[0123] Exemplarily, an etching process is used to remove the initial second insulating layer 421 located in the target area S1 to form the second insulating layer 42. For example, a photoresist layer 91 is formed on the side of the gate 30 away from the substrate 10. In a direction perpendicular to the substrate 10, the photoresist layer 91 covers the gate 30 and the initial second insulating layer 421 located in the interval. Then, the portion of the initial second insulating layer 421 not covered by the photoresist layer 91 is etched to form the second insulating layer 42, and the first sub-portion 42a covers the side m3 of the gate 30.

[0124] It is understandable that when the first sub-portion 42 a of the second insulating layer 42 is formed, the second sub-portion 42 b of the second insulating layer 42 is formed simultaneously, and the second sub-portion 42 b is located on a side of the gate 30 close to the substrate 10 .

[0125] R26. Remove the initial first insulating layer 411 located in the target area S1 to form a first insulating layer 41.

[0126] For example, a portion of the initial first insulating layer 411 not covered by the photoresist layer 91 is removed to form the first insulating layer 41 .

[0127] R3, such as Figure 7 As shown, a first metal layer 92 is formed, and the first metal layer 92 covers the gate 30 and the epitaxial layer 20 that is not covered by the first insulating layer 41 .

[0128] Exemplarily, the first metal layer 92 includes: a first sublayer 921 and a second sublayer 922; the first sublayer 921 is located on the side of the epitaxial layer 20 away from the substrate 10, and the first sublayer 921 and the gate 30 have no overlap in the direction perpendicular to the substrate 10; the second sublayer 922 is located on the side of the gate 30 away from the substrate 10.

[0129] Exemplarily, the material of the first metal layer 92 includes nickel or titanium.

[0130] Exemplarily, the first metal layer 92 is formed by a deposition process.

[0131] When forming the first metal layer 92 , the first sub-portion 42 a can effectively prevent the first sub-layer 921 of the first metal layer 92 from being connected to the gate 30 , thereby effectively solving the short circuit problem caused by the connection between the gate 30 and the epitaxial layer 20 .

[0132] In some examples, such as Figure 6 As shown, before forming the first metal layer 92, the method for preparing the semiconductor device also includes: injecting silicon atoms into the epitaxial layer 20 not covered by the first insulating layer 41; or, forming a first silicon film (not shown in the figure) on the side of the epitaxial layer 20 not covered by the first insulating layer 41 away from the substrate 10.

[0133] Exemplarily, a plasma ion implantation method is used to implant silicon atoms into the epitaxial layer 20 that is not covered by the first insulating layer 41. The photoresist layer 91 covers the gate 30 and the first sub-portion 42a of the second insulating layer 42, and the area outside the area where the photoresist layer 91 is located is the area of ​​the epitaxial layer 20 that is not covered by the first insulating layer 41. Alternatively, a deposition process is used to form a first silicon film, for example, the thickness of the first silicon film ranges from 10 angstroms to 30 angstroms, for example, the thickness of the first silicon film is 10 angstroms, 20 angstroms, or 30 angstroms, etc., which is not limited here.

[0134] As can be seen from the above introduction to the rapid annealing temperature of the RTA equipment, the higher the silicon content in the semiconductor, the lower the required rapid annealing temperature. Therefore, by increasing the silicon content in the epitaxial layer 20 through silicon atom implantation or forming a first silicon film, the epitaxial layer 20 and the first metal layer 92 can form metal silicide at a relatively low rapid annealing temperature to form an ohmic contact between the semiconductor and the metal.

[0135] In some examples, such as Figure 7 As shown, in the epitaxial layer 20, the ratio of the number of silicon atoms implanted to the number of atoms contained in the material of the epitaxial layer 20 is in the range of 0.5% to 3%.

[0136] For example, the material of the epitaxial layer 20 includes silicon atoms and carbon atoms, and the ratio of the number of implanted silicon atoms to the sum of the silicon atoms and the carbon atoms in the epitaxial layer 20 is in the range of 0.5% to 3%.

[0137] For example, the ratio of the number of implanted silicon atoms to the number of atoms contained in the material of the epitaxial layer 20 is 0.5%, 1%, 1.5%, 2% or 3%, etc., which is not limited here.

[0138] By setting the ratio of the number of atoms of implanted silicon to the number of atoms contained in the material of the epitaxial layer 20 to be in the range of 0.5% to 3%, the epitaxial layer 20 and the first metal layer 92 can form metal silicide at a relatively low rapid annealing temperature.

[0139] In the process of forming an ohmic contact between a metal and a semiconductor, the metal will flow under high temperature conditions, and the metal will cause changes in its structure in the flowing state, such as poor uniformity of the metal thickness, thereby causing poor uniformity of the thickness of the formed metal silicide film layer, and the thickness uniformity of the metal silicide film layer has an important influence on the electrical performance of the semiconductor device 100. Therefore, by injecting silicon atoms or forming a first silicon film to reduce the rapid annealing temperature, at a lower rapid annealing temperature, the temperature has less effect on the metal flow, which is conducive to forming an ohmic contact with better uniformity, thereby improving the electrical performance of the semiconductor device 100.

[0140] After implanting silicon atoms into the epitaxial layer 20 not covered by the first insulating layer 41 , or forming a first silicon film on a side of the epitaxial layer 20 not covered by the first insulating layer 41 away from the substrate 10 , the method for preparing the semiconductor device further includes: stripping the photoresist layer 91 .

[0141] In some embodiments, Figure 7 As shown, after forming the first metal layer 92 , the method for preparing the semiconductor device further includes: forming a cap layer 93 on a side of the first metal layer 92 away from the substrate 10 .

[0142] Exemplarily, the material of the cap layer 93 includes titanium nitride, with a chemical formula of TiN.

[0143] At the rapid annealing temperature, due to the setting of the cap layer 93, the cap layer 93 has a pressing effect on the first metal layer 92, which can effectively reduce the flow problem of the first metal layer 92, thereby further improving the uniformity of the formed ohmic contact, thereby improving the electrical performance of the semiconductor device 100.

[0144] R4, such as Figure 7 As shown, an annealing process is performed, and the first metal layer 92 and a portion of the epitaxial layer 20 form a source ohmic contact layer 51 , and the first metal layer 92 and a portion of the gate 30 form a gate ohmic contact layer 52 .

[0145] like Figure 7As shown, annealing treatment is performed, and the first metal layer 92 and part of the epitaxial layer 20 form a source ohmic contact layer 51, and the first metal layer 92 and part of the gate 30 form a gate ohmic contact layer 52, including steps R41-R42.

[0146] R41, such as Figure 7 As shown, a first annealing process is performed, and the first metal layer 92 and a portion of the gate 30 and a portion of the epitaxial layer 20 form a first metal silicide.

[0147] For example, a portion of the first sublayer 921 close to the epitaxial layer 20 and a portion of the epitaxial layer 20 close to the first sublayer 921 form a first metal silicide; a portion of the second sublayer 922 close to the gate 30 and a portion of the gate 30 close to the second sublayer 922 form a first metal silicide.

[0148] Exemplarily, the temperature range of the first annealing treatment is 200°C to 300°C, for example, the temperature of the first annealing treatment is 200°C, 220°C, 250°C, 260°C, 280°C or 300°C, etc., which is not limited here. The time range of the first annealing treatment is 20s to 30s, for example, the time of the first annealing treatment is 20s, 23s, 25s, 27s, 28s or 30s, etc., which is not limited here.

[0149] In the process of forming the ohmic contact of the gate and the ohmic contact of the source / drain in steps, the temperature of the first annealing of the source / drain is about 650° C. In the method for preparing a semiconductor device provided by the embodiment of the present disclosure, the temperature range of the first annealing treatment is 200° C. to 300° C., and the rapid annealing temperature is relatively low. This is because before forming the first metal layer 92, silicon atoms are implanted into the epitaxial layer 20 or a first silicon film is formed on the surface of the epitaxial layer 20 away from the substrate 10, thereby reducing the rapid annealing temperature.

[0150] It can be seen from the above content that the lower the rapid annealing temperature is, the more conducive it is to forming an ohmic contact with better uniformity, thereby improving the electrical performance of the semiconductor device 100 .

[0151] Exemplarily, the first metal silicide includes Ni2Si of C49 phase or Ti2Si of C49 phase. Wherein, C49 phase refers to a body-centered orthorhombic structure. Compared with NiSi2 of C54 phase, Ni2Si of C49 phase has a higher resistance. Compared with TiSi2 of C54 phase, Ti2Si of C49 phase has a higher resistance.

[0152] R42, such as Figure 7As shown, a second annealing process is performed, and the first metal silicide forms a second metal silicide. The second metal silicide on the side of the epitaxial layer 20 away from the substrate 10 forms a source ohmic contact layer 51, and the second metal silicide on the side of the gate 30 away from the substrate 10 forms a gate ohmic contact layer 52.

[0153] Exemplarily, the second metal silicide includes NiSi2 of C54 phase or TiSi2 of C54 phase.

[0154] Exemplarily, the temperature range of the second annealing treatment is 400°C to 450°C, for example, the temperature of the second annealing treatment is 400°C, 410°C, 420°C, 430°C, 440°C or 450°C, etc., which is not limited here. The time range of the second annealing treatment is 4min to 7min, for example, the time of the second annealing treatment is 4min, 5min, 6min or 7min, etc., which is not limited here.

[0155] In the process of forming the ohmic contact of the gate and the ohmic contact of the source / drain in steps, the temperature of the second annealing of the source / drain is about 950°C. In the method for preparing a semiconductor device provided in the embodiment of the present disclosure, the temperature range of the second annealing treatment is 400°C to 450°C. The lower the rapid annealing temperature, the more conducive it is to forming an ohmic contact with better uniformity, thereby improving the electrical performance of the semiconductor device 100.

[0156] It should be noted that in the process of forming an ohmic contact, two rapid annealing processes are generally used to process the metal and the semiconductor to form the second metal silicide. If a single rapid annealing process is used to process the metal and the semiconductor to form the second metal silicide, the required rapid annealing temperature is much higher than 950° C., which will cause serious diffusion of the metal and the semiconductor, and the formed second metal silicide will cause a short circuit in the semiconductor device 100.

[0157] In some examples, after the first annealing treatment is performed and before the second annealing treatment is performed, the process further includes: removing the cap layer 93 and the remaining first metal layer 92 .

[0158] Exemplarily, an etching solution is used to remove the remaining first metal layer 92. For example, the etching solution includes: NH4OH and H2O2.

[0159] R5, such as Figure 2 and Figure 8 As shown, a source interconnection layer 71 and a gate interconnection layer 72 are formed, the source interconnection layer 71 is located on the side of the source ohmic contact layer 51 away from the substrate 10, and the gate interconnection layer 72 is located on the side of the gate ohmic contact layer 52 away from the substrate 10, thereby obtaining a semiconductor device 100.

[0160] Exemplarily, the material of the source interconnection layer 71 and the material of the gate interconnection layer 72 both include aluminum.

[0161] The steps of forming the source interconnection layer 71 and the gate interconnection layer 72 include: R51 to R54.

[0162] R51 . Form an interlayer dielectric layer 60 . The interlayer dielectric layer 60 has a first via hole H1 exposing the source ohmic contact layer 51 and a second via hole H2 exposing the gate ohmic contact layer 52 .

[0163] R52, injecting silicon atoms into the source ohmic contact layer 51 and the gate ohmic contact layer 52 through the first via hole H1 and the second via hole H2, or forming a second silicon film (not shown) on the side of the source ohmic contact layer 51 and the gate ohmic contact layer 52 away from the substrate 10.

[0164] Exemplarily, a plasma ion implantation method is used to implant silicon atoms into the source ohmic contact layer 51 and the gate ohmic contact layer 52. Alternatively, a deposition process is used to form a second silicon film, for example, the thickness of the second silicon film is in the range of 10 angstroms to 30 angstroms, for example, the thickness of the second silicon film is 10 angstroms, 20 angstroms or 30 angstroms, etc., which is not limited here.

[0165] By injecting silicon atoms into the source ohmic contact layer 51 and the gate ohmic contact layer 52, or forming a second silicon film on the side of the source ohmic contact layer 51 and the gate ohmic contact layer 52 away from the substrate 10, a source connection portion 81 and a gate connection portion 82 are formed. For an introduction to the structure of the source connection portion 81 and the gate connection portion 82, please refer to the above content and will not be repeated here.

[0166] In some examples, in the source ohmic contact layer 51, the ratio of the number of silicon atoms injected to the number of atoms contained in the material of the source ohmic contact layer 51 ranges from 0.5% to 3%; in the gate ohmic contact layer 52, the ratio of the number of silicon atoms injected to the number of atoms contained in the material of the gate ohmic contact layer 52 ranges from 0.5% to 3%.

[0167] Exemplarily, the source ohmic contact layer 51 and the gate ohmic contact layer 52 include silicon atoms and nickel atoms. In the source ohmic contact layer 51, the ratio of the number of silicon atoms implanted to the sum of silicon atoms and nickel atoms in the source ohmic contact layer 51 is in the range of 0.5% to 3%. In the gate ohmic contact layer 52, the ratio of the number of silicon atoms implanted to the sum of silicon atoms and nickel atoms in the gate ohmic contact layer 52 is in the range of 0.5% to 3%.

[0168] For example, the ratio of the number of atoms of the implanted silicon to the number of atoms contained in the material of the source ohmic contact layer 51 is 0.5%, 1%, 1.5%, 2%, or 3%, etc., which is not limited here. The ratio of the number of atoms of the implanted silicon to the number of atoms contained in the material of the gate ohmic contact layer 52 is 0.5%, 1%, 1.5%, 2%, or 3%, etc., which is not limited here.

[0169] The number of silicon atoms to be implanted is set so that the requirements for forming the source connection portion 81 and the gate connection portion 82 are met.

[0170] R53. A second metal layer 701 is formed on a side of the interlayer dielectric layer 60 away from the substrate 10. A portion of the second metal layer 701 fills the first via hole H1 and contacts the source ohmic contact layer 51. Another portion of the second metal layer 701 fills the second via hole H2 and contacts the gate ohmic contact layer 52.

[0171] Exemplarily, the second metal layer 701 is formed by a deposition process, and the material of the second metal layer 701 includes aluminum.

[0172] R54. Perform a third annealing treatment, whereby a portion of the second metal layer 701 and a portion of the source ohmic contact layer 51 fuse together to form a source connection portion 81, and a portion of the second metal layer 701 and a portion of the gate ohmic contact layer 52 fuse together to form a gate connection portion 82; the remaining second metal layer 701 in the first via hole H1 forms a source interconnection layer 71, and the remaining second metal layer 701 in the second via hole H2 forms a gate interconnection layer 72.

[0173] Exemplarily, the temperature range of the third annealing treatment is 200°C to 400°C, for example, the temperature of the third annealing treatment is 200°C, 250°C, 270°C, 300°C, 350°C or 400°C, etc., which is not limited here. The time range of the third annealing treatment is 55min to 65min, for example, the time of the third annealing treatment is 55min, 57min, 59min, 60min, 61min, 62min, 63min, 64min or 65min, etc., which is not limited here.

[0174] Through the third annealing treatment, the portion of the second metal layer 701 located in the first via H1 forms a spike structure embedded in the source connection part 81, and the portion of the second metal layer 701 located in the second via H2 forms a spike structure embedded in the gate connection part 82. For the introduction of the structure of the source connection part 81 and the gate connection part 82, please refer to the above content and will not be repeated here.

[0175] Exemplarily, the second metal layer 701 is etched by an etching process to obtain a source interconnection layer 71 and a gate interconnection layer 72 to form the semiconductor device 100 .

[0176] The embodiment of the present disclosure simultaneously forms the ohmic contact of the source and the ohmic contact of the gate of the semiconductor device 100 through steps R1 to R6, that is, simultaneously forms the source ohmic contact layer 51 and the gate ohmic contact layer 52 of the semiconductor device 100. Moreover, the rapid annealing temperature used is relatively low, which is conducive to forming an ohmic contact with better uniformity, thereby improving the electrical performance of the semiconductor device 100.

[0177] In some examples, when the drain and the source are located on the same side of the substrate 10 , the drain and the source may have the same structure, so that the gate, the source, and the drain are formed by the same preparation process.

[0178] like Fig. 9 As shown, an embodiment of the present disclosure further provides an electronic device 1000, which includes the semiconductor device 100 provided in any of the above embodiments. The electronic device 1000 also includes a substrate 200, on which the semiconductor device 100 is disposed.

[0179] Exemplarily, the electronic device 1000 may be applied to, but not limited to: power supplies, photovoltaic systems, industrial motors, electric vehicles, etc.

[0180] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming an epitaxial layer on one side of the substrate; forming a first insulating layer, a second insulating layer and a gate in sequence on a side of the epitaxial layer away from the substrate; The gate is located on a side of the first insulating layer away from the substrate, and the first insulating layer does not cover the epitaxial layers on both sides of the gate; the second insulating layer includes: a first sub-portion and a second sub-portion, the first sub-portion covers the side of the gate, and the second sub-portion is located on a side of the gate close to the first insulating layer; the oxygen content in the first insulating layer is greater than the oxygen content in the second insulating layer; forming a first metal layer, wherein the first metal layer covers the gate and the epitaxial layer not covered by the first insulating layer; Performing annealing treatment, so that the first metal layer and part of the epitaxial layer form a source ohmic contact layer, and the first metal layer and part of the gate form a gate ohmic contact layer; Forming a source interconnection layer and a gate interconnection layer, wherein the source interconnection layer is located on a side of the source ohmic contact layer away from the substrate, and the gate interconnection layer is located on a side of the gate ohmic contact layer away from the substrate, to obtain a semiconductor device; The step of forming a first insulating layer, a second insulating layer and a gate on a side of the epitaxial layer away from the substrate comprises: forming an initial first insulating layer on a side of the epitaxial layer away from the substrate; forming an initial second insulating layer on a side of the initial first insulating layer away from the substrate; forming a groove on the initial second insulating layer; forming a gate filled in the groove; The initial second insulating layer located in the target area is removed to form the second insulating layer; the target area is located on both sides of the gate and has a gap with the gate, the initial second insulating layer located in the gap is retained to form a first sub-portion of the second insulating layer covering the side of the gate; the initial second insulating layer located on the side of the gate close to the initial first insulating layer forms the second sub-portion; The initial first insulating layer located in the target area is removed to form the first insulating layer.

2. The method for preparing a semiconductor device according to claim 1, wherein: The annealing process is performed so that the first metal layer and a portion of the epitaxial layer form a source ohmic contact layer, and the first metal layer and a portion of the gate form a gate ohmic contact layer, including: Performing a first annealing process, so that the first metal layer, a portion of the gate, and a portion of the epitaxial layer form a first metal silicide; A second annealing treatment is performed, the first metal silicide forms a second metal silicide, the second metal silicide on the side of the epitaxial layer away from the substrate forms a source ohmic contact layer, and the second metal silicide on the side of the gate away from the substrate forms a gate ohmic contact layer.

3. The method for preparing a semiconductor device according to claim 1 or 2, characterized in that: Before forming the first metal layer, the method further comprises: implanting silicon atoms into the epitaxial layer not covered by the first insulating layer; or, A first silicon film is formed on a side of the epitaxial layer not covered by the first insulating layer and away from the substrate.

4. The method for preparing a semiconductor device according to claim 2, characterized in that: In the epitaxial layer, the ratio of the number of silicon atoms implanted to the number of atoms contained in the material of the epitaxial layer is in the range of 0.5% to 3%.

5. The method for preparing a semiconductor device according to claim 2, characterized in that: The temperature range of the first annealing treatment is 200°C to 300°C; the temperature range of the second annealing treatment is 400°C to 450°C.

6. The method for preparing a semiconductor device according to claim 1, wherein: The forming of the source interconnection layer and the gate interconnection layer comprises: forming an interlayer dielectric layer, wherein the interlayer dielectric layer has a first via hole exposing the source ohmic contact layer and a second via hole exposing the gate ohmic contact layer; Injecting silicon atoms into the source ohmic contact layer and the gate ohmic contact layer through the first via hole and the second via hole, or forming a second silicon film on a side of the source ohmic contact layer and the gate ohmic contact layer away from the substrate; forming a second metal layer on a side of the interlayer dielectric layer away from the substrate, wherein a portion of the second metal layer fills the first via hole and contacts the source ohmic contact layer, and another portion of the second metal layer fills the second via hole and contacts the gate ohmic contact layer; A third annealing treatment is performed, whereby a portion of the second metal layer and a portion of the source ohmic contact layer fuse together to form a source connection portion, and a portion of the second metal layer and a portion of the gate ohmic contact layer fuse together to form a gate connection portion; the remaining second metal layer in the first via hole forms a source interconnection layer, and the remaining second metal layer in the second via hole forms a gate interconnection layer.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: In the source ohmic contact layer, the ratio of the number of injected silicon atoms to the number of atoms contained in the material of the source ohmic contact layer is in the range of 0.5% to 3%; and / or, in the gate ohmic contact layer, the ratio of the number of injected silicon atoms to the number of atoms contained in the material of the gate ohmic contact layer is in the range of 0.5% to 3%.

8. The method for preparing a semiconductor device according to claim 6 or 7, characterized in that: The temperature range of the third annealing treatment is 200°C to 400°C.

9. The method for preparing a semiconductor device according to claim 1, wherein: Before the first annealing treatment is performed, the method further includes: forming a cap layer on a side of the first metal layer away from the substrate; After the first annealing treatment and before the second annealing treatment, the method further includes: removing the cap layer and the remaining first metal layer.

10. A semiconductor device obtained by the method for preparing a semiconductor device according to any one of claims 1 to 9, characterized in that: include: A substrate, and an epitaxial layer stacked on one side of the substrate; A first insulating layer, located on a side of the epitaxial layer away from the substrate; a gate, located on a side of the first insulating layer away from the substrate; a source ohmic contact layer and a gate ohmic contact layer, wherein the source ohmic contact layer is located on a side of the epitaxial layer away from the substrate, and the gate ohmic contact layer is located on a side of the gate away from the substrate; The second insulating layer includes a first sub-portion, which covers the side of the gate; the second insulating layer also includes a second sub-portion connected to the first sub-portion, and the second sub-portion is located on the side of the gate close to the first insulating layer; the oxygen content in the first insulating layer is greater than the oxygen content in the second insulating layer.

11. The semiconductor device according to claim 10, characterized in that The first insulating layer has a size ranging from 10 angstroms to 40 angstroms in a direction perpendicular to the substrate.

12. The semiconductor device according to claim 11, characterized in that A size of the second sub-portion in a direction perpendicular to the substrate is smaller than or equal to a size of the first insulating layer in a direction perpendicular to the substrate.

13. The semiconductor device according to claim 12, characterized in that The second sub-portion has a size ranging from 10 angstroms to 30 angstroms in a direction perpendicular to the substrate.

14. The semiconductor device according to claim 10, characterized in that Also includes: A gate interconnection layer, located on a side of the gate ohmic contact layer away from the substrate; The gate connecting portion is located between the gate interconnection layer and the gate ohmic contact layer, and connects the gate interconnection layer and the gate ohmic contact layer.

15. The semiconductor device according to claim 14, characterized in that Also includes: A source interconnection layer, located on a side of the source ohmic contact layer away from the substrate; The source connecting portion is located between the source interconnection layer and the source ohmic contact layer, and connects the source interconnection layer and the source ohmic contact layer.

16. The semiconductor device according to claim 15, characterized in that The gate ohmic contact layer and the source ohmic contact layer include metal silicide, and the metal silicide includes a first metal element; the gate interconnection layer and the source interconnection layer include a second metal element; The materials of the gate connection portion and the source connection portion include a first metal element, a second metal element and silicon that are mutually melted.

17. The semiconductor device according to claim 16, characterized in that The second metal element includes aluminum; wherein the aluminum is embedded in the gate connection part and the source connection part in a spike structure.

18. An electronic device, characterized in that: include: The semiconductor device according to any one of claims 10 to 17; A substrate, on which the semiconductor device is arranged.

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