RF drive circuit, RF power amplifier and RF power supply system

Abstract

The present application provides a radio frequency driving circuit, a radio frequency power amplification device and a radio frequency power supply system, which relate to the field of radio frequency technology. The radio frequency driving circuit includes a first driving unit, a second driving unit, a first switch unit, a second switch unit and a coupling unit; the first switch unit is used to be in a corresponding switching state in response to a first driving signal; the second switch unit is used to be in a corresponding switching state in response to a second driving signal; wherein the first switch unit and the second switch unit cooperate to convert a first power supply voltage into a radio frequency driving signal under the drive of the first driving signal and the second driving signal respectively; the coupling unit is connected to both the first switch unit and the second switch unit, and the coupling unit is used to couple the radio frequency driving signal to the control electrode of at least one radio frequency transistor to drive at least one radio frequency transistor to be turned on or off. The present application can drive at least one radio frequency transistor.

Description

Technical Field

[0001] The present application relates to the field of radio frequency technology, and in particular to a radio frequency drive circuit, a radio frequency power amplifier device, and a radio frequency power supply system. Background Art

[0002] At present, with the rapid development of radio frequency technology, radio frequency power supplies are increasingly used in various core devices to provide electrical energy for various core devices. In addition, during the operation of the radio frequency power supply, it is often necessary to amplify the radio frequency signal output by the radio frequency power supply to meet the power requirements of various core devices. However, in high-frequency and high-power application scenarios, the input capacitance of the radio frequency transistor for radio frequency power amplification is large, and sufficient driving current is required to ensure the normal operation of the radio frequency transistor. The existing driving circuit often cannot meet the driving conditions of the radio frequency transistor. Therefore, how to meet the driving conditions of the radio frequency transistor to drive the radio frequency transistor to work normally has become a problem that needs to be considered. Summary of the invention

[0003] The present application provides a radio frequency driving circuit, a radio frequency power amplification device and a radio frequency power supply system, which can meet the driving conditions of a radio frequency transistor to drive at least the radio frequency transistor to work normally.

[0004] In a first aspect, a radio frequency driving circuit is provided, the radio frequency driving circuit is used to drive at least one radio frequency transistor, and the radio frequency driving circuit includes: a first driving unit, a second driving unit, a first switching unit, a second switching unit and a coupling unit; the first driving unit is used to output a first driving signal; the second driving unit is used to output a second driving signal; the first switching unit is connected to the first driving unit, and the first switching unit is used to be in a corresponding switching state in response to the first driving signal; the second switching unit is connected to the second driving unit, and the second switching unit is used to be in a corresponding switching state in response to the second driving signal; wherein the first switching unit and the second switching unit cooperate to convert a first power supply voltage into a radio frequency driving signal under the drive of the first driving signal and the second driving signal respectively; the coupling unit is connected to both the first switching unit and the second switching unit, and the coupling unit is used to couple the radio frequency driving signal to the control electrode of the at least one radio frequency transistor to drive the at least one radio frequency transistor to be turned on or off.

[0005] In a possible implementation, the RF driving circuit further includes a first dead zone adjustment circuit and a second dead zone adjustment circuit, the first dead zone adjustment circuit is connected to the first driving unit, the first dead zone adjustment circuit is used to obtain a first control signal according to an original pulse width modulation signal, and output the first control signal to the first driving unit, the second dead zone adjustment circuit is connected to the second driving unit, the second dead zone adjustment circuit is used to obtain the second control signal according to the original pulse width modulation signal, and output the second control signal to the second driving unit; wherein the first driving unit obtains the first driving signal at least according to the first control signal, and the second driving unit obtains the second driving signal at least according to the second control signal.

[0006] In a possible implementation manner, the first drive signal includes a first sub-drive signal and a second sub-drive signal, the first sub-drive signal and the second sub-drive signal are complementary, the second drive signal includes a third sub-drive signal and a fourth sub-drive signal, the third sub-drive signal and the fourth sub-drive signal are complementary, the RF drive circuit further includes two first input ports, each of the first input ports is used to input the first power supply voltage; the first switch unit includes a first switch and a second switch, the first switch and the second switch are connected in series between one of the first input ports and the ground, the connection point between the first switch and the second switch is connected to the coupling unit, the control electrode of the first switch and the control electrode of the second switch are both connected to the first drive unit, wherein the first switch and the second switch are alternately turned on according to the driving of the first sub-drive signal and the second sub-drive signal; The second switch unit includes a third switch and a fourth switch, wherein the third switch and the fourth switch are connected in series between another first input port and the ground, a connection point between the third switch and the fourth switch is connected to the coupling unit, and a control electrode of the third switch and a control electrode of the fourth switch are both connected to the second driving unit, wherein the third switch and the fourth switch are alternately turned on according to the driving of the third sub-driving signal and the fourth sub-driving signal; wherein the first sub-driving signal and the third sub-driving signal are in phase, so that when the first switch and the fourth switch are turned on, the second switch and the third switch are turned off, and when the first switch and the fourth switch are turned off, the second switch and the third switch are turned on, and the first power supply voltage obtains the RF driving signal of the AC signal according to the on or off state of the first switch, the second switch, the third switch and the fourth switch.

[0007] In a possible implementation, the first switch unit further includes a first inductor and a first capacitor, which are connected in series at both ends of the second switch, wherein a resonant frequency of the first inductor and the parasitic capacitance of the first switch or the first inductor and the parasitic capacitance of the second switch is greater than a switching frequency of the first switch, the second switch, the third switch, and the fourth switch; the second switch unit further includes a second inductor and a second capacitor, which are connected in series at both ends of the fourth switch, wherein a resonant frequency of the second inductor and the parasitic capacitance of the third switch or the second inductor and the parasitic capacitance of the fourth switch is greater than a switching frequency of the first switch, the second switch, the third switch, and the fourth switch.

[0008] In a possible implementation, the at least one RF transistor includes a first RF transistor; the coupling unit includes a first transformer, the first transformer having a first winding and a second winding, one end of the first winding is connected to a connection point between the first switch and the second switch, the other end of the first winding is connected to a connection point between the third switch and the fourth switch, one end of the second winding is connected to a control electrode of the first RF transistor, and the other end of the second winding is grounded, wherein the RF drive signal on one side of the first winding is coupled to one side of the second winding, and drives the first RF transistor in a positive half cycle of the RF drive signal of the AC signal.

[0009] In a possible implementation, the at least one RF transistor also includes a second RF transistor; the coupling unit also includes a second transformer, the second transformer having a third winding and a fourth winding, one end of the third winding is connected to the connection point between the first switch and the second switch, the other end of the third winding is connected to the connection point between the third switch and the fourth switch, one end of the fourth winding is grounded, and the other end of the second winding is connected to the control electrode of the second RF transistor, wherein the RF drive signal on one side of the third winding is coupled to one side of the fourth winding, and drives the second RF transistor in the negative half cycle of the RF drive signal of the AC signal.

[0010] In a possible implementation manner, the first control signal includes a first sub-control signal and a second sub-control signal, the first sub-control signal and the second sub-control signal have a first dead time period in which they are both at a low level, the second control signal includes a third sub-control signal and a fourth sub-control signal, the third sub-control signal and the fourth sub-control signal have a second dead time period in which they are both at a low level; the first driving unit includes a first driving module and a second driving module, the first driving module is connected to a control electrode of the first switch, the first driving module is used to power amplify the first sub-control signal to obtain the first sub-driving signal, the second driving module is connected to a control electrode of the second switch, the second driving module is used to power amplify the second sub-control signal to obtain the second sub-driving signal; the second driving unit includes a third driving module and a fourth driving module, the third driving module is connected to a control electrode of the third switch, the third driving module is used to power amplify the third sub-control signal to obtain the third sub-driving signal, the fourth driving module is connected to a control electrode of the fourth switch, the fourth driving module is used to power amplify the fourth sub-control signal to obtain the fourth sub-driving signal.

[0011] In a possible implementation, the first driving unit further includes a first power isolation module, a first signal isolation module and a second signal isolation module, the first power isolation module is respectively connected to the first signal isolation module and the first driving module, the first signal isolation module is connected between the first dead zone adjustment circuit and the first driving module, and the second signal isolation module is connected between the first dead zone adjustment circuit and the second driving module, wherein a second power supply voltage provides power to the first driving module, the second driving module, the first signal isolation module and the second signal isolation module, the first power isolation module is used to isolate a power supply outputting the second power supply voltage from the first driving module and the first signal isolation module, the first signal isolation module is used to isolate the first dead zone adjustment circuit from the first driving module, and the second signal isolation module is used to isolate the first dead zone adjustment circuit from the second driving module The second driving unit further comprises a second power supply isolation module, a third signal isolation module and a fourth signal isolation module, wherein the second power supply isolation module is respectively connected to the third signal isolation module and the third driving module, the third signal isolation module is connected between the second dead zone adjustment circuit and the third driving module, and the fourth signal isolation module is connected between the second dead zone adjustment circuit and the fourth driving module, wherein a second power supply voltage provides electrical energy for the third driving module, the fourth driving module, the third signal isolation module and the fourth signal isolation module, the second power supply isolation module is used to isolate a power supply that outputs the second power supply voltage from the third driving module and the third signal isolation module, the third signal isolation module is used to isolate the second dead zone adjustment circuit from the third driving module, and the fourth signal isolation module is used to isolate the second dead zone adjustment circuit from the fourth driving module.

[0012] In a second aspect, a radio frequency power amplification device is also provided, the radio frequency power amplification device comprising a radio frequency driving circuit. The radio frequency driving circuit is used to drive at least one radio frequency transistor, and the radio frequency driving circuit comprises: a first driving unit, a second driving unit, a first switching unit, a second switching unit and a coupling unit; the first driving unit is used to output a first driving signal; the second driving unit is used to output a second driving signal; the first switching unit is connected to the first driving unit, and the first switching unit is used to be in a corresponding switching state in response to the first driving signal; the second switching unit is connected to the second driving unit, and the second switching unit is used to be in a corresponding switching state in response to the second driving signal; wherein the first switching unit and the second switching unit cooperate to convert the first power supply voltage into a radio frequency driving signal under the drive of the first driving signal and the second driving signal respectively; the coupling unit is connected to both the first switching unit and the second switching unit, and the coupling unit is used to couple the radio frequency driving signal to the control electrode of the at least one radio frequency transistor to drive the at least one radio frequency transistor to be turned on or off.

[0013] In a third aspect, a radio frequency power supply system is further provided, wherein the radio frequency power supply system comprises a radio frequency power amplification device and the radio frequency power amplification device comprises a radio frequency driving circuit.

[0014] The RF drive circuit, RF power amplification device and RF power supply system of the present application are configured such that the first switch unit and the second switch unit are in corresponding switching states in response to the corresponding first drive signal and the second drive signal respectively, thereby cooperating to convert the first power supply voltage into an RF drive signal, and the RF drive signal is coupled to the control electrode of at least one RF transistor by configuring a coupling unit, so as to provide sufficient drive current for at least one RF transistor in high-frequency and high-power application scenarios, meet the drive conditions of at least one RF transistor, and then drive at least one RF transistor to be turned on or off. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0016] Figure 1 Schematic diagram of a block diagram of a radio frequency driving circuit in an embodiment of the present application.

[0017] Figure 2 It is a block diagram of a radio frequency driving circuit in yet another embodiment of the present application.

[0018] Figure 3 Schematic diagram of a radio frequency driving circuit in an embodiment of the present application.

[0019] Figure 4 4 is a block diagram of a first dead zone adjustment circuit in an embodiment of the present application.

[0020] Figure 5 4 is a block diagram of a first dead zone adjustment circuit in yet another embodiment of the present application.

[0021] Figure 6 3 is a waveform diagram of the first sub-control signal, the second sub-control signal, etc. in one embodiment of the present application.

[0022] Figure 7 FIG. 4 is a circuit diagram of a first dead zone adjustment circuit in an embodiment of the present application.

[0023] Figure 8 Schematic diagram of a circuit of a first bidirectional control module in an embodiment of the present application.

[0024] Fig. 9 Schematic diagram of a circuit of a second bidirectional control module in an embodiment of the present application.

[0025] Fig.10 FIG. 4 is a block diagram of a first dead zone adjustment circuit in yet another embodiment of the present application.

[0026] Fig.11 FIG. 4 is a block diagram of a first dead zone adjustment circuit in another embodiment of the present application.

[0027] Fig.12 It is a block diagram of a radio frequency power amplification device in one embodiment of the present application.

[0028] Fig.13 It is a block diagram of a radio frequency power supply system in one embodiment of the present application.

[0029] Description of the accompanying drawings: 2000, RF power supply system, RF, RF power supply, 1000, RF power amplifier device, RFMOS1, first RF transistor, RFMOS2, second RF transistor, 10, RF driving circuit, V2, second power supply voltage, 100, first driving unit, 110, first driving module, 120, second driving module, 130, first power isolation module, 140, first signal isolation module, 150, second signal isolation module, VS1, first driving signal, VG1, first sub-driving signal, VG2, second sub-driving signal, 200, second driving unit, 210, third driving module, 220, fourth driving module, 230, second power isolation module, 240, first Three signal isolation modules, 250, fourth signal isolation module, VS2, second drive signal, VG3, third sub-drive signal, VG4, fourth sub-drive signal, V1, first power supply voltage, 300, first switch unit, Q1, first switch, Q2, second switch, L1, first inductor, C1, first capacitor, Vsw1, first connection point voltage, 400, second switch unit, Q3, third switch, Q4, fourth switch, L2, second inductor, C2, second capacitor, Vsw2, second connection point voltage, 500, coupling unit, 510, first transformer, W1, first winding, W2, second winding, 520, second transformer, W3, third winding, W4, fourth winding, VRF, RF drive signal, PWM, original pulse width modulation signal, 600, first dead zone adjustment circuit, P1, first pulse width modulation signal, P2, second pulse width modulation signal, 610, first dead zone adjustment unit, In1, first input terminal, In2, second input terminal, Out1, first output terminal, 611, first logic gate, OP1, first operation result signal, 612, first bidirectional control module, R1, first resistor, D1, first diode, R2, second resistor, D2, second diode, C3, third capacitor, 613, first trigger, Pm1, first intermediate pulse width modulation signal, 620, second dead zone adjustment unit, In3, third input terminal, In4, fourth input terminal, Out2, second output terminal, 621, second logic gate gate, OP2, second operation result signal, 622, second bidirectional control module, R3, third resistor, D3, third diode, R4, fourth resistor, D4, fourth diode, C4, fourth capacitor, 623, second trigger, Pm2, second intermediate pulse width modulation signal, 630, first inversion unit, In5, first inversion input terminal, Out3, first inversion output terminal, 640, second inversion unit, In6, second inversion input terminal, Out4, second inversion output terminal, 650, first buffer unit, 660, second buffer unit, 670, control unit, 671, third logic gate, 672, fourth logic gate, EN, enable signal, CS1, first control signal, PWM1, first sub-control signal,PWM2, second sub-control signal, T1, first time period, T2, second time period, T3, third time period, T4, fourth time period, ta, first sub-time period, tb, second sub-time period, tc, third sub-time period, td, fourth sub-time period, 700, second dead zone adjustment circuit, CS2, second control signal, PWM3, third sub-control signal, PWM4, fourth sub-control signal, EP, equipotential, GND, ground. , DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] In the following, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third", "fourth", etc. may explicitly or implicitly include one or more of the feature. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more.

[0033] In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or device.

[0034] See also Figure 1 , Figure 1 FIG. 1 is a block diagram of a radio frequency driving circuit in an embodiment of the present application. Figure 1As shown, the present application provides a radio frequency driving circuit 10, the radio frequency driving circuit 10 is used to drive at least one radio frequency transistor, and the radio frequency driving circuit 10 includes: a first driving unit 100, a second driving unit 200, a first switching unit 300, a second switching unit 400 and a coupling unit 500; the first driving unit 100 is used to output a first driving signal VS1; the second driving unit 200 is used to output a second driving signal VS2; the first switching unit 300 is connected to the first driving unit 100, and the first switching unit 300 is used to respond to the first driving signal VS1 and be in a corresponding switching state; the second switching unit 200 is used to output a second driving signal VS2; the first switching unit 300 is connected to the first driving unit 100, and the first switching unit 300 is used to respond to the first driving signal VS1 and be in a corresponding switching state; The element 400 is connected to the second driving unit 200, and the second switch unit 400 is used to be in a corresponding switching state in response to the second driving signal VS2; wherein the first switch unit 300 and the second switch unit 400 cooperate to convert the first power supply voltage V1 into a RF driving signal VRF under the drive of the first driving signal VS1 and the second driving signal VS2 respectively; the coupling unit 500 is connected to both the first switch unit 300 and the second switch unit 400, and the coupling unit 500 is used to couple the RF driving signal VRF to the control electrode of at least one RF transistor to drive at least one RF transistor to be turned on or off.

[0035] Thus, the above-mentioned RF driving circuit 10 in the present application is in a corresponding switching state by setting the first switch unit 300 and the second switch unit 400 to respond to the corresponding first drive signal VS1 and the second drive signal VS2 respectively, so as to cooperate in converting the first power supply voltage V1 into the RF drive signal VRF, and by setting the coupling unit 500, the RF drive signal VRF is coupled to the control electrode of at least one RF transistor, so as to provide sufficient driving current for at least one RF transistor in a high-frequency and high-power application scenario, meet the driving conditions of at least one RF transistor, and then drive at least one RF transistor to be turned on or off.

[0036] Specifically, the high-frequency application scenario may be an RF frequency such as 13.56 MHz. In such a high-frequency, high-power application scenario, the input capacitance of at least one RF transistor reaches 5000 pF or even higher, and the input capacitance of at least one RF transistor needs to be charged and discharged at high frequency to enable at least one RF transistor to operate normally.

[0037] See also Figure 2 , Figure 2 FIG. 1 is a block diagram of a radio frequency driving circuit in another embodiment of the present application. Figure 2As shown, the RF driving circuit 10 also includes a first dead zone adjustment circuit 600 and a second dead zone adjustment circuit 700. The first dead zone adjustment circuit 600 is connected to the first driving unit 100, and the first dead zone adjustment circuit 600 is used to obtain a first control signal CS1 according to an original pulse width modulation signal PWM, and output the first control signal CS1 to the first driving unit 100. The second dead zone adjustment circuit 700 is connected to the second driving unit 200, and the second dead zone adjustment circuit 700 is used to obtain a second control signal CS2 according to the original pulse width modulation signal PWM, and output the second control signal CS2 to the second driving unit 200; wherein the first driving unit 100 at least obtains the first driving signal VS1 according to the first control signal CS1, and the second driving unit 200 at least obtains the second driving signal VS2 according to the second control signal CS2.

[0038] Therefore, the RF driving circuit 10 in the present application respectively performs dead zone adjustment on the original pulse width modulation signal PWM by setting the first dead zone adjustment circuit 600 and the second dead zone adjustment circuit 700 to obtain the first control signal CS1 and the second control signal CS2 accordingly.

[0039] See also Figure 3 , Figure 3 FIG. 1 is a circuit diagram of a radio frequency driving circuit in an embodiment of the present application. Figure 3As shown, the first driving signal VS1 includes a first sub-driving signal VG1 and a second sub-driving signal VG2, the first sub-driving signal VG1 and the second sub-driving signal VG2 are complementary, the second driving signal VS2 includes a third sub-driving signal VG3 and a fourth sub-driving signal VG4, the third sub-driving signal VG3 and the fourth sub-driving signal VG4 are complementary, the RF driving circuit 10 also includes two first input ports, each of which is used to input the first power supply voltage V1; the first switching unit 300 includes a first switch Q1 and a second switch Q2, the first switch Q1 and the second switch Q2 are connected in series between one of the first input ports and the ground GND, the connection point between the first switch Q1 and the second switch Q2 is connected to the coupling unit 500, the control electrode of the first switch Q1 and the control electrode of the second switch Q2 are both connected to the first driving unit 100, wherein the first switch Q1 and the second switch Q2 are alternately turned on according to the driving of the first sub-driving signal VG1 and the second sub-driving signal VG2; The second switch unit 400 includes a third switch Q3 and a fourth switch Q4, which are connected in series between another first input port and the ground GND, a connection point between the third switch Q3 and the fourth switch Q4 is connected to the coupling unit 500, a control electrode of the third switch Q3 and a control electrode of the fourth switch Q4 are both connected to the second driving unit 200, wherein the third switch Q3 and the fourth switch Q4 are alternately turned on according to the driving of the third sub-driving signal VG3 and the fourth sub-driving signal VG4; wherein the first sub-driving signal VG1 and the third sub-driving signal VG3 are in phase, so that when the first switch Q1 and the fourth switch Q4 are turned on, the second switch Q2 and the third switch Q3 are turned off, and when the first switch Q1 and the fourth switch Q4 are turned off, the second switch Q2 and the third switch Q3 are turned on, and the first power supply voltage V1 obtains the radio frequency driving signal VRF of the AC signal according to the on or off state of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4.

[0040] Therefore, the above-mentioned RF driving circuit 10 in the present application provides sufficient driving current for at least one RF transistor through two Class D circuits by setting a Class D circuit composed of a first switch Q1 and a second switch Q2 and another Class D circuit composed of a third switch Q3 and a fourth switch Q4.

[0041] In one or more embodiments, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 may all be N-type or P-type power field effect transistors (Metal Oxide Semiconductor FET, MOSFET), insulated gate bipolar transistors (Insulate-Gate Bipolar Transistor, IGBT) or other controllable switch devices, etc. Generally speaking, in high-frequency and high-power application scenarios, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 may all be N-type MOSFET.

[0042] like Figure 3 As shown, the first switch unit 300 further includes a first inductor L1 and a first capacitor C1, which are connected in series at both ends of the second switch Q2, wherein the resonant frequency of the parasitic capacitance of the first inductor L1 and the first switch Q1 or the parasitic capacitance of the first inductor L1 and the second switch Q2 is greater than the switching frequency of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4; the second switch unit 400 further includes a second inductor L2 and a second capacitor C2, which are connected in series at both ends of the fourth switch Q4, wherein the resonant frequency of the parasitic capacitance of the second inductor L2 and the third switch Q3 or the parasitic capacitance of the second inductor L2 and the fourth switch Q4 is greater than the switching frequency of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4.

[0043] Therefore, in the above-mentioned RF driving circuit 10 in the present application, the resonant frequency of the parasitic capacitance of the first inductor L1 and the first switch Q1 or the resonant frequency of the parasitic capacitance of the first inductor L1 and the second switch Q2 is greater than the switching frequency of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4. By configuring the resonant frequency of the parasitic capacitance of the second inductor L2 and the third switch Q3 or the resonant frequency of the parasitic capacitance of the second inductor L2 and the fourth switch Q4 to be greater than the switching frequency of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4, zero voltage switching (Zero Voltage Switch, ZVS) is achieved, thereby improving the efficiency of the RF driving circuit 10.

[0044] In one or more embodiments, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are relatively large, that is, the resonant frequency of the first inductor L1 and the first capacitor C1 is lower than the switching frequency of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4, and the resonant frequency of the second inductor L2 and the second capacitor C2 is lower than the switching frequency of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4.

[0045] In particular, it is difficult to achieve ZVS in a Class D circuit. By using two Class D circuits and configuring LC resonant branches consisting of inductors and parasitic capacitors for the two Class D circuits respectively, and by setting the resonant frequency of the LC resonant branches, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 can achieve ZVS.

[0046] like Figure 3 As shown, at least one RF transistor includes a first RF transistor RFMOS1; the coupling unit 500 includes a first transformer 510, the first transformer 510 has a first winding W1 and a second winding W2, one end of the first winding W1 is connected to the connection point between the first switch Q1 and the second switch Q2, the other end of the first winding W1 is connected to the connection point between the third switch Q3 and the fourth switch Q4, one end of the second winding W2 is connected to the control electrode of the first RF transistor RFMOS1, and the other end of the second winding W2 is grounded GND, wherein the RF drive signal VRF on one side of the first winding W1 is coupled to one side of the second winding W2, and drives the first RF transistor RFMOS1 in the positive half cycle of the RF drive signal VRF of the AC signal.

[0047] Therefore, the above-mentioned RF driving circuit 10 in the present application, by setting the coupling unit 500 to include a first transformer 510, can couple the RF driving signal VRF on one side of the first winding W1 to the second winding W2 side, and drive the first RF transistor RFMOS1 in the positive half cycle of the RF driving signal VRF of the AC signal.

[0048] like Figure 3 As shown, at least one RF transistor also includes a second RF transistor RFMOS2; the coupling unit 500 also includes a second transformer 520, the second transformer 520 has a third winding W3 and a fourth winding W4, one end of the third winding W3 is connected to the connection point between the first switch Q1 and the second switch Q2, the other end of the third winding W3 is connected to the connection point between the third switch Q3 and the fourth switch Q4, one end of the fourth winding W4 is grounded GND, and the other end of the second winding W2 is connected to the control electrode of the second RF transistor RFMOS2, wherein the RF drive signal VRF on one side of the third winding W3 is coupled to one side of the fourth winding W4, and drives the second RF transistor RFMOS2 in the negative half cycle of the RF drive signal VRF of the AC signal.

[0049] Therefore, the above-mentioned RF driving circuit 10 in the present application, by setting the coupling unit 500 also includes a second transformer 520, so that the RF driving signal VRF on one side of the third winding W3 can be coupled to the fourth winding W4 side, and the second RF transistor RFMOS2 can be driven in the negative half cycle of the RF driving signal VRF of the AC signal, and then the RF driving circuit 10 can drive the two RF transistors in a complementary state, which greatly reduces the cost of the RF driving circuit 10.

[0050] In one or more embodiments, the first transformer 510 and the second transformer 520 are both planar transformers with high transformation ratio, so as to provide sufficient driving current for two RF transistors.

[0051] In one or more embodiments, Figure 3 The connections between the first transformer 510 and the second transformer 520 and the first RF transistor RFMOS1 and the second RF transistor RFMOS2 are merely schematic. It can be understood that the first RF transistor RFMOS1 can be connected to the same-name end of the first winding W1, and the second RF transistor RFMOS2 can be connected to the opposite-name end of the third winding W3, so as to be driven in the positive half-cycle and negative half-cycle of the RF drive signal VRF of the AC signal, respectively.

[0052] like Figure 3 As shown, the first control signal CS1 includes a first sub-control signal PWM1 and a second sub-control signal PWM2, the first sub-control signal PWM1 and the second sub-control signal PWM2 have a first dead time period of low level at the same time, the second control signal CS2 includes a third sub-control signal PWM3 and a fourth sub-control signal PWM4, the third sub-control signal PWM3 and the fourth sub-control signal PWM4 have a second dead time period of low level at the same time; the first driving unit 100 includes a first driving module 110 and a second driving module 120, the first driving module 110 is connected to the control electrode of the first switch Q1, and the first driving module 110 is used to power amplify the first sub-control signal PWM1 to obtain the second The first sub-drive signal VG1 is provided, and the second drive module 120 is connected to the control electrode of the second switch Q2, and the second drive module 120 is used to power amplify the second sub-control signal PWM2 to obtain the second sub-drive signal VG2; the second drive unit 200 includes a third drive module 210 and a fourth drive module 220, the third drive module 210 is connected to the control electrode of the third switch Q3, and the third drive module 210 is used to power amplify the third sub-control signal PWM3 to obtain the third sub-drive signal VG3, the fourth drive module 220 is connected to the control electrode of the fourth switch Q4, and the fourth drive module 220 is used to power amplify the fourth sub-control signal PWM4 to obtain the fourth sub-drive signal VG4.

[0053] Thus, the RF driving circuit 10 in the present application configures the first driving module 110, the second driving module 120, the third driving module 210 and the fourth driving module 220 to respectively power amplify the first sub-control signal PWM1, the second sub-control signal PWM2, the third sub-control signal PWM3 and the fourth sub-control signal PWM4, so as to obtain the first sub-drive signal VG1, the second sub-drive signal VG2, the third sub-drive signal VG3 and the fourth sub-drive signal VG4 that can be used to drive the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4.

[0054] like Figure 3 As shown, the first driving unit 100 also includes a first power isolation module 130, a first signal isolation module 140 and a second signal isolation module 150, the first power isolation module 130 is connected to the first signal isolation module 140 and the first driving module 110 respectively, the first signal isolation module 140 is connected between the first dead zone adjustment circuit 600 and the first driving module 110, and the second signal isolation module 150 is connected between the first dead zone adjustment circuit 600 and the second driving module 120, wherein a second power supply voltage V2 provides power to the first driving module 110, the second driving module 120, the first signal isolation module 140 and the second signal isolation module 150, the first power isolation module 130 is used to isolate a power supply outputting the second power supply voltage V2 from the first driving module 110 and the first signal isolation module 140, the first signal isolation module 140 is used to isolate the first dead zone adjustment circuit 600 from the first driving module 110, and the second signal isolation module 150 is used to isolate the first dead zone adjustment circuit 600 from the second driving module 120. The second driving unit 200 further includes a second power isolation module 230, a third signal isolation module 240 and a fourth signal isolation module 250. The second power isolation module 230 is connected to the third signal isolation module 240 and the third driving module 210 respectively. The third signal isolation module 240 is connected between the second dead zone adjustment circuit 700 and the third driving module 210. The fourth signal isolation module 250 is connected between the second dead zone adjustment circuit 700 and the fourth driving module 220. A second power supply voltage V2 provides power to the third driving module 210, the fourth driving module 220, the third signal isolation module 240 and the fourth signal isolation module 250. The second power isolation module 230 is used to isolate a power supply outputting the second power supply voltage V2 from the third driving module 210 and the third signal isolation module 240. The third signal isolation module 240 is used to isolate the second dead zone adjustment circuit 700 from the third driving module 210. The fourth signal isolation module 250 is used to isolate the second dead zone adjustment circuit 700 from the fourth driving module 220.

[0055] Therefore, in order to avoid mutual influence between devices, the above-mentioned RF driving circuit 10 in the present application isolates the corresponding devices by setting a first power isolation module 130, a second power isolation module 230, a first signal isolation module 140, a second signal isolation module 150, a third signal isolation module 240 and a fourth signal isolation module 250, thereby ensuring the normal operation of the RF driving circuit 10 and avoiding problems such as losing the driving ability of at least one RF transistor.

[0056] In one or more embodiments, the first power isolation module 130 and the second power isolation module 230 may include devices such as transformers, and the first signal isolation module 140, the second signal isolation module 150, the third signal isolation module 240 and the fourth signal isolation module 250 may include devices such as signal followers.

[0057] In one or more embodiments, the first signal isolation module 140 and the third signal isolation module 240 can obtain power through a second power supply voltage V2 output by a power supply, and simultaneously obtain power through the corresponding first power isolation module 130 and the second power isolation module 230 .

[0058] In one or more embodiments, the second signal isolation module 150 and the fourth signal isolation module 250 may also be connected to the ground GND.

[0059] In one or more embodiments, the first signal isolation module 140 and the first driving module 110 can also be connected to the connection point between the first switch Q1 and the second switch Q2, the third signal isolation module 240 and the third driving module 210 can also be connected to the connection point between the third switch Q3 and the fourth switch Q4, and the first signal isolation module 140, the second signal isolation module 150, the third signal isolation module 240 and the fourth signal isolation module 250 can also be connected to the same potential EP.

[0060] Among them, Figure 3As shown, the voltage at the connection point between the first switch Q1 and the second switch Q2 is the first connection point voltage Vsw1, the voltage at the connection point between the third switch Q3 and the fourth switch Q4 is the second connection point voltage Vsw2, the equipotential EP connected to the first signal isolation module 140 and the second signal isolation module 150 can be the first connection point voltage Vsw1, and the equipotential EP connected to the third signal isolation module 240 and the fourth signal isolation module 250 can be the second connection point voltage Vsw2. Furthermore, by setting the first signal isolation module 140, the first driving module 110 can also be connected to the connection point between the first switch Q1 and the second switch Q2, and the third signal isolation module 240 and the third driving module 210 can also be connected to the connection point between the third switch Q3 and the fourth switch Q4. At the same time, by using the first power isolation module 130 to isolate a power supply that outputs the second power supply voltage V2 from the first driving module 110 and the first signal isolation module 140, the first signal isolation module 140 is used to isolate the first dead zone adjustment circuit 600 from the first driving module 110, and by using the second power isolation module 230 to isolate a power supply that outputs the second power supply voltage V2 from the third driving module 210 and the third signal isolation module 240, it is avoided that the first sub-driving signal VG1 cannot drive the first switch Q1, and at the same time, it is avoided that the third sub-driving signal VG3 cannot drive the third switch Q3.

[0061] See also Figure 4 , Figure 4 FIG. 1 is a block diagram of a first dead zone adjustment circuit in an embodiment of the present application. Figure 4As shown, taking the first dead zone adjustment circuit 600 as an example, the first dead zone adjustment circuit 600 is used to obtain a first sub-control signal PWM1 and a second sub-control signal PWM2 that can generate a first dead zone time period. The first dead zone adjustment circuit 600 includes a first dead zone adjustment unit 610, a second dead zone adjustment unit 620, a first inverting unit 630 and a second inverting unit 640; wherein the first dead zone adjustment unit 610 is used to at least receive a first pulse width modulation signal P1, and at least invert the first pulse width modulation signal P1 and increase the on-duty ratio, so as to obtain a first intermediate pulse width modulation signal Pm1 whose on-duty ratio is greater than the first pulse width modulation signal P1; the second dead zone adjustment unit 620 is used to at least receive a second pulse width modulation signal P2 that is complementary to the first pulse width modulation signal P1, and at least invert the second pulse width modulation signal P2 and increase the on-duty ratio, so as to obtain a second intermediate pulse width modulation signal Pm1 whose on-duty ratio is greater than the second pulse width modulation signal P2. Pm2; the first inversion unit 630 is used to receive the first intermediate pulse width modulation signal Pm1, and invert the first intermediate pulse width modulation signal Pm1 to output the first sub-control signal PWM1 which is inverted to the first intermediate pulse width modulation signal Pm1; the second inversion unit 640 is used to receive the second intermediate pulse width modulation signal Pm2, and invert the second intermediate pulse width modulation signal Pm2 to output the second sub-control signal PWM2 which is inverted to the second intermediate pulse width modulation signal Pm2; wherein any high-level time segment of one of the first sub-control signal PWM1 and the second pulse width modulation signal P2 falls within the corresponding low-level time segment of the other of the first sub-control signal PWM1 and the second pulse width modulation signal P2, so that the first sub-control signal PWM1 and the second sub-control signal PWM2 generate a first dead time segment, wherein the time segment in which the first sub-control signal PWM1 and the second sub-control signal PWM2 are both low-level is the first dead time segment.

[0062] Thus, the first dead zone adjustment circuit 600 in the present application obtains the first intermediate pulse width modulation signal Pm1 by setting the first dead zone adjustment unit 610 to invert the first pulse width modulation signal P1 and increase the on-duty cycle, and obtains the second intermediate pulse width modulation signal Pm2 by setting the second dead zone adjustment unit 620 to invert the second pulse width modulation signal P2 and increase the on-duty cycle, and then the first inversion unit 630 and the second inversion unit 640 are set to invert the first intermediate pulse width modulation signal Pm1 and the second intermediate pulse width modulation signal Pm2 respectively, so that the first sub-control signal PWM1 and the second sub-control signal PWM2 can generate a first dead zone time period in which both are low level time periods.

[0063] In one or more embodiments, the first dead zone adjustment unit 610 and the second dead zone adjustment unit 620 may include logic gates such as inverters, Schmitt triggers, operational amplifiers, and NAND gates to invert corresponding signals.

[0064] In one or more embodiments, the first dead zone adjustment unit 610 and the second dead zone adjustment unit 620 may further include a controller to improve the conduction duty cycle of the corresponding signal, wherein the controller may be a general processor such as a central processing unit (CPU), or a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate logic devices, transistor logic devices and other logic control devices, or a microcontroller such as a microcontroller unit (MCU). The first dead zone adjustment unit 610 and the second dead zone adjustment unit 620 may also include analog switches, operational amplifiers, counters, timers and other devices that can improve the conduction duty cycle of the corresponding signal.

[0065] In one or more embodiments, the first inversion unit 630 and the second inversion unit 640 may include logic gates such as inverters, Schmitt triggers, operational amplifiers, and NAND gates to invert corresponding signals.

[0066] Please also read Figure 5 , Figure 6 , Figure 5 is a block diagram of a first dead zone adjustment circuit in yet another embodiment of the present application, Figure 6 : is a waveform diagram of the first sub-control signal, the second sub-control signal, etc. in an embodiment of the present application. In some embodiments, the first dead zone adjustment circuit 600 in the present application can be Figure 5 The structure in is used to obtain the first sub-control signal PWM1 and the second sub-control signal PWM2 for generating the first dead time period. That is, Figure 5 , Figure 6As shown, the first dead zone adjustment unit 610 includes a first input terminal In1, a second input terminal In2 and a first output terminal Out1, the second dead zone adjustment unit 620 includes a third input terminal In3, a fourth input terminal In4 and a second output terminal Out2, the first inverting unit 630 includes a first inverting input terminal In5 and a first inverting output terminal Out3, and the second inverting unit 640 includes a second inverting input terminal In6 and a second inverting output terminal Out4; the first input terminal In1 is used to receive the first pulse width modulation signal P1, and the second input terminal In2 is connected to The first dead zone adjustment unit 610 has a first conduction state and a second conduction state, and the first dead zone adjustment unit 610 has a first conduction state and a second conduction state, and the first dead zone adjustment unit 610 has a first conduction state and a second conduction state, and the first dead zone adjustment unit 610 has a second ... first conduction state and a second conduction state, and the first dead zone adjustment unit 0 is used to alternately be in a first conduction state and a second conduction state according to a first pulse width modulation signal P1 inputted from a first input terminal In1 and a second intermediate pulse width modulation signal Pm2 inputted from a second input terminal In2, so as to obtain a first intermediate pulse width modulation signal Pm1 having a conduction duty ratio greater than that of the first pulse width modulation signal P1, a first inversion unit 630 is used to receive the first intermediate pulse width modulation signal Pm1, and output a first sub-control signal PWM1 which is inverted with the first intermediate pulse width modulation signal Pm1 through an output terminal; a second dead zone adjustment unit 620 has a third conduction state The second dead zone adjustment unit 620 is used to alternately be in the third conduction state and the fourth conduction state according to the second pulse width modulation signal P2 inputted from the third input terminal In3 and the first intermediate pulse width modulation signal Pm1 inputted from the fourth input terminal In4, so as to obtain a second intermediate pulse width modulation signal Pm2 whose conduction duty ratio is greater than the second pulse width modulation signal P2, and the second inverting unit 640 is used to receive the second intermediate pulse width modulation signal Pm2, and output a second sub-control signal PWM2 which is inverted to the second intermediate pulse width modulation signal Pm2 through the output terminal.

[0067] Thus, in the first dead zone adjustment circuit 600 in the present application, when the first dead zone adjustment unit 610 has the first conduction state and the second conduction state, the first dead zone adjustment unit 610 can be alternately in the first conduction state and the second conduction state according to the first pulse width modulation signal P1 inputted by the first input terminal In1 and the second intermediate pulse width modulation signal Pm2 inputted by the second input terminal In2, so as to obtain the first intermediate pulse width modulation signal Pm1 with a conduction duty ratio greater than the first pulse width modulation signal P1, and the second dead zone adjustment unit 620 has the third conduction state and the fourth conduction state, and the second dead zone adjustment unit 620 can be alternately in the third conduction state and the fourth conduction state according to the second pulse width modulation signal P2 inputted by the third input terminal In3 and the first intermediate pulse width modulation signal Pm1 inputted by the fourth input terminal In4, so as to obtain the second intermediate pulse width modulation signal Pm2 with a conduction duty ratio greater than the second pulse width modulation signal P2. The first dead zone adjustment unit 610 and the second dead zone adjustment unit 620 switched by multiple states are conducive to adjusting the first dead zone time period and the conduction duty ratio of the two signals.

[0068] The second pulse width modulation signal P2 complementary to the first pulse width modulation signal P1 can be as follows: Figure 4 From the same signal input terminal as shown, it can also be Figure 5 The signal input terminals shown are from different signal input terminals, but the present application is not limited thereto. It is only necessary that the first pulse width modulation signal P1 and the second pulse width modulation signal P2 are complementary to each other.

[0069] like Figure 6 As shown, any high level time period of one of the first sub-control signal PWM1 and the second pulse width modulation signal P2 is shorter than the corresponding low level time period of the other one of the first sub-control signal PWM1 and the second pulse width modulation signal P2.

[0070] Therefore, in the first dead zone adjustment circuit 600 in the present application, any high level time period of a signal is shorter than the corresponding low level time period of another signal, so as to avoid the high level time periods of the two signals from overlapping and thus causing damage to the related power supply.

[0071] like Figure 6As shown, the first sub-control signal PWM1, which is in phase with the first intermediate pulse width modulation signal Pm1, delays the first time period T1 from switching from a low level to a high level compared to the first pulse width modulation signal P1, and delays the second time period T2 from switching from a high level to a low level, and the second sub-control signal PWM2, which is in phase with the second intermediate pulse width modulation signal Pm2, delays the third time period T3 from switching from a low level to a high level compared to the second pulse width modulation signal P2, and delays the fourth time period T4 from switching from a high level to a low level; wherein the time length of the first time period T1 is greater than the time length of the second time period T2, and the time length of the third time period T3 is greater than the time length of the fourth time period T4.

[0072] Thus, the first dead zone adjustment circuit 600 in the present application configures the time length of the first time period T1 to be greater than the time length of the second time period T2, and the time length of the third time period T3 to be greater than the time length of the fourth time period T4. Then, the on-duty cycle of the first sub-control signal PWM1 after double delay is slightly smaller than the first pulse width modulation signal P1, and the on-duty cycle of the second sub-control signal PWM2 after double delay is slightly smaller than the second pulse width modulation signal P2.

[0073] like Figure 6 As shown, the first time period T1 includes a first sub-time period ta and a second sub-time period tb, the third time period T3 includes a third sub-time period tc and a fourth sub-time period td, the second time period T2 includes the third sub-time period tc, the fourth time period T4 includes the first sub-time period ta, and the first dead time period is adjusted according to the time length of the second sub-time period tb and the time length of the fourth sub-time period td.

[0074] Therefore, the first dead zone adjustment circuit 600 in the present application can adjust the first dead zone time periods of the two signals according to the time length of the second sub-time period tb and the time length of the fourth sub-time period td, so as to flexibly control the first dead zone time period to the required time length.

[0075] like Figure 6 As shown, when the first preset relationship is satisfied between the first sub-time period ta, the third sub-time period tc and the duty cycle of the first pulse width modulation signal P1 or the duty cycle of the second pulse width modulation signal P2, the duty cycle of the first sub-control signal PWM1 is the same as the duty cycle of the second sub-control signal PWM2.

[0076] Therefore, the first dead zone adjustment circuit 600 in the present application can obtain the first sub-control signal PWM1 and the second sub-control signal PWM2 with the same conduction duty cycle for the first pulse width modulation signal P1 or the second pulse width modulation signal P2 with any conduction duty cycle when the first preset relationship is satisfied, that is, Figure 6As shown, the on-duty cycle of the first sub-control signal PWM1 is d1, and the on-duty cycle of the second sub-control signal PWM2 is d2, d1=d2, so as to better cooperate with the related power supply to output electric energy normally.

[0077] like Figure 6 As shown, Don is the on-duty cycle of the first pulse width modulation signal P1, Doff is the on-duty cycle of the second pulse width modulation signal P2, that is, the off-duty cycle of the first pulse width modulation signal P1, so that the first preset relationship satisfied between the first sub-time period ta, the third sub-time period tc and the duty cycle of the first pulse width modulation signal P1 or the duty cycle of the second pulse width modulation signal P2 is (Don-Doff) / 2=ta-tc.

[0078] See also Figure 7 , Figure 7 FIG. 1 is a circuit diagram of a first dead zone adjustment circuit in an embodiment of the present application. Figure 7As shown, the first dead zone adjustment unit 610 includes a first logic gate 611, a first bidirectional control module 612 and a first trigger 613, the first input terminal In1 and the second input terminal In2 are two input terminals of the first logic gate 611, the first output terminal Out1 is the output terminal of the first trigger 613, the output terminal of the first logic gate 611 is connected to the input terminal of the first bidirectional control module 612, and the output terminal of the first bidirectional control module 612 is connected to the input terminal of the first trigger 613; wherein the first logic gate 611 is used to perform AND-NOT on the first pulse width modulation signal P1 and the second intermediate pulse width modulation signal Pm2. The first bidirectional control module 612 is configured to be in the first conduction state when the first operation result signal OP1 is at a high level to increase the voltage at the output end, and to be in the second conduction state when the first operation result signal OP1 is at a low level to reduce the voltage at the output end. The first trigger 613 is configured to output a high level when the voltage at the input end is greater than a first voltage threshold, and to output a low level when the voltage at the input end is less than a second voltage threshold, so as to obtain a first intermediate pulse width modulation signal Pm. 1; The second dead zone adjustment unit 620 includes a second logic gate 621, a second bidirectional control module 622 and a second trigger 623, the third input terminal In3 and the fourth input terminal In4 are two input terminals of the second logic gate 621, the second output terminal Out2 is the output terminal of the second trigger 623, the output terminal of the second logic gate 621 is connected to the input terminal of the second bidirectional control module 622, and the output terminal of the second bidirectional control module 622 is connected to the input terminal of the second trigger 623; wherein the second logic gate 621 is used to perform a non-AND operation on the second pulse width modulation signal P2 and the first intermediate pulse width modulation signal Pm1 , to output the second operation result signal OP2 through the output terminal, the second bidirectional control module 622 has a third conduction state and a fourth conduction state, the second bidirectional control module 622 is used to be in the third conduction state when the second operation result signal OP2 is at a high level, to increase the voltage at the output terminal, and is in the fourth conduction state when the second operation result signal OP2 is at a low level, to reduce the voltage at the output terminal, the second trigger 623 is used to output a high level when the voltage at the input terminal is greater than the first voltage threshold, and output a low level when the voltage at the input terminal is less than the second voltage threshold, to obtain the second intermediate pulse width modulation signal Pm2.

[0079] Therefore, the first dead zone adjustment circuit 600 in the present application obtains the required first intermediate pulse width modulation signal Pm1 and second intermediate pulse width modulation signal Pm2 by setting logic gates, bidirectional control modules and triggers to cooperate with each other.

[0080] In particular, the first logic gate 611 and the second logic gate 621 can both include NAND gates to perform NAND operations on corresponding signals, the first trigger 613 and the second trigger 623 can both include Schmitt triggers, the first voltage threshold and the second voltage threshold are both the upper voltage threshold and the lower voltage threshold of the Schmitt trigger itself, and a Schmitt trigger with a suitable first voltage threshold and second voltage threshold can be selected according to specific needs.

[0081] Please also read Figure 8 , Fig. 9 , Figure 8 is a circuit diagram of a first bidirectional control module in an embodiment of the present application, Fig. 9 FIG. 1 is a circuit diagram of a second bidirectional control module in an embodiment of the present application. Figure 6 , Figure 8 , Fig. 9As shown, the first bidirectional control module 612 includes a third capacitor C3, a first resistor R1, a second resistor R2, a first diode D1 and a second diode D2, the third capacitor C3 is connected between the output end of the first bidirectional control module 612 and the ground GND, the cathode of the first diode D1 is connected to the input end of the first bidirectional control module 612 through the first resistor R1, the anode of the first diode D1 is connected to the output end of the first bidirectional control module 612, the anode of the second diode D2 is connected to the input end of the first bidirectional control module 612 through the second resistor R2, and the cathode of the second diode D2 is connected to the output end of the first bidirectional control module 612; wherein, when the first operation result signal OP1 is at a high level, the first The diode D1 is turned on, the second diode D2 is turned off, the first bidirectional control module 612 is in a first conduction state, and the third capacitor C3 is charged to increase the voltage at the output end of the first bidirectional control module 612; when the first operation result signal OP1 is at a low level, the first diode D1 is turned off, the second diode D2 is turned on, the first bidirectional control module 612 is in a second conduction state, and the third capacitor C3 is discharged to reduce the voltage at the output end of the first bidirectional control module 612; the second bidirectional control module 622 includes a fourth capacitor C4, a third resistor R3, a fourth resistor R4, a third diode D3 and a fourth diode D4, and the fourth capacitor C4 is connected between the output end of the second bidirectional control module 622 and the ground GND. The anode of the third diode D3 is connected to the input end of the second bidirectional control module 622 through the third resistor R3, the cathode of the third diode D3 is connected to the output end of the second bidirectional control module 622, the cathode of the fourth diode D4 is connected to the input end of the second bidirectional control module 622 through the fourth resistor R4, and the anode of the fourth diode D4 is connected to the output end of the second bidirectional control module 622; wherein, when the second operation result signal OP2 is at a high level, the third diode D3 is turned on and the fourth diode D4 is turned off, so that the second bidirectional control module 622 is in a third conduction state, and the fourth capacitor C4 is charged to increase the voltage at the output end of the second bidirectional control module 622; when the second operation result signal OP2 is at a high level, the third diode D3 is turned on and the fourth diode D4 is turned off, so that the second bidirectional control module 622 is in a third conduction state, and the fourth capacitor C4 is charged to increase the voltage at the output end of the second bidirectional control module 622; 2 is a low level, the third diode D3 is disconnected and the fourth diode D4 is turned on, so that the second bidirectional control module 622 is in the fourth conduction state, and the fourth capacitor C4 is discharged to reduce the voltage at the output end of the second bidirectional control module 622; wherein, the time length of the first sub-time period ta is related to the resistance value of the third resistor R3 and the capacitance value of the fourth capacitor C4, the time length of the second sub-time period tb is related to the resistance value of the second resistor R2 and the capacitance value of the third capacitor C3, the time length of the third sub-time period tc is related to the resistance value of the first resistor R1 and the capacitance value of the third capacitor C3, and the time length of the fourth sub-time period td is related to the resistance value of the fourth resistor R4 and the capacitance value of the fourth capacitor C4.

[0082] Therefore, the first dead zone adjustment circuit 600 in the present application can increase or decrease the voltage at the corresponding output terminal by coordinating the resistor, diode and capacitor and utilizing the unidirectional conduction characteristics of the diode and the charge and discharge characteristics of the resistor and capacitor.

[0083] It should be noted that the above connection relationship is merely exemplary. It can be understood that as long as two branches are included, the unidirectional conduction direction of the diode in each branch is different, and corresponding resistors and capacitors are used, the voltage at the corresponding output terminal can be increased or decreased.

[0084] Specifically, due to the setting of the resistor, diode and capacitor, the time length of the first sub-time period ta is related to the resistance value of the third resistor R3 and the capacitance value of the fourth capacitor C4, the time length of the second sub-time period tb is related to the resistance value of the second resistor R2 and the capacitance value of the third capacitor C3, the time length of the third sub-time period tc is related to the resistance value of the first resistor R1 and the capacitance value of the third capacitor C3, and the time length of the fourth sub-time period td is related to the resistance value of the fourth resistor R4 and the capacitance value of the fourth capacitor C4, that is, ta=R3×C4, tb=R2×C3, tc=R1×C3, td=R4×C4. Further, when it is necessary to adjust the first dead time period, the resistance value of the second resistor R2, the resistance value of the fourth resistor R4, the capacitance value of the third capacitor C3 and the capacitance value of the fourth capacitor C4 can be adjusted, and when it is necessary to adjust the duty cycle, the resistance value of the third resistor R3, the resistance value of the first resistor R1, the capacitance value of the third capacitor C3 and the capacitance value of the fourth capacitor C4 can be adjusted.

[0085] In one or more embodiments, generally speaking, the second sub-time period tb and the fourth sub-time period td are equal. However, in some cases, such as for different parasitic parameters, in order to achieve zero voltage switching, fine-tuning can be performed so that the second sub-time period tb and the fourth sub-time period td are not equal.

[0086] In one or more embodiments, the selection of the first diode D1, the second diode D2, the third diode D3 and the fourth diode D4 needs to pay attention to the junction capacitance. If the junction capacitance of the selected diode is large, when the frequency of the relevant signal is as high as the RF frequency of 13.56 MHz, the diode may not be able to play a reverse cutoff role. Specifically, the junction capacitance of the first diode D1, the second diode D2, the third diode D3 and the fourth diode D4 can be less than 1.5 pF.

[0087] See also Fig.10 , Fig.10 FIG. 1 is a block diagram of a first dead zone adjustment circuit in another embodiment of the present application. Fig.10As shown, the first dead zone adjustment circuit 600 also includes a first buffer unit 650 and a second buffer unit 660. The input end of the first buffer unit 650 is used to receive an original pulse width modulation signal PWM, and the output end of the first buffer unit 650 is connected to the first input end In1. The first buffer unit 650 is used to output a first pulse width modulation signal P1 that is in phase with the original pulse width modulation signal PWM according to the original pulse width modulation signal PWM; the input end of the second buffer unit 660 is used to receive the original pulse width modulation signal PWM, and the output end of the second buffer unit 660 is connected to the third input end In3. The second buffer unit 660 is used to output a second pulse width modulation signal P2 that is in phase with the original pulse width modulation signal PWM according to the original pulse width modulation signal PWM, so that the first pulse width modulation signal P1 is complementary to the second pulse width modulation signal P2.

[0088] Thus, the first dead zone adjustment circuit 600 in the present application can make the first pulse width modulation signal P1 complementary to the second pulse width modulation signal P2 by setting the first buffer unit 650 to output the first pulse width modulation signal P1 in phase with the original pulse width modulation signal PWM according to the original pulse width modulation signal PWM, and can avoid the device delay caused by the second buffer unit 660 compared with the first pulse width modulation signal P1 caused by the second buffer unit 660 due to only inverting the original pulse width modulation signal PWM and not processing the first pulse width modulation signal P1 in phase with the original pulse width modulation signal PWM.

[0089] In one or more embodiments, the first buffer unit 650 may include a non-inverting buffer, and the second buffer unit 660 may include an inverting buffer.

[0090] See also Fig.11 , Fig.11 FIG. 1 is a block diagram of a first dead zone adjustment circuit in another embodiment of the present application. Fig.11 As shown, the first dead zone adjustment circuit 600 also includes a control unit 670, which is connected to both the first inverted output terminal Out3 and the second inverted output terminal Out4. The control unit 670 is used to control the output or non-output of the obtained first sub-control signal PWM1 and / or the second sub-control signal PWM2.

[0091] Therefore, the above-mentioned first dead zone adjustment circuit 600 in the present application can output or not output the first sub-control signal PWM1 and / or the second sub-control signal PWM2 according to specific needs by setting the control unit 670 to control the output or not of the first sub-control signal PWM1 and / or the second sub-control signal PWM2.

[0092] In one or more embodiments, the control unit 670 may include the above-mentioned controller, and may also include a third logic gate 671 and a fourth logic gate 672. The third logic gate 671 is used to output the first sub-control signal PWM1 when the enable signal EN is at a high level according to the first sub-control signal PWM1 and an enable signal EN, and does not output the first sub-control signal PWM1 when the enable signal EN is at a low level. The fourth logic gate 672 is used for the second sub-control signal PWM2 and an enable signal EN, so as to output the second sub-control signal PWM2 when the enable signal EN is at a high level, and does not output the second sub-control signal PWM2 when the enable signal EN is at a low level.

[0093] Among them, the third logic gate 671 and the fourth logic gate 672 can both include AND gates and can also include tri-state gates. The present application is not limited to this, as long as the first sub-control signal PWM1 and / or the second sub-control signal PWM2 can be controlled to be output or not output.

[0094] In one or more embodiments, the enable signal EN received by the third logic gate 671 and the fourth logic gate 672 may be the same enable signal EN or different enable signals EN. For example, in some cases, multiple groups of two signals with a first dead time period are required to cooperate with related power supplies to output power. In general, the same enable signal EN is used to control the first sub-control signal PWM1 and the second sub-control signal PWM2 to be output simultaneously or not output simultaneously.

[0095] In particular, such as Figure 2 The second dead zone adjustment circuit 700 shown can have the same structure and function as the first dead zone adjustment circuit 600 in any of the aforementioned embodiments, so as to obtain a third sub-control signal PWM3 and a fourth sub-control signal PWM4 that can generate a second dead zone time period as needed, that is, the more specific structure of the second dead zone adjustment circuit 700 can refer to the relevant content of the first dead zone adjustment circuit 600 in any of the aforementioned embodiments, which will not be repeated here.

[0096] In one or more embodiments, generally speaking, the first dead zone period and the second dead zone period are equal. Figure 3 The parasitic capacitances of the first switch Q1 , the second switch Q2 , the third switch Q3 and the fourth switch Q4 shown can be adjusted as needed so that the first dead time period and the second dead time period are not equal.

[0097] The RF driving circuit 10 of the present application, through the above-mentioned structure, can provide sufficient driving current for the two RF transistors in high-frequency and high-power application scenarios, meet the driving conditions of the two RF transistors, and then drive the two RF transistors to be turned on or off, greatly reducing costs, and can also achieve ZVS to improve efficiency. It can also obtain four signals with the same on-duty cycle and can generate dead time for the original pulse width modulation signal PWM with any on-duty cycle, so as to cooperate with the relevant power supply to output electrical energy normally.

[0098] See also Fig.12 , Fig.12 FIG. 1 is a block diagram of a radio frequency power amplification device in an embodiment of the present application. Fig.12 As shown, the present application also provides a radio frequency power amplification device 1000, and the radio frequency power amplification device 1000 includes the radio frequency driving circuit 10 in any of the aforementioned embodiments.

[0099] like Figure 1 As shown, the RF driving circuit 10 is used to drive at least one RF transistor, and the RF driving circuit 10 includes: a first driving unit 100, a second driving unit 200, a first switch unit 300, a second switch unit 400 and a coupling unit 500; the first driving unit 100 is used to output a first driving signal VS1; the second driving unit 200 is used to output a second driving signal VS2; the first switch unit 300 is connected to the first driving unit 100, and the first switch unit 300 is used to respond to the first driving signal VS1 and be in a corresponding switching state; the second switch unit 400 is connected to the second driving unit 200, and the second switch unit 400 is used to respond to the second driving signal VS2 and be in a corresponding switching state; wherein the first switch unit 300 and the second switch unit 400 cooperate to convert the first power supply voltage V1 into the RF driving signal VRF under the drive of the first driving signal VS1 and the second driving signal VS2 respectively; the coupling unit 500 is connected to both the first switch unit 300 and the second switch unit 400, and the coupling unit 500 is used to couple the RF driving signal VRF to the control electrode of at least one RF transistor to drive at least one RF transistor to be turned on or off.

[0100] The more specific structure of the RF driving circuit 10 may refer to the relevant content of the RF driving circuit 10 in any of the aforementioned embodiments, which will not be described in detail here.

[0101] The RF driving circuit 10 and the RF power amplifier device 1000 of the present application, through the above-mentioned structure, can provide sufficient driving current for the two RF transistors in high-frequency and high-power application scenarios, meet the driving conditions of the two RF transistors, and then drive the two RF transistors to be turned on or off, greatly reducing costs, and can also achieve ZVS to improve efficiency. It can also obtain four signals with the same on-duty cycle and can generate dead time for the original pulse width modulation signal PWM with any on-duty cycle, so as to better cooperate with the RF power amplifier device 1000 to power amplify the RF signal, and then cooperate with the relevant power supply to normally output electrical energy.

[0102] See also Fig.13 , Fig.13 FIG. 1 is a block diagram of a radio frequency power supply system in an embodiment of the present application. Fig.13 As shown, the present application further provides a radio frequency power supply system 2000, and the radio frequency power supply system 2000 includes the radio frequency power amplification device 1000 in any of the aforementioned embodiments.

[0103] like Fig.12 As shown, the radio frequency power amplification device 1000 includes a radio frequency driving circuit 10 .

[0104] Among them, the more specific structure of the RF power amplifying device 1000 can refer to the relevant content of the RF power amplifying device 1000 in any of the aforementioned embodiments, which will not be repeated here.

[0105] like Fig.13 As shown, the RF power system 2000 further includes a RF power source RF, and the RF power source RF is used to output a RF signal.

[0106] In one or more embodiments, the RF power amplifying device 1000 is used to amplify the power of the RF signal according to at least one driven RF transistor, and output the power-amplified RF signal to a load, thereby outputting electrical energy to the load.

[0107] The RF driving circuit 10, RF power amplifying device 1000 and RF power supply system 2000 of the present application, through the above-mentioned structure, can provide sufficient driving current for two RF transistors in high-frequency and high-power application scenarios, meet the driving conditions of the two RF transistors, greatly reduce costs, and can also achieve ZVS to improve efficiency, thereby driving the two RF transistors to be turned on or off, and can obtain four signals with the same on-duty cycle and capable of generating dead time for the original pulse width modulation signal PWM with any on-duty cycle, so as to better cooperate with the RF power amplifying device 1000 to power amplify the RF signal, and then cooperate with the RF power supply system 2000 to output electrical energy normally.

[0108] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application; in the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A radio frequency driving circuit for driving at least one radio frequency transistor, characterized in that: include: A first driving unit, configured to output a first driving signal; A second driving unit, used for outputting a second driving signal; A first switch unit, connected to the first drive unit, the first switch unit being configured to be in a corresponding switch state in response to the first drive signal; a second switch unit connected to the second drive unit, the second switch unit being configured to be in a corresponding switch state in response to the second drive signal; wherein the first switch unit and the second switch unit cooperate to convert the first power supply voltage into a radio frequency drive signal under the drive of the first drive signal and the second drive signal respectively; and a coupling unit connected to both the first switch unit and the second switch unit, the coupling unit being used to couple the RF drive signal to the control electrode of the at least one RF transistor to drive the at least one RF transistor to be turned on or off; The RF driving circuit further includes a first dead zone adjustment circuit, the first dead zone adjustment circuit is connected to the first driving unit, the first dead zone adjustment circuit is used to obtain a first control signal according to an original pulse width modulation signal, and output the first control signal to the first driving unit; the first control signal includes a first sub-control signal and a second sub-control signal, and the first sub-control signal and the second sub-control signal have a first dead zone time period that is simultaneously low level; The first dead zone adjustment circuit comprises a first dead zone adjustment unit, a second dead zone adjustment unit, a first inverting unit and a second inverting unit; the first dead zone adjustment unit comprises a first input terminal, a second input terminal and a first output terminal, the second dead zone adjustment unit comprises a third input terminal, a fourth input terminal and a second output terminal, the first inverting unit comprises a first inverting input terminal and a first inverting output terminal, the second inverting unit comprises a second inverting input terminal and a second inverting output terminal; the first input terminal is used to receive a first pulse width modulation signal, the second input terminal is connected to a connection point between the second output terminal and the second inverting input terminal, the third input terminal is used to receive a second pulse width modulation signal complementary to the first pulse width modulation signal, the fourth input terminal is connected to a connection point between the first output terminal and the first inverting input terminal, the first output terminal is used to output a first intermediate pulse width modulation signal, and the second output terminal is used to output a second intermediate pulse width modulation signal; wherein the first dead zone adjustment unit has a first conduction state and a second conduction state, and the first dead zone adjustment unit is used to output a second intermediate pulse width modulation signal according to the The first pulse width modulation signal inputted by the first input terminal and the second intermediate pulse width modulation signal inputted by the second input terminal are alternately in the first conduction state and the second conduction state to obtain the first intermediate pulse width modulation signal having a conduction duty ratio greater than the first pulse width modulation signal, the first inverting unit is used to receive the first intermediate pulse width modulation signal, and output the first sub-control signal which is inverted to the first intermediate pulse width modulation signal through the first inverting output terminal; the second dead zone adjustment unit has a third conduction state and a fourth conduction state, the second dead zone adjustment unit is used to alternately be in the third conduction state and the fourth conduction state according to the second pulse width modulation signal inputted by the third input terminal and the first intermediate pulse width modulation signal inputted by the fourth input terminal to obtain the second intermediate pulse width modulation signal having a conduction duty ratio greater than the second pulse width modulation signal, the second inverting unit is used to receive the second intermediate pulse width modulation signal, and output the second sub-control signal which is inverted to the second intermediate pulse width modulation signal through the second inverting output terminal; The first dead zone adjustment unit includes a first logic gate, a first bidirectional control module and a first trigger, the first input end and the second input end are two input ends of the first logic gate, the first output end is the output end of the first trigger, the output end of the first logic gate is connected to the input end of the first bidirectional control module, and the output end of the first bidirectional control module is connected to the input end of the first trigger; wherein the first logic gate is used to perform a negative AND operation on the first pulse width modulation signal and the second intermediate pulse width modulation signal to output a first operation result signal through the output end, the first bidirectional control module has a first conduction state and a second conduction state, the first bidirectional control module is used to be in the first conduction state when the first operation result signal is at a high level to increase the voltage at the output end, and is in the second conduction state when the first operation result signal is at a low level to reduce the voltage at the output end, the first trigger is used to output a high level when the voltage at the input end is greater than a first voltage threshold, and output a low level when the voltage at the input end is less than a second voltage threshold, so as to obtain the first intermediate pulse width modulation signal; The second dead zone adjustment unit includes a second logic gate, a second bidirectional control module and a second trigger, the third input terminal and the fourth input terminal are two input terminals of the second logic gate, the second output terminal is the output terminal of the second trigger, the output terminal of the second logic gate is connected to the input terminal of the second bidirectional control module, and the output terminal of the second bidirectional control module is connected to the input terminal of the second trigger; wherein the second logic gate is used to perform a negative AND operation on the second pulse width modulation signal and the first intermediate pulse width modulation signal to output a second operation result signal through the output terminal, the second bidirectional control module has a third conduction state and a fourth conduction state, the second bidirectional control module is used to be in the third conduction state when the second operation result signal is at a high level to increase the voltage at the output terminal, and is in the fourth conduction state when the second operation result signal is at a low level to reduce the voltage at the output terminal, the second trigger is used to output a high level when the voltage at the input terminal is greater than a first voltage threshold, and output a low level when the voltage at the input terminal is less than a second voltage threshold, so as to obtain the second intermediate pulse width modulation signal; The first sub-control signal, which is inverted with the first intermediate pulse width modulation signal, delays the switching from low level to high level for a first time period compared to the first pulse width modulation signal, and delays the switching from high level to low level for a second time period; the second sub-control signal, which is inverted with the second intermediate pulse width modulation signal, delays the switching from low level to high level for a third time period compared to the second pulse width modulation signal, and delays the switching from high level to low level for a fourth time period; wherein the time length of the first time period is greater than the time length of the second time period, and the time length of the third time period is greater than the time length of the fourth time period.

2. The radio frequency driving circuit according to claim 1, characterized in that: The RF driving circuit also includes a second dead zone adjustment circuit, which is connected to the second driving unit, and the second dead zone adjustment circuit is used to obtain a second control signal according to the original pulse width modulation signal, and output the second control signal to the second driving unit; wherein the first driving unit obtains the first driving signal at least according to the first control signal, and the second driving unit obtains the second driving signal at least according to the second control signal.

3. The radio frequency driving circuit according to claim 2, characterized in that: The first drive signal includes a first sub-drive signal and a second sub-drive signal, the first sub-drive signal and the second sub-drive signal are complementary, the second drive signal includes a third sub-drive signal and a fourth sub-drive signal, the third sub-drive signal and the fourth sub-drive signal are complementary, the RF drive circuit also includes two first input ports, each of the first input ports is used to input the first power supply voltage; the first switch unit includes a first switch and a second switch, the first switch and the second switch are connected in series between one of the first input ports and the ground, the connection point between the first switch and the second switch is connected to the coupling unit, the control electrode of the first switch and the control electrode of the second switch are both connected to the first drive unit, wherein the first switch and the second switch are alternately turned on according to the driving of the first sub-drive signal and the second sub-drive signal; The second switch unit includes a third switch and a fourth switch, wherein the third switch and the fourth switch are connected in series between another first input port and the ground, a connection point between the third switch and the fourth switch is connected to the coupling unit, and a control electrode of the third switch and a control electrode of the fourth switch are both connected to the second driving unit, wherein the third switch and the fourth switch are alternately turned on according to the driving of the third sub-driving signal and the fourth sub-driving signal; The first sub-driving signal and the third sub-driving signal are in phase, so that when the first switch and the fourth switch are turned on, the second switch and the third switch are turned off, and when the first switch and the fourth switch are turned off, the second switch and the third switch are turned on, and the first power supply voltage obtains the RF driving signal of the AC signal according to the on or off state of the first switch, the second switch, the third switch and the fourth switch.

4. The radio frequency driving circuit according to claim 3, characterized in that: The first switch unit further includes a first inductor and a first capacitor, wherein the first inductor and the first capacitor are connected in series to two ends of the second switch, wherein a resonant frequency of the first inductor and the parasitic capacitance of the first switch or the first inductor and the parasitic capacitance of the second switch is greater than a switching frequency of the first switch, the second switch, the third switch, and the fourth switch; The second switch unit further includes a second inductor and a second capacitor, wherein the second inductor and the second capacitor are connected in series at two ends of the fourth switch, wherein a resonant frequency of the second inductor and the parasitic capacitance of the third switch or a resonant frequency of the second inductor and the parasitic capacitance of the fourth switch is greater than a switching frequency of the first switch, the second switch, the third switch, and the fourth switch.

5. The radio frequency driving circuit according to claim 3, characterized in that: The at least one RF transistor includes a first RF transistor; the coupling unit includes a first transformer, the first transformer has a first winding and a second winding, one end of the first winding is connected to the connection point between the first switch and the second switch, the other end of the first winding is connected to the connection point between the third switch and the fourth switch, one end of the second winding is connected to the control electrode of the first RF transistor, and the other end of the second winding is grounded, wherein the RF drive signal on one side of the first winding is coupled to one side of the second winding, and drives the first RF transistor in the positive half cycle of the RF drive signal of the AC signal.

6. The radio frequency driving circuit according to claim 5, characterized in that: The at least one RF transistor also includes a second RF transistor; the coupling unit also includes a second transformer, the second transformer having a third winding and a fourth winding, one end of the third winding is connected to the connection point between the first switch and the second switch, the other end of the third winding is connected to the connection point between the third switch and the fourth switch, one end of the fourth winding is grounded, and the other end of the fourth winding is connected to the control electrode of the second RF transistor, wherein the RF drive signal on one side of the third winding is coupled to one side of the fourth winding, and drives the second RF transistor in the negative half cycle of the RF drive signal of the AC signal.

7. The radio frequency driving circuit according to claim 3, characterized in that: The second control signal includes a third sub-control signal and a fourth sub-control signal, and the third sub-control signal and the fourth sub-control signal have a second dead time period that is simultaneously at a low level; the first driving unit includes a first driving module and a second driving module, the first driving module is connected to the control electrode of the first switch, and the first driving module is used to power amplify the first sub-control signal to obtain the first sub-driving signal, and the second driving module is connected to the control electrode of the second switch, and the second driving module is used to power amplify the second sub-control signal to obtain the second sub-driving signal; The second driving unit includes a third driving module and a fourth driving module, the third driving module is connected to the control electrode of the third switch, the third driving module is used to power amplify the third sub-control signal to obtain the third sub-driving signal, and the fourth driving module is connected to the control electrode of the fourth switch, the fourth driving module is used to power amplify the fourth sub-control signal to obtain the fourth sub-driving signal.

8. The radio frequency driving circuit according to claim 7, characterized in that: The first driving unit also includes a first power isolation module, a first signal isolation module and a second signal isolation module, the first power isolation module is connected to the first signal isolation module and the first driving module respectively, the first signal isolation module is connected between the first dead zone adjustment circuit and the first driving module, and the second signal isolation module is connected between the first dead zone adjustment circuit and the second driving module, wherein a second power supply voltage provides electric energy for the first driving module, the second driving module, the first signal isolation module and the second signal isolation module, the first power isolation module is used to isolate a power supply that outputs the second power supply voltage from the first driving module and the first signal isolation module, the first signal isolation module is used to isolate the first dead zone adjustment circuit from the first driving module, and the second signal isolation module is used to isolate the first dead zone adjustment circuit from the second driving module; The second driving unit also includes a second power isolation module, a third signal isolation module and a fourth signal isolation module. The second power isolation module is connected to the third signal isolation module and the third driving module respectively. The third signal isolation module is connected between the second dead zone adjustment circuit and the third driving module, and the fourth signal isolation module is connected between the second dead zone adjustment circuit and the fourth driving module. A second power supply voltage provides electrical energy to the third driving module, the fourth driving module, the third signal isolation module and the fourth signal isolation module. The second power isolation module is used to isolate a power supply that outputs the second power supply voltage from the third driving module and the third signal isolation module. The third signal isolation module is used to isolate the second dead zone adjustment circuit from the third driving module, and the fourth signal isolation module is used to isolate the second dead zone adjustment circuit from the fourth driving module.

9. A radio frequency power amplification device, characterized in that: Comprising the radio frequency driving circuit as described in any one of claims 1 to 8.

10. A radio frequency power supply system, characterized in that: Comprising the radio frequency power amplification device as described in claim 9.

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