Data bundling communication protocol implementation system based on snn layered gals architecture

Abstract

This invention provides a data bundling communication protocol implementation system based on an SNN-layered GALS architecture, comprising: a four-phase asynchronous pulse event communication protocol circuit, a two-phase asynchronous pulse event communication protocol circuit, a four-phase to two-phase asynchronous pulse event communication protocol circuit, and a two-phase to four-phase asynchronous pulse event communication protocol circuit; all four circuits are implemented using single-track data bundling asynchronous digital circuits; the single-track data bundling asynchronous digital circuits are implemented based on an asynchronous pipelined structure, ensuring data transmission correctness by directly sending handshake signals between the preceding and following stages.

Description

Technical Field

[0001] This invention relates to the field of asynchronous event-driven SNN neuron communication router circuit technology, specifically to a data bundling communication protocol implementation system based on SNN hierarchical GALS architecture, and more specifically to an asynchronous handshake communication protocol based on four-phase single-track coding protocol, two-phase single-track coding protocol, and mutual conversion between four-phase and two-phase protocols. Background Technology

[0002] Spiking Neural Networks (SNNs), as the third generation of neural networks, possess enormous potential. Due to their brain-like characteristics, SNNs not only have a massive number of interconnected neuron computational cores but also a large number of router communication components. The hierarchical GALS architecture can effectively adapt to the connection and communication characteristics between SNN neurons. Local synchronous clock signals control the computational cores of the spiking neurons and the internal operation of the routers, while asynchronous event-driven circuits handle the communication handshakes and corresponding data transmission between spiking neurons.

[0003] Asynchronous communication of spiking neurons is characterized by high biological similarity, low power consumption, and high frequency. The key technical challenge lies in the need to implement different combinations of communication methods at different levels according to different computing scales; to provide scalability of the SNN computing core while ensuring low-latency information transmission; and to ensure compatibility with different interconnect topologies and communication protocols. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this invention is to provide a data bundling communication protocol implementation system based on an SNN hierarchical GALS architecture.

[0005] According to the present invention, a data bundling communication protocol implementation system based on SNN hierarchical GALS architecture includes: a four-phase asynchronous pulse event communication protocol circuit, a two-phase asynchronous pulse event communication protocol circuit, a four-phase to two-phase asynchronous pulse event communication protocol circuit, or a two-phase to four-phase asynchronous pulse event communication protocol circuit.

[0006] The four-phase asynchronous pulse event communication protocol circuit, the two-phase asynchronous pulse event communication protocol circuit, the four-phase to two-phase asynchronous pulse event communication protocol circuit, or the two-phase to four-phase asynchronous pulse event communication protocol circuit are all implemented using a single-track data-bundled asynchronous digital circuit.

[0007] Preferably, the asynchronous digital circuit for single-track data bundling is implemented based on an asynchronous pipeline structure, and the correctness of data transmission is ensured by directly sending handshake signals between the front and rear stages.

[0008] Preferably, both the four-phase asynchronous pulse event communication protocol circuit and the two-phase asynchronous pulse event communication protocol circuit are implemented using a pipelined Muller-C device combined with a latch unit, and are used to support multi-point broadcast and one-to-one single-point asynchronous communication modes in the SNN hierarchical GALS architecture, respectively.

[0009] Preferably, both the four-phase to two-phase asynchronous pulse event communication protocol circuit and the two-phase to four-phase asynchronous pulse event communication protocol circuit are implemented using a preset edge-triggered circuit, which are used to support the mutual conversion between one-to-one single-point asynchronous communication and multi-point broadcast asynchronous communication modes in the SNN hierarchical GALS architecture.

[0010] Preferably, the four-phase asynchronous pulse event communication protocol circuit includes: a Muller pipeline and an enable latch; the enable control signal of the latch unit is pulled high to realize data latching, and the enable signal is generated by the Muller pipeline.

[0011] Preferably, the two-phase asynchronous pulse event communication protocol circuit includes: a Muller pipeline and a CP latch; the latch unit enters the connected state when the enable signals C and P are the same, realizing data latching, and enters the locked state when the C and P inputs are different, and the latching state ends.

[0012] Preferably, the four-phase to two-phase asynchronous pulse event communication protocol circuit and the two-phase to four-phase asynchronous pulse event communication protocol circuit use a waveform conversion module based on a dual-clock reset circuit, combined with a Muller pipeline, latch unit, D flip-flop and T flip-flop, to realize the mutual conversion of handshake signals between two-phase and four-phase protocols.

[0013] Preferably, the four-phase to two-phase asynchronous pulse event communication protocol circuit includes: a Muller pipeline, an enable latch, a dual-clock reset circuit, and a T flip-flop; wherein, the four-phase req_out signal serves as the clock for the T flip-flop, generating the two-phase req_out signal; the four-phase ack_in signal is generated by the dual-clock reset circuit, which has two input clocks CK1 and CK2; wherein, the input signal of CK1 is the two-phase ack_in signal, and the input signal of CK2 is the four-phase req_out signal; CK1 is a dual-edge triggered clock, and triggering CK1 sets the output to 1, while CK2 is a falling-edge triggered clock, and triggering CK2 sets the output to 0, thus completing the conversion from the four-phase communication handshake protocol to the two-phase communication handshake protocol.

[0014] Preferably, the two-phase to four-phase asynchronous pulse event communication protocol circuit includes: a Muller pipeline, a CP latch, a dual-clock reset circuit, a D flip-flop, and a T flip-flop; wherein, the ack_out signal at the two-phase end is the output of the D flip-flop; the D flip-flop takes the ack_out signal of the Muller pipeline and CP latch combination module as the input signal, and the req_out signal at the two-phase end is the clock signal; the ack_in signal at the four-phase end is used as the clock of the T flip-flop to generate the ack_in signal at the two-phase end, while the req_out signal at the four-phase end is generated by the dual-clock reset circuit, which has two input clocks CK1 and CK2; wherein, the CK2 input signal is the inverted ack_in signal at the four-phase end, and the CK1 input signal is the req_out signal at the two-phase end; CK1 is a dual-edge triggered clock, and the triggering of CK1 sets the output to 1, while CK2 is a falling-edge clock, and the triggering of CK2 sets the output to 0, thus completing the conversion from the two-phase end communication handshake protocol to the four-phase end communication handshake protocol.

[0015] Compared with existing technologies, this invention has the following advantages: The asynchronous data bundling unit implemented in this invention is the core module for implementing handshake protocols in asynchronous routers, and can be directly applied to the neuromorphic interconnect layered GALS architecture. The two-phase handshake protocol is suitable for one-to-one single-point communication, while the four-phase handshake is suitable for multi-point broadcasting. Both transmission modes coexist in the neural network, and the two handshake protocols can be switched flexibly, supporting different information transmission modes, and featuring low power consumption, high frequency, and low latency. Attached Figure Description

[0016] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0017] Figure 1 This invention relates to a four-phase single-rail data bundling communication protocol circuit.

[0018] Figure 2 This invention relates to a two-phase single-track data bundling communication protocol circuit.

[0019] Figure 3 This invention relates to a four-phase to two-phase single-rail data bundling communication protocol circuit.

[0020] Figure 4 This invention relates to a two-phase to four-phase single-rail data bundling communication protocol circuit.

[0021] Figure 5 This is the core circuit of the two-phase and four-phase protocol conversion of the present invention—the dual-clock set-to-1 and set-to-0 circuit.

[0022] Figure 6 This describes the specific process of the four-phase single-track data bundling communication protocol of the present invention.

[0023] Figure 7 This describes the specific process of the two-phase single-track data bundling communication protocol of the present invention.

[0024] Figure 8 This describes the specific process of the four-phase to two-phase data bundling communication protocol of the present invention.

[0025] Figure 9 This describes the specific process of the two-phase to four-phase data bundling communication protocol of the present invention. Detailed Implementation

[0026] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0027] Example 1

[0028] To overcome the challenges of asynchronous communication in the aforementioned SNN hierarchical GALS architecture, this invention provides a data bundling communication protocol implementation system based on the SNN hierarchical GALS architecture. This system includes four-phase, two-phase, four-phase to two-phase, and two-phase to four-phase asynchronous pulse event single-track communication protocol circuits. The two-phase handshake protocol is suitable for one-to-one single-point communication between spiking neurons, while the four-phase handshake is suitable for multi-point broadcast communication between spiking neurons. The protocol conversion can flexibly support different asynchronous pulse event-triggered handshake communication modes, featuring low power consumption, high frequency, and low latency, thus solving the challenges of asynchronous communication between spiking neurons in the SNN hierarchical GALS architecture.

[0029] The data bundling communication protocol implementation system based on the SNN hierarchical GALS architecture provided by the present invention includes four-phase, two-phase, four-phase to two-phase, and two-phase to four-phase asynchronous pulse event communication protocol circuits. All of the circuits are designed using the asynchronous digital circuit concept of single-track data bundling.

[0030] The four communication protocol circuits are implemented based on a unified "asynchronous pipelined" structure, ensuring data transmission correctness by directly sending handshake signals between the preceding and following stages. The pipelined Muller-C devices, combined with latch units, respectively implement four-phase and two-phase single-rail data bundling communication protocol circuits, supporting multi-point broadcast and one-to-one single-point asynchronous communication modes in the SNN hierarchical GALS architecture. The four-phase to two-phase and two-phase to four-phase handshake protocols use a preset edge-triggered circuit to convert between the four-phase and two-phase handshake communication protocols, supporting the mutual conversion between one-to-one single-point asynchronous communication and multi-point broadcast asynchronous communication modes in the SNN hierarchical GALS architecture.

[0031] The four-phase single-rail data bundling communication protocol circuit consists of a Muller pipeline and an enable latch. Data latching is achieved by pulling the enable control signal high in its latch unit, and the enable signal is generated by the Muller pipeline. Assuming that initially req_in, req_out, ack_in, and ack_out are all low (0), when pulse information is transmitted, req_in is set high (1), ack_in remains low (0), and the enable signal, req_out, and ack_out output by the Muller pipeline are set high (1) to perform data latching. Then, ack_in is set high (1), req_in is set low (0), the enable signal is set low (0), data input is invalid, and the circuit enters a zero-reset state.

[0032] The two-phase single-rail data bundling communication protocol circuit consists of a Muller pipeline and a CP latch. Its latching unit enters a connected state when the enable signals C and P are the same, achieving data latching; it enters a locked state when the C and P inputs are different, ending the latching state. Assuming that initially req_in, req_out, ack_in, and ack_out are all low (0), when pulse information is transmitted, req_in flips to high (1), ack_in remains low (0), the C enable signal output from the Muller pipeline is set to high (1), and simultaneously req_out flips to high (1), followed by ack_in flipping to high (1). Since ack_in is connected to the P enable signal of the latching unit, CP is high for data latching. If a pulse signal arrives later, req_in toggles to low (0). At this time, the C enable signal and req_out toggles to low (0), followed by ack_in toggling to low (0). Both CP are low to latch the data and the circuit state remains unchanged.

[0033] The four-phase to two-phase and two-phase to four-phase data bundling communication transmission protocol uses a waveform conversion module based on a dual-clock reset circuit, combined with a Muller pipeline, latch unit, D flip-flop, and T flip-flop, to realize the mutual conversion of handshake signals between two-phase and four-phase protocols. This can directly solve the difficulty of mutual conversion between different asynchronous communication modes of spiking neurons in the SNN hierarchical GALS architecture.

[0034] More specifically, the four-phase to two-phase single-rail data bundling communication protocol circuit consists of a Muller pipeline, an enable latch, a dual-clock reset circuit, and a T flip-flop. The four-phase req_out signal serves as the clock for the T flip-flop, generating the two-phase req_out signal. The four-phase ack_in signal is generated by the dual-clock reset circuit, which has two input clocks, CK1 and CK2. CK1 is the two-phase ack_in input, and CK2 is the four-phase req_out input. CK1 is a dual-edge triggered (DDR) clock, which sets the output to 1, while CK2 is a falling-edge triggered (SDR) clock, which sets the output to 0, thus completing the conversion from a four-phase to a two-phase communication handshake protocol.

[0035] More specifically, the two-phase to four-phase single-rail data bundling communication protocol circuit consists of a Muller pipeline, a CP latch, a dual-clock reset circuit, a D flip-flop, and a T flip-flop. The ack_out signal at the two-phase input is the output of the D flip-flop, which takes the ack_out signal from the Muller-C-Latch-CP (a combination module of the Muller pipeline and the CP latch) as its input signal, and the req_out signal at the two-phase input as its clock signal. The ack_in signal at the four-phase input is used as the clock for the T flip-flop to generate the ack_in signal at the two-phase input, while the req_out signal at the four-phase input is generated by the dual-clock reset circuit, which has two input clocks, CK1 and CK2. The CK2 input signal is the inverted version of the four-phase ack_in signal, and the CK1 input signal is the req_out signal at the two-phase input. Similarly, CK1 is a dual-edge triggered (DDR) clock, which triggers the output to 1, while CK2 is a falling edge triggered (SDR) clock, which triggers the output to 0, thus completing the conversion from a two-phase communication handshake protocol to a four-phase communication handshake protocol.

[0036] Example 2

[0037] Example 2 is a preferred example of Example 1.

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation processes.

[0039] The equivalent digital circuit structure of the four-phase single-rail data bundling communication protocol is as follows: Figure 1 As shown, asynchronous data transmission is achieved through a Muller-C pipeline combined with an enable latch unit. When the enable signal is high (1), the system enters the connected state; when the enable signal is low (0), it enters the locked state. The equivalent digital circuit structure of the two-phase single-rail data bundling communication protocol is as follows: Figure 2As shown, the two-phase asynchronous handshake signal generation circuit is also based on the Muller-C pipeline design. It uses a CP latch unit to realize asynchronous data transmission. When the C and P inputs are the same, it enters the connected state, and when the C and P inputs are different, it enters the locked state.

[0040] The equivalent digital circuit structure of a four-phase to two-phase data bundling communication protocol is as follows: Figure 3 As shown, the equivalent digital circuit structure of the two-phase to four-phase data bundling communication protocol is as follows: Figure 4 As shown, Figure 5 The core circuit for the conversion is the dual-clock set-to-1 / set-to-0 circuit. This circuit has two clocks, CK1 and CK2. CK1 is a dual-edge triggered (DDR) clock, which sets the output to 1 when triggered. CK2 is a falling-edge triggered (SDR) clock, which sets the output to 0 when triggered.

[0041] The following describes the specific process of the invented data bundling communication protocol:

[0042] When performing multi-point broadcast communication of spiking neurons, the invented four-phase single-track data bundling communication protocol is involved, the process of which is as follows: Figure 6 As shown. First, the sending end prepares the data and sees ACK at a low level (0), indicating the receiving end is idle. REQ is then set high (1) to notify the receiving end to receive data. Second, the receiving end sees REQ at a high level (1), completes data latching, and sets ACK at a high level (1) to notify the sending end that data reception is complete. Third, the sending end sees ACK at a high level (1), resets the REQ signal (sets it low), and simultaneously cancels the data transmission. Finally, the receiving end sees REQ at a low level (0), resets the ACK signal (sets it low), and completes one information transmission of the spiking neuron.

[0043] When spiking neurons communicate one-to-one at a single point, the invented two-phase single-track data bundling communication protocol is involved, the process of which is as follows: Figure 7 As shown, in the first step, the transmitting end flips the REQ signal after data preparation to notify the receiving end to receive the data. In the second step, the receiving end sees the REQ flip, completes data latching, and then flips the ACK level to notify the transmitting end that reception has been completed. In the final step, the transmitting end sees the ACK flip, the REQ signal remains unchanged, and simultaneously cancels the data transmission, completing one information transmission cycle of the spiking neuron.

[0044] When communication in a spiking neuron architecture includes one-to-one single-point communication and multi-point broadcast communication, it involves the invented four-phase to two-phase data bundling communication protocol and two-phase to four-phase data bundling communication protocol. The conversion processes of the invention are as follows: Figure 8 , Figure 9As shown. Four-phase to two-phase data bundling communication can convert multi-point broadcast communication to one-to-one single-point communication. Its input consists of four-phase request and response signals, which are adapted to the two-phase request and response signals at the output through a protocol conversion circuit. Conversely, two-phase to four-phase data bundling communication can convert one-to-one single-point communication to multi-point broadcast communication. Its input consists of two-phase request and response signals, which are adapted to the four-phase request and response signals at the output through a protocol conversion circuit.

[0045] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0046] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A system for implementing a data bundling communication protocol based on a hierarchical GALS architecture of SNN, characterized in that, include: Four-phase asynchronous pulse event communication protocol circuit, two-phase asynchronous pulse event communication protocol circuit, four-phase to two-phase asynchronous pulse event communication protocol circuit and two-phase to four-phase asynchronous pulse event communication protocol circuit; The four-phase asynchronous pulse event communication protocol circuit, the two-phase asynchronous pulse event communication protocol circuit, the four-phase to two-phase asynchronous pulse event communication protocol circuit, and the two-phase to four-phase asynchronous pulse event communication protocol circuit are all implemented using single-track data-bundled asynchronous digital circuits. The four-phase to two-phase asynchronous pulse event communication protocol circuit includes: a Muller pipeline, an enable latch, a dual-clock reset circuit, and a T flip-flop. The four-phase req_out signal serves as the clock for the T flip-flop, generating the two-phase req_out signal. The four-phase ack_in signal is generated by the dual-clock reset circuit, which has two input clocks, CK1 and CK2. CK1 is the two-phase ack_in input, and CK2 is the four-phase req_out input. CK1 is a dual-edge triggered clock, and its triggering sets the output to 1. CK2 is a falling-edge triggered clock, and its triggering sets the output to 0, thus completing the conversion from a four-phase to a two-phase communication handshake protocol. The two-phase to four-phase asynchronous pulse event communication protocol circuit includes: a Muller pipeline, a CP latch, a dual-clock reset circuit, a D flip-flop, and a T flip-flop. The ack_out signal at the two-phase input is the output of the D flip-flop. The D flip-flop uses the ack_out signal from the Muller pipeline and CP latch combination module as its input signal, and the req_out signal at the two-phase input is the clock signal. The ack_in signal at the four-phase input is used as the clock for the T flip-flop to generate the ack_in signal at the two-phase input. The req_out signal at the four-phase input is generated by the dual-clock reset circuit, which has two input clocks, CK1 and CK2. The CK2 input signal is the inverted version of the four-phase ack_in signal, and the CK1 input signal is the req_out signal at the two-phase input. CK1 is a dual-edge triggered clock; triggering CK1 sets the output to 1. CK2 is a falling-edge clock; triggering CK2 sets the output to 0, thus completing the conversion from a two-phase to a four-phase communication handshake protocol.

2. The data bundling communication protocol implementation system based on SNN hierarchical GALS architecture according to claim 1, characterized in that, The asynchronous digital circuit for single-track data bundling is implemented based on an asynchronous pipeline structure, and the correctness of data transmission is ensured by directly sending handshake signals between the front and rear stages.

3. The data bundling communication protocol implementation system based on SNN hierarchical GALS architecture according to claim 1, characterized in that, Both the four-phase asynchronous pulse event communication protocol circuit and the two-phase asynchronous pulse event communication protocol circuit are implemented using pipelined Muller-C devices combined with latch units, and are used to support multi-point broadcast and one-to-one single-point asynchronous communication modes in the SNN hierarchical GALS architecture, respectively.

4. The data bundling communication protocol implementation system based on SNN hierarchical GALS architecture according to claim 1, characterized in that, Both the four-phase to two-phase asynchronous pulse event communication protocol circuit and the two-phase to four-phase asynchronous pulse event communication protocol circuit are implemented using a preset edge-triggered circuit, which are used to support the mutual conversion between one-to-one single-point asynchronous communication and multi-point broadcast asynchronous communication modes in the SNN hierarchical GALS architecture.

5. The data bundling communication protocol implementation system based on SNN hierarchical GALS architecture according to claim 4, characterized in that, The four-phase to two-phase asynchronous pulse event communication protocol circuit and the two-phase to four-phase asynchronous pulse event communication protocol circuit use a waveform conversion module based on a dual-clock reset circuit, combined with a Muller pipeline, latch unit, D flip-flop and T flip-flop, to realize the mutual conversion of handshake signals between two-phase and four-phase protocols.

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