A method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, and is applied to the technical field of semiconductors. In the application, after a plurality of cutting grooves are formed, a sacrificial layer is further filled in each cutting groove, then the hard mask layer is removed with the sacrificial layer as a barrier to form an isolation structure between adjacent connecting pad structures; since the sacrificial layer filled in the cutting groove can protect the component materials at the bottom of the cutting groove when the hard mask layer is removed, the problems such as short circuit and electric leakage caused by over-etching when the cutting groove is formed in the prior art are avoided, and the reliability and performance of the semiconductor device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a manufacturing method of semiconductor device. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a kind of volatile memory, including array area composed of a plurality of memory cells and peripheral area composed of control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected with the transistor, and the transistor controls the storage or release of the charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell through the word line (WL) and the bit line (120) across the array area and electrically connected with each memory cell, to control the access of data of each memory cell.

[0003] In order to obtain higher chip density, the structure of the memory cell has developed towards three dimensions, such as using buried word line connection and stacked capacitor technology. The stacked capacitor technology refers to arranging the capacitor of the memory cell above the substrate, and realizing the electrical connection in the vertical direction between the transistor in the substrate and the capacitor through the connection pad structure, thereby saving the substrate area occupied by the capacitor. How to maintain the electrical isolation between the memory cells and at the same time remove the hard mask layer remaining in the preparation of the connection pad structure is an important technical problem faced by the field. SUMMARY

[0004] The purpose of the present application is to provide a manufacturing method of semiconductor device, which can effectively avoid the short circuit, leakage and other problems derived from over-etching of the cutting groove in the prior art, thereby improving the reliability and performance of the semiconductor device.

[0005] To solve the above technical problems, the present application provides a manufacturing method of semiconductor device, which can at least include:

[0006] providing a substrate;

[0007] forming a plurality of mutually separated bit line structures and side wall structures, the bit line structures being located on the substrate, and the side wall structures being located on the side walls of the bit line structures;

[0008] forming a contact structure, a connection pad structure and a hard mask layer stacked from bottom to top, the contact structure being located between adjacent bit line structures, the connection pad structure being located on the contact structure, and the hard mask layer being located on the connection pad structure;

[0009] forming a plurality of cut slots through the hard mask layer, the connection pad structure and the bit line structure, and exposing part of the sidewall structure;

[0010] forming a sacrificial layer in the cut slots, the sacrificial layer covering top surfaces of the sidewall structure;

[0011] removing the hard mask layer with the sacrificial layer as a barrier;

[0012] removing the sacrificial layer and forming an isolation structure between adjacent connection pad structures.

[0013] In some optional examples, the hard mask layer and the sacrificial layer are made of different materials.

[0014] In some optional examples, the sacrificial layer is made of an oxide, and the hard mask layer is made of a nitride.

[0015] In some optional examples, the contact structure is made of a silicon-containing semiconductor material.

[0016] In some optional examples, the method for manufacturing a semiconductor device further comprises, after forming the contact structure and before forming the connection pad structure:

[0017] forming a silicide layer on the contact structure.

[0018] In some optional examples, the top surface of the sidewall structure is higher than the top surface of the silicide layer in the vertical direction.

[0019] In some optional examples, the isolation structure is distributed between the bit line structure and the connection pad structure in the vertical direction.

[0020] In some optional examples, the bottom surface of the isolation structure is higher than the top surface of the silicide layer in the vertical direction.

[0021] In some optional examples, the isolation structure is in direct contact with the sidewall of the corresponding sidewall structure.

[0022] In some optional examples, the process for removing the hard mask layer comprises an etching process, and the etching process comprises at least one of a dry etching process and a wet etching process.

[0023] In the present application, the sacrificial layer filled in the cut slots can protect the materials of the components at the bottom of the cut slots when the hard mask layer is removed, thereby avoiding the problems of short circuit and leakage caused by over-etching when forming the cut slots in the prior art, and further improving the reliability and performance of the semiconductor device. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0025] Figures 1-9 This is a schematic diagram of the structure corresponding to the corresponding steps of the semiconductor device fabrication method provided in the embodiments of the present invention;

[0026] The attached figures are labeled as follows:

[0027] 100 - Substrate; 110 - Insulating layer; R1 - Recess; 101 - Isolation structure; 120 - Bit line structure; 121 - Semiconductor layer; 122 - Barrier layer; 123 - Metal layer; 124 - Cap layer; 130 - Sidewall structure; 131 - First sidewall; 132 - Second sidewall; SNC - Contact structure; 150 - Connector pad material layer; 151 - First connector pad layer; 152 - Second connector pad layer; 160 - Hard mask layer; R2 - Groove; 170 - Sacrificial layer; 170' - Planarized sacrificial layer; 180 - Isolation structure; CP - Capacitor structure; BE - Lower electrode; DL - Dielectric layer; TE - Upper electrode.

[0028] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0029] The method for manufacturing the semiconductor device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0030] As used in this application and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The terms "comprises" and "comprising" are intended to be open-ended, meaning that they include both the recited elements and other elements not recited, which are also claimed. Generally, the term "comprises" is intended to mean that the method or device includes the recited elements, but not excluding others. In describing the embodiments of the present application, specific terminology is used for the sake of clarity. The use of particular descriptive terms is not intended to limit the scope of the present application. Furthermore, the drawings are not drawn to scale unless specifically noted.

[0031] For the convenience of understanding, the horizontal direction and the vertical direction are defined below, wherein the horizontal direction is the direction parallel to the surface of the substrate 100, and the vertical direction is the direction perpendicular to the surface of the substrate 100. Figures 1-9 The X direction and the Y direction are defined in

[0032] Figures 1-9 A schematic diagram of the manufacturing steps of the semiconductor device according to the embodiment of the present application.

[0033] Referring to Figure 1 , first, a substrate 100 is provided, wherein the substrate 100 is any suitable substrate material known in the art, for example, a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), a silicon-on-insulator substrate, or a substrate composed of other suitable material, but not limited thereto. The substrate 100 includes a plurality of isolation structures 101, and a plurality of active regions defined by the plurality of isolation structures 101. The isolation structure 101 can include a single layer or multiple layers of dielectric material, and suitable dielectric material can include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), nitrogen-doped silicon carbon nitride (NDC), low-k dielectric material such as fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or a combination thereof, but not limited thereto. The isolation structure 101 is exemplarily in a strip shape with the long axis extending along the Y direction.

[0034] Please continue to refer to Figure 1, then an etching process is performed to remove part of the insulating layer 110, the substrate 100 and the isolation structure 101, so as to form a recess R1 on the substrate 100, which penetrates the insulating layer 110 and exposes the top surface of the middle part of the active region and the isolation structure 101 on both sides of the middle part. Then, a bit line material stack (not shown) is formed to cover the substrate 101 and fill the recess R1, and an etching process is performed to remove the excess part of the bit line material stack, so as to obtain a plurality of bit line structures 120. The bit line structures 120 respectively extend along the Y direction and are arranged at intervals along the X direction, and are in direct contact with the active region exposed by the recess R1.

[0035] According to an embodiment of the present application, as shown in Figure 1 , the insulating layer 110 can be a single layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but is not limited thereto. The bit line structure 120 has a multi-layer structure, for example, can include a semiconductor layer 121, a barrier layer 122, a metal layer 123 and a cap layer 124 from bottom to top. The material of the semiconductor layer 121 can include crystalline silicon, poly silicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The material of the barrier layer 122 can include metal, metal silicide or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The material of the metal layer 123 can include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy and / or composite layer of the aforementioned metal materials, but is not limited thereto. The cap layer 124 can include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination of the aforementioned materials, but is not limited thereto. According to an embodiment of the present application, the material of the semiconductor layer 121 includes poly silicon, the material of the barrier layer 122 includes cobalt silicide (CoSi), the material of the metal layer 123 includes tungsten (W), and the material of the cap layer 124 includes silicon nitride (SiN).

[0036] Please continue to refer to Figure 1 , then a sidewall structure 130 self-aligned to the sidewall of the bit line structure 120 is formed on both sides of the bit line structure 120; the sidewall structure 130 has a multi-layer structure, for example Figure 1The first sidewall 131 and the second sidewall 132, stacked sequentially along the X direction, are shown. The first sidewall 131 and the second sidewall 132 respectively comprise dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but are not limited thereto. According to one embodiment of the invention, the material of the first sidewall 131 comprises silicon nitride (SiN), while the material of the second sidewall 132 comprises silicon oxide (SiO2). According to one embodiment of the invention, as... Figure 1 As shown, the first sidewall 131 is in direct contact with the sidewall of the bit line 120 structure, and the second sidewall 132 is in direct contact with the contact structure SNC (…). Figure 2 (As shown) direct contact.

[0037] Please see Figure 2 Using an etching process, the Y-direction is etched downwards to form a memory node contact trench on the outer side of the sidewall structure 130 after removing the insulating layer 110 and part of the substrate 100. Then, a contact material layer (not shown) is formed to completely cover the substrate 100 and fill the memory node contact trench. An etching or planarization process is then used to remove the contact material layer outside the memory node contact trench until the top surfaces of the bit line structure 120 and the sidewall structure 130 are exposed, thereby obtaining contact structures SNC located in the memory node contact trench. The contact structures SNC are located between the bit line structures 120, separated from the bit line structures 120 on both sides by the sidewall structure 130 and not in direct contact, while the bottom is in direct contact with the end of the active region. The material of the contact structure SNC may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable silicon-containing semiconductor materials, but is not limited thereto. According to one embodiment of the present invention, the material of the contact structure SNC includes phosphorus-doped silicon (SiP).

[0038] Continue reading Figure 2 Next, a metal material layer (not shown) is formed to completely cover the substrate 100. The metal material layer and the substrate 100 are then silicided to make the material a silicon-containing semiconductor material, such as silicon phosphorus-doped silicon (SiP). The top of the contact structure SNC reacts with the metal material layer to form a silicide layer 140. Then, a connection pad material layer 150 is formed to conformally cover the top surface of the contact structure SNC, the top surface of the sidewall structure 130, and the top surface of the bit line structure 120. Finally, a hard mask layer 160 is formed on the top surface of the connection pad material layer 150. For example... Figure 2As shown, the connecting pad material layer 150 can be a multilayer structure, such as a first connecting pad layer 151 and a second connecting pad layer 152. The material of the first connecting pad layer 151 may include, but is not limited to, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) and other conductive barrier materials. The material of the second connecting pad layer 152 may include metals, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, but is not limited to these. According to one embodiment of the present invention, the material of the first connecting pad layer 151 includes titanium nitride (TiN), the material of the second connecting pad layer 152 includes tungsten (W), and the material of the hard mask layer 160 is silicon nitride.

[0039] Please see Figure 3 Using an etching process, such as dry etching or wet etching, grooves R2 are formed along the Y direction on the hard mask layer 160, the connector pad material layer 150, and a portion of the bit line structure 120 on one side of the bit line structure 120 to expose a portion of the sidewall structure 130. At this time, multiple grooves R2 divide the hard mask layer 160 and the connector pad material layer 150 along the X direction, forming a connector pad structure located on the contact structure SNC and a hard mask layer 160 located on the connector pad structure. According to one embodiment of the present invention, the top surface of the sidewall structure 130 is higher than the top surface of the silicide layer 140 in the Y direction.

[0040] Please see Figure 4 Next, a sacrificial layer 170 is formed to completely cover the substrate 100, that is, the sacrificial layer 170 fills the groove R2 and extends to cover the surface of the hard mask layer 160 located on the connecting pad structure. The material of the sacrificial layer 170 must be different from the material of the hard mask layer 160. Subsequently, the different etching rates of the two are utilized in the etching process to selectively remove the hard mask layer 160. This protects the component materials at the bottom of the groove R2 during the removal of the hard mask layer 160, thus avoiding short circuits and leakage problems caused by over-etching during groove formation in the prior art. According to one embodiment of the present invention, the material of the sacrificial layer 170 includes oxides, such as silicon oxide, but is not limited thereto.

[0041] Please see Figure 5 and Figure 6Next, a planarization process, such as chemical mechanical polishing (CMP), is used to planarize the sacrificial layer 170 until the hard mask layer 160 on the connector pad structure is exposed, resulting in a planarized sacrificial layer 170' flush with the top surface of the hard mask layer 160. Then, an etching process, such as at least one of wet etching and dry etching, is used to etch the planarized sacrificial layer 170' to remove the hard mask layer 160 outside the notch R2. During this etching process, the component material exposed at the bottom of the notch R2, such as the sidewall structure 130, the bit line structure 120, and the material of the connector pad structure exposed on the sidewall of the notch R2, is blocked by the planarized sacrificial layer 170'. Therefore, by adjusting the selectivity of the etching solution in this etching process, the hard mask layer 160 can be selectively removed, resulting in... Figure 6 The structure shown.

[0042] Please see Figure 7 and Figure 8 Next, an etching process is used to remove the remaining planarized sacrificial layer 170' within the groove R2, forming an isolation material layer. Further chemical mechanical polishing (CMP) and etching processes are used to remove excess isolation material, resulting in an isolation structure 180 used to isolate adjacent connection pad structures. The isolation structure 180 is distributed in the Y direction between the bit line structure 120 and the connection pad structure; that is, the bottom surface of the isolation structure 180 is higher than the top surface of the silicide layer 140 in the Y direction, meaning the isolation structure 180 is in direct contact with the sidewall of the corresponding sidewall structure 130. The material of the isolation structure 180 includes nitrides, such as silicon nitride, and may also include oxides, such as silicon oxide. According to an embodiment of the present invention, the material of the isolation structure 180 includes silicon nitride.

[0043] Please see Figure 9 Next, a capacitor structure CP is formed on the connection pad structure, wherein the capacitor structure CP includes a lower electrode BE, a dielectric layer DL, and an upper electrode TE. The lower electrode BE is disposed on the connection pad structure, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper electrode TE and the lower electrode BE.

[0044] It should be understood that "common" in the embodiments of the present invention refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.

[0045] In summary, in the manufacturing method of the semiconductor device provided in the embodiment of the present application, it can specifically include: providing a substrate, forming a plurality of mutually separated bit line structures and side wall structures, the bit line structures being located on the substrate, the side wall structures being located on the side walls of the bit line structures, forming a contact structure, a connection pad structure and a hard mask layer which are sequentially stacked from bottom to top, the contact structure being located between adjacent bit line structures, the connection pad structure being located on the contact structure, the hard mask layer being located on the connection pad structure, forming a plurality of cutting grooves which pass through the hard mask layer, the connection pad structure and the bit line structure and expose part of the side wall structure, forming a sacrificial layer in the cutting groove, the sacrificial layer covering the top surface of the side wall structure, removing the hard mask layer with the sacrificial layer as a barrier, removing the sacrificial layer, and forming an isolation structure between adjacent connection pad structures.

[0046] In the present application, the sacrificial layer filled in the cutting groove can protect the component materials at the bottom of the cutting groove when the hard mask layer is removed, that is, the problems of short circuit and electric leakage caused by over-etching when forming the cutting groove in the prior art are avoided, thereby improving the reliability and performance of the semiconductor device.

[0047] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any such actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0048] Each of the embodiments in the specification is described in a relevant manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments. Especially, for the device, electronic device and computer readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0049] The above only describes the preferred embodiments of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; Multiple mutually separated position line structures and sidewall structures are formed, wherein the position line structures are located on the substrate, and the sidewall structures are located on the sidewalls of the position line structures; A contact structure, a connecting pad structure, and a hard mask layer are formed and stacked sequentially from bottom to top. The contact structure is located between adjacent bit line structures, the connecting pad structure is located on the contact structure, and the hard mask layer is located on the connecting pad structure. Multiple grooves are formed, which pass through the hard mask layer, the connecting pad structure and part of the bit line structure on one side of the bit line structure in a direction perpendicular to the substrate surface, and expose part of the sidewall structure; A sacrificial layer is formed within the groove, and the sacrificial layer covers the top surface of the sidewall structure; Using the sacrificial layer as a barrier, the hard mask layer is removed; Remove the sacrificial layer and form an isolation structure between adjacent connecting pad structures; The hard mask layer and the sacrificial layer are made of different materials.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The material of the sacrificial layer includes oxides, and the material of the hard mask layer includes nitrides.

3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The material of the contact structure includes silicon-containing semiconductor materials.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, After forming the contact structure and before forming the connecting pad structure, the method further includes: A silicide layer is formed on the contact structure.

5. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The top surface of the sidewall structure is higher than the top surface of the silicide layer in the vertical direction.

6. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The isolation structure is distributed vertically between the bit line structure and the connecting pad structure.

7. A method for manufacturing a semiconductor device as described in claim 6, characterized in that, The bottom surface of the isolation structure is higher than the top surface of the silicide layer in the vertical direction.

8. A method for manufacturing a semiconductor device as described in claim 7, characterized in that, The isolation structure is in direct contact with the sidewall of the corresponding sidewall structure.

9. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The process for removing the hard mask layer includes an etching process, which includes at least one of dry etching and wet etching.

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