Cache-based computing circuits, chips, and computing devices

Abstract

The disclosed embodiment discloses a computing circuit, chip and computing device based on cache mapping, wherein the circuit includes: a controller, a first memory and a preset number of storage and computing unit arrays; the first memory includes a preset first target number of buffer rows for storing feature data required for performing convolution operations; the controller determines a second target number of storage and computing unit arrays for performing convolution operations from the preset number of storage and computing unit arrays; the first target number of buffer rows included in the first memory are divided into blocks to obtain buffer blocks corresponding to each storage and computing unit array; the feature data in each buffer block is input into the corresponding storage and computing unit array; the storage and computing unit array calculates the received feature data and the stored weight data, and outputs the calculation result. The disclosed embodiment reduces power consumption waste, alleviates the timing pressure in the back-end layout and wiring stage, the circuit has a better topological structure, and improves the utilization rate of the storage and computing unit array.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a computing circuit, chip and computing device based on cache mapping. Background Art

[0002] The storage and computing unit array is the basic structure of the storage and computing integrated neural network accelerator. Each array has a fixed size and can perform fixed-size matrix multiplication calculations. Almost all calculations in each layer of the neural network can be converted to matrix multiplication operations and can be mapped and arranged in the storage and computing unit array for execution.

[0003] However, the matrix multiplication of a layer in a neural network is large in scale, and it is generally necessary to split a large matrix multiplication into multiple storage and computing unit arrays for calculation. Each array performs a part of the matrix-vector multiplication operation, outputs the partial sum and result, and finally adds these partial sums and results together to get the final result of the large matrix multiplication.

[0004] In a neural network, although the matrix multiplication of one layer is very large, according to its algorithm characteristics, there will be a lot of repetitive feature data and weight data in these matrix multiplications, that is, there are multiple repeated multipliers and multiplicands. If these repeated multipliers and multiplicands need to be read out from the storage space every time, it will cause a lot of power consumption and waste of storage space. The different ways of mapping and arranging to the storage and computing unit array will directly affect the reusability of feature data and weight data. Summary of the invention

[0005] An embodiment of the present disclosure provides a computing circuit based on cache mapping, which includes: a controller, a first memory and a preset number of storage and computing unit arrays; the first memory includes a preset first target number of buffer rows for storing feature data required for performing convolution operations; the controller is used to determine a second target number of storage and computing unit arrays for performing convolution operations from the preset number of storage and computing unit arrays according to the data volume of the target convolution kernel and the number of storage and computing units included in a single storage and computing unit array; according to the number of storage and computing units included in a single storage and computing unit array, the first target number of buffer rows included in the first memory are divided into blocks to obtain buffer blocks corresponding to each storage and computing unit array in the second target number of storage and computing unit arrays; according to the preset correspondence between the storage and computing units in the storage and computing unit array and the storage units in the buffer block, the feature data in each buffer block is input into the corresponding storage and computing unit array; each storage and computing unit array in the second target number of storage and computing unit arrays is used to calculate the received feature data and the stored weight data, and output the calculation result.

[0006] In some embodiments, the circuit further includes an accumulation calculation unit for performing accumulation calculation on the calculation results respectively output by each storage and calculation unit array in the second target number of storage and calculation unit arrays to obtain an accumulation result.

[0007] In some embodiments, the weight data stored in each storage and computing unit array and the feature data stored in each buffer row are arranged in priority order of channel number, column number, and row number.

[0008] In some embodiments, the circuit also includes a second memory; the controller is further used to: in response to triggering a first convolution operation on a target feature map stored in the second memory, extract feature data required for the first convolution operation from the second memory; and store the extracted feature data as feature data in the corresponding buffer rows in sequence by row.

[0009] In some embodiments, the controller is further used to: perform a remainder calculation by dividing the number of rows of the target convolution kernel by the maximum number of rows of weight data that can be stored in a single storage and computing unit array, and obtain a remainder; according to a preset data filling method corresponding to the remainder, the extracted feature data is stored as feature data in the corresponding buffer rows in sequence by row.

[0010] In some embodiments, the controller is further used to: in response to triggering a non-first convolution operation on the target feature map, extract updated feature data of the current convolution operation compared to the previous convolution operation from the second memory; according to a preset data filling method corresponding to the remainder, store the updated feature data as feature data in the corresponding buffer row.

[0011] In some embodiments, the first target number is a preset integer multiple of the maximum number of rows of weight data that can be stored in a single storage and computing unit array.

[0012] In some embodiments, the controller is further used to: round up the quotient obtained by dividing the data volume of the target convolution kernel by the data volume of a single storage and computing unit array to obtain a second target quantity.

[0013] According to another aspect of an embodiment of the present disclosure, a chip is provided, which includes the above-mentioned cache mapping-based computing circuit.

[0014] According to another aspect of an embodiment of the present disclosure, a computing device is provided, which includes the above chip.

[0015] The computing circuit, chip and computing device based on cache mapping provided by the above-mentioned embodiments of the present disclosure, by setting buffer rows and a corresponding number of storage and computing unit arrays, and a mapping relationship between buffer rows and storage and computing unit arrays, that is, according to the number of storage and computing units included in a single storage and computing unit array, multiple buffer rows are divided into blocks to obtain a buffer block corresponding to each storage and computing unit array, and according to the preset correspondence between the storage and computing units in the storage and computing unit array and the storage unit in the buffer block, the data in each buffer block is input into the corresponding storage and computing unit array, thereby realizing the maximum reuse of the data required for the convolution operation, reducing power consumption waste, and eliminating the need for the transmission of input data between storage and computing unit arrays, thereby alleviating the timing pressure of the back-end layout and wiring stage. In addition, it can also support the joint calculation of any number of storage and computing unit arrays, and the data of the storage and computing unit array and the buffer row are closely mapped and arranged, the circuit has a better topological structure, and greatly improves the utilization rate of the storage and computing unit array.

[0016] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps;

[0018] Figure 1 is a schematic diagram of a structure of a computing circuit based on cache mapping provided by an exemplary embodiment of the present disclosure;

[0019] Figure 2 is an exemplary schematic diagram of a cache block and a corresponding storage and computing unit array provided by an exemplary embodiment of the present disclosure;

[0020] Figure 3 is another structural schematic diagram of a computing circuit based on cache mapping provided by an exemplary embodiment of the present disclosure;

[0021] Figure 4 is an exemplary schematic diagram of an arrangement of data in a storage and computing unit array and a buffer row provided by an exemplary embodiment of the present disclosure;

[0022] Figure 5A is an exemplary schematic diagram of a data filling method for a buffer row when the remainder is 2 provided by an exemplary embodiment of the present disclosure;

[0023] Figure 5Bis an exemplary schematic diagram of a data filling method for a buffer row in a multiple convolution operation process when the remainder is 2 provided by an exemplary embodiment of the present disclosure;

[0024] Figure 5C is an exemplary schematic diagram of a mapping relationship between feature data and a storage and computing unit array in a process of multiple convolution operations when the remainder is 2 provided by an exemplary embodiment of the present disclosure;

[0025] Fig. 6A is an exemplary schematic diagram of a data filling method for a buffer row when the remainder is 0 provided by an exemplary embodiment of the present disclosure;

[0026] Figure 6B is an exemplary schematic diagram of a data filling method for a buffer row in a multiple convolution operation process when the remainder is 0 provided by an exemplary embodiment of the present disclosure;

[0027] Figure 6C is an exemplary schematic diagram of a mapping relationship between feature data and a storage and computing unit array in a process of multiple convolution operations when the remainder is 0 provided by an exemplary embodiment of the present disclosure;

[0028] Fig. 7A is an exemplary schematic diagram of a data filling method for a buffer row when the remainder is 1 provided by an exemplary embodiment of the present disclosure;

[0029] Figure 7B is an exemplary schematic diagram of a data filling method for a buffer row in a multiple convolution operation process when the remainder is 1 provided by an exemplary embodiment of the present disclosure;

[0030] Figure 7C It is an exemplary schematic diagram of the mapping relationship between feature data and storage and computing unit arrays in multiple convolution operations when the remainder is 1 provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0032] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0033] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0034] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0035] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0036] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0037] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0038] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0039] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0040] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0041] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0042] Application Overview

[0043] The convolution mapping arrangement method of existing neural network accelerators is not flexible enough. Different convolution specifications need to be manually and pre-configured in a targeted manner. It cannot support the mapping arrangement of any convolution specification. As the number of supported convolution specifications increases, more arrangement logic will be added to the hardware, resulting in a waste of hardware resources and increasing the complexity of the design.

[0044] The mapping method of the existing solution is not sufficiently reusable for feature data and weight data. Repeated reading and writing of stored data will cause more power consumption, increase more buffer space, and occupy a larger chip area.

[0045] Existing solutions usually require the transmission of input feature data between storage and computing unit arrays. As the number of storage and computing unit arrays increases, the timing of the back-end layout and routing stage is difficult to converge.

[0046] The mapping arrangement of the existing solution has a low utilization rate of the storage and computing unit array, which affects the release of computing power.

[0047] In order to solve the above technical problems, the embodiment of the present disclosure provides a computing circuit based on cache mapping. By setting the buffer row and the corresponding number of storage and computing unit arrays, as well as the mapping relationship between the buffer row and the storage and computing unit array, the data required for the convolution operation is reused to the greatest extent, power consumption is reduced, and there is no need to transmit input data between the storage and computing unit arrays, which reduces the timing pressure in the back-end layout and wiring stage. In addition, the solution has a better topological structure, supports joint calculation of any number of unit arrays, and supports convolution of any specifications, increasing the scalability of the convolution circuit.

[0048] Exemplary Structure

[0049] Figure 1 The schematic diagram of the structure of a computing circuit based on cache mapping provided by an exemplary embodiment of the present disclosure is shown in FIG. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0050] like Figure 1 As shown, the circuit includes: a controller 101, a first memory 102 and a preset number of storage and computing unit arrays 103.

[0051] In this embodiment, the first memory 102 includes a preset first target number of buffer lines for storing feature data required for performing a convolution operation. The feature data is usually feature data included in a feature graph targeted by the convolution operation. The first memory 102 can be various types of memory, such as a random access memory (RAM). The area in the first memory 102 for caching feature data required for a convolution operation can exist in the form of buffer lines. Figure 2 As shown, the first target number is 6, that is, the first memory 102 includes 6 buffer lines, buff0-buff5. Since the convolution operation is performed one by one, the first target number of buffer lines stores all the feature data required for one convolution operation. After one convolution operation is completed, the feature data stored in the first target number of buffer lines can be updated, the feature data that can be reused in the next convolution operation is retained, and the feature data newly added in the next convolution operation is added.

[0052] It should be noted that the buffer row here can be an actual row composed of multiple storage units in the physical space, or it can be a logical row, that is, multiple storage units that are not physically arranged in rows, but for the convenience of operation, these storage units are set to storage units that are logically operated in rows.

[0053] In this embodiment, the controller 101 is used to determine a second target number of storage and computing unit arrays 1031 for performing convolution operations from a preset number of storage and computing unit arrays 103 based on the data volume of the target convolution kernel and the number of storage and computing units included in a single storage and computing unit array.

[0054] The target convolution kernel may be a convolution kernel included in a neural network, and the target convolution kernel is usually composed of multiple matrices, each of which corresponds to a channel of a feature map to be convolved. For example, the scale of the target convolution kernel is expressed as W×H×C (W represents the width of the convolution kernel, H represents the height of the convolution kernel, and C represents the number of channels of the convolution kernel).

[0055] Optionally, the quotient obtained by dividing the data volume of the target convolution kernel by the data volume of a single storage and computing unit array may be rounded up to obtain the second target quantity. For example, if the data volume of the target convolution kernel is W×H×C, and the data volume of the weight data stored in a single storage and computing unit array is 3×3×64, then the second target quantity is W×H×C / 3 / 3 / 64. If it cannot be divided evenly, it is rounded up.

[0056] In this embodiment, the controller 101 can further divide the first target number of buffer rows included in the first memory 102 into blocks according to the number of storage and computing units included in a single storage and computing unit array, and obtain buffer blocks corresponding to each storage and computing unit array in the second target number of storage and computing unit arrays 1031.

[0057] Specifically, the buffer block corresponding to each storage and computing unit array can be set according to the arrangement of the data included in the convolution kernel pre-set in the storage and computing unit array. For example, the number of storage and computing units that can be included in a single storage and computing unit array is 3×3×64 (w×h×c), and 64 data corresponding to the same w and h are set as one unit, then each storage and computing unit array includes 3 rows, 3 columns, and 9 units, and the first target number of buffer rows are divided into a buffer block every 3 columns of the first target number of buffer rows according to the same unit division method, so as to determine the buffer blocks corresponding to each storage and computing unit array.

[0058] In this embodiment, the controller 101 may further input the characteristic data in each buffer block into the corresponding storage and computing unit array according to a preset correspondence between the storage and computing units in the storage and computing unit array and the storage units in the buffer block.

[0059] According to the above preset corresponding relationship, the position of the feature data input to each storage unit in each storage unit array in the corresponding buffer block during each convolution operation can be determined.

[0060] like Figure 2 As shown, during the first convolution operation, for buffer block 301, the feature data in the 9 units included in buff0-buff2 are input into the corresponding storage and computing unit array; similarly, for buffer blocks 302 and 303, the feature data in the 9 units included in buff0-buff2 are input into the corresponding storage and computing unit array. Further, during the second convolution operation, for buffer block 301, the feature data in the 9 units included in buff1-buff3 are input into the corresponding storage and computing unit array 304; similarly, for buffer blocks 302 and 303, the feature data in the 9 units included in buff1-buff3 are input into the corresponding storage and computing unit arrays 305 and 306.

[0061] In this embodiment, each storage and computing unit array in the second target number of storage and computing unit arrays 1031 is used to calculate the received feature data and the stored weight data, and output the calculation result.

[0062] Typically, each storage and computing unit in the storage and computing unit array can perform a multiplication operation on the weight data stored therein and the feature data input therein to obtain a corresponding product as a calculation result.

[0063] Optional, such as Figure 3 As shown, the circuit may further include an accumulation calculation unit 104, which is used to accumulate the calculation results output by each storage calculation unit array in the second target number of storage calculation unit arrays 1031 to obtain an accumulation result. Usually, since each storage calculation unit array outputs multiple products, the accumulated result obtained is the calculation result after performing a convolution operation on the feature map using the above-mentioned target convolution kernel. By setting the accumulation calculation unit 104, it is possible to implement the convolution operation by hardware based on the mapping rules based on the buffer row and the storage calculation unit array. The circuit has a better topological structure, supports joint calculation of any number of unit arrays, and supports convolution of any specifications, thereby increasing the scalability of the convolution circuit.

[0064] The circuit provided by the above-mentioned embodiment of the present disclosure sets buffer rows and a corresponding number of storage and computing unit arrays, as well as a mapping relationship between buffer rows and storage and computing unit arrays, that is, according to the number of storage and computing units included in a single storage and computing unit array, multiple buffer rows are divided into blocks to obtain a buffer block corresponding to each storage and computing unit array, and according to the preset correspondence between the storage and computing units in the storage and computing unit array and the storage unit in the buffer block, the data in each buffer block is input into the corresponding storage and computing unit array, thereby realizing the maximum reuse of the data required for the convolution operation, reducing power consumption waste, and eliminating the need for transmission of input data between storage and computing unit arrays, thereby alleviating the timing pressure of the back-end layout and wiring stage. In addition, it can also support the joint calculation of any number of storage and computing unit arrays, and the data of the storage and computing unit array and the buffer row are closely mapped and arranged, so that the circuit has a better topological structure and greatly improves the utilization rate of the storage and computing unit array.

[0065] In some optional implementations, the weight data stored in each storage and computing unit array and the feature data stored in each buffer row are arranged in priority order of channel number (c), column number (w), and row number (h).

[0066] The above column numbers are the numbers of multiple rows of data arranged in the height direction of the feature map and the convolution kernel. Figure 4 As shown, for a feature map with W×H×C of 2×20×64, the coordinates of each cell are expressed as (h, w, c), and each cell represents the data of 64 channels corresponding to the same column number and row number. For example, (0, 0, 0) represents the data of 64 channels in the 0th row and 0th column, and (0, 1, 0) represents the data of 64 channels in the 0th row and 1st column; (1, 0, 0) represents the data of 64 channels in the 1st row and 0th column, and (1, 1, 0) represents the data of 64 channels in the 1st row and 1st column…

[0067] This embodiment arranges the data in each storage unit array and each buffer row in the priority order of channel number, column number, and row number, so that during the convolution operation, according to the rules of the convolution operation, the mapping relationship between the convolution kernel and the feature map can be more conveniently set, thereby improving the flexibility and convenience of the convolution mapping arrangement.

[0068] In some optional implementations, such as Figure 3 As shown, the circuit further includes a second memory 105. The controller 101 may be further used for:

[0069] In response to triggering a first convolution operation on a target feature map stored in the second memory 105, feature data required for the first convolution operation is extracted from the second memory 105; the extracted feature data is stored as feature data in the corresponding buffer rows in sequence row by row.

[0070] The second memory 105 may be the same memory as the first memory 102, or may be a memory different from the first memory 102. It should be understood that the terms "first", "second" and the like described in the embodiments of the present disclosure are only used as functional distinctions and do not limit the physical characteristics of the hardware itself.

[0071] As an example, Figure 5A As shown in the figure, if the size of the target convolution kernel is 5×5×64, during the first convolution operation, the feature data of size 5×5×64 corresponding to this convolution operation is determined from the target feature map, and the feature data is stored in buff0-buff4 row by row.

[0072] This embodiment stores the feature data included in the target feature map in the buffer rows in sequence by row, thereby establishing a mapping relationship between each row of data in the feature map and each buffer row. According to the mapping relationship, the feature data required for the convolution operation process can be conveniently extracted and cached, and then when establishing a mapping relationship between the buffer block and the storage and calculation array, the feature data can be allocated to the corresponding storage and calculation array by row, thereby further improving the flexibility and convenience of the convolution mapping arrangement.

[0073] In some optional implementations, the controller 101 is further configured to:

[0074] The number of rows of the target convolution kernel is divided by the maximum number of rows of weight data that can be stored in a single storage unit array to obtain a remainder; according to a preset data filling method corresponding to the remainder, the extracted feature data is stored as feature data in the corresponding buffer row in sequence.

[0075] As an example, if the size of the target convolution kernel is 5×5×64, that is, the number of rows is 5, the maximum scale of weight data that can be stored in a single storage unit array is 3×3×64, that is, the maximum number of rows is 3, then the remainder of the division of 5 and 3 is 2, and the remainder 2 corresponds to a data filling method.

[0076] like Figure 5A As shown, 501 is the six buffer rows set, including buff0-buff5, each cell in 501 represents the data in the 64 channels corresponding to the same point in the feature map, that is, every 64 feature data is a unit, and the coordinates in each cell are the row coordinates and column coordinates of the feature data. Each cell in 502 represents the data in the 64 channels corresponding to the same point of the target convolution kernel in the storage array, and similarly, every 64 feature data is a unit.

[0077] 502 includes three (i.e., the second target number is 3) 3×3 blocks, each of which represents 9 units stored in a storage unit array. According to the method for determining the second target number described above, the quotient obtained by dividing the data volume of the target convolution kernel (5×5×64) by the maximum scale (3×3×64) of the weight data that can be stored in the storage unit array is rounded up to determine that three storage arrays are required.

[0078] According to the data filling method corresponding to remainder 2, the 5 rows of feature data corresponding to the current convolution operation are first stored in the first 5 columns of cells of buff0-buff4 in sequence, and then the last two rows of feature data corresponding to remainder 2 are stored in the last four columns of cells. Since each row of the last four columns of cells cannot store a complete row of feature data, the remaining cell of each of the last two rows of feature data needs to be stored in buff4.

[0079] In the subsequent processing, you can follow the Figure 5A As shown by the arrows, the feature data in the three buffer blocks in 501 are respectively input into the corresponding three storage and calculation arrays shown in 502, and each storage and calculation array calculates the input feature data and the stored weight data.

[0080] As another example, the maximum scale of weight data that can be stored in the storage and computing unit array remains unchanged. If the size of the target convolution kernel is 5×6×64, that is, the number of rows is 6, then the remainder of 6 and 3 is calculated by division, and the remainder is 0. The remainder 0 corresponds to a data filling method. It should be noted that the quotient of 6 divided by 3 is 2 and the remainder is 0, which is equivalent to the quotient being 1 and the remainder being 3. Therefore, the data filling method corresponding to the remainder 0 can be described here as the data filling method corresponding to the remainder 3.

[0081] like Fig. 6A As shown, 601 is the six buffer rows set, including buff0-buff5. According to the method for determining the second target quantity described above, the quotient obtained by dividing the data volume of the target convolution kernel (5×6×64) by the maximum scale of the weight data that can be stored in the storage and computing unit array (3×3×64) is rounded up to determine that four storage and computing arrays are required. 602 includes four 3×3 blocks, each of which represents 9 units stored in a storage and computing unit array.

[0082] According to the data filling method corresponding to the remainder 3 (or 0), first store the 6 rows of feature data corresponding to the current convolution operation in the first 5 columns of cells of buff0-buff5, and then store the last three rows of feature data corresponding to the remainder 3 in the last 7 columns of cells. In the subsequent processing, you can follow the following steps: Fig. 6A As shown by the arrows, the feature data in the four buffer blocks in 601 are respectively input into the corresponding four storage and calculation arrays shown in 602.

[0083] As another example, the maximum scale of weight data that can be stored in the storage unit array remains unchanged. If the size of the target convolution kernel is 5×4×64, that is, the number of rows is 4, then the remainder of the division of 4 and 3 is 1, and the remainder 1 corresponds to a data filling method.

[0084] like Fig. 7A As shown, 701 is the six buffer rows set, including buff0-buff5. According to the method for determining the second target quantity described above, the quotient obtained by dividing the data volume of the target convolution kernel (5×4×64) by the maximum scale of the weight data that can be stored in the storage and computing unit array (3×3×64) is rounded up to determine that three storage and computing arrays are required. 702 includes three 3×3 blocks, each of which represents 9 units stored in a storage and computing unit array.

[0085] According to the data filling method corresponding to remainder 1, the feature data of the 0th to 3rd rows corresponding to the current convolution operation are first stored in the 0th to 4th columns of buff0-buff3, and then the feature data of the last row (3rd row) corresponding to remainder 1 is stored in the 5th to 8th columns of the cells.

[0086] In the subsequent processing, you can follow the Fig. 7A As shown by the arrows, the feature data in the four buffer blocks in 701 are respectively input into the corresponding three storage and calculation arrays shown in 702.

[0087] This embodiment determines the corresponding data filling method by calculating the remainder, thereby automatically setting the mapping relationship between the feature data stored in the buffer row and the weight data stored in the storage and computing unit array for convolution kernels of various scales, thereby improving the scalability of the convolution operation. At the same time, the feature data in the buffer row can be tightly arranged and mapped to the storage and computing array, thereby maximizing the utilization rate of the storage and computing array.

[0088] In some optional implementations, the controller 101 is further configured to:

[0089] In response to triggering a non-first convolution operation on the target feature map, updated feature data of the current convolution operation compared to the previous convolution operation is extracted from the second memory 105; according to a preset data filling method corresponding to the remainder, the updated feature data is stored as feature data in the corresponding buffer row.

[0090] like Figure 5BAs shown in the figure, if the stride of the convolution is 1, after the first convolution operation is completed, the range of the feature data corresponding to the next convolution in the feature map is relatively moved by one row, that is, the 5th row of the original feature data is stored in buff5, so as to use the corresponding three storage arrays for the second convolution operation. Then, during the third to sixth convolution operations, according to Figure 5B After the feature data in the buffer row is updated, the corresponding three storage and calculation unit arrays are updated as shown in the data filling method. Figure 5C The mapping rules shown receive feature data input therein and perform calculations with the stored weight data.

[0091] Similar, such as Figure 6B and Figure 7B As shown, it shows the data filling method of storing feature data in each buffer row from the second convolution operation to the sixth convolution operation. After the feature data in the buffer row is updated, the corresponding four storage and calculation unit arrays are as follows Figure 6C and Figure 7C The mapping rules shown receive feature data input therein and perform calculations with the stored weight data.

[0092] This embodiment uses a data filling method based on the remainder corresponding to the data. During multiple convolution operations, the feature data that has been updated compared with the previous convolution operation is stored in the corresponding cache line, and the unupdated feature data continues to be stored in the buffer line, thereby achieving maximum reuse of data in the buffer line, reducing power consumption waste caused by data update, reducing the delay caused by data update, and improving the efficiency of convolution operation.

[0093] In some optional implementations, the first target number is a preset integer multiple of the maximum number of rows of weight data that can be stored in a single storage and computing unit array.

[0094] Typically, the preset integer multiple is set to 2. For example, if the scale of weight data that can be stored in a single storage unit array is 3×3×64, the maximum number of rows is 3. Therefore, the first target number is 6, that is, 6 buffer rows are set in the first memory 102.

[0095] This embodiment sets the number of buffer rows to a preset integer multiple of the maximum number of rows of weight data that can be stored in a single storage and computing unit array, so that the number of buffer rows and the number of storage and computing unit arrays can be better matched, thereby helping to better set the circuit topology and improve circuit performance.

[0096] The embodiment of the present disclosure further provides a chip on which a calculation circuit based on cache mapping is integrated. The technical details of the calculation circuit based on cache mapping are as follows: Figure 1-7C As shown in the relevant description, no further description is given here.

[0097] The embodiments of the present disclosure also provide a computing device, which includes the chip described in the above embodiments. In addition, the computing device may also include an input device, an output device, and necessary memory, etc. Among them, the input device may include such as a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting feature data. The output device may include such as a display, a printer, and a communication network and its connected remote output device, etc., for outputting the result of the convolution calculation. The memory is used to store the data input by the above input device, and the data generated during the operation of the computing circuit based on the cache mapping. The memory may include a volatile memory and / or a non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc.

[0098] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0099] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other.

[0100] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0101] The circuits of the present disclosure may be implemented in many ways. For example, the circuits of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the functions of the circuits of the present disclosure. Thus, the present disclosure also covers recording media storing programs for executing the functions of the circuits of the present disclosure.

[0102] It should also be noted that in the circuit of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as an equivalent solution of the present disclosure.

[0103] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0104] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A computing circuit based on cache mapping, comprising: A controller, a first memory and a preset number of storage and computing unit arrays; The first memory includes a preset first target number of buffer lines for storing feature data required to perform a convolution operation; The controller is used to determine a second target number of storage and computing cell arrays for performing convolution operations from the preset number of storage and computing cell arrays according to the data volume of the target convolution kernel and the number of storage and computing cells included in a single storage and computing cell array; block the first target number of buffer rows included in the first memory according to the number of storage and computing cells included in the single storage and computing cell array to obtain buffer blocks corresponding to each storage and computing cell array in the second target number of storage and computing cell arrays, and each storage and computing cell array in the second target number of storage and computing cell arrays corresponds to a buffer block; according to a preset correspondence between the storage and computing cells in the storage and computing cell array and the storage cells in the buffer block, input the characteristic data in each buffer block into the corresponding storage and computing cell array, and the preset correspondence is used to characterize the storage and computing cells in the storage and computing cell array corresponding to the storage cells in each buffer block; Each storage and computing unit array in the second target number of storage and computing unit arrays is used to calculate the received feature data and the stored weight data, and output the calculation result.

2. The circuit according to claim 1, wherein The circuit also includes an accumulation calculation unit, which is used to accumulate the calculation results output by each storage and calculation unit array in the second target number of storage and calculation unit arrays to obtain an accumulation result.

3. The circuit according to claim 1, wherein: The weight data stored in each storage and computing unit array and the feature data stored in each buffer row are arranged in the priority order of channel number, column number, and row number.

4. The circuit according to claim 1, wherein: The circuit also includes a second memory; The controller is further configured to: In response to triggering a first convolution operation on a target feature map stored in a second memory, extracting feature data required for the first convolution operation from the second memory; The extracted feature data is stored as feature data in the corresponding buffer row by row.

5. The circuit according to claim 4, wherein: The controller is further configured to: Performing a remainder calculation on the number of rows of the target convolution kernel and the maximum number of rows of weight data that can be stored in a single storage unit array, to obtain a remainder; According to a preset data filling method corresponding to the remainder, the extracted characteristic data is stored in the corresponding buffer row in sequence as characteristic data.

6. The circuit according to claim 5, wherein: The controller is further configured to: In response to triggering a non-first convolution operation for the target feature map, extracting updated feature data of a current convolution operation compared to a previous convolution operation from the second memory; According to a preset data filling mode corresponding to the remainder, the updated characteristic data is stored as characteristic data in a corresponding buffer row.

7. The circuit according to any one of claims 1 to 6, wherein: The first target number is a preset integer multiple of the maximum number of rows of weight data that can be stored in a single storage and computing unit array.

8. The circuit according to any one of claims 1 to 6, wherein: The controller is further configured to: The quotient obtained by dividing the data volume of the target convolution kernel by the data volume of a single storage and computing unit array is rounded up to obtain the second target quantity.

9. A chip, characterized in that: The method comprises a cache mapping-based computing circuit according to any one of claims 1 to 8.

10. A computing device, characterized in that: Comprising the chip according to claim 9.

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