Transistor, method for manufacturing the same and electronic device

Abstract

The transistor, preparation method thereof and electronic device provided by the present disclosure include a substrate; a gate located on one side of the substrate, the gate defining a gate region; a source and a drain located on the same side of the substrate as the gate, the source and the drain defining source and drain regions spaced from the gate region; a channel layer located between the layer where the gate is located and the substrate, the channel layer including a first via located in the source and drain regions; an n-type heavily doped layer located between the channel layer and the substrate, the orthographic projection of the n-type heavily doped layer on the substrate overlapping the orthographic projection of the first via on the substrate, and the n-type heavily doped layer ohmically contacts the source and drain at the first via. In the process of preparing a transistor with ultra-low ohmic contact resistance, the influence on the gate or epitaxial device of the transistor can be avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a transistor, a manufacturing method thereof, and an electronic device. Background Art

[0002] The third generation of semiconductor materials represented by gallium nitride has a series of advantages such as large bandgap, high electron saturation rate, and high critical breakdown electric field. It is widely used in fields such as radio frequency and power electronics, and can produce high electron mobility transistors (HEMT) with lower on-resistance, higher withstand voltage, and greater power density. The on-resistance directly affects the output power of gallium nitride high electron mobility transistors, and the ohmic contact resistance is an important factor that must be considered when preparing high-performance AlGaN / GaN HEMT devices. Especially in medium and low voltage gallium nitride devices, the ohmic contact resistance accounts for a larger proportion of the overall on-resistance of the device. Therefore, it is of great significance to optimize the gallium nitride contact resistance and prepare ultra-low ohmic contact resistance. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a transistor, a method for manufacturing the same, and an electronic device to solve the impact on the gate or epitaxial device of the transistor during the process of manufacturing a transistor with ultra-low ohmic contact resistance.

[0004] Therefore, the embodiments of the present disclosure provide a transistor, a method for manufacturing the same, and an electronic device, and the specific solutions are as follows:

[0005] In one aspect, an embodiment of the present disclosure provides a transistor, comprising:

[0006] substrate;

[0007] A gate, located at one side of the substrate, wherein the gate defines a gate region;

[0008] A source and a drain are located on the same side of the substrate as the gate, and the source and the drain define source and drain regions spaced apart from the gate region;

[0009] A channel layer, located between the layer where the gate is located and the substrate, the channel layer comprising a first via hole located in the source and drain regions;

[0010] An n-type heavily doped layer is located between the channel layer and the substrate, the orthographic projection of the n-type heavily doped layer on the substrate overlaps with the orthographic projection of the first via hole on the substrate, and the n-type heavily doped layer is in ohmic contact with the source and drain at the first via hole.

[0011] In some embodiments, the transistor provided in the embodiments of the present disclosure further includes an epitaxial layer between the substrate and the channel layer, and the n-type heavily doped layer is partially embedded in the epitaxial layer.

[0012] In some embodiments, the above-mentioned transistor provided by the embodiments of the present disclosure further includes an epitaxial layer located between the substrate and the channel layer, and in the region where the n-type heavily doped layer is located, a surface of the n-type heavily doped layer away from the substrate is coplanar with a surface of the epitaxial layer away from the substrate.

[0013] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, the material of the n-type heavily doped layer includes Si and GaN, and the doping concentration of Si in GaN is 10 15 cm -3 ~10 20 cm -3 The thickness of the n-type heavily doped layer is 10 nm to 5 μm.

[0014] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, the material of the channel layer includes iGaN, and the thickness of the channel layer is 50 nm to 10 μm.

[0015] In some embodiments, the above-mentioned transistor provided by the embodiments of the present disclosure further includes a barrier layer located between the channel layer and the layer where the gate is located, and the barrier layer includes a second via hole that is arranged to penetrate the first via hole.

[0016] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, the material of the barrier layer includes AlGaN, the Al component in AlGaN is 5% to 35%, and the thickness of the barrier layer is 5nm to 100nm.

[0017] In some embodiments, the above-mentioned transistor provided by the embodiments of the present disclosure further includes a p-type heavily doped layer located between the barrier layer and the layer where the gate is located, and the orthographic projection of the p-type heavily doped layer on the substrate covers the orthographic projection of the gate on the substrate.

[0018] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, the material of the p-type heavily doped layer includes Mg and GaN, and the doping concentration of Mg in GaN is 10 17 cm -3 ~10 21 cm -3 , the thickness of the p-type heavily doped layer is 20nm to 1000nm.

[0019] Based on the same inventive concept, the present disclosure provides a method for manufacturing the above transistor, including:

[0020] providing a substrate;

[0021] forming an n-type heavily doped layer locally on the substrate;

[0022] forming a channel layer on the entire surface of the n-type heavily doped layer;

[0023] forming a gate defining a gate region on the channel layer;

[0024] Etching the channel layer to form a first via hole that at least partially exposes the n-type heavily doped layer;

[0025] A source and a drain are formed on the channel layer at the first via hole, which are in ohmic contact with the n-type heavily doped layer and define source and drain regions.

[0026] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, forming an n-type heavily doped layer locally on the substrate specifically includes:

[0027] Forming an insulating layer having a third via hole by patterning on the substrate;

[0028] forming an n-type heavily doped layer at the third via hole by epitaxial growth or ion implantation;

[0029] The insulating layer is removed to obtain the n-type heavily doped layer.

[0030] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, after forming a channel layer on the entire surface of the n-type heavily doped layer and before forming a gate defining a gate region on the channel layer, the method further includes: forming a barrier layer on the entire surface of the channel layer;

[0031] While etching the channel layer to form a first via hole that at least partially exposes the n-type heavily doped layer, the method further includes: etching the barrier layer to form a second via hole that is interpenetrating with the first via hole.

[0032] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, after forming the barrier layer on the entire surface of the channel layer and before forming a gate defining a gate region on the channel layer, the method further includes: forming a p-type heavily doped layer on the entire surface of the barrier layer;

[0033] While forming the gate defining the gate region, the method further includes: forming a p-type heavily doped layer located in the gate region;

[0034] Alternatively, after forming a gate defining the gate region, the method further comprises: using the gate as a shield, etching to form a p-type heavily doped layer located in the gate region.

[0035] In some embodiments, in the above preparation method provided by the embodiments of the present disclosure, while forming the channel layer, barrier layer, and p-type heavily doped layer on the entire surface, it also includes: high temperature activation of the n-type heavily doped layer formed by ion implantation.

[0036] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, after providing a substrate and before forming an n-type heavily doped layer locally on the substrate, it also includes: forming an epitaxial layer on the entire surface of the substrate.

[0037] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, including the above-mentioned transistor provided by an embodiment of the present disclosure.

[0038] The beneficial effects of the present disclosure are as follows:

[0039] The transistor, preparation method thereof and electronic device provided by the embodiments of the present disclosure include a substrate; a gate located on one side of the substrate, the gate defining a gate region; a source and a drain located on the same side of the substrate as the gate, the source and the drain defining source and drain regions spaced apart from the gate region; a channel layer located between the layer where the gate is located and the substrate, the channel layer including a first via located in the source and drain regions; an n-type heavily doped layer located between the channel layer and the substrate, the orthographic projection of the n-type heavily doped layer on the substrate overlapping the orthographic projection of the first via on the substrate, the n-type heavily doped layer making ohmic contact with the source and drain at the first via. Since the n-type heavily doped layer is located below the channel layer and the gate is located above the channel layer, it is necessary to first form the n-type heavily doped layer, then form the channel layer, and then form the gate located above the channel layer during the preparation of the transistor. It can be seen that, unlike the related art in which the gate is formed first and the n-type heavily doped layer is formed later, the present disclosure forms the n-type heavily doped layer first and the gate later. Based on this, the high temperature in the process of forming the n-type heavily doped layer in the present disclosure will not affect the gate, and when the n-type heavily doped layer is formed by the epitaxial process, since the gate has not yet been made, the Ti metal of the gate will not cause contamination to the epitaxial cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1a A schematic diagram of a structure of a transistor provided in an embodiment of the present disclosure;

[0041] Figure 1b A schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;

[0042] Figure 2a A schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;

[0043] Figure 2b A schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;

[0044] Figure 3 A flow chart of manufacturing a transistor provided by an embodiment of the present disclosure;

[0045] Figure 4 for Figure 1a and Figure 2a A schematic diagram of a structure of a transistor during the preparation process shown;

[0046] Figure 5 for Figure 1a and Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0047] Figure 6 for Figure 1a and Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0048] Figure 7 for Figure 1a and Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0049] Figure 8 for Figure 1a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0050] Fig. 9 for Figure 1a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0051] Fig.10 for Figure 1a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0052] Fig.11 for Figure 1a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0053] Fig.12 for Figure 1a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0054] Fig.13 for Figure 1a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0055] Fig.14 for Figure 1a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0056] Fig.15 for Figure 1a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0057] Fig.16 for Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0058] Fig.17 for Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0059] Fig.18 for Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0060] Fig.19 for Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0061] Fig. 20 for Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0062] Fig.21 for Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0063] Fig. 22 for Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0064] Fig.23 for Figure 2a Another schematic diagram of the structure of the transistor during the preparation process shown;

[0065] Fig.24 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that in the drawings, the thickness of the layer, film, panel, area, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shape of the area shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes are not intended to illustrate the exact shape of the area, do not reflect the true proportion, and the purpose is only to illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0067] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0068] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0069] In the relevant preparation process of transistors with ultra-low ohmic contact resistance, a channel layer is first formed on the entire surface, and then a gate is prepared in the gate region. After that, an n-type heavily doped layer is formed on the channel layer corresponding to the source and drain regions, and finally a source and drain with ultra-low ohmic contact resistance between the n-type heavily doped layer and the n-type heavily doped layer are formed. However, the high temperature in the process of forming the n-type heavily doped layer will cause the gate structure to be damaged, affecting the overall performance of the transistor; and when the n-type heavily doped layer is formed by an epitaxial process and the gate material is TiN, since Ti is a highly active metal, the cavity of the epitaxial machine will be contaminated by Ti metal.

[0070] In order to solve the above technical problems existing in the related art, the present disclosure provides a transistor, such as Figure 1a , Figure 1b , Figure 2a and Figure 2b As shown, including:

[0071] Substrate 101; in some embodiments, the substrate 101 may be a Si substrate, a SiC substrate, a sapphire substrate, etc., and the thickness of the substrate 101 is 100μm to 1200μm, for example, 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, 1100μm, 1200μm, etc.

[0072] The gate 102 is located on one side of the substrate 101 and defines a gate region g. Optionally, the material of the gate 102 includes but is not limited to TiN, Ni, Ti / Al, etc. The gate 102 can be a single-layer structure or a composite-layer structure, which is not limited in the present disclosure.

[0073] The source and drain electrodes 105 include a source electrode 1051 and a drain electrode 1052 disposed on the same side of the substrate 101 as the gate electrode 102. The source and drain electrodes 105 define a source and drain region sd disposed spaced apart from the gate region g. In some embodiments, the material of the source and drain electrodes 105 may include a Ti / Al-based material, such as Ti / Al / Ni / Au or Ti / Al / Ti / TiN.

[0074] The channel layer 103 is located between the layer where the gate 102 is located and the substrate 101. The channel layer 103 includes a first via hole V1 located in the source and drain regions sd. Optionally, the size of the first via hole V1 is less than or equal to the size of the source and drain regions sd. In some embodiments, the material of the channel layer 103 includes i GaN, and the thickness of the channel layer 103 is 50nm to 10μm, for example, 50nm, 100nm, 500nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc.

[0075] The n-type heavily doped layer 104 is located between the channel layer 103 and the substrate 101. The n-type heavily doped layer 104 is located in the source and drain regions sd, and the orthographic projection of the n-type heavily doped layer 104 on the substrate 101 overlaps with the orthographic projection of the first via hole V1 on the substrate 101, so that the n-type heavily doped layer 104 is in ohmic contact with the source and drain 105 at the first via hole V1. Optionally, the orthographic projection of the first via hole V1 on the substrate 101 is located within the orthographic projection of the n-type heavily doped layer 104 on the substrate 101, or the orthographic projection of the first via hole V1 on the substrate 101 coincides with the orthographic projection of the n-type heavily doped layer 104 on the substrate 101, or the orthographic projection of the first via hole V1 on the substrate 101 covers the orthographic projection of the n-type heavily doped layer 104 on the substrate 101, or the orthographic projection of the first via hole V1 on the substrate 101 partially overlaps with the orthographic projection of the n-type heavily doped layer 104 on the substrate 101, and the rest do not overlap (i.e., are staggered). In some embodiments, the material of the n-type heavily doped layer 104 includes Si and GaN, and the doping concentration of Si in GaN is 10 15 cm -3 ~10 20 cm -3 , for example, 10 15 cm -3 , 10 16 cm -3 , 10 17 cm -3 , 10 18 cm -3 , 10 19 cm -3 , 10 20 cm -3etc.; the thickness of the n-type heavily doped layer 104 is 10 nm to 5 μm, for example, 10 nm, 50 nm, 100 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.

[0076] In the above transistor provided by the embodiment of the present disclosure, since the n-type heavily doped layer 104 is located below the channel layer 103 and the gate 102 is located above the channel layer 103, it is necessary to first form the n-type heavily doped layer 104, then form the channel layer 103, and then form the gate 102 located above the channel layer 103 during the preparation process of the transistor. It can be seen that, unlike the related art in which the gate 102 is formed first and then the n-type heavily doped layer 104 is formed, the present disclosure forms the n-type heavily doped layer 104 first and then the gate 102 is formed. Based on this, the high temperature in the process of forming the n-type heavily doped layer 104 in the present disclosure will not affect the gate 102, and when the n-type heavily doped layer 104 is formed by the epitaxial process, since the gate 102 has not yet been made, the Ti metal of the gate 102 will not cause contamination to the epitaxial cavity.

[0077] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 1a and Figure 1b As shown, an epitaxial layer 106 located between the substrate 101 and the channel layer 103 may also be included. A growth region of an n-type heavily doped layer may be formed in the source and drain regions sd by an etching process, and an n-type heavily doped layer 104 may be formed on the epitaxial layer 106 by epitaxial growth. In this case, the surface of the n-type heavily doped layer 104 facing the substrate 101 is in contact with the surface of the epitaxial layer 106 away from the substrate 101, and due to the etching accuracy, the epitaxial layer 106 in the source and drain regions sd may have a slight etching loss, so that the n-type heavily doped layer 104 is partially embedded in the epitaxial layer 106. In some embodiments, the epitaxial layer 106 includes a stacked nucleation layer 1061 and a buffer layer 1062, the surface of the n-type heavily doped layer 104 facing the substrate 101 is specifically in contact with the surface of the buffer layer 1062 away from the substrate 101, and the n-type heavily doped layer 104 is partially embedded in the buffer layer 1062.

[0078] In some embodiments, in the above transistor provided in the embodiments of the present disclosure, the n-type heavily doped layer 104 may also be formed by ion implantation. In this case, Figure 2a and Figure 2bAs shown, in the region where the n-type heavily doped layer 104 is located, the surface of the n-type heavily doped layer 104 away from the substrate 101 can be coplanar with the surface of the epitaxial layer 106 away from the substrate 101. Exemplarily, the epitaxial layer 106 includes a stacked nucleation layer 1061 and a buffer layer 1062, and the surface of the n-type heavily doped layer 104 away from the substrate 101 is specifically coplanar with the surface of the buffer layer 1062 away from the substrate 101.

[0079] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, the above-mentioned "coplanarity" may be exactly coplanar or may have some deviations. Therefore, as long as the "coplanarity" relationship between the above-mentioned features satisfies the error allowance, it belongs to the protection scope of the present disclosure.

[0080] In some embodiments, the material of the nucleation layer 1061 of the present disclosure includes but is not limited to AlN / AlSiN, and the thickness of the nucleation layer 1061 is 1 nm to 500 nm, for example, 1 nm, 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, etc. The material of the buffer layer 1062 may include GaN, and the thickness of the buffer layer 1062 is 50 nm to 10 μm, for example, 5 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0081] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 1a , Figure 1b , Figure 2a and Figure 2bAs shown, a barrier layer 107 is also included between the channel layer 103 and the layer where the gate 102 is located. Optionally, the material of the barrier layer 107 includes AlGaN, and the Al component in AlGaN is 5% to 35%, for example, 5%, 10%, 15%, 20%, 25%, 30%, 35%, etc.; the thickness of the barrier layer 107 is 5nm to 100nm, for example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc. A two-dimensional electron gas (2DEG) is formed between the barrier layer 107 made of AlGaN and the channel layer 103 made of iGaN, and the source 1051 and the drain 1052 can transmit electrical energy through a current path formed by the two-dimensional electron gas. In some embodiments, to achieve ohmic contact between the source and drain electrodes 105 and the n-type heavily doped layer 104 below the channel layer 103 , the barrier layer 107 may include a second via hole V2 that penetrates the first via hole V1 of the channel layer 103 .

[0082] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 1a , Figure 1b , Figure 2a and Figure 2b As shown, it also includes a p-type heavily doped layer 108 located between the barrier layer 107 and the layer where the gate 102 is located, and the orthographic projection of the p-type heavily doped layer 108 on the substrate 101 covers the orthographic projection of the gate 102 on the substrate 101. Optionally, as shown in Figure 1a and Figure 2a As shown, the size of the p-type heavily doped layer 108 can be the same as the size of the gate 102; or Figure 1b and Figure 2b As shown, the p-type heavily doped layer 108 may be expanded outward compared to the gate 102, that is, the gate 102 is retracted inward compared to the p-type heavily doped layer 108. In some embodiments, the material of the p-type heavily doped layer 108 includes Mg and GaN, and the doping concentration of Mg in GaN is 10 17 cm -3 ~10 21 cm -3 , for example, 10 17 cm -3 , 10 18 cm -3 , 10 19 cm -3 , 10 20 cm -3 , 10 21 cm -3etc.; the thickness of the p-type heavily doped layer is 20nm to 1000nm. When the gate 102 is not applied with a positive voltage, the p-type heavily doped layer 108 can deplete the two-dimensional electron gas thereunder, so that the two-dimensional electron gas between the source 1051 and the drain 1052 is disconnected, and at this time, the transistor is turned off; when the gate 102 is applied with a positive voltage greater than the threshold voltage, the transistor is turned on.

[0083] In some embodiments, in the above transistors provided in the embodiments of the present disclosure, if Figure 1a , Figure 1b , Figure 2a and Figure 2b As shown, it may also include a passivation layer 109 covering the gate 102 and the barrier layer 107, and the passivation layer 109 includes a fourth via hole V4 that is connected to the second via hole V2 of the barrier layer 107, and the source and drain 105 are in ohmic contact with the n-type heavily doped layer 104 via the fourth via hole V4, the second via hole V2, and the first via hole V1. Other essential components of the transistor should be understood by those skilled in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.

[0084] Based on the same inventive concept, the present disclosure provides a method for preparing the above transistor, such as Figure 3 As shown, the following steps may be included:

[0085] S301, providing a substrate;

[0086] S302, forming an n-type heavily doped layer locally on the substrate;

[0087] S303, forming a channel layer on the entire surface of the n-type heavily doped layer;

[0088] S304, forming a gate defining a gate region on the channel layer;

[0089] S305, etching the channel layer to form a first via hole that at least partially exposes the n-type heavily doped layer;

[0090] S306 , forming a source and a drain on the channel layer at the first via hole, which are in ohmic contact with the n-type heavily doped layer and define source and drain regions.

[0091] It can be seen from the above preparation method that the present invention first forms an n-type heavily doped layer and then forms a gate. Based on this, the high temperature in the process of forming the n-type heavily doped layer in the present invention will not affect the gate, and when the n-type heavily doped layer is formed by the epitaxial process, since the gate has not yet been made, the Ti metal of the gate will not cause contamination to the epitaxial cavity.

[0092] In order to better understand the above preparation method provided by the embodiments of the present disclosure, Figure 1aand Figure 2a The preparation process of the transistor shown is described in detail.

[0093] in, Figure 1a The preparation process of the transistor shown may specifically include the following steps:

[0094] The first step, such as Figure 4 As shown, a substrate 101 is provided. The substrate 101 may be a Si substrate, a SiC substrate, a sapphire substrate, etc. The thickness of the substrate 101 is 100 μm to 1200 μm.

[0095] The second step is, Figure 5 As shown, an epitaxial layer 106 including a nucleation layer 1061 and a buffer layer 1062 is formed on a substrate 101, wherein the nucleation layer 1061 may be a composite layer of AlN / AlSiN, but not limited to AlN / AlSiN, with a thickness of 1nm to 500nm; the buffer layer 1062 may be a GaN layer with a thickness of 50nm to 10μm.

[0096] The third step is Figure 6 As shown, an insulating layer 110 composed of at least one material such as silicon oxide and silicon nitride is deposited on the buffer layer 1062 by in-situ growth, plasma enhanced chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition, etc., and the thickness of the insulating layer 110 can be 10nm to 600nm, for example, 10nm, 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, etc.; and then a third via hole V3 for growing the n-type heavily doped layer 104 is prepared by processes such as photolithography and etching, and the buffer layer 1062 is slightly lost at the third via hole V3 due to the etching process, as shown in FIG. Figure 7 shown.

[0097] The fourth step is Figure 8 As shown, epitaxial growth of the n-type heavily doped layer 104 is performed at the third via hole V3 (equivalent to the source and drain regions sd) by secondary epitaxy, so that the n-type heavily doped layer 104 is partially embedded in the buffer layer 1062. The growth method of the n-type heavily doped layer 104 can be organic metal chemical vapor deposition, molecular beam epitaxy, etc. The n-type heavily doped layer 104 can be Si-doped GaN, and the Si concentration is 1*10 15 cm -3 ~10 20 cm -3 , thickness is 10nm~5μm.

[0098] Step 5: Fig. 9 As shown, the insulating layer 110 on the buffer layer 1062 is removed by a dry or wet etching process, so that the n-type heavily doped layer 104 and the buffer layer 1062 are exposed.

[0099] Step 6: Figures 10 to 12 As shown, epitaxial growth of a channel layer 103, a barrier layer 107 and a p-type heavily doped layer 108 is sequentially performed on the n-type heavily doped layer 104; wherein the channel layer 103 may be an iGaN layer with a thickness of 50nm to 10μm; the barrier layer 107 may be an AlGaN layer, in which the Al component is 5% to 35%, and the thickness of the AlGaN layer is 5nm to 100nm; the p-type heavily doped layer 108 may be a PGaN layer, which may be doped with Mg, and the doping concentration is 1*10 17 cm -3 ~10 21 cm -3 , thickness is 20nm~1000nm.

[0100] Step 7: Fig.13 As shown, a gate metal layer is deposited, and the gate metal layer and the p-type heavily doped layer are processed by processes such as photolithography, etching, and annealing to obtain a gate 102 and a p-type heavily doped layer 108 defining a gate region g; in some embodiments, two etching processes may be performed to form the gate 102 and the p-type heavily doped layer 108 respectively. The gate 102 may be a composite layer such as TiN, Ni, and Ti / Al, but is not limited thereto. The metal deposition method may be sputtering, evaporation, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc. During the etching process of the gate metal layer and the p-type heavily doped layer 108, the loss amount of the barrier layer 107 is 1nm to 10nm.

[0101] Step 8: Fig.14 As shown, a dielectric layer or a combination of several film layers is deposited as a passivation layer 109 by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) and other processes, and the thickness can be 10nm to 600nm to passivate and protect the barrier layer 107 and the gate 102, and ion implantation or mesa etching is used to form an isolation member 111. The ion implantation can be helium ion implantation or nitrogen ion implantation to form a high resistance region to achieve device isolation.

[0102] Step 9: Fig.15 As shown, a fourth via hole V4 overlapping with the n-type heavily doped layer 104 and penetrating the passivation layer 109, a second via hole V2 penetrating the barrier layer 107, and a first via hole V1 penetrating the channel layer 103 are formed by photolithography, etching and other processes, and the first via hole V1, the second via hole V2, and the fourth via hole V4 are connected from top to bottom.

[0103] Step 10: Figure 1aAs shown, a source-drain metal layer is deposited, and a source and a drain 105 including a source 1051 and a drain 1052 are formed by etching, annealing and other processes, so that the source and the drain 105 form an ohmic contact with the n-type heavily doped layer 104 through a first via hole V1, a second via hole V2, and a fourth via hole V4 that penetrate from top to bottom. The metal structure used in the source-drain metal layer is a titanium / aluminum-based material, which can be titanium / aluminum / nickel / gold or titanium / aluminum / titanium / titanium nitride. The deposition method of the source-drain metal layer is an evaporation coating method or a sputtering coating method. The annealing adopts rapid thermal annealing (RTA), the annealing environment is nitrogen, the annealing temperature is 500°C to 900°C, and the annealing time is 20s to 100s.

[0104] So far, Figure 1a The basic structure of the transistor shown is completed, and the final processing of the electronic device containing the transistor is completed by subsequently making field plates, metal connections, and final passivation.

[0105] It should be noted that Figure 2a The transistor shown with Figure 1a The difference of the transistor shown is that the n-type heavily doped layer 104 is realized by ion implantation, and the n-type heavily doped layer 104 is activated by utilizing the high temperature during the epitaxial growth of the channel layer 103, the barrier layer 107, and the p-type heavily doped layer 108, thereby saving the annealing activation process for the n-type heavily doped layer 104.

[0106] In some embodiments, Figure 2a The preparation process of the transistor shown may include the following steps:

[0107] The first step, such as Figure 4 As shown, a substrate 101 is provided. The substrate 101 may be a Si substrate, a SiC substrate, a sapphire substrate, etc. The thickness of the substrate 101 is 100 μm to 1200 μm.

[0108] The second step is, Figure 5 As shown, an epitaxial layer 106 including a nucleation layer 1061 and a buffer layer 1062 is formed on a substrate 101, wherein the nucleation layer 1061 may be a composite layer of AlN / AlSiN, but not limited to AlN / AlSiN, with a thickness of 1nm to 500nm; the buffer layer 1062 may be a GaN layer with a thickness of 50nm to 10μm.

[0109] The third step is Figure 6As shown, an insulating layer 110 composed of at least one material such as silicon oxide and silicon nitride is deposited on the buffer layer 1062 by in-situ growth, plasma enhanced chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition, etc., and the thickness of the insulating layer 110 can be 10nm to 600nm, for example, 10nm, 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, etc.; and then a third via hole V3 for growing the n-type heavily doped layer 104 is prepared by processes such as photolithography and etching, as shown in FIG. Figure 7 shown.

[0110] The fourth step is Fig.16 As shown, an ion implantation process is used to perform ion implantation doping at the third via hole V3 (equivalent to the source and drain regions sd), the doping element may be Si element, the energy is 50KeV to 500KeV, and the dose is 1*10 15 cm -3 ~10 18 cm -3 , an n-type heavily doped layer 104 is formed, the thickness of which is 10 nm to 5 μm, and the upper surface of the n-type heavily doped layer 104 is coplanar with the upper surface of the buffer layer 1062 .

[0111] Step 5: Fig.17 As shown, the insulating layer 110 on the buffer layer 1062 is removed by a dry or wet etching process, so that the n-type heavily doped layer 104 and the buffer layer 1062 are exposed.

[0112] Step 6: Figures 18 to 20 As shown, epitaxial growth of a channel layer 103, a barrier layer 107 and a p-type heavily doped layer 108 is sequentially performed on the n-type heavily doped layer 104, and the n-type heavily doped layer 104 is activated by high temperature during epitaxial growth; wherein the channel layer 103 may be an iGaN layer with a thickness of 50nm to 10μm; the barrier layer 107 may be an AlGaN layer, the Al component in the AlGaN is 5% to 35%, and the thickness of the AlGaN layer is 5nm to 100nm; the p-type heavily doped layer may be a PGaN layer, which may be doped with Mg, and the doping concentration is 1*10 17 cm -3 ~10 21 cm -3 , thickness is 20nm~1000nm.

[0113] Step 7: Fig.21As shown, a gate metal layer is deposited, and the gate metal layer and the p-type heavily doped layer are processed by processes such as photolithography, etching, and annealing to obtain a gate 102 and a p-type heavily doped layer 108 defining a gate region g; in some embodiments, two etching processes may be performed to form the gate 102 and the p-type heavily doped layer 108 respectively. The gate 102 may be a composite layer such as TiN, Ni, and Ti / Al, but is not limited thereto. The metal deposition method may be sputtering, evaporation, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc. During the etching process of the gate metal layer and the p-type heavily doped layer 108, the loss amount of the barrier layer 107 is 1nm to 10nm.

[0114] Step 8: Fig. 22 As shown, a dielectric layer or a combination of several film layers is deposited as a passivation layer 109 by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) and other processes, and the thickness can be 10nm to 600nm to passivate and protect the barrier layer 107 and the gate 102, and ion implantation or mesa etching is used to form an isolation member 111. The ion implantation can be helium ion implantation or nitrogen ion implantation to form a high resistance region to achieve device isolation.

[0115] Step 9: Fig.23 As shown, a fourth via hole V4 overlapping with the n-type heavily doped layer 104 and penetrating the passivation layer 109, a second via hole V2 penetrating the barrier layer 107, and a first via hole V1 penetrating the channel layer 103 are formed by photolithography, etching and other processes, and the first via hole V1, the second via hole V2, and the fourth via hole V4 are connected from top to bottom.

[0116] Step 10: Figure 2a As shown, a source-drain metal layer is deposited, and a source and drain electrode 105 including a source electrode 1051 and a drain electrode 1052 is formed by etching, annealing and other processes, so that the source and drain electrode 105 form an ohmic contact with the n-type heavily doped layer 104 through a first via hole V1, a second via hole V2, and a fourth via hole V4 that penetrate from top to bottom. The metal structure used in the source-drain metal layer is a titanium / aluminum-based material, which can be titanium / aluminum / nickel / gold or titanium / aluminum / titanium / titanium nitride. The deposition method of the source-drain metal layer is an evaporation coating method or a sputtering coating method. The annealing adopts a rapid thermal annealing (RTA), the annealing environment is nitrogen, the annealing temperature is 500°C to 900°C, and the annealing time is 20s to 100s.

[0117] So far, Figure 2a The basic structure of the transistor shown is completed, and the final processing of the electronic device containing the transistor is completed by subsequently making field plates, metal connections, and final passivation.

[0118] It should be noted that in the above-mentioned preparation method provided in the embodiment of the present disclosure, the patterning process involved in forming each layer structure may include not only part or all of the process such as deposition, photoresist coating, mask template masking, exposure, development, etching, photoresist stripping, etc., but also other process, which is subject to the pattern of the required pattern formed in the actual production process and is not limited here. For example, a post-baking process may also be included after development and before etching.

[0119] Based on the same inventive concept, the present disclosure provides an electronic device, such as Fig.24 As shown, it includes the transistor 001 provided in the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the transistor, the implementation of the electronic device provided in the embodiment of the present disclosure can refer to the implementation of the transistor provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0120] In some embodiments, the electronic device provided by the embodiments of the present disclosure may include but is not limited to: radio frequency amplifiers, mixers, radars, satellites, etc. Of course, the electronic device provided by the present disclosure may include other structures in addition to transistors. For example, when the electronic device is a radar, it also includes: transmitters, antennas, receivers, etc.; when the electronic device is a mixer, it also includes: input ports, output ports, etc.

[0121] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A transistor, characterized in that: include: substrate; A gate, located at one side of the substrate, wherein the gate defines a gate region; A source and a drain are located on the same side of the substrate as the gate, and the source and the drain define source and drain regions spaced apart from the gate region; A channel layer, located between the layer where the gate is located and the substrate, the channel layer comprising a first via hole located in the source and drain regions; An n-type heavily doped layer is located between the channel layer and the substrate, the orthographic projection of the n-type heavily doped layer on the substrate overlaps with the orthographic projection of the first via hole on the substrate, and the n-type heavily doped layer is in ohmic contact with the source and drain at the first via hole.

2. The transistor according to claim 1, wherein The method further comprises an epitaxial layer located between the substrate and the channel layer, wherein the n-type heavily doped layer is partially embedded in the epitaxial layer.

3. The transistor according to claim 1, wherein It also includes an epitaxial layer located between the substrate and the channel layer. In the region where the n-type heavily doped layer is located, a surface of the n-type heavily doped layer away from the substrate is coplanar with a surface of the epitaxial layer away from the substrate.

4. The transistor according to any one of claims 1 to 3, characterized in that: The material of the n-type heavily doped layer includes Si and GaN, and the doping concentration of Si in GaN is 10 15 cm -3 ~10 20 cm -3 The thickness of the n-type heavily doped layer is 10 nm to 5 μm.

5. The transistor according to any one of claims 1 to 3, characterized in that: The material of the channel layer includes i GaN, and the thickness of the channel layer is 50 nm to 10 μm.

6. The transistor according to any one of claims 1 to 3, characterized in that: It also includes a barrier layer located between the channel layer and the layer where the gate is located, and the barrier layer includes a second via hole that is arranged to penetrate the first via hole.

7. The transistor according to claim 6, characterized in that The material of the barrier layer includes AlGaN, the Al component in AlGaN is 5% to 35%, and the thickness of the barrier layer is 5nm to 100nm.

8. The transistor according to claim 6, characterized in that It also includes a p-type heavily doped layer located between the barrier layer and the layer where the gate is located, and the orthographic projection of the p-type heavily doped layer on the substrate covers the orthographic projection of the gate on the substrate.

9. The transistor according to claim 8, characterized in that The material of the p-type heavily doped layer includes Mg and GaN, and the doping concentration of Mg in GaN is 10 17 cm -3 ~10 21 cm -3 , the thickness of the p-type heavily doped layer is 20nm to 1000nm.

10. A method for preparing a transistor according to any one of claims 1 to 9, characterized in that: include: providing a substrate; forming an n-type heavily doped layer locally on the substrate; forming a channel layer on the entire surface of the n-type heavily doped layer; forming a gate defining a gate region on the channel layer; Etching the channel layer to form a first via hole that at least partially exposes the n-type heavily doped layer; A source and a drain are formed on the channel layer at the first via hole, which are in ohmic contact with the n-type heavily doped layer and define source and drain regions.

11. The preparation method according to claim 10, characterized in that: Forming an n-type heavily doped layer locally on the substrate specifically includes: Forming an insulating layer having a third via hole by patterning on the substrate; forming an n-type heavily doped layer at the third via hole by epitaxial growth or ion implantation; The insulating layer is removed to obtain the n-type heavily doped layer.

12. The preparation method according to claim 11, characterized in that: After forming a channel layer on the entire surface of the n-type heavily doped layer and before forming a gate defining a gate region on the channel layer, the method further includes: forming a barrier layer on the entire surface of the channel layer; While etching the channel layer to form a first via hole that at least partially exposes the n-type heavily doped layer, the method further includes etching the barrier layer to form a second via hole that penetrates the first via hole.

13. The preparation method according to claim 12, characterized in that: After forming a barrier layer on the entire surface of the channel layer and before forming a gate defining a gate region on the channel layer, the method further includes: forming a p-type heavily doped layer on the entire surface of the barrier layer; While forming the gate defining the gate region, the method further includes: forming a p-type heavily doped layer located in the gate region; Alternatively, after forming a gate defining the gate region, the method further comprises: using the gate as a shield, etching to form a p-type heavily doped layer located in the gate region.

14. The preparation method according to claim 13, characterized in that: While forming the channel layer, the barrier layer and the p-type heavily doped layer on the entire surface, the method also includes: activating the n-type heavily doped layer formed by ion implantation at a high temperature.

15. The preparation method according to any one of claims 10 to 14, characterized in that: After providing a substrate and before forming an n-type heavily doped layer locally on the substrate, the method further includes: forming an epitaxial layer on the entire surface of the substrate.

16. An electronic device, characterized in that: Comprising the transistor according to any one of claims 1 to 9.

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