Multi-level driving circuit and method for suppressing siC mosfet cross-talk

Abstract

The application discloses a kind of multi-level drive circuit and method for inhibiting SiC MOSFET crosstalk, it is related to power electronics field.The multi-level drive circuit of the application includes control component, drive circuit and auxiliary circuit, the circuit has the function of simultaneously inhibiting SiC MOSFET positive crosstalk and negative crosstalk, when positive crosstalk occurs, the gate-source voltage of SiC MOSFET is controlled to be negative voltage, so as to inhibit positive crosstalk voltage, when negative crosstalk occurs, the gate-source voltage of SiC MOSFET is controlled to be zero voltage, so as to inhibit negative crosstalk voltage, by three segment drive voltage control, positive and negative crosstalk voltage is kept within safe threshold.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a multilevel drive circuit and method for suppressing crosstalk in SiC MOSFETs. Background Technology

[0002] SiC materials, due to their high breakdown voltage, wide bandgap, high thermal conductivity, high electron saturation velocity, and high carrier mobility, have led to the widespread adoption of Si-based devices in power electronics, replacing Si-based devices. Among these, SiC MOSFETs are currently the most commonly used SiC devices, offering advantages such as high switching frequency, high temperature resistance, and low conduction losses, making them the most promising for application. However, increasing the switching frequency and speed of SiC MOSFETs generates significant du / dt and di / dt during turn-on and turn-off. Furthermore, the crosstalk problem is exacerbated by stray parameters in the circuit loop, easily causing SiC MOSFETs to mis-turn on, resulting in shoot-through of the upper and lower bridge arms. This shoot-through current not only increases additional switching losses but can even break down the SiC MOSFET. Crosstalk limits the improvement of SiC MOSFET switching frequency, affecting the optimization of converter efficiency and power density; therefore, the crosstalk problem of SiC MOSFETs must be suppressed.

[0003] Traditional crosstalk suppression circuits are mainly divided into the following types:

[0004] (1) Connect a capacitor larger than the gate-source parasitic capacitance in parallel across the SiC MOSFET. This can reduce the impedance of the drive circuit and suppress crosstalk voltage. However, this method will reduce the switching speed of the SiC MOSFET and thus increase the switching loss.

[0005] (2) Using negative voltage to turn off SiC MOSFET can effectively suppress forward crosstalk voltage, but it exacerbates reverse crosstalk voltage, causing the reverse crosstalk voltage to exceed the gate negative voltage limit of SiC MOSFET.

[0006] (3) Add a transistor series capacitor branch or a MOSFET series capacitor branch to the SiC MOSFET to provide a low-impedance conduction loop through the conduction of the transistor or MOSFET. However, this method has limited effect on suppressing forward voltage crosstalk and reverse voltage crosstalk. Summary of the Invention

[0007] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a multilevel driving circuit and method for suppressing SiC MOSFET crosstalk.

[0008] The technical solution adopted in this invention is:

[0009] A multi-level drive circuit for suppressing SiC MOSFET crosstalk includes:

[0010] The control component includes a first control signal source V3 and a second control signal source V4, which are used to generate control signals to control the turning on and off of the SiC MOSFET;

[0011] The driving circuit includes an upper driving chain circuit, a lower driving chain circuit, a first power supply V1, and a second power supply V2.

[0012] The upper drive chain circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventeenth MOS transistor. The drain of the first MOS transistor is connected to the drain of the fourth MOS transistor, and the connection point is connected to the gate of the second MOS transistor and the gate of the fifth MOS transistor. The drain of the second MOS transistor is connected to the drain of the fifth MOS transistor, and the connection point is connected to the gate of the third MOS transistor and the gate of the sixth MOS transistor. The drain of the third MOS transistor is connected to the drain of the sixth MOS transistor, and the connection point is connected to the gate of the seventeenth MOS transistor. The positive terminal of the first control signal source V3 is connected to the gate of the first MOS transistor and the gate of the fourth MOS transistor. The positive terminal of the first power supply V1 is connected to the source of the first MOS transistor, the source of the second MOS transistor, the source of the third MOS transistor, and the source of the seventeenth MOS transistor. The positive terminal of the second power supply V2 is connected to the source of the fourth MOS transistor, the source of the fifth MOS transistor, and the source of the sixth MOS transistor.

[0013] The lower drive chain circuit includes a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, and an eighteenth MOSFET. The drain of the seventh MOSFET is connected to the drain of the tenth MOSFET, and the connection point is connected to the gate of the eighth MOSFET and the gate of the eleventh MOSFET. The drain of the eighth MOSFET is connected to the drain of the eleventh MOSFET, and the connection point is connected to the gate of the ninth MOSFET and the gate of the twelfth MOSFET. The drain of the ninth MOSFET is connected to the drain of the twelfth MOSFET, and the connection point is connected to the gate of the eighteenth MOSFET. The positive terminal of the second control signal source V4 is connected to the gate of the seventh MOSFET and the gate of the tenth MOSFET. The source of the seventh MOSFET, the source of the eighth MOSFET, and the source of the ninth MOSFET are all grounded. The drain of the eighteenth MOSFET is connected to the drain of the seventeenth MOSFET, and the connection point is connected to the gate of the SiC MOSFET through a drive resistor.

[0014] Furthermore, the multi-level driving circuit also includes an auxiliary circuit; the control component also includes a third control signal source V5;

[0015] The auxiliary circuit includes a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, and a third power supply V6. The drain of the thirteenth MOSFET is connected to the drain of the fifteenth MOSFET, and the connection point is connected to the gate of the fourteenth MOSFET and the gate of the sixteenth MOSFET. The drain of the fourteenth MOSFET is connected to the drain of the sixteenth MOSFET, and the connection point is connected to the source of the tenth MOSFET, the eleventh MOSFET, the twelfth MOSFET, and the eighteenth MOSFET. The positive terminal of the third control signal source V5 is connected to the gate of the thirteenth MOSFET and the gate of the fifteenth MOSFET. The sources of the thirteenth MOSFET and the fourteenth MOSFET are grounded, and the sources of the fifteenth MOSFET and the sixteenth MOSFET are connected to the positive terminal of the third power supply V6.

[0016] Furthermore, the first MOSFET, the second MOSFET, the third MOSFET, the seventh MOSFET, the eighth MOSFET, the ninth MOSFET, the thirteenth MOSFET, the fourteenth MOSFET, and the seventeenth MOSFET are all P-channel MOSFETs.

[0017] Furthermore, the fourth, fifth, sixth, tenth, eleventh, twelfth, fifteenth, sixteenth, and eighteenth MOSFETs are all N-channel MOSFETs.

[0018] Furthermore, the voltage provided by the first power supply V1 is greater than or equal to the driving voltage that turns on the SiC MOSFET, and the voltage provided by the third power supply V6 is less than or equal to the magnitude of the maximum negative voltage that the SiC MOSFET can withstand.

[0019] Furthermore, the first power supply V1 provides a voltage of 20V, the second power supply V2 provides a voltage of 15V, and the third power supply V6 provides a voltage of -5V.

[0020] Furthermore, the first control signal source V3 outputs a pulse voltage of 15-20V, the second control signal source V4 outputs a pulse voltage of -5-0V, and the third control signal source V5 outputs a pulse voltage of -5-0V.

[0021] Furthermore, the resistance of the driving resistor is 5 ohms.

[0022] Another technical solution adopted in this invention is:

[0023] A control method, applied to a multilevel drive circuit for suppressing SiC MOSFET crosstalk as described above, includes the following steps:

[0024] When the SiC MOSFET receives the turn-on signal, the first control signal source V3 outputs a high level, and the seventeenth MOSFET is turned on due to receiving a low-level gate signal. The second control signal source V4 outputs a high level, and the eighteenth MOSFET is turned off due to receiving a low-level gate signal. The gate-source voltage of the SiC MOSFET is the voltage provided by the first power supply V1, and the SiC MOSFET is turned on.

[0025] When the SiC MOSFET receives a turn-off signal, the first control signal source V3 outputs a low level, and the seventeenth MOSFET is turned off due to receiving a high-level gate signal. The second control signal source V4 outputs a low level, and the third control signal source V5 outputs a low level. Therefore, the gate of the eighteenth MOSFET receives a high-level signal, and the source of the eighteenth MOSFET receives a low-level signal, so the eighteenth MOSFET is turned on. The gate-source voltage of the SiC MOSFET is the voltage provided by the third power supply V6, and the SiC MOSFET is turned off. When the first control signal source V3 outputs a low level, the second control signal source V4 outputs a low level, and the third control signal source V5 outputs a high level, the seventeenth MOSFET is turned off, the eighteenth MOSFET is turned off, the gate-source voltage of the SiC MOSFET is close to 0V, and the SiC MOSFET is turned off.

[0026] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0027] (1) The multi-level driving circuit proposed in this invention can generate negative voltage driving, which can effectively suppress positive voltage crosstalk.

[0028] (2) The multi-level driving circuit proposed in this invention can generate a gate-source driving voltage close to 0V through the auxiliary circuit, which can effectively suppress reverse voltage crosstalk.

[0029] (3) When the SiC MOSFET is turned on, the gate-source drive voltage rises from 0V to 20V. Compared with the traditional method of rising from negative voltage to 20V, the multi-level drive circuit proposed in this invention improves the switching speed of the SiC MOSFET.

[0030] (4) The auxiliary circuit structure of the multi-level driving circuit proposed in this invention is relatively simple and is easy to integrate into the driving chip. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of the multi-level drive circuit for suppressing SiC MOSFET crosstalk in an embodiment of the present invention;

[0033] Figure 2 These are waveforms of the control signal source and the gate-source voltage of the SiC MOSFET in an embodiment of the present invention.

[0034] Figure 3 This is a waveform diagram of the gate-source voltage of the upper and lower bridge arms of the multi-level driving circuit applied to the half-bridge circuit in an embodiment of the present invention.

[0035] Figure 4 This is a waveform diagram of positive crosstalk generated by the multi-level driving circuit applied to the lower bridge arm in a half-bridge circuit in an embodiment of the present invention.

[0036] Figure 5 This is a waveform diagram of negative crosstalk generated by the multi-level driving circuit applied to the lower bridge arm in a half-bridge circuit in an embodiment of the present invention.

[0037] Figure 6 This is a waveform diagram of the gate-source voltage of the upper and lower bridge arms when a traditional zero-voltage turn-off drive circuit is applied to a half-bridge circuit.

[0038] Figure 7 This is a waveform diagram of the gate-source voltage of the upper and lower bridge arms in a half-bridge circuit, as shown in the embodiment of the present invention, where the negative voltage turn-off drive circuit is applied. Detailed Implementation

[0039] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0040] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0041] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first" or "second" is used, it is only for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features. Furthermore, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0042] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0043] To address the existing technical problems, the present invention aims to provide a multi-level driving circuit and its control method for suppressing crosstalk in SiC MOSFETs. This multi-level driving circuit, without affecting the switching speed of the SiC MOSFET, suppresses bridge arm crosstalk by controlling the driving voltage, keeping both positive and negative crosstalk voltages within a safe threshold. Specifically, the multi-level driving circuit proposed in this invention simultaneously suppresses both positive and negative crosstalk in SiC MOSFETs. When positive crosstalk occurs, the gate-source voltage of the SiC MOSFET is controlled to be negative, thereby suppressing the positive crosstalk voltage. When negative crosstalk occurs, the gate-source voltage of the SiC MOSFET is controlled to be zero, thereby suppressing the negative crosstalk voltage. Through three-stage driving voltage control, both positive and negative crosstalk voltages are kept within a safe threshold.

[0044] like Figure 1 As shown, this embodiment provides a multi-level drive circuit for suppressing SiC MOSFET crosstalk, including: a control component, a drive circuit, and an auxiliary circuit.

[0045] The control component includes a first control signal source V3, a second control signal source V4, and a third control signal source V5, which are used to generate control signals to control the turning on and off of the SiC MOSFET.

[0046] The driving circuit includes an upper driving chain circuit, a lower driving chain circuit, a first power supply V1, and a second power supply V2. The upper driving chain circuit includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, and a seventeenth MOSFET M17. The drain of the first MOSFET M1 is connected to the drain of the fourth MOSFET M4, and the connection point is connected to the gate of the second MOSFET M2 and the gate of the fifth MOSFET M5. The drain of the second MOSFET M2 is connected to the drain of the fifth MOSFET M5. The connection point connects the gate of the third MOSFET M3 and the gate of the sixth MOSFET M6. The drain of the third MOSFET M3 and the drain of the sixth MOSFET M6 are connected. The connection point also connects to the gate of the seventeenth MOSFET M17. The positive terminal of the first control signal source V3 is connected to the gate of the first MOSFET M1 and the gate of the fourth MOSFET M4. The positive terminal of the first power supply V1 is connected to the source of the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the seventeenth MOSFET M17. The positive terminal of the second power supply V2 is connected to the fourth MOSFET M4. The sources of the fifth MOSFET M5 and the sixth MOSFET M6 are connected. The lower drive chain circuit includes the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, and the eighteenth MOSFET M18. The drain of the seventh MOSFET M7 and the drain of the tenth MOSFET M10 are connected, and the connection point is connected to the gate of the eighth MOSFET M8 and the gate of the eleventh MOSFET M11. The drain of the eighth MOSFET M8 and the drain of the eleventh MOSFET M11 are connected, and the connection point is connected to... The gates of the ninth MOSFET M9 and the twelfth MOSFET M12 are connected. The drains of the ninth MOSFET M9 and the twelfth MOSFET M12 are connected. The connection point is connected to the gate of the eighteenth MOSFET M18. The positive terminal of the second control signal source V4 is connected to the gates of the seventh MOSFET M7 and the tenth MOSFET M10. The sources of the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9 are all grounded. The drain of the eighteenth MOSFET M18 is connected to the drain of the seventeenth MOSFET M17. The connection point is connected to the gate of the SiC MOSFET through a drive resistor.

[0047] The auxiliary circuit includes a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, and a third power supply V6. The drain of the thirteenth MOSFET M13 is connected to the drain of the fifteenth MOSFET M15. The connection point is connected to the gate of the fourteenth MOSFET M14 and the gate of the sixteenth MOSFET M16. The drain of the fourteenth MOSFET M14 is connected to the drain of the sixteenth MOSFET M16. The connection point is connected to the source of the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, and the eighteenth MOSFET M18. The positive terminal of the third control signal source V5 is connected to the gate of the thirteenth MOSFET M13 and the fifteenth MOSFET M15. The sources of the thirteenth MOSFET M13 and the fourteenth MOSFET M14 are grounded. The sources of the fifteenth MOSFET M15 and the sixteenth MOSFET M16 are connected to the positive terminal of the third power supply V6.

[0048] In some embodiments, the resistance of the drive resistor is 5 ohms.

[0049] As an optional implementation, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, the thirteenth MOSFET M13, the fourteenth MOSFET M14, and the seventeenth MOSFET M17 are all P-channel MOSFETs, preferably of model FDC638P.

[0050] As an optional implementation, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, the fifteenth MOSFET M15, the sixteenth MOSFET M16, and the eighteenth MOSFET M18 are all N-channel MOSFETs, preferably of model BSB012N03LX3.

[0051] As an optional implementation, the voltage provided by the first power supply is greater than or equal to the driving voltage that turns on the SiC MOSFET, and the voltage provided by the third power supply is less than or equal to the magnitude of the maximum negative voltage that the SiC MOSFET can withstand.

[0052] In some embodiments, the voltage provided by the first power supply is 20V, the voltage provided by the second power supply is 15V, and the voltage provided by the third power supply is -5V.

[0053] In some embodiments, the first control signal source V3 outputs a pulse voltage of 15-20V, the second control signal source V4 outputs a pulse voltage of -5-0V, and the third control signal source V5 outputs a pulse voltage of -5-0V.

[0054] The control signal source waveform of the multi-level drive circuit proposed in this embodiment and the gate-source voltage waveform of the SiC MOSFET are as follows: Figure 2 As shown, t0-t3 is one cycle, and the control methods for each stage are as follows:

[0055] During the t0-t1 phase, the first control signal source V3 outputs a 20V voltage, which is reversed through the upper drive chain. The gate of M17 receives a 15V voltage, and the source of M17 is at the 20V power supply voltage, so M17 is turned on. The second control signal source V4 outputs a 0V voltage, which is reversed through the lower drive chain. The gate of M18 receives a -5V voltage. The third control signal source V5 outputs a 0V voltage, and the source of M18 receives a 0V voltage, so M18 is turned off. The gate-source voltage of the SiC MOSFET is the 20V power supply voltage, so the SiC MOSFET is turned on.

[0056] During the t1-t2 phase, the first control signal source V3 outputs a 15V voltage, which is reversed through the upper drive chain. The gate of M17 receives a 20V voltage, and the source of M17 is at the 20V power supply voltage, so M17 is turned off. The second control signal source V4 outputs a -5V voltage, which is reversed through the lower drive chain. The gate of M18 receives a 0V voltage. The third control signal source V5 outputs a -5V voltage, and the source of M18 receives a -5V voltage, so M18 is turned on. The gate-source voltage of the SiC MOSFET is the -5V power supply voltage, so the SiC MOSFET is turned off.

[0057] During the t2-t3 phase, the first control signal source V3 outputs a 15V voltage, which is reversed through the upper drive chain. The gate of M17 receives a 20V voltage, and the source of M17 is at the 20V power supply voltage, so M17 is turned off. The second control signal source V4 outputs a -5V voltage, which is reversed through the lower drive chain. The gate of M18 receives a 0V voltage, and the third control signal source V5 outputs a 0V voltage. The source of M18 receives a 0V voltage, so M18 is turned off. The gate-source voltage of the SiC MOSFET is close to 0V, so the SiC MOSFEET is turned off.

[0058] By controlling the signal source, this multi-level drive circuit generates three driving voltages of 20V, 0V, and -5V, which have a good suppression effect on positive and negative crosstalk voltages.

[0059] Figure 3 The waveforms of the gate-source voltage of the upper and lower bridge arms when the multi-level driving circuit is applied to a half-bridge circuit are shown below. From top to bottom, they are the gate-source voltage waveforms of the upper and lower bridge arms, respectively. The waveforms show that when the lower bridge arm is off and the upper bridge arm is on, the circuit generates positive crosstalk; when the lower bridge arm is off and the upper bridge arm is off, the circuit generates negative crosstalk. Figure 4The waveform diagram shows the positive crosstalk generated by the multi-level drive circuit when applied to the lower arm of a half-bridge circuit. As can be seen from the figure, the amplitude of the positive crosstalk voltage is -3.78V. Figure 5 The waveform diagram shows the negative crosstalk generated when the multi-level drive circuit is applied to the lower arm of a half-bridge circuit. As can be seen from the figure, the amplitude of the negative crosstalk voltage is -1.49V. Figure 6 The figure shows the gate-source voltage waveforms of the upper and lower arms of a traditional zero-voltage turn-off drive circuit applied to a half-bridge circuit. As can be seen from the figure, the amplitude of the positive crosstalk voltage is 2.06V and the amplitude of the negative crosstalk voltage is -1.16V. Figure 7 The figure shows the gate-source voltage waveforms of the upper and lower arms of a half-bridge circuit when the negative voltage turn-off drive circuit is applied. It can be seen from the figure that the amplitude of the positive crosstalk voltage is -4.10V, and the amplitude of the negative crosstalk voltage is -6.02V. The comparison shows that this multi-level drive circuit can effectively suppress positive crosstalk voltage compared to the zero-voltage turn-off drive circuit, and can effectively suppress negative crosstalk voltage compared to the negative voltage turn-off drive circuit.

[0060] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0061] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0062] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A multi-level drive circuit for suppressing crosstalk in SiC MOSFETs, characterized in that, include: The control component includes a first control signal source V3 and a second control signal source V4, which are used to generate control signals to control the turning on and off of the SiCMOSFET; The driving circuit includes an upper driving chain circuit, a lower driving chain circuit, a first power supply V1, and a second power supply V2. The upper drive chain circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventeenth MOS transistor. The drain of the first MOS transistor is connected to the drain of the fourth MOS transistor, and the connection point is connected to the gate of the second MOS transistor and the gate of the fifth MOS transistor. The drain of the second MOS transistor is connected to the drain of the fifth MOS transistor, and the connection point is connected to the gate of the third MOS transistor and the gate of the sixth MOS transistor. The drain of the third MOS transistor is connected to the drain of the sixth MOS transistor, and the connection point is connected to the gate of the seventeenth MOS transistor. The positive terminal of the first control signal source V3 is connected to the gate of the first MOS transistor and the gate of the fourth MOS transistor. The positive terminal of the first power supply V1 is connected to the source of the first MOS transistor, the source of the second MOS transistor, the source of the third MOS transistor, and the source of the seventeenth MOS transistor. The positive terminal of the second power supply V2 is connected to the source of the fourth MOS transistor, the source of the fifth MOS transistor, and the source of the sixth MOS transistor. The lower drive chain circuit includes a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, and an eighteenth MOSFET. The drain of the seventh MOSFET and the drain of the tenth MOSFET are connected, and the connection point is connected to the gate of the eighth MOSFET and the gate of the eleventh MOSFET. The drain of the eighth MOSFET and the drain of the eleventh MOSFET are connected, and the connection point is connected to the gate of the ninth MOSFET and the gate of the twelfth MOSFET. The drain of the ninth MOSFET and the drain of the twelfth MOSFET are connected, and the connection point is connected to the gate of the eighteenth MOSFET. The positive terminal of the second control signal source V4 is connected to the gate of the seventh MOSFET and the gate of the tenth MOSFET. The source of the seventh MOSFET, the source of the eighth MOSFET, and the source of the ninth MOSFET are all grounded. The drain of the eighteenth MOSFET and the drain of the seventeenth MOSFET are connected, and the connection point is connected to the gate of the SiC MOSFET through a drive resistor. The multi-level driving circuit also includes an auxiliary circuit; the control component also includes a third control signal source V5. The auxiliary circuit includes a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, and a third power supply V6. The drain of the thirteenth MOSFET is connected to the drain of the fifteenth MOSFET, and the connection point is connected to the gate of the fourteenth MOSFET and the gate of the sixteenth MOSFET. The drain of the fourteenth MOSFET is connected to the drain of the sixteenth MOSFET, and the connection point is connected to the source of the tenth MOSFET, the eleventh MOSFET, the twelfth MOSFET, and the eighteenth MOSFET. The positive terminal of the third control signal source V5 is connected to the gate of the thirteenth MOSFET and the gate of the fifteenth MOSFET. The sources of the thirteenth MOSFET and the fourteenth MOSFET are grounded, and the sources of the fifteenth MOSFET and the sixteenth MOSFET are connected to the positive terminal of the third power supply V6.

2. The multi-level drive circuit for suppressing SiC MOSFET crosstalk according to claim 1, characterized in that, The first, second, third, seventh, eighth, ninth, thirteenth, fourteenth, and seventeenth MOSFETs are all P-channel MOSFETs.

3. The multi-level drive circuit for suppressing SiC MOSFET crosstalk according to claim 1, characterized in that, The fourth, fifth, sixth, tenth, eleventh, twelfth, fifteenth, sixteenth, and eighteenth MOSFETs are all N-channel MOSFETs.

4. The multi-level drive circuit for suppressing SiC MOSFET crosstalk according to claim 1, characterized in that, The voltage provided by the first power supply V1 is greater than or equal to the driving voltage that turns on the SiC MOSFET, and the voltage provided by the third power supply V6 is less than or equal to the magnitude of the maximum negative voltage that the SiC MOSFET can withstand.

5. A multi-level drive circuit for suppressing SiC MOSFET crosstalk according to claim 1, characterized in that, The first power supply V1 provides a voltage of 20V, the second power supply V2 provides a voltage of 15V, and the third power supply V6 provides a voltage of -5V.

6. The multi-level drive circuit for suppressing SiC MOSFET crosstalk according to claim 1, characterized in that, The first control signal source V3 outputs a pulse voltage of 15-20V, the second control signal source V4 outputs a pulse voltage of -5-0V, and the third control signal source V5 outputs a pulse voltage of -5-0V.

7. The multi-level drive circuit for suppressing SiC MOSFET crosstalk according to claim 1, characterized in that, The resistance of the driving resistor is 5 ohms.

8. A control method applied to a multi-level drive circuit for suppressing SiC MOSFET crosstalk as described in any one of claims 1-7, characterized in that, Includes the following steps: When the SiC MOSFET receives the turn-on signal, the first control signal source V3 outputs a high level, and the seventeenth MOSFET is turned on due to receiving a low-level gate signal. The second control signal source V4 outputs a high level, and the eighteenth MOSFET is turned off due to receiving a low-level gate signal. The gate-source voltage of the SiC MOSFET is the voltage provided by the first power supply V1, and the SiC MOSFET is turned on. When the SiC MOSFET receives a turn-off signal, the first control signal source V3 outputs a low level, and the seventeenth MOSFET is turned off due to receiving a high-level gate signal. The second control signal source V4 outputs a low level, and the third control signal source V5 outputs a low level. Therefore, the gate of the eighteenth MOSFET receives a high-level signal, and the source of the eighteenth MOSFET receives a low-level signal, so the eighteenth MOSFET is turned on. The gate-source voltage of the SiC MOSFET is the voltage provided by the third power supply V6, and the SiC MOSFET is turned off. When the first control signal source V3 outputs a low level, the second control signal source V4 outputs a low level, and the third control signal source V5 outputs a high level, the seventeenth MOSFET is turned off, the eighteenth MOSFET is turned off, the gate-source voltage of the SiC MOSFET is close to 0V, and the SiC MOSFET is turned off.

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