Array substrate and display panel

Abstract

The present application belongs to the field of display panels and provides an array substrate and a display panel, wherein the array substrate includes a base substrate, a first signal line, a gate drive unit, and a first pattern layer, wherein the first signal line includes a first linear body and a first connecting portion connected to each other, the first connecting portion being located on one side of the first linear body; the first pattern layer includes a bridge line and a main pattern layer, one end of the bridge line is connected to the first connecting portion via a first via, and the other end is connected to the gate drive unit, and the main pattern layer is connected to one end of the first signal line via a second via. During the process of releasing static electricity, the charge accumulated in the first signal line mainly moves along the first linear body, and the first via is located to the side of the first linear body. The path direction from the first linear body to the first via is inconsistent with the extension direction of the first linear body, so that the amount of charge passing through the first via is reduced, thereby reducing the risk of the first via being burned or even destroyed by static electricity.

Description

Technical Field

[0001] The present application relates to the field of display panels, and in particular to an array substrate and a display panel. Background Art

[0002] An array substrate is an important structure in various display devices, such as a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and an Organic Light-Emitting Diode (OLED) display device.

[0003] The array substrate includes a base substrate and circuits formed on its surface. The circuit structure on the surface of the array substrate is relatively delicate, and some parts are prone to charge accumulation, which eventually causes electrostatic discharge, resulting in partial damage to the circuit structure, thereby affecting the normal function of the array substrate. For example, signal lines are usually distributed on the edge of the base substrate, and the gate drive unit of the array substrate is connected to these signal lines through bridge wires. The bridge wires and signal lines are connected by vias. If a large amount of charge accumulates on the signal line, a large amount of charge will move along the signal line during the process of discharging static electricity. The vias connecting the signal line and the bridge wire may be burned or even burned by static electricity, causing damage to the array substrate. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a display panel, which can reduce the possibility of burning of vias connecting bridge lines and signal lines due to electrostatic discharge.

[0005] A first aspect of an embodiment of the present application provides an array substrate, comprising:

[0006] A base substrate having a display area and a non-display area;

[0007] a first signal line located in the non-display area, comprising a first linear body and a first connecting portion connected to each other, wherein the first connecting portion is located on one side of the first linear body;

[0008] a gate driving unit, located between the first signal line and the display area;

[0009] The first pattern layer is arranged in a different layer from the first signal line, and includes a bridge line and a main pattern layer. One end of the bridge line is connected to the first connecting part through a first via hole, and the other end is connected to the gate driving unit. The main pattern layer is connected to one end of the first signal line through a second via hole.

[0010] In some examples, the first connecting portion is located on a side of the first linear body close to the display area.

[0011] In some examples, the array substrate includes a plurality of first signal lines, the plurality of first signal lines are arranged in parallel, the first pattern layer includes a plurality of bridge lines, the plurality of bridge lines are arranged at intervals along an extension direction of the first signal lines, and the bridge lines are connected to the first signal lines in a one-to-one correspondence;

[0012] The width of the first linear body at an intersection with the bridge line is smaller than the width of the non-intersection.

[0013] In some examples, a side of the first linear body has a recessed area, and the recessed area is located at the intersection of the first linear body and the bridge line;

[0014] Among adjacent first signal lines, the first connection portion of one first signal line is located in the recessed region of the first linear body of another first signal line.

[0015] In some examples, the bridging wire includes a second linear body and a second connecting portion connected to each other, the second connecting portion being located at an end of the second linear body and connected to the first connecting portion through the first via, and the orthographic projection of the second connecting portion on the base substrate being located within the orthographic projection of the first connecting portion on the base substrate.

[0016] In some examples, in the plurality of bridging lines, the length and width of the second linear body are positively correlated.

[0017] In some examples, a diameter of the first via hole is larger than a width of the first linear body.

[0018] In some examples, the first signal line further includes a branch connected to one side of the first linear body, and the branch partially overlaps with the bridge line.

[0019] In some examples, the main pattern layer includes a source and drain pattern layer, the array substrate also includes an electrostatic protection circuit, the electrostatic protection circuit includes a diode ring, the diode ring is located in the non-display area of ​​the base substrate, the diode ring includes a gate pattern layer and the source and drain pattern layer, the gate pattern layer is arranged on the same layer as the first signal line, the source and drain pattern layer is arranged on the same layer as the bridge line, and the source and drain pattern layer is connected to the gate pattern layer through a third via.

[0020] A second aspect of the embodiments of the present application further provides a display panel, comprising a cell substrate and the array substrate as described in the first aspect, wherein the cell substrate is arranged opposite to the array substrate.

[0021] In a first aspect of an embodiment of the present application, a bridge wire is provided to connect a first signal line and a gate drive unit. The first signal line includes a first linear body and a first connecting portion connected thereto. The bridge wire is connected to the first connecting portion of the first signal line via a first via. The provision of the first connecting portion moves the first via connecting the bridge wire and the first signal line outside the main body of the first signal line. During the discharge of static electricity, the charge accumulated in the first signal line mainly moves along the first linear body, and the first via is located to the side of the first linear body. The path direction from the first linear body to the first via is inconsistent with the extension direction of the first linear body, so that the amount of charge passing through the first via is reduced, thereby reducing the risk of the first via being burned or even destroyed by static electricity, which is beneficial to improving the yield of the array substrate.

[0022] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 is a schematic top view of an array substrate provided in Example 1 of the present application;

[0025] Figure 2 This is a schematic diagram of a partial structure of an array substrate provided in an embodiment of the present application;

[0026] Figure 3 This is a schematic diagram of a partial structure of an array substrate provided in Example 2 of the present application;

[0027] Figure 4 This is a schematic diagram of a partial structure of an array substrate provided in an embodiment of the present application;

[0028] Figure 5 is an equivalent circuit diagram of the electrostatic protection circuit provided in an embodiment of the present application;

[0029] Figure 6 yes Figure 3 AA cross-section in;

[0030] Figure 7 yes Figure 3 BB cross-section diagram in;

[0031] Figure 8This is an equivalent circuit diagram of an electrostatic protection circuit for an array substrate provided in Example 3 of the present application;

[0032] Figure 9 This is a structural diagram of an array substrate provided in Example 3 of the present application;

[0033] Figure 10 This is a schematic diagram of the partial structure of an array substrate provided in Example 4 of the present application.

[0034] Figure Number:

[0035] Substrate: 10; display area: 10a; non-display area: 10b; first signal line: 11; first connection portion: 111; recessed area: 111a; first linear body: 112; third connection portion: 113; branch: 114; electrostatic protection circuit: 20; second signal line: 21; diode ring: 22; gate pattern layer: 221; source and drain pattern layer: 222; active pattern layer: 223; first gate: 2211; second gate: 2212; third gate: 2213; fourth gate: 2214; fourth connection portion: 2215; first active layer: 22 31; second active layer: 2232; third active layer: 2233; fourth active layer: 2234; first source-drain layer: 2221; second source-drain layer: 2222; third source-drain layer: 2223; first electrode: 222a; second electrode: 222b; first insulating layer: 31; second insulating layer: 32; third insulating layer: 33; fourth insulating layer: 34; first via: 31a; third via: 31b; fourth via: 31c; gate driving unit: 40; bridge line: 41; first via: 41a; second linear body: 411; second connecting portion: 412. DETAILED DESCRIPTION

[0036] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0037] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0038] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0039] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0040] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0041] References to "one embodiment" or "some embodiments" in the present specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "Multiple" means two or more.

[0042] Example 1

[0043] Figure 1 : is a top view schematic diagram of an array substrate provided in Example 1 of the present application. Figure 1 As shown, the array substrate includes a base substrate 10 and circuitry formed on one side of the base substrate 10. The base substrate 10 serves as a carrier and has a display area 10a and a non-display area 10b. The display area 10a is generally located in the center of the base substrate 10, while the non-display area 10b is generally located at the edge of the base substrate 10. A first signal line 11 and an electrostatic protection circuit 20 are provided in the non-display area 10b of the base substrate 10. One end of the first signal line 11 is connected to the electrostatic protection circuit 20.

[0044] The array substrate further includes a bridge line 41 and a plurality of gate drive units 40. The plurality of gate drive units 40 are located between the first signal line 11 and the display area 10a and are arranged in sequence along the length of the first signal line 11. The first signal line 11 and the gate drive units 40 are connected via the bridge line 41.

[0045] The circuits on the surface of the substrate 10 generally include pixel circuits located in the display area 10a and driver circuits located in the non-display area 10b. The driver circuit in the non-display area 10b may, for example, include a gate driver on array (GOA) circuit, which may include a gate driver unit (Circuit) and a bus unit (busline). The gate driver unit is connected to the pixel circuit located in the display area 10a, and the bus unit may include a clock signal line (Clock, CK). As an example, in an embodiment of the present application, the first signal line 11 may be a clock signal line.

[0046] Figure 2 : is a partial structural diagram of an array substrate provided in an embodiment of the present application. Figure 2 As shown, the bridge line 41 is connected to the first signal line 11 through a first via 41a. A main pattern layer 200 is connected to one end of the first signal line 11 through a second via 31a. The main pattern layer 200 is on the same layer as the bridge line 41. In the embodiment of the present application, the main pattern layer 200 can be a structure in the electrostatic protection circuit 20.

[0047] In the embodiments of the present application, unless otherwise specified, connection through a via refers to achieving electrical connection, and the electrical connection is achieved by a structure located within the via. The structure used to achieve electrical connection within the via can be a part of either of the two structures at the ends of the via, or can be a structure other than the two structures at the ends of the via. For example, the bridge wire 41 and the first signal line 11 are connected through the first via 41a, which means that the two structures of the bridge wire 41 and the first signal line 11 form an electrical connection, and the structure within the first via 41a used to achieve electrical connection between the bridge wire 41 and the first signal line 11 is the portion of the bridge wire 41 located within the first via 41a.

[0048] The length of the first signal line 11 is generally relatively long. The longer the length, the easier it is to accumulate charge. In the process of preparing a structure connected to the first signal line 11 through a via, for example, in the process of preparing the main pattern layer 200 and the bridge line 41, the electrostatic charge accumulated in the first signal line 11 will be released through the first via 41a and the second via 31a. The relative positional relationship between the first via 41a, the second via 31a and the first signal line 11 will affect the ratio of the amount of charge released through the first via 41a and the amount of charge released through the second via 31a. The discharge path is along the first signal line 11. During the discharge process, a large amount of charge moves along the first signal line 11. The first via 41a is directly connected to the first signal line 11. Due to the large amount of charge released, it is relatively easy for the first via 41a to be burned or destroyed, resulting in abnormal function of the array substrate, which directly affects the yield of the array substrate. In particular, uneven etching at the first via 41a makes the shape of the first via 41a irregular, or has burrs or foreign matter residues, which further increases the risk of the first via 41a being burned or burned. In addition, during the use of the array substrate, even if the gate drive unit 40 is in the off state, since the first via 41a is closely connected to the first signal line 11, when static electricity is released in the first signal line 11, the charge moves along the first signal line 11, and the first via 41a is also easily damaged by static electricity. The portion where the first signal line 11 is connected to the first via 41a may also be damaged by static electricity, causing damage to the first signal line 11 and affecting the normal function of the array substrate.

[0049] Example 2

[0050] Figure 3 This is a partial structural diagram of an array substrate provided in Example 2 of this application. Figure 3 As shown, in the array substrate, the first signal line 11 includes a first linear body 112 and a first connecting portion 111 connected to each other. The first connecting portion 111 is located on one side of the first linear body 112 .

[0051] The first pattern layer 2000 is arranged on a different layer from the first signal line 11. The first pattern layer 2000 includes a bridge line 41 and a main pattern layer 200. One end of the bridge line 41 is connected to the first connecting portion 111 through a first via 41a, and the other end of the bridge line 41 is connected to the gate driving unit 40. The main pattern layer 200 is connected to one end of the first linear body 112 through a second via 31a.

[0052] As an example, in the embodiment of the present application, the main pattern layer 200 may be a structure in the electrostatic protection circuit 20. In other possible implementations, the main pattern layer 200 may also be another structure connected to one end of the first linear body 112 through a via. In this example, only the electrostatic protection circuit 20 is used as an example for description.

[0053] The first signal line 11 and the gate driving unit 40 are connected by setting a bridge line 41. The first signal line 11 includes a first linear body 112 and a first connecting portion 111 connected to each other. The bridge line 41 is connected to the first connecting portion 111 of the first signal line 11 through a first via 41a. The setting of the first connecting portion 111 moves the first via 41a connecting the bridge line 41 and the first signal line 11 outside the main body of the first signal line 11 (i.e., the first linear body 112). In the process of releasing static electricity, the charge accumulated in the first signal line 11 is mainly It moves along the first linear body 112, and the first via 41a is located on the side of the first linear body 112. The path direction from the first linear body 112 to the first via 41a is inconsistent with the extension direction of the first linear body 112. This changes the ratio of the amount of charge accumulated in the first signal line 11 released through the first via 41a and the amount of charge released through the second via 31a, so that the amount of charge passing through the first via 41a is reduced, thereby reducing the risk of the first via 41a being burned or even destroyed by static electricity, which is beneficial to improving the yield of the array substrate.

[0054] Furthermore, during use of the array substrate, when the gate drive unit 40 is in the off state, static electricity in the first signal line 11 is discharged along the first linear body 112 through the second via 31a. Since the first via 41a is located on one side of the first linear body 112 and is not directly connected to the first linear body 112, the first via 41a is outside the static electricity discharge path and is therefore not damaged by static electricity. This also prevents damage to the first linear body 112, allowing electrical signals to be transmitted normally within the first linear body 112 and preventing malfunctions in the array substrate.

[0055] The orthographic projection of the first via 41a on the base substrate 10 is located outside the orthographic projection of the first linear body 112 on the base substrate 10. The greater the distance between the first via 41a and the first linear body 112, that is, the greater the distance between the first via 41a and the first linear body 112, the less charge is released through the first via 41a. However, the structures in the array substrate are complex and space is limited. If the first via 41a is too far away from the first linear body 112, it will affect the layout of other structures. By completely offsetting the first via 41a from the first linear body 112, it not only avoids a significant impact on the layout of other structures, but also significantly reduces the amount of electrostatic charge released through the first via 41a.

[0056] In some possible implementations, the length of the first connecting portion 111 can be greater than the width of the first linear body 112 in a direction perpendicular to the first linear body 112. This helps further increase the distance between the first via 41a and the first linear body 112, reducing the risk of electrostatic damage to the first via 41a.

[0057] In some possible implementations, the diameter of the first via hole 41 a may be greater than the width of the first line-shaped body 112 .

[0058] exist Figure 2 In the example shown, the diameter of the first via 41a is limited by the width of the first signal line 11. However, in the embodiment of the present application, since the first via 41a is connected to the first connecting portion 111, the diameter of the first via 41a can exceed the width limit of the first linear body 112 if the size of the first connecting portion 111 allows. Increasing the diameter of the first via 41a helps improve the anti-static ability of the first via 41a, further reducing the risk of static burns or even burning of the first via 41a.

[0059] Figure 4 : is a partial structural diagram of an array substrate provided in an embodiment of the present application. Figure 4 As shown, the array substrate includes a plurality of first signal lines 11 and a plurality of bridge lines 41. The plurality of first signal lines 11 are arranged in parallel. The plurality of bridge lines 41 are arranged at intervals along the extension direction of the first signal lines 11. The bridge lines 41 are connected to the first signal lines 11 in a one-to-one correspondence. The bridge lines 41 are also connected to the gate drive units 40 in a one-to-one correspondence.

[0060] As an example, the plurality of bridge lines 41 may be parallel to each other; the bridge line 41 and the first signal line 11 may be perpendicular to each other.

[0061] like Figure 4 As shown, for the first connecting portion 111 and the first linear body 112 connected thereto, the first connecting portion 111 is located on a side of the first linear body 112 close to the display area 10 a .

[0062] Since the gate driving unit 40 is located on the side of the first signal line 11 close to the display area 10 a, arranging the first connecting portion 111 on the side of the first linear body 112 close to the display area 10 a can reduce the length of the bridge line 41 and reduce the number of first signal lines 11 crossing the bridge line 41.

[0063] The intersection here means that the orthographic projections of the two on the base substrate 10 intersect each other. For example, the first signal line 11 intersecting the bridge line 41 means that the orthographic projection of the first signal line 11 on the base substrate 10 intersects the orthographic projection of the bridge line 41 on the base substrate 10 .

[0064] Among the multiple first signal lines 11, for the first signal line 11 closest to the display area 10a, the first connection portion 111 of the first signal line 11 can be located on the side of the first linear body 112 away from the display area 10a. This allows the first connection portion 111 to be fully utilized in the gaps between adjacent first signal lines 11, eliminating the need to occupy the space between the first signal line 11 closest to the display area 10a and the gate driver unit 40, leaving more space for the arrangement of other structures.

[0065] like Figure 4 As shown, the width of the first linear body 112 at the intersection with the bridge line 41 is smaller than the width of the non-intersection.

[0066] The intersection here refers to a portion of the first linear body 112 whose orthographic projection on the base substrate 10 is located within the orthographic projection of the bridge line 41 on the base substrate 10. The non-intersection here refers to a portion of the first linear body 112 whose orthographic projection on the base substrate 10 is located outside the orthographic projection of the bridge line 41 on the base substrate 10.

[0067] Capacitance is formed at the intersection of the first linear body 112 and the bridge line 41, which may affect the operation of the array substrate. By reducing the width of the first linear body 112, the width of the first linear body 112 at the intersection with the bridge line 41 is reduced, thereby reducing the area of ​​the intersection between the first linear body 112 and the bridge line 41. This reduces the capacitance formed and minimizes the impact on the operation of the array substrate.

[0068] Similarly, the width of the intersection of the bridge line 41 and the first linear body 112 can also be smaller than the width of the non-intersection. The intersection here refers to the portion of the bridge line 41 whose orthographic projection on the base substrate 10 is located within the orthographic projection of the first linear body 112 on the base substrate 10. The non-intersection here refers to the portion of the bridge line 41 whose orthographic projection on the base substrate 10 is located outside the orthographic projection of the first linear body 112 on the base substrate 10.

[0069] During the process of preparing the array substrate, the shape of the first linear body 112 may be designed through a patterning process so that the first linear body 112 has different widths at intersections and non-intersections.

[0070] like Figure 4 As shown, a side of the first linear body 112 has a recessed area 111 a , and the recessed area 111 a is located at the intersection of the first linear body 112 and the bridge line 41 .

[0071] During the patterning process, the recessed area 111 a is formed so that different areas of the first linear body 112 have different widths.

[0072] The recessed regions 111a may be located on both sides of the first linear body 112. Each first linear body 112 may have a plurality of recessed regions 111a, which are spaced apart along the length of the first linear body 112.

[0073] Among the adjacent first signal lines 11 , the first connection portion 111 of one first signal line 11 is located in the recessed area 111 a of the first linear body 112 of the other first signal line 11 .

[0074] The first connection portion 111 is accommodated by the recessed area 111 a of the first linear body 112 of the adjacent first signal line 11 , which helps save wiring space and enables the spacing between adjacent first signal lines 11 to be set smaller.

[0075] like Figure 4 As shown, the bridge line 41 includes a second linear body 411 and a second connecting portion 412. The second connecting portion 412 is located at the end of the second linear body 411 and is connected to the first connecting portion 111 through a first via 41a. The orthographic projection of the second connecting portion 412 on the base substrate 10 is located within the orthographic projection of the first connecting portion 111 on the base substrate 10.

[0076] The second connection portion 412 may form capacitance with other surrounding conductive structures, such as the adjacent first signal line 11. These capacitances may have a certain impact on the performance of the array substrate. The orthographic projection of the second connection portion 412 on the base substrate 10 is located within the orthographic projection of the first connection portion 111 on the base substrate 10. This reduces the area of ​​the second connection portion 412, thereby reducing the capacitance formed between the second connection portion 412 and other structures, thereby reducing the impact on the performance of the array substrate.

[0077] In some possible implementations, among the plurality of bridging lines 41 , the length of the second linear body 411 may be positively correlated with its width.

[0078] Since the distances from different first signal lines 11 to the gate drive unit 40 are different, the lengths of the multiple bridge wires 41 are also different, that is, the lengths of the second linear bodies 411 are different. The resistance of the second linear body 411 is proportional to its length. The longer the length, the greater the resistance. The resistance of the second linear body 411 is inversely proportional to its width. The greater the width, the smaller the resistance. The resistance of the second linear body 411 affects the attenuation of the electrical signal transmitted in the second linear body 411. Different resistances have different effects on the attenuation of the electrical signal. By setting the width of the second linear body 411 with a longer length to be larger and the width of the second linear body 411 with a shorter length to be smaller, the resistance of the multiple bridge wires 41 is made closer, so that the difference in the attenuation effect of different bridge wires 41 on the electrical signal is smaller.

[0079] Figure 5 : is an equivalent circuit diagram of the electrostatic protection circuit provided in the embodiment of the present application. Figure 5 As shown, the electrostatic protection circuit 20 may include a second signal line 21 and a plurality of diode rings (DR) 22. The diode rings 22 are located in the non-display area 10b.

[0080] Reference Figure 3 As shown, the diode ring 22 includes a gate pattern layer 221, a source / drain pattern layer 222, and an active pattern layer 223. The active pattern layer 223 and the source / drain pattern layer 222 are both located on the side of the gate pattern layer 221 away from the base substrate 10. The main pattern layer 200 may include the source / drain pattern layer 222. The source / drain pattern layer 222 is arranged on the same layer as the bridge line 41.

[0081] In the embodiment of the present application, the gate pattern layer 221 , the active pattern layer 223 and the source and drain pattern layer 222 form two thin film transistors.

[0082] The gate pattern layer 221 includes a first gate 2211 and a second gate 2212 .

[0083] The active pattern layer 223 includes a first active layer 2231 and a second active layer 2232. The first active layer 2231 is located on a side of the first gate electrode 2211 away from the base substrate 10, and the first active layer 2231 at least partially overlaps with the first gate electrode 2211. The second active layer 2232 is located on a side of the second gate electrode 2212 away from the base substrate 10, and the second active layer 2232 at least partially overlaps with the second gate electrode 2212.

[0084] In the embodiment of the present application, the overlapping of two structures means that the orthographic projections of the two structures on the surface of the base substrate 10 overlap, that is, the orthographic projection of one structure on the surface of the base substrate 10 is at least partially located within the orthographic projection of the other structure on the surface of the base substrate 10. For example, the partial overlap of the second active layer 2232 and the second gate 2212 here means that the orthographic projection of the second active layer 2232 on the surface of the base substrate 10 overlaps with the orthographic projection of the second gate 2212 on the surface of the base substrate 10, that is, the orthographic projection of the second active layer 2232 on the surface of the base substrate 10 is at least partially located within the orthographic projection of the second gate 2212 on the surface of the base substrate 10.

[0085] The source-drain pattern layer 222 includes a first source-drain layer 2221 and a second source-drain layer 2222, wherein the first source-drain layer 2221 includes a first electrode 222a and a second electrode 222b, and the second source-drain layer 2222 also includes a first electrode 222a and a second electrode 222b, the first electrode 222a is one of the source and the drain, and the second electrode 222b is the other of the source and the drain.

[0086] The first gate 2211 is connected to the first signal line 11 , and there are gaps between the second gate 2212 and the first gate 2211 , and between the second gate 2212 and the first signal line 11 .

[0087] The first source-drain electrode layer 2221 partially overlaps with the first gate electrode 2211 and the second gate electrode 2212. The first electrode 222a of the first source-drain electrode layer 2221 partially overlaps with the first gate electrode 2211 and partially overlaps with the first active layer 2231. The second electrode 222b of the first source-drain electrode layer 2221 partially overlaps with the second gate electrode 2212 and partially overlaps with the second active layer 2232.

[0088] The second source-drain electrode layer 2222 partially overlaps with the first gate electrode 2211 and the second gate electrode 2212. The first electrode 222a of the second source-drain electrode layer 2222 partially overlaps with the second gate electrode 2212 and partially overlaps with the second active layer 2232. The second electrode 222b of the second source-drain electrode layer 2222 partially overlaps with the first gate electrode 2211 and partially overlaps with the first active layer 2231.

[0089] Figure 6 yes Figure 3 AA cross-section diagram in. Figure 7 yes Figure 3 The BB cross-section diagram in Figure 6 and Figure 7As shown, the array substrate further includes a first insulating layer 31, which is located on a side of the first signal line 11 away from the base substrate 10. The first via 41a and the second via 31a can be located in the first insulating layer 31. The first signal line 11 is connected to the first source and drain layer 2221 through the second via 31a.

[0090] The first insulating layer 31 further has a third via hole 31 b , and the second source-drain electrode layer 2222 is connected to the second gate 2212 through the third via hole 31 b .

[0091] In the embodiment of the present application, the gate pattern layer 221 is arranged on the same layer as the first signal line 11 .

[0092] Since they are arranged in the same layer, the gate pattern layer 221 and the first signal line 11 can be formed by the same patterning process, thereby saving the process.

[0093] like Figure 3 As shown, the first signal line 11 further includes a third connection portion 113. The third connection portion 113 is connected to one end of the first linear body 112. The width of the third connection portion 113 is greater than the width of the first linear body 112. The third connection portion 113 partially overlaps with the first source and drain electrode layer 2221 and is connected through the second via 31a.

[0094] In the embodiment of the present application, the width of the first linear body 112 refers to the distance between two opposite sides of the first linear body 112 in a direction parallel to the base substrate 10 and perpendicular to the first linear body 112. The width of the third connecting portion 113 refers to the distance between two opposite sides of the third connecting portion 113 in a direction parallel to the base substrate 10 and perpendicular to the first linear body 112.

[0095] The first linear body 112 is thinner, which is beneficial to reducing the space occupied by the first signal line 11 and facilitating wiring. The third connecting portion 113 is wider, which can facilitate the arrangement of a larger second via hole 31a.

[0096] As an example, the first gate 2211 may be connected to the third connection portion 113 to form an integrated structure.

[0097] like Figure 3 As shown, the gate pattern layer 221 further includes a fourth connection portion 2215. The fourth connection portion 2215 is connected to the second gate 2212, partially overlaps with the second source and drain electrode layer 2222, and is connected through the third via hole 31b.

[0098] The fourth connection portion 2215 provides a portion with a relatively large area to facilitate the connection between the gate pattern layer 221 and the second source and drain electrode layer 2222 through the third via hole 31 b.

[0099] like Figure 3 As shown, the second signal line 21 is arranged in the same layer as the source and drain pattern layer 222 and is connected to each other.

[0100] In the embodiment of the present application, the second signal line 21 is connected to the second source-drain electrode layer 2222 , and for example, can be an integral structure with the second source-drain electrode layer 2222 .

[0101] The second signal line 21 is used to release static electricity. For example, the second signal line 21 can be a common signal line, that is, the common signal line is reused to release static electricity. In other possible implementations, the second signal line 21 can also be a signal line other than the common signal line.

[0102] Exemplarily, the first signal line 11 can be a single-layer structure made of metal material, such as a single-layer structure formed by metal copper Cu, or it can be a multi-layer structure made of metal material, such as Al / Mo / MTD material, that is, a multi-layer structure of aluminum layer, molybdenum layer, and molybdenum nickel titanium alloy layer.

[0103] The first insulating layer 31 may be located in the display area 10a and the non-display area 10b. For example, the first insulating layer 31 may be a gate insulating layer. The first insulating layer 31 may be made of an inorganic non-metallic material. For example, the first insulating layer 31 may include at least one of a silicon nitride layer and a silicon oxide layer. For example, the first insulating layer 31 may include SiN x layers and stacks in SiN x The SiO layer on the side away from the base substrate 10 x layer.

[0104] For example, the thin film transistors in the electrostatic protection circuit 20 may be oxide thin film transistors, and the first active layer 2231 and the second active layer 2232 may be metal oxide semiconductor layers. In some examples, the thin film transistors may also be polycrystalline silicon thin film transistors, amorphous silicon thin film transistors, or other thin film transistors.

[0105] like Figure 6 As shown, the array substrate further includes a second insulating layer 32, a third insulating layer 33, and a fourth insulating layer 34. The second insulating layer 32 covers the side of the source and drain pattern layer 222 away from the base substrate 10, the third insulating layer 33 is located on the side of the second insulating layer 32 away from the base substrate 10, and the fourth insulating layer 34 is located on the side of the third insulating layer 33 away from the base substrate 10.

[0106] The second insulating layer 32 may be located in the display area 10a and the non-display area 10b of the base substrate 10. For example, the second insulating layer 32 may be a passivation layer (PVX), and the second insulating layer 32 may be made of an inorganic non-metallic material. For example, the second insulating layer 32 may include at least one of a silicon nitride layer and a silicon oxide layer. For example, the second insulating layer 32 may include SiO x Layers and stacks in SiO x The SiN layer on the side away from the substrate 10 x layer.

[0107] The third insulating layer 33 can be made of an inorganic non-metallic material, for example, a resin layer, a photoresist layer, or an acrylic layer. For example, the third insulating layer 33 can be made of perfluoroalkoxy resin PFA.

[0108] Optionally, the thickness of the third insulating layer 33 is 1.5 μm to 3 μm. The thickness of the third insulating layer 33 is set relatively thick to form a relatively flat surface, so that the film layer formed subsequently is relatively flat.

[0109] Example 3

[0110] Figure 8 This is an equivalent circuit diagram of an electrostatic protection circuit of an array substrate provided in Example 3 of the present application. Figure 8 As shown, in the electrostatic protection circuit, the diode ring 22 includes four thin film transistors. Figure 9 This is a schematic diagram of the structure of an array substrate provided in Example 3 of this application. Figure 3 The example shown, Figure 9 In the array substrate shown, the gate pattern layer 221 , the active pattern layer 223 and the source and drain pattern layer 222 form four thin film transistors.

[0111] like Figure 9 As shown, in the array substrate, the gate pattern layer 221 further includes a third gate 2213 and a fourth gate 2214. The third gate 2213 is connected to the second gate 2212, and there is a gap between the fourth gate 2214 and the third gate 2213, and between the fourth gate 2214 and the second gate 2212.

[0112] The active pattern layer 223 further includes a third active layer 2233 and a fourth active layer 2234. The third active layer 2233 is located on a side of the third gate 2213 away from the base substrate 10, and the third active layer 2233 at least partially overlaps with the third gate 2213. The fourth active layer 2234 is located on a side of the fourth gate 2214 away from the base substrate 10, and the fourth active layer 2234 at least partially overlaps with the fourth gate 2214.

[0113] The second source-drain electrode layer 2222 partially overlaps with the first gate 2211, the second gate 2212, the third gate 2213, and the fourth gate 2214, respectively. The second source-drain electrode layer 2222 includes two first electrodes 222a and two second electrodes 222b. One first electrode 222a partially overlaps with the second gate 2212 and the second active layer 2232; the other first electrode 222a partially overlaps with the third gate 2213 and the third active layer 2233; one second electrode 222b partially overlaps with the first gate 2211 and the first active layer 2231; and the other second electrode 222b partially overlaps with the fourth gate 2214 and the fourth active layer 2234.

[0114] The source-drain pattern layer 222 further includes a third source-drain layer 2223. The third source-drain layer 2223 includes a first electrode 222a and a second electrode 222b.

[0115] The third source and drain layer 2223 partially overlaps with the third gate 2213 and the fourth gate 2214 respectively, wherein the first pole 222a of the third source and drain layer 2223 partially overlaps with the fourth gate 2214 and partially overlaps with the fourth active layer 2234; the second pole 222b of the third source and drain layer 2223 partially overlaps with the third gate 2213 and partially overlaps with the third active layer 2233.

[0116] In the embodiment of the present application, the third source-drain layer 2223 is connected to the fourth gate 2214 through the fourth via 31c. In the embodiment of the present application, the electrostatic protection circuit 20 includes more thin film transistors and a more complex circuit structure, which provides better electrostatic protection for the array substrate during operation.

[0117] The specific structure of the electrostatic protection circuit 20 can have various forms. As an example, the embodiment of the present application provides an electrostatic protection circuit 20 with 4 thin film transistors. In other examples, the number of thin film transistors in the electrostatic protection circuit 20 can also be 3, 5, 6, etc.

[0118] Example 4

[0119] Figure 10 This is a partial structural diagram of an array substrate provided in the fourth embodiment of the present application. Figure 10 As shown, in this example, the first signal line 11 further includes a branch 114 . The branch 114 is connected to one side of the first linear body 112 , and the branch 114 partially overlaps with the bridge line 41 .

[0120] The overlap here refers to the overlap of the orthographic projections of the two on the base substrate 10. The branch 114 partially overlaps with the bridge line 41, that is, the orthographic projections of the branch 114 on the base substrate 10 partially overlap with the orthographic projections of the bridge line 41 on the base substrate 10.

[0121] Exemplarily, the branch 114 may partially overlap with the second linear body 411 .

[0122] If the first via 41a is damaged during the preparation or use of the array substrate, welding can be performed on the overlapping portion of the branch 114 and the bridge line 41 to connect the branch 114 and the bridge line 41, thereby restoring the normal function of the array substrate.

[0123] For example, laser welding may be used for welding.

[0124] In addition, cutting may be performed at the connection between the first connection portion 111 and the first linear body 112 , and cutting may be performed at the connection between the second connection portion 412 and the second linear body 411 , so as to completely disconnect the damaged first via 41 a from the circuit structure.

[0125] For example, laser cutting may be used for cutting.

[0126] Example 5

[0127] Embodiment 5 of the present application provides a display panel, which can be, but is not limited to, a display panel in a mobile phone, tablet computer, laptop computer, monitor, smart wearable device, or in-vehicle display device. The display panel includes a cell substrate and an array substrate, which can be any of the array substrates described in the previous embodiments.

[0128] Example 6

[0129] Embodiment 6 of the present application provides a display device, which includes the display panel of the aforementioned embodiment. The display device can be, but is not limited to, a mobile phone, a tablet computer, a laptop computer, a monitor, a smart wearable device, or a vehicle-mounted display device.

[0130] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: A base substrate (10) having a display area (10a) and a non-display area (10b); A first signal line (11), located in the non-display area (10b), comprises a first linear body (112) and a first connecting portion (111) connected to each other, wherein the first connecting portion (111) is located on one side of the first linear body (112); A gate driving unit (40) is located between the first signal line (11) and the display area (10a); The first pattern layer (2000) is arranged in a different layer from the first signal line (11), and comprises a bridge line (41) and a main pattern layer (200); one end of the bridge line (41) is connected to the first connecting portion (111) through a first via hole (41a), and the other end is connected to the gate drive unit (40); the main pattern layer (200) is connected to one end of the first signal line (11) through a second via hole (31a).

2. The array substrate according to claim 1, wherein: The first connecting portion (111) is located on a side of the first linear body (112) close to the display area (10a).

3. The array substrate according to claim 1, wherein: The array substrate comprises a plurality of first signal lines (11), the plurality of first signal lines (11) are arranged in parallel, the first pattern layer (2000) comprises a plurality of bridge lines (41), the plurality of bridge lines (41) are arranged at intervals along the extension direction of the first signal lines (11), and the bridge lines (41) are connected to the first signal lines (11) in a one-to-one correspondence; The width of the first linear body (112) at the intersection with the bridging line (41) is smaller than the width of the non-intersection.

4. The array substrate according to claim 3, wherein: The side of the first linear body (112) has a recessed area (111a), and the recessed area (111a) is located at the intersection of the first linear body (112) and the bridge line (41); Among adjacent first signal lines (11), the first connection portion (111) of one first signal line (11) is located in a recessed area (111a) of the first linear body (112) of another first signal line (11).

5. The array substrate according to claim 3, wherein: The bridging wire (41) comprises a second linear body (411) and a second connecting portion (412) connected to each other. The second connecting portion (412) is located at the end of the second linear body (411) and is connected to the first connecting portion (111) through the first via hole (41a). The orthographic projection of the second connecting portion (412) on the base substrate (10) is located within the orthographic projection of the first connecting portion (111) on the base substrate (10).

6. The array substrate according to claim 5, wherein: In the plurality of bridge lines (41), the length and width of the second linear body (411) are positively correlated.

7. The array substrate according to any one of claims 1 to 6, wherein: The aperture of the first through hole (41a) is greater than the width of the first linear body (112).

8. The array substrate according to any one of claims 1 to 6, wherein: The first signal line (11) further includes a branch (114), the branch (114) being connected to one side of the first linear body (112), and the branch (114) partially overlapping with the bridge line (41).

9. The array substrate according to any one of claims 1 to 6, wherein: The main pattern layer (200) includes a source-drain pattern layer (222); the array substrate further includes an electrostatic protection circuit (20); the electrostatic protection circuit (20) includes a diode ring (22); the diode ring (22) is located in the non-display area (10b) of the base substrate (10); the diode ring (22) includes a gate pattern layer (221) and the source-drain pattern layer (222); the gate pattern layer (221) and the first signal line (11) are arranged in the same layer; the source-drain pattern layer (222) and the bridge line (41) are arranged in the same layer; the source-drain pattern layer (222) is connected to the gate pattern layer (221) through a third via hole (31b).

10. A display panel, characterized in that: The invention comprises a cell substrate and the array substrate according to any one of claims 1 to 9, wherein the cell substrate is arranged opposite to the array substrate.

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