Delay calibration circuit for time-to-digital converter

Abstract

The application relates to a delay calibration circuit for a time-to-digital converter. The delay calibration circuit comprises a frequency discriminator, a charge pump, a filtering capacitor, a bias voltage generating unit and a voltage-controlled delay chain; the voltage-controlled delay chain is used for receiving a starting signal and outputting a feedback signal after time delay; the frequency discriminator is used for receiving the starting signal and the feedback signal, converting a phase difference between the starting signal and the feedback signal into a voltage pulse signal, and outputting the voltage pulse signal to the charge pump; the charge pump is used for outputting a current signal with a corresponding pulse width to the filtering capacitor under the control of the voltage pulse signal; the filtering capacitor is used for converting the current signal into a time delay control voltage, and applying the time delay control voltage to an input end of the bias voltage generating unit; the bias voltage generating unit is used for generating a bias voltage under the action of the time delay control voltage, and controlling a delay time of the voltage-controlled delay chain by using the bias voltage. The delay calibration circuit is convenient to realize and high in precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of time-to-digital converter, and particularly relates to a delay calibration circuit for a time-to-digital converter. BACKGROUND

[0002] A time-to-digital converter is a circuit for converting a time signal into a digital signal, which is widely used in a phase-locked loop system. A time-to-digital converter applied to a charge pump type phase-locked loop to realize a fast locking function generally has certain requirements for a working range, and the working range usually needs to cover a reference period of the phase-locked loop system. A delay chain type time-to-digital converter structure is a more current time-to-digital converter.

[0003] However, the current delay chain type time-to-digital converter uses a switched capacitor array and a digital calibration algorithm to calibrate the delay gain, and however, the circuit of this structure needs complex digital logic circuit to assist calibration, and the calibration precision is low and difficult to realize. SUMMARY

[0004] Therefore, it is necessary to provide a delay calibration circuit for a time-to-digital converter which is convenient to realize and has high precision in view of the above technical problems.

[0005] The present application provides a delay calibration circuit. The delay calibration circuit is used in a fast locking phase-locked loop, and the delay calibration circuit comprises a frequency discriminator, a charge pump, a filter capacitor, a bias voltage generating unit and a voltage-controlled delay chain. The voltage-controlled delay chain is used to receive a start signal and output a feedback signal after time delay. The voltage-controlled delay chain and a sampling circuit together constitute a target time-to-digital converter for quantizing a time interval between the start signal and an end signal into a digital signal. The frequency discriminator is used to receive the start signal and the feedback signal, convert a phase difference between the start signal and the feedback signal into a voltage pulse signal, and output the voltage pulse signal to the charge pump. The charge pump is used to output a current signal with a corresponding pulse width to the filter capacitor under the control of the voltage pulse signal. The filter capacitor is used to convert the current signal into a delay control voltage, and apply the delay control voltage to an input end of the bias voltage generating unit. The bias voltage generating unit is used to generate a bias voltage under the action of the delay control voltage, and control a delay time of the voltage-controlled delay chain by using the bias voltage.

[0006] In one of the embodiments, the frequency and phase detector comprises a first flip-flop, a second flip-flop and a third flip-flop; the frequency and phase detector further receives an external input enable signal; under the actions of the start signal, the feedback signal and the enable signal, the first flip-flop and the second flip-flop output the voltage pulse signal, and the third flip-flop is used to block the start signal in an initial stage; wherein the initial stage is a stage before the rising edge of the feedback signal arrives for the first time.

[0007] In one of the embodiments, when the enable signal jumps from low level to high level and the feedback signal is low level, before the rising edge of the feedback signal arrives for the first time, the third flip-flop outputs low level, so that the first flip-flop is in a reset state to block the start signal in the initial stage; when the rising edge of the feedback signal arrives for the first time, the third flip-flop outputs high level, so that the first flip-flop changes from the reset state to a sampling state; and the second flip-flop changes from the sampling state to a trigger state and outputs the voltage pulse signal; when the rising edge of the start signal in a non-initial stage arrives, the first flip-flop changes from the sampling state to the trigger state; and the first flip-flop outputs the voltage pulse signal.

[0008] In one of the embodiments, after the first flip-flop and the second flip-flop output the voltage pulse signal, the first flip-flop and the second flip-flop change from the trigger state to the reset state.

[0009] In one of the embodiments, the frequency and phase detector further comprises a first inverter, a second inverter, a third inverter, a first AND gate, a first OR gate, a second OR gate and a buffer; the input end of the third inverter inputs the enable signal, the output end of the third inverter is connected with the reset end of the third flip-flop and the input end of the second OR gate; the clock end of the third flip-flop inputs the feedback signal, the output end of the third flip-flop is connected with the input end of the second inverter; the output end of the second inverter is connected with the input end of the first OR gate; the input end of the first OR gate is also connected with the input end of the second OR gate, and the output end of the first OR gate is connected with the reset end of the first flip-flop; the clock end of the first flip-flop inputs the start signal, and the output end of the first flip-flop is connected with the first inverter to output the voltage pulse signal through the output end of the first inverter; the input end of the first AND gate is connected with the output end of the first inverter and the output end of the second flip-flop, and the output end of the first AND gate is connected with the input end of the first OR gate and the second OR gate; the output end of the second OR gate is connected with the reset end of the second flip-flop; the clock end of the second flip-flop inputs the feedback signal, and the output end of the second flip-flop is further connected with the buffer to output the voltage pulse signal through the output end of the buffer.

[0010] In one of the embodiments, the first flip-flop, the second flip-flop and the third flip-flop are D flip-flops.

[0011] In one of the embodiments, the voltage-controlled delay chain comprises a plurality of cascaded delay units; the output terminal of the bias voltage generating unit is connected to each delay unit; the bias voltage generating unit is configured to adjust the current of each delay unit by using the bias voltage, so as to control the delay time of the voltage-controlled delay chain.

[0012] In one of the embodiments, the bias voltage generating unit comprises a pre-charge transistor; the pre-charge transistor is configured to adjust the control voltage of the input terminal of the bias voltage generating unit to the power supply voltage, so as to make the delay time of each delay unit to be the minimum value, in the case that the externally input enable signal is low and the delay calibration circuit is in the open loop state.

[0013] In one of the embodiments, the pre-charge transistor is specifically configured to charge the filter capacitor under the action of the enable signal, so as to adjust the voltage of the input terminal of the bias voltage generating unit to the power supply voltage, in the case that the delay calibration circuit is not in the working state.

[0014] In one of the embodiments, the bias voltage generating unit further comprises a plurality of switch transistors; the input terminal of each switch transistor is connected to the enable signal; each switch transistor is configured to control the bias voltage generating unit to stop working when the enable signal is low.

[0015] In one of the embodiments, the bias voltage generating unit further comprises a control transistor and a current mirror circuit; the control transistor is connected to the current mirror circuit; the control transistor is configured to control the current mirror circuit to output the bias voltage to the delay unit according to the voltage of the input terminal of the bias voltage generating unit.

[0016] In one of the embodiments, the pre-charge transistor, each switch transistor and the control transistor are transistors; the switch transistor comprises a first switch transistor, a second switch transistor and a third switch transistor; the gate of the pre-charge transistor is connected to the enable signal, the gate of the pre-charge transistor is connected to the power supply voltage, and the drain of the pre-charge transistor is connected to the input terminal of the bias voltage generating unit; the gate of the control transistor is connected to the input terminal of the bias voltage generating unit, the drain of the control transistor is connected to the current mirror circuit, and the source of the control transistor is connected to the drain of the first switch transistor; the drain of the second switch transistor and the drain of the third switch transistor are both connected to the current mirror circuit; the gate of the first switch transistor, the gate of the second switch transistor and the gate of the third switch transistor are all connected to the enable signal and the source is all grounded; the current mirror circuit is further connected to each delay unit.

[0017] In one of the embodiments, each delay unit is a current-starved circuit structure.

[0018] In the delay calibration circuit for a time-to-digital converter, the delay calibration circuit is used in a fast locking phase-locked loop, and the delay calibration circuit comprises a frequency discriminator, a charge pump, a filter capacitor, a bias voltage generating unit and a voltage-controlled delay chain; the voltage-controlled delay chain is configured to receive a start signal and output a feedback signal after time delay; the voltage-controlled delay chain and a sampling circuit together constitute a target time-to-digital converter configured to quantize a time interval between the start signal and an end signal into a digital signal; the frequency discriminator is configured to receive the start signal and the feedback signal, convert a phase difference between the start signal and the feedback signal into a voltage pulse signal, and output the voltage pulse signal to the charge pump; the charge pump is configured to output a current signal with a corresponding pulse width to the filter capacitor under the control of the voltage pulse signal; the filter capacitor is configured to convert the current signal into a time delay control voltage, and apply the time delay control voltage to an input end of the bias voltage generating unit; and the bias voltage generating unit is configured to generate a bias voltage under the action of the time delay control voltage, and control a delay time of the voltage-controlled delay chain by using the bias voltage. The delay calibration circuit uses the voltage-controlled delay chain in the target time-to-digital converter, so that real-time delay calibration of the time-to-digital converter is realized by using an analog delay lock loop, without the need of complex digital calibration logic, and the analog circuit calibration precision is higher, and the time-to-digital converter quantization error is smaller, so that high precision is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0020] Figure 1 FIG. 1 is a structural schematic diagram of a delay calibration circuit in an embodiment;

[0021] Figure 2 FIG. 2 is a structural schematic diagram of a radio frequency phase-locked loop system in an embodiment;

[0022] Figure 3 FIG. 3 is a structural schematic diagram of a frequency discriminator in an embodiment;

[0023] Figure 4 FIG. 4 is a structural schematic diagram of another delay calibration circuit in an embodiment;

[0024] Figure 5 FIG. 5 is a structural schematic diagram of a delay unit in an embodiment;

[0025] Figure 6 FIG. 6 is a structural schematic diagram of a bias voltage generating unit in an embodiment;

[0026] Figure 7 a convergence result of the charge pump output voltage VC in one embodiment;

[0027] Figure 8 a convergence result of the time-to-digital converter quantization output in one embodiment;

[0028] Figure 9 a simulation comparison result of the time-to-digital converter resolution before and after calibration in one embodiment. DETAILED DESCRIPTION

[0029] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to fully understand the present application, but the present application can be implemented in many different ways from those described herein, and those skilled in the art can make similar improvements without departing from the scope of the present application, and therefore the present application is not limited to the specific embodiments disclosed below.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] It can be understood that the terms "first", "second", etc. used in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of the present application, the first resistor can be referred to as the second resistor, and similarly, the second resistor can be referred to as the first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0032] It can be understood that "connection" in the following embodiments, if the circuits, modules, units, etc. connected to each other have transmission of electrical signals or data, it should be understood as "electrically connected", "communicatively connected" and the like.

[0033] It can be understood that "at least one" means one or more, and "a plurality of" means two or more. "At least part of an element" means part or all of the element.

[0034] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0035] A time-to-digital converter (TD-SCDMA) is a circuit that converts a time signal into a digital signal. It quantizes the phase difference between a reference signal and a feedback signal, and is therefore widely used in phase-locked loop (PLL) systems. In charge-pump PLL systems, the TD-SCDMA, together with an auxiliary charge pump, can form a fast locking path on top of a traditional loop, accelerating the entire loop establishment process.

[0036] Time-to-digital converters (TD-DC converters) used in charge-pump phase-locked loops (PLLs) for fast locking generally do not require high resolution accuracy but do have certain operating range requirements, typically needing to cover one reference cycle of the PLL system. Therefore, counter-type or delay-chain-type TD-DC structures are more commonly used. Counter-type TD-DC converters have a simple operating principle but require an additional high-frequency clock signal for counting, increasing design complexity and limiting application scenarios. Delay-chain-type TD-DC converters are simple to implement but have poor linearity and are easily affected by deviations in temperature, power supply voltage, and process angles. Currently, switched-capacitor arrays and digital calibration algorithms are used to calibrate the delay gain of delay-chain-type TD-DC converters. However, this circuitry requires complex digital logic circuitry for calibration, resulting in low calibration accuracy and difficulty in implementation. Furthermore, its calibration accuracy and range are limited by the minimum capacitor unit and the size of the capacitor array.

[0037] In view of this, this application provides a delay calibration circuit for a time-to-digital converter based on a delay-locked loop (DLL) for fast locking applications in phase-locked loop systems. This circuit improves the linearity of the delay-chain time-to-digital converter circuit, is easy to implement, and has high accuracy.

[0038] In one embodiment, such as Figure 1 The diagram shows a schematic of a delay calibration circuit provided in an embodiment of this application. This delay calibration circuit is implemented through a delay-locked loop (PLL), which is used for rapid locking within the PLL. Specifically, the delay calibration circuit 100 includes a frequency and phase detector 101, a charge pump 102, a filter capacitor C1, a bias voltage generation unit 103, and a voltage-controlled delay chain 104.

[0039] The voltage-controlled delay chain 104 is configured to receive the start signal and output a feedback signal after time delay; wherein the voltage-controlled delay chain 104, together with the sampling circuit, forms a target time-to-digital converter configured to quantize a time interval between the start signal and the end signal into a digital signal; the frequency discriminator 101 is configured to receive the start signal and the feedback signal, convert a phase difference between the start signal and the feedback signal into a voltage pulse signal, and output the voltage pulse signal to the charge pump 102; the charge pump 102 is configured to output a current signal with a corresponding pulse width to the filter capacitor C1 under the control of the voltage pulse signal; the filter capacitor C1 is configured to convert the current signal into a time delay control voltage, and apply the time delay control voltage to an input terminal of the bias voltage generating unit 103; and the bias voltage generating unit 103 is configured to generate a bias voltage under the action of the time delay control voltage, and control the delay time of the voltage-controlled delay chain 104 by using the bias voltage.

[0040] The delay calibration circuit 100 can be used in a target time-to-digital converter, and the voltage-controlled delay chain 104 used in the delay calibration circuit 100 is also used in the target time-to-digital converter. Optionally, the target time-to-digital converter is a delay chain type time-to-digital converter. Further, the target time-to-digital converter with the delay calibration circuit 100 can be applied to a radio frequency phase-locked loop system, for example, Figure 2 A structure schematic diagram of a radio frequency phase-locked loop system is shown, and the target time-to-digital converter with the delay calibration circuit 100 provided by the embodiments of the present application can be applied to the radio frequency phase-locked loop system as shown in Figure 2 to realize the function of accelerating loop locking with the auxiliary charge pump 102 in the radio frequency phase-locked loop system.

[0041] The delay calibration circuit 100 provided by the embodiments of the present application is realized based on a delay-locked loop, mainly composed of the frequency discriminator 101, the charge pump 102, the bias voltage generating unit 103, and the voltage-controlled delay chain 104. The delay calibration circuit 100 acquires a start signal and a feedback signal output by the voltage-controlled delay chain 104 to perform delay calibration, and can realize real-time calibration of a delay range of a time-to-digital converter delay chain under different temperatures, power supply voltages, and process angle deviations, so as to ensure that a dynamic range of the time-to-digital converter is within 1 reference period.

[0042] It should be noted that the radio frequency phase-locked loop system includes a frequency discriminator connected with a buffer and a time-to-digital converter, and the frequency discriminator is also included in the embodiments of the present application. The frequency discriminator 101 in the embodiments of the present application can be distinguished from the frequency discriminator in the radio frequency phase-locked loop system. The frequency discriminator can output a voltage pulse signal, which can specifically include an up signal (UP signal) and a down signal (DN signal).

[0043] The voltage-controlled delay chain 104 and the sampling circuit together constitute a target time digital converter. In operation of the target time digital converter, the voltage-controlled delay chain 104 receives a start signal, and the sampling circuit receives an end signal. In this regard, the start signal can be an up signal in a voltage pulse signal output by a frequency discriminator in a radio frequency phase-locked loop system, and the end signal received by the sampling circuit can be a down signal in the voltage pulse signal output by the frequency discriminator in the radio frequency phase-locked loop system. Figure 2

[0044] Optionally, the voltage-controlled delay chain 104 is further connected with a logic circuit, and the down signal and the up signal in the voltage pulse signal output by the frequency discriminator in the radio frequency phase-locked loop system are subjected to digital logic operation by the logic circuit to obtain the start signal and the end signal, respectively. The start signal is given to an input port of the voltage-controlled delay chain 104, and the end signal is given to a clock port of the sampling circuit. The target time digital converter can quantize a time interval between the start signal and the end signal into a digital signal. Specifically, the target time digital converter can convert a pulse width between the start signal and the end signal into a multi-bit digital control code to output the digital signal. Optionally, the digital signal is output via the sampling circuit.

[0045] Meanwhile, the voltage-controlled delay chain 104 delays the start signal to obtain a feedback signal, and outputs the feedback signal subjected to the delay to the frequency discriminator 101 in the delay calibration circuit 100. In addition to receiving the feedback signal, the frequency discriminator 101 also receives the start signal to generate the voltage pulse signal based thereon.

[0046] The charge pump 102 outputs a current signal corresponding to a pulse width to the filter capacitor C1 under control of the voltage pulse signal, controls charging and discharging of the filter capacitor C1, and then the filter capacitor C1 converts the current signal into a delay control voltage and applies the delay control voltage to an input end of the bias voltage generation unit 103. For example, when the frequency discriminator 101 in the delay calibration circuit 100 outputs the up signal, the charge pump 102 charges the capacitor, and when the frequency discriminator 101 in the delay calibration circuit 100 outputs the down signal, the capacitor discharges.

[0047] The bias voltage generation unit 103 is connected with the voltage-controlled delay chain 104. Optionally, the bias voltage generation unit 103 adjusts a current of the voltage-controlled delay chain 104 by using a bias voltage, so as to control a delay time of the voltage-controlled delay chain 104, thereby realizing delay calibration of the target time digital converter.

[0048] ​The delay calibration circuit 100 provided by the embodiment of the present application comprises a phase-frequency detector 101, a charge pump 102, a filter capacitor C1, a bias voltage generation unit 103 and a voltage-controlled delay chain 104; the voltage-controlled delay chain 104 is configured to receive a start signal and output a feedback signal after time delay; wherein the voltage-controlled delay chain 104 and a sampling circuit together constitute a target time digital converter configured to quantize a time interval between the start signal and an end signal into a digital signal; the phase-frequency detector 101 is configured to receive the start signal and the feedback signal, convert a phase difference between the start signal and the feedback signal into a voltage pulse signal, and output the voltage pulse signal to the charge pump 102; the charge pump 102 is configured to output a current signal with a corresponding pulse width to the filter capacitor C1 under the control of the voltage pulse signal; the filter capacitor C1 is configured to convert the current signal into a time delay control voltage, and apply the time delay control voltage to an input end of the bias voltage generation unit 103; the bias voltage generation unit 103 is configured to generate a bias voltage under the action of the time delay control voltage, and control a delay time of the voltage-controlled delay chain 104 by using the bias voltage. Wherein the delay calibration circuit 100 utilizes the voltage-controlled delay chain 104 in the target time digital converter, so that the real-time delay calibration of the time digital converter is realized by using an analog delay-locked loop, without the need of complex digital calibration logic, which is convenient to implement, has higher calibration accuracy of the analog circuit, smaller quantization error of the time digital converter and high precision.

[0049] The phase-frequency detector of the traditional edge trigger structure is composed of two D flip-flops and a reset delay path, and generates phase advance signals and phase lag signals with a certain pulse width through the rising edges of the start signal and the feedback signal; in the delay calibration application, the inputs of the delay-locked loop phase-frequency detector are the reference signal A without time delay and the feedback signal A' with time delay, respectively; when the initial reference signal rising edge is not blocked, the phase-frequency detector will generate an advance signal to control the delay chain to shorten the delay time according to the phase relationship between A and A', and the zero frequency locking problem occurs; the reference blocking phase-frequency detector provided by the embodiment of the present application adds a D flip-flop for blocking the initial start signal and a digital logic for generating a reset signal based on the traditional edge trigger structure, which can avoid the initial start signal mis-triggering and solve the zero frequency locking problem caused by the initial start signal mis-triggering.

[0050] The structure of the phase-frequency detector 101 in the delay calibration circuit 100 is exemplarily described below.

[0051] In one embodiment, the phase-frequency detector 101 comprises a first flip-flop, a second flip-flop and a third flip-flop; the phase-frequency detector 101 also receives an external input enable signal; under the action of a start signal, a feedback signal and the enable signal, the first flip-flop and the second flip-flop output a voltage pulse signal, and the third flip-flop is used to block the start signal in an initial stage; wherein the initial stage is a stage before the rising edge of the feedback signal arrives for the first time.

[0052] When the enable signal jumps from low to high and the feedback signal is low, before the rising edge of the feedback signal arrives for the first time, the third flip-flop outputs low, so that the first flip-flop is in a reset state to block the start signal in the initial stage; when the rising edge of the feedback signal arrives for the first time, the third flip-flop outputs high, so that the first flip-flop changes from the reset state to a sampling state; and the second flip-flop changes from the sampling state to a trigger state and outputs the voltage pulse signal; when the rising edge of the start signal in a non-initial stage arrives, the first flip-flop changes from the sampling state to the trigger state; and the first flip-flop outputs the voltage pulse signal.

[0053] Wherein, the traditional edge-triggered phase-frequency detector 101 structure is mainly composed of two D flip-flops and a reset delay link, which can realize the phase detection function in the range of-2π to 2π; if this structure is directly used in a delay-locked loop, the phenomenon of zero frequency locking may occur, the phase-frequency detector 101 is no longer to lock the delayed rising edge A~ and the next rising edge A+1 without delay, but to lock the delayed rising edge A~ and the rising edge A without delay. This zero frequency locking is similar to the period slip phenomenon often occurring in a phase-locked loop system, which is to lock to the wrong rising or falling edge. The phase-locked loop system finally realizes the locking of frequency and phase, and the period slip phenomenon does not affect the final locking result, but only prolongs the locking time; but in the delay-locked loop, if the phenomenon of zero frequency locking occurs, the phase-frequency detector 101 will always generate a phase advance signal, forcing the delay chain to continuously shorten the delay time, and thus making the delay of the delay chain always keep the minimum value, which seriously affects the actual circuit function.

[0054] The phase-frequency detector 101 in the embodiment of the application can block the start signal in the initial stage, avoiding the problem of zero frequency locking caused by the false triggering of the start signal in the initial stage.

[0055] And when the rising edge of the feedback signal arrives for the first time in the subsequent stage, the third flip-flop outputs high, so that the first flip-flop changes from the reset state to the sampling state; and the second flip-flop changes from the sampling state to the trigger state and outputs the voltage pulse signal; when the rising edge of the start signal in the non-initial stage arrives, the first flip-flop changes from the sampling state to the trigger state; and the first flip-flop outputs the voltage pulse signal, so that the start signal is not blocked in the subsequent stage.

[0056] In one embodiment, after the first flip-flop and the second flip-flop output the voltage pulse signal, the first flip-flop and the second flip-flop change from the trigger state to the reset state, so that the loop accurately performs the delay calibration next time.

[0057] In one embodiment, as Figure 3 An exemplary structural diagram of a frequency discriminator provided by an embodiment of the present application is shown. The frequency discriminator 101 includes a first flip-flop DFF1, a second flip-flop DFF2, and a third flip-flop DFF3, and further includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a first AND gate AND1, a first OR gate OR1, a second OR gate OR2, and a buffer BUF1. An input end of the third inverter inputs an enable signal, an output end of the third inverter is connected with a reset end of the third flip-flop and an input end of the second OR gate; a clock end of the third flip-flop inputs a feedback signal, an output end of the third flip-flop is connected with an input end of the second inverter; an output end of the second inverter is connected with an input end of the first OR gate; the input end of the first OR gate is also connected with an input end of the second OR gate, and an output end of the first OR gate is connected with a reset end of the first flip-flop; a clock end of the first flip-flop inputs a start signal, and an output end of the first flip-flop is connected with the first inverter, so as to output a voltage pulse signal through an output end of the first inverter; input ends of the first AND gate are connected with the output end of the first inverter and an output end of the second flip-flop, and an output end of the first AND gate is connected with input ends of the first OR gate and the second OR gate; an output end of the second OR gate is connected with a reset end of the second flip-flop; a clock end of the second flip-flop inputs the feedback signal, and an output end of the second flip-flop is further connected with the buffer, so as to output the voltage pulse signal through an output end of the buffer.

[0058] That is, for the phase frequency detector 101, mainly includes three D flip-flops DFF1, DFF2, DFF3 and simple combination digital logic circuit, wherein DFF1 and DFF2 are used to generate pull-up signal UP and pull-down signal DN respectively, and DFF3 is used to block the initial start signal. The clock end of DFF1 is connected to the start signal, the reset end is connected to the output end of OR gate OR1, the output end Q is connected to the input end of inverter INV1 and the input end of AND gate AND1; the clock end of DFF2 is connected to the feedback signal, the reset end is connected to the output end of OR gate OR2, and the output end Q is connected to the input end of buffer BUF1 and the input end of AND gate AND1; the clock end of DFF3 is connected to the feedback signal, the reset end is connected to the output end of inverter INV3, and the output end Q is connected to the input end of inverter INV2. The output end of INV1 outputs the pull-up signal UP, and the output end of BUF1 outputs the pull-down signal DN; the output end of AND1 is connected to the input end of OR1 and OR2. The output end of INV2 is connected to the input end of OR1, and the output end of INV3 is connected to the reset end of DFF3 and the input end of OR2. The PFDEN signal is the enable signal of the phase frequency detector 101, when the PFDEN is low, the phase frequency detector 101 is closed, at this time, the reset ends of the three D flip-flops are high; when the PFDEN is high, DFF2 and DFF3 first enter the trigger state, when the rising edge of the feedback signal comes, DFF3 outputs high, DFF1 enters the trigger state, and the phase frequency detector 101 starts to identify the phase difference. When DFF1 and DFF2 are triggered, AND1 generates high level and controls the reset of DFF1 and DFF2 through OR1 and OR2 respectively, and the D flip-flop reenters the trigger state and waits for triggering.

[0059] It can be understood that the phase frequency detector 101 can also be other structures for realizing the above functions, which are not completely illustrated here.

[0060] Optionally, the first trigger, the second trigger and the third trigger are D flip-flops.

[0061] Optionally, as described above, the voltage pulse signal output by the phase frequency detector 101 includes the UP signal and the DN signal, and here, the voltage pulse signal output by the first trigger can be the DN signal, and the voltage pulse signal output by the second trigger can be the DN signal.

[0062] Exemplarily, taking the feedback signal leading the start signal as an example, the reference block frequency discriminator phase discriminator 101 provided by the embodiment of the present application has the following functions: when the enable signal PFDEN is low, the D flip-flop DFF1, DFF2 and DFF3 are all in the reset state, and the output end Q keeps low; when the enable signal PFDEN jumps to high, the frequency discriminator phase discriminator 101 enters the working state, before the feedback signal fFB arrives, the output end Q of DFF3 keeps low, and through the inverter INV2 and the OR gate OR1, high is maintained, so as to control DFF1 to be still in the reset state, at this time, when the rising edge of the start signal fREF arrives, DFF1 cannot be triggered, and thus the initial start signal is blocked.

[0063] Specifically, after the rising edge of the feedback signal fFB arrives, DFF2 triggers to output high, and after passing through the buffer BUF1, the pull-down signal DN is generated, DFF3 also triggers to output high, and after passing through INV2 and OR1, low is generated, so that DFF1 is no longer in the reset state, and waits for the rising edge of the start signal fREF to arrive to trigger; after the rising edge of the second start signal arrives, DFF1 triggers and outputs high, and after passing through the inverter INV1, the pull-up signal UP is generated, at this time, the two input ends of AND1 are both high, and thus the high level signal output by AND1 resets DFF1 and DFF2, and a round of frequency discrimination and phase discrimination operation is completed. Since DFF3 will not be reset by the high level output by AND1, the subsequent process DFF2 output continues to be high, and the start signal will not be blocked again.

[0064] In one embodiment, refer to Figure 4 , which shows the structure schematic diagram of another delay calibration circuit provided by the embodiment of the present application. Wherein, the voltage-controlled delay chain 104 includes a plurality of cascaded delay units 1041; the output end of the bias voltage generating unit 103 is connected with each delay unit 1041; the bias voltage generating unit 103 is used for adjusting the current of each delay unit 1041 by using the bias voltage, so as to control the delay time of the voltage-controlled delay chain 104. Optionally, as shown in Figure 4 , the sampling circuit in the target time digital converter is composed of a plurality of cascaded D flip-flops.

[0065] Optionally, the quantized digital signal output by the sampling circuit is a 9-bit digital signal Q<8:0>.

[0066] In one embodiment, each delay unit 1041 is a current-starved circuit structure.

[0067] Exemplarily, as shown in Figure 5A structure diagram of a delay unit is shown. Here, the delay unit 1041 is composed of MOS tubes M11 to M16. The source of M11 can be connected to a power supply voltage VDD, the source of M16 can be connected to the ground, VCP and VCN are connected to the bias voltage generating unit 103 to be controlled by the bias voltage generating unit to achieve current regulation. VI is an input voltage, and VO is an output voltage.

[0068] Here, the current of the delay unit 1041 is regulated by controlling the gate voltage VCP of the pull-up transistor M11 and the gate voltage VCN of the pull-down transistor M16, and then the delay time is accurately controlled in real time.

[0069] Reference Figure 5 It can be known that the delay unit 1041 of the application adopts double voltage control, and compared with the single voltage control structure, the delay unit 1041 of the application has better delay symmetry, wider regulation range, and smaller signal waveform damage.

[0070] In addition to the zero frequency locking problem, when the delay time of the delay chain is too long, the frequency multiplication locking problem of the delay locked loop can also occur. At this time, the phase detector 101 will try to lock the delayed rising edge A~ and the rising edge A+2 together, resulting in a phase lag signal being generated all the time, forcing the delay chain to continuously lengthen the delay time, and then making the delay of the delay chain always keep the maximum value.

[0071] In the related art, the voltage-to-current unit usually adopts a traditional current mirror structure to generate a bias voltage to control the current of the delay chain. When factors such as process deviation, temperature change, power supply voltage fluctuation, etc. cause the initial delay of the delay chain to exceed one period, the phase detector will miss the starting signal A+1, and will compare the feedback signal A~ with the starting signal A+2, resulting in that the actual delay time of the delay chain is 2 reference periods. The bias voltage generating unit 103 provided in the application additionally introduces a pre-charge tube to pre-charge the output capacitor of the charge pump 102, so as to ensure that when the loop is turned on, the output bias voltage makes the delay chain in a minimum delay state, and the delay time is less than one reference period, thereby avoiding the problem of frequency multiplication locking. Meanwhile, the switch tube is introduced to ensure that when the loop is not working, no large static power consumption will be generated due to the pre-charge tube.

[0072] The structure of the bias voltage generating unit 103 will be exemplarily described below.

[0073] In one embodiment, the bias voltage generating unit 103 includes a pre-charge tube. The pre-charge tube is configured to, in a case that an external input enable signal is at a low level and the delay calibration circuit 100 is in an open loop state, adjust a control voltage at an input end of the bias voltage generating unit 103 to a power supply voltage, so as to make the delay time of each delay unit 1041 be a minimum value.

[0074] The pre-charge tube is specifically used for charging the filter capacitor C1 under the action of the enable signal to adjust the voltage of the input end of the bias voltage generating unit 103 to the power supply voltage in the case that the delay calibration circuit 100 is not in the working state.

[0075] In the embodiment of the application, in order to avoid the problem of frequency multiplication locking, the bias voltage generating unit 103 provided in the embodiment charges the filter capacitor C1 through the pre-charge tube in the case that the loop is not started, that is, in the case of the switch state, the voltage of the input end of the bias voltage generating unit 103 connected with the pre-charge tube is charged to the power supply voltage VDD, and correspondingly, the delay unit 1041 can be in the minimum delay state, thereby ensuring the flexibility of the delay calibration of the delay calibration circuit 100.

[0076] In one embodiment, the bias voltage generating unit 103 further comprises a plurality of switch tubes; the input end of each switch tube is connected with the enable signal; and each switch tube is used for controlling the bias voltage generating unit 103 to stop working when the enable signal is at a low level.

[0077] Optionally, the enable signal connected with the input end of each switch tube is the same enable signal as the external enable signal connected with the blocking frequency discriminator phase detector 101.

[0078] In the embodiment, the bias voltage generating unit 103 normally works when the enable signal is at a high level, and stops working when the enable signal jumps to a low level, so that there is no static power consumption overhead and power consumption is saved.

[0079] In one embodiment, the bias voltage generating unit 103 further comprises a control tube and a current mirror circuit; the control tube is connected with the current mirror circuit; and the control tube is used for controlling the current mirror circuit to output the bias voltage to the delay unit 1041 according to the voltage of the input end of the bias voltage generating unit 103.

[0080] In the embodiment, the control tube is connected with the input end of the bias voltage generating unit 103 and also connected with the current mirror circuit, and the current mirror circuit is connected with the delay unit 1041. When the voltage of the input end changes, the control tube acts on the current mirror circuit, and the current mirror circuit correspondingly outputs the bias voltage to the delay unit 1041.

[0081] Optionally, the current mirror circuit can be composed of a plurality of MOS tubes. As long as the function of the current mirror can be realized, the embodiment does not completely show the example.

[0082] Optionally, each switch tube, the above-mentioned pre-charge tube and the control tube can be a MOS tube.

[0083] Please refer to Figure 6An exemplary structure diagram of a bias voltage generation unit is shown in FIG. 3. In the exemplary structure diagram, the pre-charge transistor M1, each switch transistor and the control transistor M4 are transistors; the switch transistors include the first switch transistor M8, the second switch transistor M9 and the third switch transistor M10; the gate of the pre-charge transistor is connected to an enable signal EN, the gate of the pre-charge transistor is connected to a power supply voltage VDD, and the drain of the pre-charge transistor is connected to an input terminal VC of the bias voltage generation unit 103; the gate of the control transistor is connected to the input terminal of the bias voltage generation unit 103, the drain of the control transistor is connected to a current mirror circuit, and the source of the control transistor is connected to the drain of the first switch transistor; the drains of the second switch transistor and the third switch transistor are both connected to the current mirror circuit; the gates of the first switch transistor, the second switch transistor and the third switch transistor are all connected to the enable signal, and the sources of the first switch transistor, the second switch transistor and the third switch transistor are all grounded; and the current mirror circuit is also connected to each delay unit 1041. It should be noted that, for the convenience of understanding, Figure 6 The connection relationship between the bias voltage generation unit 103 and the delay unit 1041 is also shown in FIG. 3. In the exemplary structure diagram, the current mirror circuit can be composed of transistors M2 to M7.

[0084] The drain of M2 in the current mirror circuit is connected to the gate of M11 in the delay unit 1041, and a bias voltage VCP is provided. The drain of M7 in the current mirror circuit is connected to the gate of M16 in the delay unit 1041, and a bias voltage VCN is provided.

[0085] For the bias voltage generation unit 103, the transistors M2 to M7 are used to generate the bias voltages VCP and VCN, wherein the current flowing through M2 is controlled by the gate voltage VC of M4. When the VC voltage decreases, the current flowing through M4 decreases, and then the drain voltage of M2 increases. Since M2 is connected in a diode mode, and the gate of M2 is connected together with the gate of M3, the current flowing through M3 also decreases, and the drain voltage of M3 decreases accordingly. Therefore, with the decrease of the VC voltage, the bias voltages VCP and VCN increase and decrease respectively, and accordingly, for the voltage-controlled delay chain 104, the delay time of the voltage-controlled delay chain 104 increases.

[0086] It should be noted that the sizes of the transistors M11 to M16 in the delay unit 1041 need to be designed properly to ensure that the waveform of the input signal will not be distorted after being delayed.

[0087] The pre-charge transistor M1 can charge the capacitor C1 in advance in the state that the loop is closed, and charging the VC voltage to VDD can ensure that the delay range of the voltage-controlled delay chain 104 in the initial state is at a minimum value, and then the problem of frequency multiplication locking of the loop can be avoided.

[0088] Please refer to Figure 7 The convergence results of the output voltage VC of the charge pump under different processes, temperatures and power supply voltages (under different PVTs) are shown in FIG. 4, and the convergence results of the output voltage VC of the charge pump under different processes, temperatures and power supply voltages (under different PVTs) are shown in FIG. 5.Figure 8 The convergence results of the time-to-digital converter quantization output under different PVTs are shown. The calibration process is completed within 10 reference clock cycles, and the voltage VC is stably maintained at a fixed level, ensuring that the dynamic range of the time-to-digital converter is within 1 reference cycle. After the calibration phase is completed, the time-to-digital converter can correctly output the quantization result to the subsequent auxiliary charge pump, control the size of the auxiliary current, and thus realize the effect of accelerating the phase-locked loop to lock.

[0089] In addition, Figure 9 are simulation comparison results of the resolution of the time-to-digital converter before and after calibration under different PVTs, wherein S1 is the resolution simulation result of the time-to-digital converter without the delay calibration circuit 100 under different PVTs, and S2 is the resolution simulation result of the time-to-digital converter with the delay calibration circuit 100 under different PVTs. It can be seen that the delay calibration circuit 100 based on the phase-locked loop provided in the embodiments of the present application can significantly reduce the influence of process deviation and other factors on the resolution of the time-to-digital converter, significantly improve the robustness of the circuit, and better assist in realizing the function of accelerating the phase-locked loop to lock.

[0090] The delay calibration circuit 100 provided in the embodiments of the present application can calibrate the delay range of the voltage-controlled delay chain 104 in real time, ensure that the working range of the time-to-digital converter is always maintained within one reference cycle of the phase-locked loop system, thereby reducing the influence of process deviation, power voltage fluctuation, temperature change and other factors on the dynamic range and resolution of the time-to-digital converter, improving the robustness of the time-to-digital converter, improving the linearity of the delay chain type time-to-digital converter circuit, and realizing the real-time calibration function of the delay range of the delay chain under different temperatures, power voltages and process angles. The delay of the delay chain can be calibrated in real time to ensure that its dynamic range and resolution do not change with environmental temperature or power voltage fluctuation, and the loop calibration speed is fast, which can complete the locking within 10 reference cycles, has the characteristics of real-time delay calibration and fast working speed. The frequency discriminator and phase discriminator 101 and the bias voltage generation unit 103 in the loop can avoid problems such as zero frequency locking and frequency multiplication locking in the loop, and can normally realize the calibration function under different process deviations, and have high reliability and robustness.

[0091] In one embodiment, the present application also provides a phase-locked loop comprising the delay calibration circuit as described in any of the above embodiments. For other definitions of the phase-locked loop, refer to the description above, which will not be repeated here.

[0092] The technical features of the above embodiments can be combined in any way. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0093] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific manner, but should not be construed as limiting the scope of the patent of the present application. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A delay calibration circuit, characterized by, The delay calibration circuit is used in a fast locking phase-locked loop, and comprises a frequency discriminator, a charge pump, a filter capacitor, a bias voltage generating unit and a voltage-controlled delay chain. The voltage-controlled delay chain is configured to receive a start signal and output a feedback signal after time delay; wherein the voltage-controlled delay chain and a sampling circuit together constitute a target time-to-digital converter configured to quantize a time interval between the start signal and an end signal into a digital signal; wherein the start signal is a pull-up signal in a voltage pulse signal output by a frequency discriminator in a radio frequency phase-locked loop system, and the end signal is a pull-down signal in the voltage pulse signal output by the frequency discriminator in the radio frequency phase-locked loop system. The frequency discriminator is configured to receive the start signal and the feedback signal, convert a phase difference between the start signal and the feedback signal into a voltage pulse signal, and output the voltage pulse signal to the charge pump. The charge pump is configured to output a current signal with a corresponding pulse width to the filter capacitor under control of the voltage pulse signal. The filter capacitor is configured to convert the current signal into a time delay control voltage, and apply the time delay control voltage to an input end of the bias voltage generating unit. The bias voltage generating unit is configured to generate a bias voltage under action of the time delay control voltage, and control a delay time of the voltage-controlled delay chain by using the bias voltage.

2. The delay calibration circuit of claim 1, wherein, The frequency discriminator comprises a first flip-flop, a second flip-flop and a third flip-flop; and the frequency discriminator further receives an externally input enable signal. Under actions of the start signal, the feedback signal and the enable signal, the first flip-flop and the second flip-flop output the voltage pulse signal, and the third flip-flop is configured to block the start signal in an initial stage; wherein the initial stage is a stage before a rising edge of the feedback signal arrives for the first time.

3. The delay calibration circuit according to claim 2, wherein, when the enable signal jumps from a low level to a high level and the feedback signal is at a low level, before the rising edge of the feedback signal arrives for the first time, the third flip-flop outputs a low level, so that the first flip-flop is in a reset state to block the start signal in the initial stage; when the rising edge of the feedback signal arrives for the first time, the third flip-flop outputs a high level, so that the first flip-flop changes from the reset state to a sampling state; the second flip-flop changes from the sampling state to a trigger state and outputs the voltage pulse signal; when a rising edge of the start signal in a non-initial stage arrives, the first flip-flop changes from the sampling state to the trigger state; and the first flip-flop outputs the voltage pulse signal.

4. The delay calibration circuit according to claim 3, wherein, after the first flip-flop and the second flip-flop output the voltage pulse signal, the first flip-flop and the second flip-flop change from the trigger state to the reset state.

5. The delay calibration circuit of claim 2, wherein, The frequency discriminator further comprises a first inverter, a second inverter, a third inverter, a first AND gate, a first OR gate, a second OR gate and a buffer. An input end of the third inverter inputs the enable signal, and an output end of the third inverter is connected with a reset end of the third flip-flop and an input end of the second OR gate; A clock end of the third flip-flop inputs the feedback signal, and an output end of the third flip-flop is connected with an input end of the second inverter; An output end of the second inverter is connected with an input end of the first OR gate; The input end of the first OR gate is also connected with an input end of the second OR gate, and an output end of the first OR gate is connected with a reset end of the first flip-flop; A clock end of the first flip-flop inputs the start signal, and an output end of the first flip-flop is connected with the first inverter to output the voltage pulse signal through an output end of the first inverter; An input end of the first AND gate is connected with an input end of the first inverter and an output end of the second flip-flop, and an output end of the first AND gate is connected with input ends of the first OR gate and the second OR gate; An output end of the second OR gate is connected with a reset end of the second flip-flop; A clock end of the second flip-flop inputs the feedback signal, and an output end of the second flip-flop is also connected with the buffer to output the voltage pulse signal through an output end of the buffer.

6. The delay calibration circuit of claim 2, wherein, The first flip-flop, the second flip-flop and the third flip-flop are D flip-flops.

7. The delay calibration circuit of claim 1, wherein, The voltage-controlled delay chain comprises a plurality of cascaded delay units; and the bias voltage generating unit is connected with each of the delay units. The bias voltage generating unit is configured to adjust a current of each of the delay units by using the bias voltage, so as to control a delay time of the voltage-controlled delay chain.

8. The delay calibration circuit of claim 7, wherein, The bias voltage generating unit comprises a pre-charge tube. The pre-charge tube is configured to adjust a control voltage of an input end of the bias voltage generating unit to a power supply voltage when an externally input enable signal is at a low level and the delay calibration circuit is in an open loop state, so as to make a delay time of each of the delay units a minimum value.

9. The delay calibration circuit according to claim 8, wherein The pre-charge tube is specifically configured to charge the filter capacitor under the action of the enable signal to adjust the voltage of the input end of the bias voltage generating unit to the power supply voltage when the delay calibration circuit is not in a working state.

10. The delay calibration circuit of claim 8, wherein, The bias voltage generating unit further comprises a plurality of switch tubes; and an input end of each of the switch tubes is connected with the enable signal. Each of the switch tubes is configured to control the bias voltage generating unit to stop working when the enable signal is at the low level.

11. The delay calibration circuit of claim 10, wherein, The bias voltage generating unit further comprises a control tube and a current mirror circuit; and the control tube is connected with the current mirror circuit. The control tube is configured to control the current mirror circuit to output the bias voltage to the delay units according to the voltage of the input end of the bias voltage generating unit.

12. The delay calibration circuit of claim 11, wherein, The pre-charge tube, each of the switch tubes and the control tube are transistors; and the switch tubes comprise a first switch tube, a second switch tube and a third switch tube. The gate of the pre-charge transistor is connected to the enable signal, the source of the pre-charge transistor is connected to a power supply voltage, and the drain of the pre-charge transistor is connected to an input terminal of the bias voltage generating unit; The gate of the control transistor is connected to the input terminal of the bias voltage generating unit, the drain of the control transistor is connected to the current mirror circuit, and the source of the control transistor is connected to the drain of the first switch transistor; The drains of the second switch transistor and the third switch transistor are both connected to the current mirror circuit, the gates of the first switch transistor, the second switch transistor and the third switch transistor are all connected to the enable signal, and the sources of the first switch transistor, the second switch transistor and the third switch transistor are all grounded; The current mirror circuit is also connected to each of the delay units.

13. The delay calibration circuit of claim 7, wherein, Each of the delay units is a current-starved circuit structure.

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