A top-down planned hierarchical layout method for analog integrated circuits

Abstract

A top-down planned simulation integrated circuit hierarchical layout method, comprising the following steps: according to the hierarchy of the circuit netlist, the layout hierarchy of the to-be-laid-out module is divided; from top to bottom according to the layout hierarchy, it is checked whether there is a soft module not directly limited by constraint in all modules, if there is a soft module, pre-layout is carried out, and the size of the soft module is adjusted; from bottom to top according to the layout hierarchy, the bottom device module is divided into constraint groups according to the constraint type and laid out; each constraint group is taken as a macro module, and macro module layout is carried out in the uppermost layer. The layout method provided by the application can adjust the module size of the lower layer according to the pre-layout condition of the upper layer, avoid area waste caused by improper aspect ratio of the module, adopt hierarchical layout algorithm, first carry out layout on the bottom layer based on the template and optimization method, then carry out macro module layout supporting polygons on the upper layer, so that a layout result meeting the design rule requirement, having good performance and compact area is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation (EDA), and particularly relates to a top-down planning analog integrated circuit hierarchical layout method. BACKGROUND

[0002] With the development of emerging industries such as Internet of Things and 5G network, the application of analog and mixed signal integrated circuits (AMS) has increased significantly. In order to speed up the design cycle and shorten the product launch time, automatic generation of analog layout has become an indispensable technology. Similar to the manual process, the automatic generation of layout is generally divided into two stages of layout and routing.

[0003] The analog layout has a significant impact on the performance of the analog circuit, which specifies the position of each module. If it is not properly placed, it may cause the relative parameters of the device to not meet the design target, and lead to the parasitic mismatch caused by the too long wire connection. Therefore, the analog circuit is limited by various constraints such as centroid, symmetry, proximity, signal flow, etc. Most of these constraints are for bottom devices, such as differential load, differential input pair, current mirror, etc. These structures often have fixed placement patterns or optimization methods according to their respective constraint types, and have weak relationships with other modules. Since multiple optimization objectives need to be considered and the layout of all devices is limited by complex constraint conditions, it requires a large amount of time consumption and has great difficulty. SUMMARY

[0004] In order to solve the defects of the prior art, the purpose of the present application is to provide a top-down planning analog integrated circuit hierarchical layout method, which can adjust the size of the lower layer module according to the pre-layout of the upper layer, avoid the area waste caused by the inappropriate aspect ratio of the module, adopt a hierarchical layout algorithm, first perform layout on the bottom layer based on the template and optimization method, and then perform macro module layout supporting polygon on the upper layer, to obtain a layout result that meets the design rule requirements, has good performance and is compact in area.

[0005] In order to achieve the above purpose, the top-down planning analog integrated circuit hierarchical layout method provided by the present application comprises the following steps:

[0006] According to the hierarchical structure of the circuit netlist, the layout hierarchy of the to-be-laid-out module is divided;

[0007] According to the layout hierarchy from top to bottom, it is checked whether there is a soft module not directly limited by the constraint in all modules, and if there is a soft module, pre-layout is performed to adjust the size of the soft module;

[0008] According to the layout hierarchy from bottom to top, the bottom device module is divided into constraint groups according to the constraint type for layout;

[0009] The constraint groups are taken as macro modules, and the macro module layout is performed at the uppermost layer.

[0010] Further, in the AMS circuit, the layout hierarchy of the modules to be laid out is divided according to the hierarchy defined in the AMS circuit netlist.

[0011] Further, the pre-layout is a layout for one-time area optimization by using a topological representation combined with simulated annealing, so as to adjust the size of the soft modules.

[0012] Further, the step of laying out the bottom-level device modules according to the constraint type to form constraint groups from bottom to top according to the layout hierarchy further comprises: laying out the modules in the common centroid constraint group according to a first placement strategy or a second placement strategy.

[0013] The first placement strategy is to realize the common centroid constraint in a cross-coupled mode.

[0014] The second placement strategy is to realize the common centroid constraint in a flat mode, and the placement rule is as follows:

[0015] If n = 2k (k = 1, 2, 3, …),

[0016]

[0017] If n = 2k-1 (k = 1, 2, 3, …),

[0018]

[0019] Where T i,j represents the module placed in the ith row and jth column is A or B, n represents the total number of rows, m represents the total number of columns, and Z + is a set of positive integers.

[0020] Further, the step of laying out the bottom-level device modules according to the constraint type to form constraint groups from bottom to top according to the layout hierarchy further comprises:

[0021] Symmetrical modules composed of transistors are placed in row alignment;

[0022] When there are self-symmetrical modules, the self-symmetrical modules are arranged from top to bottom according to the signal flow sequence, each self-symmetrical module constitutes a row, and the symmetrical modules are inserted into each position of the existing row or as a new row;

[0023] For a module composed of multiple MOS transistors of the same size, the transistors of the same device are divided into two parts according to the symmetry mode of the current mirror, and are regarded as a pair of symmetrical new modules, which are placed in rows;

[0024] For the module of non-transistor hierarchy, the module of right half is laid out according to the rule of macro module layout, the module of left half is laid out synchronously, and the laying position is determined by symmetry.

[0025] Further, the step of laying out the bottom device module according to the constraint type from bottom to top according to the layout hierarchy further comprises: for the module of MOS tube in the adjacent constraint group, laying by row; and for other modules in the adjacent constraint group, laying by using the same method as the macro module layout.

[0026] Further, the step of laying out the macro module at the uppermost layer by taking each constraint group as a macro module further comprises: using the following polygon edge search layout algorithm to lay out the macro module.

[0027] According to the number and / or area size of the macro module, the macro module is sorted, and each time a macro module is laid out from the center to the outside according to the order, during the laying process, the laid macro module is combined into a whole polygon, the external region of all edges of the polygon is searched by edge search, all the layable positions of the to-be-laid macro module are evaluated, the optimal laying position of the to-be-laid macro module is selected, and the to-be-laid macro module is laid at the optimal laying position by sticking to the outside of the polygon.

[0028] Further, it further comprises: if two adjacent pins of adjacent MOS tubes are connected to the same wire net, the two adjacent pins are overlapped and placed;

[0029] In the co-center constraint group layout, the module at the corresponding position is flipped and translated, and the flipping rule is as follows:

[0030]

[0031] Wherein, f(j) represents whether the jth device of the module is flipped, 0 represents not flipped, and 1 represents flipped, Z + is a positive integer set, and m represents the total number of columns;

[0032] In other constraint groups, after the MOS tubes in a device are realized to share the source and drain, whether the adjacent devices can share the source and drain is considered; when the modules in the adjacent constraint group are all MOS tubes, the modules are laid by row alignment.

[0033] To achieve the above object, the application further provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor is used for executing the computer program stored in the memory to realize the top-down planning analog integrated circuit hierarchical layout method.

[0034] To achieve the above object, the application further provides a computer readable storage medium, wherein at least one instruction is stored in the storage medium, and the instruction is loaded and executed by a processor to realize the top-down planned hierarchical layout method of analog integrated circuit.

[0035] The top-down planned hierarchical layout method of analog integrated circuit provided by the application has the following beneficial effects compared with the prior art:

[0036] The size of the module in the lower layer is adjusted according to the pre-layout condition of the upper layer to avoid area waste caused by improper aspect ratio of the module; the bottom-up hierarchical layout method is adopted to first layout the device module in the bottom layer according to the constraint, then take each constraint group as a macro module, and finally perform macro module layout in the uppermost layer to obtain a layout result meeting the design rule requirement, having good performance and compact area.

[0037] Other features and advantages of the application will be described in the following description, and some will become apparent from the description, or will be learned from the practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of the specification, and together with the embodiments of the application, serve to explain the application, and do not constitute a limitation of the application. In the drawings:

[0039] Figure 1 The flow chart of the top-down planned hierarchical layout method of analog integrated circuit according to the embodiment of the application;

[0040] Figure 2 The schematic diagram of the five-tube OTA structure according to the embodiment of the application;

[0041] Figure 3 The schematic diagram of the module placement of the co-centroid constraint group according to the embodiment of the application;

[0042] Figure 4 The schematic diagram of the module placement of the module composed of multiple MOS tubes with the same size according to the embodiment of the application;

[0043] Figure 5 The schematic diagram of the module placement of the two adjacent pins of the adjacent MOS tubes overlapping according to the embodiment of the application;

[0044] Figure 6 The schematic diagram of the layout hierarchical structure according to the embodiment of the application;

[0045] Figure 7 The schematic diagram of the macro module layout according to the embodiment of the application;

[0046] Figure 8A schematic diagram of an electronic device structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are merely intended to illustrate and explain the present application, and should not be used to limit the scope of the present application.

[0048] Embodiments of the present application will be described in more detail by referring to the drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms, and should not be construed as being limited to the embodiments set forth herein, but rather the embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are merely for exemplary purposes, and should not be used to limit the scope of the present application.

[0049] The term "comprising" and variations thereof as used herein are used inclusively, i.e., "comprising, but not limited to." The term "based on" is "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments."

[0050] It should be noted that the terms "first", "second", and the like, as can be used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, and are more especially used to distinguish one element from another.

[0051] It should be noted that the terms "a" and "an" and "the" and similar referents used herein are intended to be inclusive of the plural form of the terms, unless the context clearly indicates otherwise. For example, the term "a" or "an" is used to denote "at least one" of the referenced elements.

[0052] It should be noted that the terms "module", "soft module", "hard module", and "macro module" are used herein to distinguish the following: all circuit components or sub-circuits directly involved in layout are collectively referred to as modules, among which the modules that can be adjusted in size are referred to as soft modules, and the modules that cannot be adjusted in size are referred to as hard modules; macro modules are modules that are laid out using a polygon edge search layout algorithm (in the embodiments of the present application, after layout within all constraint groups is completed, each constraint group is treated as a macro module, and a macro module layout is performed at the uppermost layer, which only optimizes line length and area, and also takes into account signal flow). The related definitions of other terms will be given in the following description.

[0053] Figure 1 A flowchart of a hierarchical layout method for a top-down planned analog integrated circuit according to an embodiment of the present application is shown in FIG. 2, and will be described below with reference to FIG. 2. Figure 1The top-down planning analog integrated circuit hierarchical layout method of the present application is described in detail.

[0054] In step 101, the shape and process parameters of the module to be laid out are read.

[0055] In this step, the shape and position of each device pin in the module to be laid out, the distance from the boundary of the MOS device to the metal layer where the source-drain pin is located, and the width of the metal layer where the source-drain pin is located are read, etc.

[0056] In step 102, the layout hierarchy is extracted.

[0057] In AMS circuits, there is an accurate hierarchy structure in the AMS circuit netlist according to the schematic diagram. The circuit is divided into multiple levels according to the hierarchy specified in the circuit netlist, and a specific optimization target is established for each level, which can effectively limit the number of modules that need to be laid out each time.

[0058] In the embodiment of the present application, on the basis of the accurate hierarchy, a virtual hierarchy structure can also be introduced to adapt to the requirements of a specific circuit, which helps to further reduce the size of the layout problem. For example, the signal path constraints of a reference circuit can not be as strict as those of a comparator circuit, and there is a difference in the optimization direction between the two. Before layout, a virtual hierarchy is first divided, and the divided virtual hierarchy structure is input into the layout. The virtual hierarchy can be divided according to the constraint type or the circuit function, such as the modules in the differential pair structure that meet the common centroid constraint can be extracted as a virtual hierarchy, and the modules on the critical signal path that need to be strictly matched can be extracted as a virtual hierarchy. Since the bottom device layout often has many constraints, and these constraints do not overlap and act on the same level, the bottom device can be divided into constraint groups according to the constraint type, and each constraint group is independently laid out.

[0059] The constraint groups can include multiple levels of nesting. Figure 2 For the five-tube OTA structure according to the embodiment of the present application, as shown in Figure 2 The five-tube OTA (Operational Transconductance Amplifier) circuit is composed of three constraint groups (differential load 1, differential pair 2, and current mirror 3), wherein the differential load 1 is symmetrically placed, the differential pair 2 is placed with a common centroid, and the current mirror 3 is placed according to the current mirror constraint. The three constraint groups should also be symmetric according to the same symmetry axis, so they are also in a common symmetric constraint group.

[0060] In step 103, it is checked whether there is a soft module in all modules of each level from top to bottom, and if there is, the soft module is pre-laid out and the size of the soft module is adjusted.

[0061] In the embodiment of the present application, the pre-layout is a layout with area optimization before the formal layout, which is performed by the method of topological representation (for example, B* tree) combined with simulated annealing, so as to adjust the size of the soft module.

[0062] In step 1031, the size of the soft module in the current level is checked according to the pre-layout result of the level.

[0063] In step 1032, if the size of the soft module is changed, the next level layout is returned to, the related modules affected by it are added with size constraints, and the pre-layout is performed again.

[0064] In step 1033, if the size of the soft module is not changed, the pre-layout of the current level is continued to be generated.

[0065] In the embodiment of the present application, the module constrained by the constraint is often of a relatively fixed shape, for example, the height of the symmetric group is often determined by the number of the self-symmetry module, and the capacitor array has a fixed size. When these modules are used for the upper layer layout, they can be regarded as hard modules with fixed size. The module not directly constrained by the constraint inside, for example, the digital logic module integrated by many small size digital modules, or the analog upper layer module composed of some analog sub-circuits, can be approximately regarded as a soft module when used for the upper layer layout. The width or length of the soft module is changed within a certain range to adapt to the requirement of the layer layout while keeping the total area unchanged.

[0066] For the level with soft module, in order to quickly locate the module affected by the change of the size of the soft module and adjust the position of the module after each change of the size of the soft module, a pre-layout can be performed before the formal layout by the method of topological representation combined with simulated annealing. The purpose of the pre-layout is only to adjust the size of the soft module according to the estimated layout condition, so the optimization target can only consider the total area, so that the size of all modules does not obviously exceed the range suitable for the overall layout. If the size of the soft module is obviously different from the original size, the module inside is subjected to size constraint and the layout is performed again.

[0067] In step 104, the bottom layer device module is laid out according to the constraint from bottom to top according to the layout level.

[0068] In the embodiment of the present application, when the device level layout is performed at the bottom layer, the separate layout for each constraint can guarantee the implementation quality of the constraint. In the device level layout, a single device only follows one constraint in a single layout. According to the common centroid constraint, the symmetry constraint or the proximity constraint, the bottom layer device is divided into constraint groups, and the corresponding placement strategy is adopted for each constraint group. The implementation method of the specific constraint is as follows:

[0069] i. Common centroid constraint:

[0070] To minimize systematic and random mismatches between devices of a certain size ratio, the device is decomposed into unit cells of the same specifications and arranged in a two-dimensional array with a common centroid. This common centroid constraint is typically applied to differential circuit structures and effectively eliminates mismatches caused by two-dimensional process gradients.

[0071] Figure 3 FIG. 1 is a schematic diagram showing the arrangement of modules of a common centroid constraint group according to an embodiment of the present invention. Figure 3 As shown, there are two placement strategies, Figure 3 (a) is to realize the common center of mass constraint according to the cross-coupling mode. Figure 3 (b) implements the common centroid constraint in a tiling mode. Figure 3 The scheme described in (b) is better than Figure 3 (a), but this will make the wiring more complicated. Figure 3 The arrangement of A and B in (b) can be described as:

[0072] If n=2k(k=1,2,3,…),

[0073]

[0074] If n=2k-1(k=1,2,3,…),

[0075]

[0076] Among them, T i,j Indicates whether the module placed in row i and column j belongs to A or B, n represents the total number of rows, m represents the total number of columns, and Z + is the set of positive integers.

[0077] ii. Symmetry constraints:

[0078] Symmetry is one of the most important constraints in analog layout design, reducing parasitic mismatch and improving process insensitivity. For symmetry-constrained groups, the layout strategy depends on the type of modules within the group. When modules consist solely of transistors, designers typically align these transistors to the same width, allowing the symmetrical modules to be aligned in rows. When self-symmetric modules are present, they are first arranged from top to bottom according to signal flow, with each module forming a separate row. Symmetrical modules are then inserted in pairs at each position in an existing row or as new rows.

[0079] Figure 4 FIG. 1 is a schematic diagram showing the arrangement of a module composed of multiple MOS tubes of the same size according to an embodiment of the present invention. Figure 4As shown, the present application considers that a device in an analog circuit can be composed of multiple MOS transistors of the same size, and the current mirror is a special symmetric mode, for a module composed of multiple MOS transistors of the same size, the transistors of the same device should be divided into two parts, and viewed as a pair of symmetric new modules, and placed in a row, so as to achieve the best matching.

[0080] For modules of non-transistor hierarchy, follow the traditional symmetric placement principle, allow the module to be placed across the row, layout the module in the right half according to the rules of macro module layout, place the module in the left half synchronously, determine the placement position through symmetry, and consider the influence of the modules on both sides on the evaluation of the layout.

[0081] iii. Adjacent constraint:

[0082] The adjacent constraint can ensure that the modules in the constraint group are preferentially laid out, and ensure that these modules are not disturbed by the modules outside the constraint group. This constraint can be used to limit the placement of certain modules, and emphasize the signal flow relationship between certain modules.

[0083] The adjacent constraint also needs to be divided into two categories, one is the adjacent constraint group composed of all MOS transistors, in order to facilitate source and drain sharing (source-drain sharing), the module is also required to be placed in a row, and the modules in other adjacent constraint groups can be placed in the same way as the macro module, and the weights of the indicators can be adjusted, and the influence of the signal flow, area or bus length indicators on the whole can be adjusted according to the content of the constraint.

[0084] In an embodiment of the present application, in order to save the total area of the layout, the following method for realizing source-drain sharing is adopted:

[0085] Figure 5 For the overlapping placement of two adjacent pins of adjacent MOS transistors according to the embodiment of the present application, as shown in Figure 5 If the two adjacent pins (S or D) of adjacent MOS transistors are connected to the same wire net, the two pins can be placed overlappingly.

[0086] Source-drain sharing will have different effects on the placement strategy of different constraint groups, for example, in the layout of the centroid constraint group, the modules in the corresponding position need to be flipped and translated, and the flipping rule is as follows:

[0087]

[0088] Wherein, f(j) represents whether the jth device of the module is flipped, 0 represents not flipped, and 1 represents flipped, Z + is a set of positive integers, and m represents the total number of columns.

[0089] In other constraints, MOS inside a device needs to be source-drain shared first, and then whether the adjacent device can be source-drain shared is considered. In a symmetric group composed of MOS modules, in order to make as many devices as possible source-drain shared, whether the device is flipped needs to be considered, which increases the number of searches, but can significantly reduce the area. In addition, a constraint of adjacent constraint in row is added, when the modules in the adjacent constraint group are all MOS, they can be placed in row to make the MOS source-drain shared.

[0090] Figure 6 For the layout hierarchy diagram according to the embodiment of the application, as shown in Figure 6 , the layout is from bottom to top according to the layout hierarchy structure, wherein G0 corresponds to a current mirror structure, and a detachable symmetric layout is performed; G1 corresponds to a differential pair structure, and a common centroid layout is performed; G2 corresponds to a differential load structure, and a symmetric layout is performed; M6 is a second stage source follower input tube, and is surrounded by a guard ring, and thus is independently a module. These modules are all in a critical signal path, and need to be placed in sequence according to a signal flow and symmetrically about a same symmetry axis, and thus there are symmetric constraints and signal flow sequence constraints in G4. Other devices are components of a control circuit, and each device can be an independent module, or can be combined according to the type of MOS to share a guard ring to save area.

[0091] In step 105, each constraint group is taken as a macro module, and macro module layout is performed in the uppermost layer.

[0092] In the embodiment of the application, after the layout in all constraint groups is completed, each constraint group is taken as a macro module, and macro module layout is performed in the uppermost layer only to optimize the line length and area and taking into account the signal flow. As shown in Figure 6 , G4, G5, G6, G7 and G8 are regarded as macro modules in the top layer, the polygon boundaries thereof are extracted, and the macro module layout is performed by using the polygon edge search layout algorithm.

[0093] In order to maximize the use of layout area and maintain the compactness of the layout in any case, the polygon boundary is extremely common in analog layout. The polygon edge search layout algorithm is used in the application, which ensures the centralized placement of the polygon and rectangular modules, and effectively uses the available space.

[0094] The polygon edge search layout algorithm is as follows:

[0095] The macro modules are sequenced, and one macro module is added into the layout of the placed macro modules in sequence each time from the center to the outside, during the placing, the placed macro modules are combined into a whole polygon, the external regions of all the edges of the polygon are searched by edge sticking, all the placeable positions of the to-be-placed macro module are evaluated, the optimal placeable position of the to-be-placed macro module is selected, and the to-be-placed macro module is placed at the optimal placeable position by sticking to the outside of the polygon.

[0096] Figure 7 As shown in the macro module layout schematic diagram according to the embodiment of the application, Figure 7 The placed macro modules can be combined into a polygon alpha, and the outside of each edge of the polygon alpha corresponds to a placeable region, allowing the next macro module beta to be placed by sticking to the edge. The placeable positions are evaluated by searching the external regions of all the edges of the polygon alpha by edge sticking, and the optimal placeable position of the macro module beta is selected. For each placeable position of the macro module, the evaluation criteria include the total wire length and compactness, and the signal flow sequence of the key level is considered. In addition, if the overlap between the modules is detected, the placeable position is discarded immediately. The macro module sequence is randomly exchanged continuously to search different layout solutions caused by different macro module sequences, and the process is ended when a sufficient number of searches is reached. During the layout, the macro modules cannot be rotated at will due to the limitation of the signal flow in each macro module, but the placement in different directions should be supported for some special macro modules such as capacitors and resistors, and the placement positions in different rotation angles (0°, 90°, 180° and 270°) need to be searched additionally at each position, and the advantages and disadvantages of these positions are compared.

[0097] In the embodiment of the application, the macro modules are sequenced according to the number of wires and the area size of the macro modules. For example, the macro modules are sequenced according to the number of wires from more to less, or the macro modules are sequenced according to the area size from large to small, or the number of wires and the area size are considered comprehensively, the macro modules are given corresponding weights according to the number of wires and the area size, and the macro modules are sequenced according to the weights.

[0098] The top-down planning analog integrated circuit hierarchical layout method has the following advantages:

[0099] By constraining the layout hierarchy, the search space of a single layout can be effectively reduced, and the difficulty of solving the layout problem is reduced. During device-level layout, separate layout for each constraint can ensure the implementation quality of the constraint. The edge sticking search layout algorithm is used for macro module layout, the polygon boundary of the macro module is extracted, the area utilization of the overall layout is improved, and the efficiency of the algorithm is ensured.

[0100] By using a hierarchical method, devices or standard cells with the same constraint are combined into a macro module, and a virtual structure can be extracted from the original structure of the circuit. In the macro module, customized layout is performed according to the constraint requirement; in the upper layer layout outside the macro module, there is no constraint limitation, and the macro module is laid out and solved by taking the total wire length, area and signal flow sequence as the optimization target.

[0101] In order to fully utilize the area of the layout, in the layout of the circuit with a multi-layer structure, the layout engineer usually plans the position of the module in advance, and controls the shape and size of some modules. This is a top-down planning process, but when the layout is automatically performed, the layout needs to follow a bottom-up sequence, and the layout of the bottom module is generated first, and then the size of the upper layer is determined.

[0102] In the embodiment of the present application, an electronic device is also provided, Figure 8 The schematic structural diagram of the electronic device according to the embodiment of the present application is shown in Figure 8 The electronic device of the present application includes a processor 801 and a memory 802, wherein,

[0103] The memory 802 stores a computer program, and when the computer program is read and executed by the processor 801, the steps in the top-down planning simulation integrated circuit hierarchical layout method embodiment described above are performed.

[0104] In the embodiment of the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program, wherein the computer program is set to execute the steps in the top-down planning simulation integrated circuit hierarchical layout method embodiment described above when running.

[0105] In the embodiment, the computer readable storage medium described above can include but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various computer program storage media.

[0106] Those skilled in the art can understand that the above description is only a preferred embodiment of the present application, and is not used to limit the present application, although the present application has been described in detail with reference to the foregoing embodiments, and those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A top-down planning method for hierarchical layout of analog integrated circuits, comprising the following steps: Divide the layout hierarchy of the modules to be laid out according to the hierarchical structure of the circuit netlist; Check all modules from top to bottom according to the layout hierarchy to see if there are any soft modules that are not directly constrained. If there are any soft modules, perform pre-layout and adjust the size of the soft modules. According to the layout hierarchy from bottom to top, the bottom device modules are divided into constraint groups according to the constraint types for layout; Treat each constraint group as a macromodule and perform macromodule layout at the top level; A single device follows only one constraint in a single layout. Based on the common centroid constraint, symmetry constraint, or proximity constraint, the underlying devices are divided into constraint groups, and the corresponding placement strategy is adopted for each constraint group.

2. The top-down planning analog integrated circuit hierarchical layout method according to claim 1, characterized in that: In the AMS circuit, the layout hierarchy of the modules to be laid out is divided according to the hierarchical structure specified in the AMS circuit netlist.

3. The top-down planning hierarchical layout method for analog integrated circuits according to claim 1, wherein: The pre-layout is to use a topological representation combined with a simulated annealing method to perform a layout that takes area optimization into consideration, thereby adjusting the size of the soft module.

4. The top-down planning hierarchical layout method for analog integrated circuits according to claim 1, wherein: The step of laying out the bottom-level device modules in constraint groups according to the constraint type from bottom to top according to the layout hierarchy further includes: laying out the modules in the common centroid constraint group according to the first placement strategy or the second placement strategy; The first placement strategy is to implement common centroid constraint in a cross-coupling mode; The second placement strategy is to implement the common centroid constraint in a tiling mode, and the placement rules are as follows: If n=2k(k=1,2,3,…), If n=2k-1(k=1,2,3,…), Among them, T i,j Indicates whether the module placed in row i and column j is A or B, n indicates the total number of rows, m indicates the total number of columns, and Z + is the set of positive integers.

5. The top-down planning analog integrated circuit hierarchical layout method according to claim 1, characterized in that: The step of laying out the bottom-level device modules in constraint groups according to constraint types from bottom to top according to the layout hierarchy further includes: The symmetrical modules composed of transistors are aligned in rows; When there are self-symmetric modules, arrange them from top to bottom according to the signal flow order. Each self-symmetric module constitutes a row. Insert the symmetric modules in pairs into each position of the existing row or as a new row. For a module composed of multiple MOS transistors of the same size, the transistors of the same device are divided into two parts according to the symmetry pattern of the current mirror. These are regarded as a pair of symmetrical new modules and arranged in rows. For modules with non-transistor hierarchical structures, they are placed across rows. The modules in the right half are laid out according to the rules of macro module layout, and the modules in the left half are placed synchronously. The placement is determined by symmetry.

6. The top-down planning analog integrated circuit hierarchical layout method according to claim 1, characterized in that: The step of laying out the bottom-level device modules in constraint groups according to constraint types from bottom to top according to the layout hierarchy further includes: arranging the modules consisting entirely of MOS transistors in adjacent constraint groups in rows; and arranging the other modules in adjacent constraint groups using the same method as the macro module layout.

7. The top-down planning analog integrated circuit hierarchical layout method according to claim 1, characterized in that: The step of using each constraint group as a macromodule and performing macromodule layout at the top layer further includes: using the following polygon edge search layout algorithm to perform macromodule layout: The macro modules are sorted according to the number of connections and / or the size of their areas. Each macro module is placed one at a time from the center outward in order. During the placement process, the placed macro modules are merged into a whole polygon. The outer areas of all sides of the polygon are searched by edge-to-edge, and all possible placement positions of the macro modules to be placed are evaluated. The optimal placement position of the macro module to be placed is selected, and the macro module to be placed is placed at the optimal placement position, close to the outer side of the polygon.

8. The top-down planning hierarchical layout method for analog integrated circuits according to claim 1, wherein: Also includes: If two adjacent pins of adjacent MOS tubes are connected to the same wire net, the two adjacent pins are placed overlappingly; In the common centroid constraint group layout, the modules at the corresponding positions are flipped and translated. The flipping rules are as follows: Among them, f(j) indicates whether the jth device of the module is flipped, 0 means no flip, 1 means flip, Z + is a set of positive integers, m represents the total number of columns; In other constraint groups, after the MOS tubes in a device share the source and drain, consider whether the adjacent devices can share the source and drain. When all the modules in the adjacent constraint group are MOS tubes, they are arranged in rows.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor is used to execute the computer program stored in the memory to implement the steps of the top-down planning analog integrated circuit hierarchical layout method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, which is loaded and executed by the processor to implement the steps of the top-down planning analog integrated circuit hierarchical layout method according to any one of claims 1 to 8.

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